Self-driven stateless pipelined data compact packing device and method

Abstract

The application discloses a self-driven stateless pipeline data compact packing device and method, relates to the technical field of data compression alignment processing, and comprises an input port, K cascaded shift processing units and an output unit. The input port receives initial input data valid signals, valid flag bit vectors and data vectors. The K shift processing units are used for sequentially checking the validity of the values of the corresponding positions in the valid flag bit vectors from high bits to low bits from the K+1th position of the valid flag bit vectors, positioning the positions of the valid flags in the valid flag bit vectors, moving the positions of the valid flags in the valid flag bit vectors to the low bits of the valid flag bit vectors, and moving the valid data units corresponding to the valid flags in the data vectors to the low bits of the data vectors according to the positions of the valid flags. The valid data in the multiple parallel data is compactly arranged in the original order to the low bit side of the output through the multi-stage pipeline shift network, and the resource consumption is significantly reduced.

Description

Technical Field

[0001] This invention relates to the field of data compression and alignment technology, specifically to a self-driven, stateless pipeline data compact packaging device and method. Background Technology

[0002] In high-speed data stream processing systems, such as image sensor interfaces, communication baseband processing, artificial intelligence accelerators, and system-on-chip interconnects using the "AXI-Stream" bus protocol, data is typically transmitted in parallel multiplexing. Each data unit has a width of DATA_WIDTH bits, and its validity is indicated by the corresponding bit in the accompanying valid flag vector. When the number of valid data streams changes dynamically, the receiving end needs to compactly arrange all valid data from the input multiple streams in their original order onto the low-order side of the output data bus for subsequent storage or computation. Simultaneously, a new valid flag vector is generated, where the low-order bits are consecutively 1 and the high-order bits are 0. This process is called data compaction or data compression alignment. In FPGA implementations, such modules are often used to compactly process sparse data output by algorithms to reduce the bandwidth requirements of subsequent processing units.

[0003] Existing technologies for achieving compact data packaging typically include barrel shifter networks, first-in-first-out (FIFO) buffers, and software-layer packet processing. Among these, the first approach, based on combinational logic barrel shifter networks, directly connects multiple input data streams to a multi-level multiplexer tree. An external controller calculates the number or position offset of valid data in the current cycle and generates a selection signal to shift the valid data to the target position in one go. For example, existing solutions use multiple barrel shifters connected in series in a pipeline structure, relying on a control module to determine the shift amount based on the length of the previous residual data. The disadvantages of this approach are: the barrel shifter requires a large number of multiplexers, and when the number of parallel paths is large, the combinational logic path depth increases significantly, limiting the circuit's maximum operating frequency. The external controller needs to calculate the shift amount in real time, introducing additional control logic and timing overhead. Furthermore, this approach requires retaining residual data from previous cycles to achieve cross-cycle packaging, increasing storage resource consumption and design complexity.

[0004] The second approach, using a first-in-first-out (FIFO) buffer in conjunction with read / write pointers for bit-width conversion or data realignment, writes input data into the FIFO and then reads it from the FIFO according to the target bit-width and reassembles it. The drawbacks of this approach are: the FIFO buffer introduces unpredictable latency and requires additional control logic to manage the read / write pointers and their empty / full states. For streaming processing scenarios, the use of FIFOs increases resource consumption and disrupts the sequential relationship of data packets.

[0005] The third approach uses software or upper-layer protocols to process data, parsing the flag fields at the packet level, removing invalid data, and then reassembling the data. This approach is mainly suitable for non-real-time or software-level data processing, but it cannot meet the low latency and high throughput requirements of hardware streaming processing, and it cannot be directly integrated into hardware bus protocols such as AXI-Stream.

[0006] In summary, existing technologies generally suffer from the following shortcomings: they rely on complex barrel shifters or FIFO buffers, leading to high resource consumption and high combinational logic latency; they require an external controller to calculate the shift amount, increasing design complexity; they lack self-driven utilization of accompanying valid flag signals and require storage of historical residual data (i.e., stateful), making it impossible to achieve fixed-latency streaming processing without historical dependencies. Therefore, there is an urgent need for a data compact packaging method and apparatus that is structurally simple, easy to control, has fixed latency, is stateless, and is compatible with streaming interface protocols. Summary of the Invention

[0007] The purpose of this invention is to provide a self-driven stateless pipeline data compact packing device and method. Without relying on an external controller or storing any historical residual data, it is self-driven based solely on the current input valid flag bit vector. Through a multi-stage pipeline shifting network, it compactly arranges the valid data in multiple parallel data streams in the original order to the low-order output side while maintaining a fixed processing delay.

[0008] To achieve the above objectives, the following solutions are proposed: In a first aspect, this application provides a self-driven, stateless pipelined data compact packaging device, including an input port, K ​​cascaded shift processing units, and an output unit. Each shift processing unit includes a valid flag register, a valid flag bit vector register, and a data vector register. The input port receives the initial input data valid signal, the valid flag bit vector, and the data vector. Starting from the Kth shift processing unit, each shift processing unit proceeds sequentially and performs the following operations at each rising edge of the clock: The first shift processing unit latches the valid input data signal, and each subsequent stage latches the valid output data signal of the previous stage. Each shift processing unit checks the validity of the specified bit in the received valid flag bit vector corresponding to the current shift processing unit, selectively performs shift operations on the valid flag bit vector and the data vector, generates the valid flag bit vector and the data vector of the next shift processing unit, registers them in the valid flag bit vector register and the data vector register respectively, and passes them to the next shift processing unit. The output unit selectively shifts the valid flag vector and the data vector output by the last shift processing unit based on the validity of the least significant bit of the valid flag vector output by the last shift processing unit, so that all valid data in the data vector are compactly arranged in the least significant bit of the data vector, thereby outputting the packaged data.

[0009] In some specific technical solutions, the data vector includes K+2 data units. Each valid flag bit in the valid flag bit vector indicates the validity of the corresponding data unit. The bit indices of the data unit and the valid flag bits range from 1 to K+2, with the K+2th bit being the most significant bit and the 1st bit being the least significant bit. K shift processing units are concatenated in order of decreasing bit indices from K to 1, where i is an integer from 1 to K. The i-th shift processing unit checks the validity of the (i+1)-th bit in the received valid flag bit vector. If the (i+1)th bit is valid, the received valid flag vector and data vector are passed directly to the next shift processing unit. If the (i+1)th bit is invalid, all data from the (i+2)th bit to the highest bit will be shifted one bit to the right to remove the current hole, and the highest bit will be automatically filled with zeros. The position of the valid flag in the valid flag bit vector will be shifted to the lower bit, and the valid data unit corresponding to the valid flag in the data vector will be shifted to the lower bit. In some specific technical solutions, the process of generating the effective flag bit vector and data vector for the next shift processing unit is as follows: The specified bit in the valid flag bit vector corresponding to the current shift processing unit is determined based on the bit index value i of the current shift processing unit in multiple shift processing units; Check if the value of a specified bit in the received valid flag bit vector is valid. If it is valid, output the received valid flag bit vector and data vector directly as the valid flag bit vector and data vector of the next shift processing unit. If invalid, all data higher than the specified bit will be shifted one bit to the right to remove the current hole, and the highest bit will be automatically filled with zero. This will shift the position of the valid flag in the valid flag bit vector to the lower bit, and at the same time shift the valid data unit corresponding to the valid flag in the data vector to the lower bit, generating the valid flag bit vector and data vector of the next shift processing unit.

[0010] In some specific technical solutions, the output unit performs the following operations: At the rising edge of the clock, the valid data signal output by the last shift processing unit is directly used as the output, and then the validity of the least significant bit of the valid flag vector output by the last shift processing unit is checked. If the least significant bit is valid, then the valid flag vector and data vector output from the last shift processing unit are directly output. If the least significant bit is invalid, the valid flag vector and data vector output by the last shift processing unit are shifted one bit to the right of the least significant bit, and the most significant bit of the valid flag vector and data vector output by the last shift processing unit is cleared to zero.

[0011] In some specific technical solutions, a delay unit is also included. The input port is also used to receive the data packet end flag signal. The delay unit is used to delay the input data packet end flag signal through a shift register chain. The number of stages in the shift register chain is the number of stages in the shift processing unit + 1, to ensure that the data packet end flag signal is output synchronously with the packaged data.

[0012] Secondly, this application provides a self-driven, stateless pipeline data compact packaging method, specifically including the following steps: S1. Receive the initial input data valid signal, valid flag bit vector and data vector, the data vector includes K+2 data units; S2. Construct K cascaded shift processing units. Starting from the (K+1)th position of the valid flag bit vector, check the validity of the corresponding position in the valid flag bit vector from the high bit to the low bit, and selectively perform shift operations on the valid flag bit vector and the data vector. S3. Based on the validity of the least significant bit of the valid flag vector output by the last shift processing unit, selectively shift the valid flag vector and the data vector output by the last shift processing unit, so that all valid data units in the data vector are compactly arranged in the least significant bit of the data vector, thereby outputting the packaged data.

[0013] In some specific technical solutions, each valid flag bit in the valid flag bit vector indicates the data validity of the corresponding data unit, wherein the bit indices of the data unit and the valid flag bits are from 1 to K+2, the K+2th bit is the most significant bit, and the 1st bit is the least significant bit; K shift processing units are concatenated in order of decreasing bit index from K to 1, where i is an integer from 1 to K. The i-th shift processing unit checks the validity of the (i+1)-th bit in the received valid flag bit vector. The specific process of step S2 is as follows: If the (i+1)th bit is valid, the received valid flag vector and data vector are passed directly to the next shift processing unit. If the (i+1)th bit is invalid, all data from the (i+2)th bit to the most significant bit are shifted one bit to the right, and the most significant bit is automatically padded with zeros. The position of the valid flag in the valid flag bit vector is shifted to the lower bit, and the valid data unit corresponding to the valid flag in the data vector is also shifted to the lower bit.

[0014] In some specific technical solutions, the specific process of step S3 is as follows: At the rising edge of the clock, the valid data signal output by the last shift processing unit is directly used as the output, and then the validity of the least significant bit of the valid flag vector output by the last shift processing unit is checked. If the least significant bit is valid, then the valid flag vector and data vector output from the last shift processing unit are directly output. If the least significant bit is invalid, the valid flag vector and data vector output by the last shift processing unit are shifted one bit to the right of the least significant bit, and the most significant bit of the valid flag vector and data vector output by the last shift processing unit is cleared to zero.

[0015] The inventive concept of this application is as follows: To address the technical problems of existing data compression and alignment schemes, such as high hardware resource overhead, long combinational logic paths, the need for external controllers to calculate shift amounts, the need to store historical residual data (stateful), and the inability to achieve fixed-latency streaming processing due to the use of barrel shifters or FIFO buffers, this application constructs multiple cascaded shift processing units corresponding to the number of intermediate bits (excluding the most and least significant bits) in the valid flag bit vector. Through multi-stage pipelined shift operations, each shift processing unit determines whether to pass through or borrow data units from higher bits and shift them right by one bit based on specific positions in the valid flag bit vector received at that stage. After a fixed number of processing stages, the compressed data is output. The entire process does not rely on any external controller, does not store any historical residual data, and the shift decision is entirely self-driven by the currently input valid flag bit vector. The multi-stage pipelined shift network compactly arranges the valid data from multiple parallel data streams in their original order to the low-order output side while maintaining a fixed processing latency.

[0016] The beneficial effects of this invention are as follows: This invention provides a self-driven, stateless pipelined data compact packaging device and method. It employs a simple network of shift registers to form multi-stage shift processing units, replacing traditional barrel shifters or FIFO buffers. Each stage of the shift processing unit requires only three sets of registers (one each for the valid flag, valid flag bit vector, and data vector) and one multiplexer, eliminating the need for complex multi-stage multiplexer trees and significantly reducing resource consumption. Furthermore, because register latching is used between each stage of the shift processing unit, the entire device can continuously process back-to-back input data without data bubble insertion, achieving full throughput.

[0017] This invention eliminates the need for an external controller to calculate the shift amount or record the length of residual data. The shift decision is entirely self-driven by the valid flag bit vector of the accompanying data—each shift processing unit only needs to check a specific bit in the valid flag bit vector received at its current stage to determine whether to pass through or shift. This self-driven mechanism makes the control logic of the device almost zero, avoiding timing convergence problems and design complexity caused by the controller. More importantly, this invention does not store any residual data from previous cycles, making it a stateless circuit that greatly simplifies the control logic. Furthermore, the total processing delay of this invention is precisely related to the number of shift processing units and is independent of the input data pattern, achieving fixed and predictable delay. In contrast, the delay of the barrel shifter scheme depends on the combinational logic path, and the delay of the FIFO scheme depends on the buffer occupancy, neither of which has a fixed delay characteristic. Attached Figure Description

[0018] Figure 1 A block diagram of a self-driven stateless pipeline data compact packaging device provided in an embodiment of the present invention; Figure 2 Flowchart of a self-driven stateless pipeline data compact packaging method provided in an embodiment of the present invention; Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example 1 like Figure 1 As shown, this embodiment provides a self-driven stateless pipelined data compact packaging device, including an input port, K ​​cascaded shift processing units, and an output unit, wherein: 1. Input Port The input port receives the initial data packet end flag signal (tlast), input data validity signal (tvalid), validity flag vector (tstrb), and data vector (tdata) from the data bus. The data vector includes K+2 data units, where the bit width of each data unit is DATA_WIDTH. The number of parallel input data units is K+2, and the total width of the data vector is (K+2) * DATA_WIDTH bits. The accompanying validity flag vector has a width of K+2 bits, and each bit in the validity flag vector indicates the validity of the corresponding data unit.

[0021] It should be noted that data in this device is transmitted according to the AXI-Stream protocol, where tstrb is redefined as a valid data unit flag (rather than a byte modifier natively defined by the AXI-Stream protocol). This extension has practical engineering value under custom hardware interfaces or specific protocol conventions.

[0022] 2. K cascaded shift processing units K cascaded shift processing units form a K-stage pipelined shift network. Each shift processing unit includes a valid flag register (for storing the tvalid signal), a valid flag bit vector register (for storing the tstrb vector), and a data vector register (for storing the tdata vector). The index numbers of each shift processing unit decrease from K to 1. When performing shift operations on the valid flag bit vector and the data vector, the K-stage shift processing units check the validity of the values ​​at the corresponding positions in each stage of the valid flag bit vector, starting from the (K+1)th position of the valid flag bit vector, and move the position of the valid flag in the valid flag bit vector to the lower bits of the valid flag bit vector. At the same time, according to the position of the valid flag, the valid data unit corresponding to the valid flag in the data vector is moved to the lower bits of the data vector.

[0023] Specifically, starting from the Kth shift processing unit, each shift processing unit proceeding downwards performs the following operation on each rising edge of the clock: 2.1 The first shift processing unit (assuming the index value is K) As the first shift processing unit, it directly accepts signals from the input port. On each rising edge of the clock, if the reset signal is invalid, it performs the following operations: First, the input tvalid signal is latched into the valid flag register of this level. Assume the bits of the valid flag vector and data vector are arranged from right to left, with the least significant bit being bit 1 and the most significant bit being bit K+2. Then, the value of bit K+1 in the input valid flag vector tstrb is checked. If this bit is 1 (indicating that a valid flag is stored at this position, and the data unit in the data vector is valid), the entire input tstrb vector and tdata vector are directly stored in the corresponding register of this level. If this bit is 0 (indicating that the data at this position is invalid), the higher-order bit (bit K+2) data unit is extracted from the input tdata vector and moved to the current invalid position. The original higher-order bit (bit K+2) valid flag value is moved to bit K+1, and the original bit K+2 is cleared; simultaneously, the original higher-order bit (bit K+2) data unit is moved to bit K+1, and the original higher-order data unit position is set to invalid (usually filled with 0).

[0024] The final valid flag vector tstrb_in is formed and input to the next shift processing unit: tstrb_in = {1'b0, tstrb[K+2], tstrb[K: 1]}. Here, the (K+2)th bit is cleared, so the new highest bit is 0. The (K+1)th bit takes the valid flag value of the original highest bit, while the lower bits remain unchanged. The shifted data vector is {0, the original highest bit data unit, the original lower K data units}. This operation shifts the higher-order valid data one bit to the right, leaving the original high-order bits empty.

[0025] 2.2 Intermediate shift processing unit (index value decreases from K-1 to 1) The processing logic of the intermediate-level shift processing unit is as follows: Each intermediate-level shift processing unit (index i) receives the output of the register of the previous intermediate-level shift processing unit (index i+1). At each rising edge of the clock, the tvalid signal of the previous intermediate-level shift processing unit is first passed to this unit. Then, the (i+1)th bit in the tstrb vector of the previous intermediate-level shift processing unit is checked.

[0026] If the bit is 1, it means that there is already valid data at the current position, and the tstrb vector and tdata vector output by the previous intermediate shift processing unit are directly stored into the register of this level.

[0027] If the bit is 0, it means the current position is invalid, and a data unit needs to be borrowed from the next higher bit (the (i+2)th bit) and shifted to the right to fill the gap. The specific operation is as follows: When the value at position i+1 in the valid flag vector is invalid, all valid flags from position i+2 to the highest position in the previous level tstrb are shifted one position to the right, and the highest position (position K+2) is automatically filled with zero; that is, the new tstrb vector is equal to {1'b0, previous level tstrb[K+2 : i+2], previous level tstrb[i:1]}. It can be seen that the high-order part of the previous level tstrb (position K+2 to position i+2) is shifted one position to the right as a whole, and it is located at position K+1 to position i+1 in the new vector. The highest position is cleared to zero, and the low-order positions remain unchanged. The new tdata vector is similar. After shifting and filling to the right level by level, all valid data gradually accumulates to the right; each level only shifts the adjacent higher-order data one position to the right, and valid data is not copied. 3. Output Unit The output unit no longer sets intermediate registers, but directly performs a final adjustment based on the output of the last shift processing unit (index 1). At the rising edge of the clock, the tvalid signal (index 1) is directly output as the data valid signal. Then, the least significant bit (bit 1) in the tstrb vector (index 1) is checked. If this bit is 1, it means the least significant bit already has valid data, and no further shifting is needed; the tstrb vector and tdata vector output by the last shift processing unit are directly output. If this bit is 0, it means the least significant bit is still empty, and the entire vector needs to be shifted one bit to the right, i.e., the least significant bit is discarded, and the data in the high K+1 bits is shifted one bit to the right, while the original highest bit is cleared. At this point, the valid flag vector m_axis_tstrb in the final output data of the output unit is {1'b0, tstrb[K+2 : 2]}, meaning the original high K+1 bits are shifted one bit to the right, and the high bits are filled with 0. Similarly, the output data vector m_axis_tdata = {0, the high (K+1)*DATA_WIDTH bits of tdata output from the shift processing unit at index 1}. Finally, the lower bits of the output data are consecutively arranged with all valid data, and the lower bits of the valid flag vector are consecutively 1, while the higher bits are 0.

[0028] 4. Delay Unit The delay unit is used to delay the input data packet end-of-processing (tlast) signal through the shift register chain. The number of stages in the shift register chain is K+1, which matches the total number of pipeline stages of K shift processing units plus the output register stage of the output unit, ensuring that the data packet end-of-processing (tlast) signal is output synchronously with the packetized data.

[0029] The shift register chain delays the packet end marker by a fixed period. The input tlast signal is delayed by a shift register chain with a delay of K+1 clock cycles (i.e., the number of stages in the shift register chain is the number of shift processing unit stages + 1). The number of stages in this delay chain is consistent with the number of all pipeline stages in the data compression network, ensuring that tlast and the corresponding compressed data appear simultaneously at the output port. The input tlast signal is delayed by K+1 clock cycles before output to ensure synchronization with the compressed data. The entire device does not contain an external controller and does not store historical residual data.

[0030] The following corresponds to a scenario in FPGA where the algorithm outputs sparse data. For example, after ReLU, the activation values ​​of a neural network generate a large number of zero values, requiring the non-zero data to be compactly packaged before being passed to subsequent modules. A specific data example is used for illustration; assuming parallel input of 4 data streams (equivalent to K=2), the data vector includes 4 data units. A two-stage shift processing unit is constructed, with indices 2 and 1 respectively. Each data unit has a bit width of 8 bits, for a total input data width of 32 bits. The valid flag bit vector tstrb is 4 bits. The bit definition of the input tstrb: the 4th bit corresponds to the most significant bit data unit, and the 1st bit corresponds to the least significant bit data unit. The complete processing is as follows: 1) Initial input (clock cycle 0): 1. The data vector tdata = {D4, D3, D2, D1}, where each data unit is 8 bits, and D4 is the most significant bit. Assume that D4 and D2 are non-zero valid data, and D3 and D1 are zero-valued invalid data.

[0031] 2. The valid flag bit vector tstrb = 4'b1010 indicates that the 4th data channel D4 is valid, the 3rd data channel D3 is invalid, the 2nd data channel D2 is valid, and the 1st data channel D1 is invalid.

[0032] 3. Input data valid signal tvalid = 1.

[0033] 4. The packet end flag signal tlast = 0 (assuming the current packet is not the end of the packet).

[0034] 2) In the shift processing unit with index 2: This level receives the raw input. The tvalid register is set to 1. The third bit of tstrb is checked; it is 0, indicating the current position is invalid (note: the fourth bit is 1, meaning the highest bit contains valid data D4, which can be borrowed to the right to fill the gap). Therefore, a right shift operation is performed: a data unit is borrowed from the next higher bit (the fourth bit), and this data unit is moved to the current third bit position. Simultaneously, the original fourth bit position becomes invalid (its validity flag is cleared, and the data is cleared).

[0035] The new tstrb vector is constructed as follows: the valid flag of the original highest bit (the 4th bit) is cleared to zero, the original 3rd bit is covered by the valid flag 1 of the original 4th bit, and the lower bits (the 2nd bit and the 1st bit) remain unchanged. That is, the new vector is "{1'b0, tstrb[4], tstrb[2],tstrb[1]}" = {0, 1, 1, 0} = 4'b0110.

[0036] The new tdata vector is constructed as follows: the original highest-order data unit D4 is moved to the 3rd position, the original highest-order position is filled with invalid data (usually 0), and the lower-order bits (D2, D1) remain unchanged. That is, the new vector is "{8'h00, D4, D2, D1}" = {0, D4, D2, D1}. The above operation shifts the valid data D4 one position to the right, filling the original invalid 3rd position, while simultaneously clearing the original 4th position.

[0037] 3) In the shift processing unit with index 1: This level receives the output of the shift processing unit register at index 2: tstrb2 = 4'b0110, tdata2 = {0, D4, D2, D1}. Checking the second bit of the previous level's 4'b0110, it is 1, indicating that valid data (D2) already exists at the current position. Therefore, a pass-through operation is performed: this level's register directly stores the entire contents of the shift processing unit register at index 2, i.e., tstrb1 = 4'b0110, tdata1 = {0, D4, D2, D1}.

[0038] 4) Output unit processing: The output of the shift processing unit register with index 1 is received: tstrb1 = 4'b0110, tdata1 = {0, D4, D2, D1}. The least significant bit (bit 1) is checked and found to be 0. Therefore, the final right shift is performed. The new tstrb is equal to the high 3 bits of tstrb1 shifted right by one bit, that is, the original 4th, 3rd, and 2nd bits (0, 1, 1) become the 3rd, 2nd, and 1st bits of the new vector, and the highest bit (4th bit) is filled with 0. This results in 4'b0011 (binary 0011).

[0039] The new tdata is equal to the high 24 bits (3 data units) of tdata1 shifted right by 8 bits. That is, the original 4th, 3rd, and 2nd bits (0, D4, D2) become the 3rd, 2nd, and 1st bits of the new vector, with the highest bit padded with 0. The final output data is {0, 0, D4, D2}.

[0040] Final output: The valid flag bit vector m_axis_tstrb = 4'b0011 indicates that the lower 2 bits are valid and the higher 2 bits are invalid.

[0041] The data vector m_axis_tdata = {0, 0, D4, D2} means that the valid data D2 and D4 are compactly arranged in the lower 16 bits of the output data, with D2 in the lower position (lower 8 bits) and D4 in the higher 8 bits. This is consistent with the original order of the data units in the input (D2 is below D4 in the input, and this relative order is maintained after packing).

[0042] To ensure alignment of the compressed data, the end-of-data packet flag signal tlast passes through a shift register chain delayed by 3 clock cycles, with tlast outputting as 0 in cycle 3. If the input tlast is 1 in any cycle, it is output after a 3-cycle delay, aligning with the compressed data.

[0043] This embodiment also features continuous processing capability. During clock cycle 1, new input data can enter the first shift processing unit, while data from the previous clock cycle is being pipelined in the second-stage shift processing unit. Therefore, this device can operate continuously at a throughput of one data packet per cycle, without data bubble insertion.

[0044] As demonstrated by the above implementation examples, the method and apparatus of this invention can continuously process input data in a pipeline manner and output compactly packaged results after a fixed delay. Throughout the process, no barrel shifters, FIFOs, or external controllers are used, and no historical residual data is stored, achieving excellent performance with low resources, simple control, statelessness, and fixed delay. When implemented in an FPGA, this device can be placed at the output of an algorithm accelerator to perform real-time compact packaging of sparse computation results, thereby reducing the bandwidth requirements for subsequent storage or transmission.

[0045] It is understood that this embodiment employs a self-driven, stateless pipelined shift mechanism: each shift network stage determines whether data needs to be borrowed from higher bits solely based on a specific location (i.e., the corresponding index bit) in the tstrb vector received at that stage. The entire device requires no external controller or shift calculation unit, nor does it need to store any historical residual data (stateless). This mechanism is the core feature that distinguishes this invention from existing barrel shifter schemes; its fundamental difference lies in being self-driven without relying on an external controller, and stateless without storing historical residual data.

[0046] This design employs a K-stage cascaded shift register network topology, where each stage performs a check for a specific bit and then selects between a pass-through or a right shift by one bit. After a fixed number of stages, all valid data is naturally compressed to the least significant bit. This topology is both systematic and scalable, and can be flexibly configured via the parameter K (corresponding to the number of parallel data paths K+2) and the bit width DATA_WIDTH for each data path. Compared to barrel shifter networks, this structure uses sequential logic registers to pass data stage by stage, resulting in extremely short combinational logic paths.

[0047] The synchronization delay chain of the tlast signal, independent of the data path, delays the input tlast signal by the same number of stages as the data compression before outputting it, ensuring that the packet end marker is aligned with the compressed data. This design ensures that the invention can be seamlessly integrated into streaming systems with packet structures. Least significant bit checking and final right shift in the output stage: An output stage is added after the last stage, and the least significant bit of tstrb is checked to determine whether to perform a final right shift. This step ensures that final compression can be completed even when the least significant bit is still invalid, making the least significant bits of the output tstrb strictly continuous with 1s.

[0048] Example 2 like Figure 2 As shown, this embodiment provides a self-driven stateless pipeline data compact packaging method applied to the device in Embodiment 1 above, specifically including the following steps: S1. Receive the initial input data valid signal, valid flag bit vector and data vector, the data vector includes K+2 data units; S2. Construct K cascaded shift processing units. Starting from the (K+1)th position of the valid flag bit vector, check the validity of the corresponding position in the valid flag bit vector from the high bit to the low bit, and selectively perform shift operations on the valid flag bit vector and the data vector. Each valid flag bit in the valid flag bit vector indicates the validity of the corresponding data unit. The bit indices of the data unit and the valid flag bits range from 1 to K+2, with the K+2th bit being the most significant bit and the 1st bit being the least significant bit. K shift processing units are concatenated in order of decreasing bit indices from K to 1, where i is an integer from 1 to K. The i-th shift processing unit checks the validity of the (i+1)-th bit in the received valid flag bit vector. The specific process of step S2 is as follows: If the (i+1)th bit is valid, the received valid flag vector and data vector are passed directly to the next shift processing unit. If the (i+1)th bit is invalid, all data from the (i+2)th bit to the most significant bit are shifted one bit to the right, and the most significant bit is automatically padded with zeros. The position of the valid flag in the valid flag bit vector is shifted to the lower bit, and the valid data unit corresponding to the valid flag in the data vector is also shifted to the lower bit.

[0049] S3. Based on the validity of the least significant bit of the valid flag vector output by the last shift processing unit, selectively shift the valid flag vector and the data vector output by the last shift processing unit, so that all valid data units in the data vector are compactly arranged in the least significant bit of the data vector, thereby outputting the packaged data.

[0050] Specifically, the process of step S3 is as follows: At the rising edge of the clock, the valid data signal output by the last shift processing unit is directly used as the output, and then the validity of the least significant bit of the valid flag vector output by the last shift processing unit is checked. If the least significant bit is valid, then the valid flag vector and data vector output from the last shift processing unit are directly output. If the least significant bit is invalid, the valid flag vector and data vector output by the last shift processing unit are shifted one bit to the right of the least significant bit, and the most significant bit of the valid flag vector and data vector output by the last shift processing unit is cleared to zero.

[0051] It is understandable that the apparatus and method of this application can significantly reduce resource consumption. When the parallel data is 8 bits and the data width of each channel is 8 bits (i.e., K=6), the data vector registers (tdata part) of each shift processing unit in this application have 8*8*6=384 flip-flops. Together with the valid flag vector registers (tstrb, 48 in total, 8 bits per stage), valid flag registers (6), output units, delay units, etc., the total number of registers is approximately 520. In contrast, the barrel shifter scheme requires a large number of combinational logic multiplexers, and the resource gap widens further as the number of channels increases. This is particularly advantageous for resource-constrained FPGA designs.

[0052] This application eliminates the need for an external controller to calculate shift amounts or record residual data lengths. Shift decisions are entirely self-driven by the accompanying data's tstrb vector—each stage only needs to check a specific position in the tstrb received at its current level to determine whether to pass through or shift. This self-driven mechanism makes the device's control logic virtually zero, avoiding timing convergence issues and design complexity associated with controllers. Furthermore, this application's compatibility with streaming interface protocols allows it to be directly used as a plug-and-play data packaging module.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Based on the technical essence of the present invention, any simple modifications, equivalent substitutions, and improvements made to the above embodiments within the spirit and principles of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A self-driven, stateless pipeline data compact packaging device, characterized in that, The system includes an input port, K ​​cascaded shift processing units, and an output unit. Each shift processing unit contains a valid flag register, a valid flag bit vector register, and a data vector register. The input port receives the initial input data valid signal, the valid flag bit vector, and the data vector. Starting from the Kth shift processing unit, each subsequent shift processing unit performs the following operations on each rising edge of the clock: The first shift processing unit latches the valid input data signal, and each subsequent stage latches the valid output data signal of the previous stage. Each shift processing unit checks the validity of the specified bit in the received valid flag bit vector corresponding to the current shift processing unit, selectively performs shift operations on the valid flag bit vector and the data vector, generates the valid flag bit vector and the data vector of the next shift processing unit, registers them in the valid flag bit vector register and the data vector register respectively, and passes them to the next shift processing unit. The output unit selectively shifts the valid flag vector and the data vector output by the last shift processing unit based on the validity of the least significant bit of the valid flag vector output by the last shift processing unit, so that all valid data in the data vector are compactly arranged in the least significant bit of the data vector, thereby outputting the packaged data.

2. The self-driven stateless pipeline data compact packaging device according to claim 1, characterized in that, The data vector comprises K+2 data units. Each valid flag bit in the valid flag bit vector indicates the validity of the corresponding data unit. The bit indices of the data unit and the valid flag bits range from 1 to K+2, with the K+2th bit being the most significant bit and the 1st bit being the least significant bit. K shift processing units are concatenated in descending order of bit index from K to 1, where i is an integer from 1 to K. The i-th shift processing unit checks the validity of the (i+1)-th bit in the received valid flag bit vector. If the (i+1)th bit is valid, the received valid flag vector and data vector are passed directly to the next shift processing unit. If the (i+1)th bit is invalid, all data from the (i+2)th bit to the most significant bit are shifted one bit to the right, and the most significant bit is automatically padded with zeros. The position of the valid flag in the valid flag bit vector is shifted to the lower bit, and the valid data unit corresponding to the valid flag in the data vector is also shifted to the lower bit.

3. The self-driven stateless pipeline data compact packaging device according to claim 2, characterized in that, The specific process for generating the valid flag vector and data vector for the next shift processing unit is as follows: The specified bit in the valid flag bit vector corresponding to the current shift processing unit is determined based on the bit index value i of the current shift processing unit in multiple shift processing units; Check if the value of a specified bit in the received valid flag bit vector is valid. If it is valid, output the received valid flag bit vector and data vector directly as the valid flag bit vector and data vector of the next shift processing unit. If invalid, all data higher than the specified bit will be shifted one bit to the right to remove the current hole, and the highest bit will be automatically filled with zero. This will shift the position of the valid flag in the valid flag bit vector to the lower bit, and at the same time shift the valid data unit corresponding to the valid flag in the data vector to the lower bit, generating the valid flag bit vector and data vector of the next shift processing unit.

4. The self-driven stateless pipeline data compact packaging device according to claim 2, characterized in that, The output unit performs the following operations: At the rising edge of the clock, the valid data signal output by the last shift processing unit is directly used as the output, and then the validity of the least significant bit of the valid flag vector output by the last shift processing unit is checked. If the least significant bit is valid, then the valid flag vector and data vector output from the last shift processing unit are directly output. If the least significant bit is invalid, the valid flag vector and data vector output by the last shift processing unit are shifted one bit to the right of the least significant bit, and the most significant bit of the valid flag vector and data vector output by the last shift processing unit is cleared to zero.

5. The self-driven stateless pipeline data compact packaging device according to claim 2, characterized in that, It also includes a delay unit. The input port is also used to receive the end-of-data packet flag signal. The delay unit is used to delay the input end-of-data packet flag signal through a shift register chain. The number of stages in the shift register chain is the number of stages in the shift processing unit + 1, ensuring that the end-of-data packet flag signal is output synchronously with the packetized data.

6. A method for compactly packaging self-driven stateless pipeline data, characterized in that, Specifically, the following steps are included: S1. Receive the initial input data valid signal, valid flag bit vector and data vector, the data vector includes K+2 data units; S2. Construct K cascaded shift processing units. Starting from the (K+1)th position of the valid flag bit vector, check the validity of the corresponding position in the valid flag bit vector from the high bit to the low bit, and selectively perform shift operations on the valid flag bit vector and the data vector. S3. Based on the validity of the least significant bit of the valid flag vector output by the last shift processing unit, selectively shift the valid flag vector and the data vector output by the last shift processing unit, so that all valid data units in the data vector are compactly arranged in the least significant bit of the data vector, thereby outputting the packaged data.

7. A method for compactly packaging self-driven stateless pipeline data according to claim 6, characterized in that, Each valid flag bit in the valid flag bit vector indicates the validity of the corresponding data unit. The bit indices of the data unit and the valid flag bits range from 1 to K+2, with the K+2th bit being the most significant bit and the 1st bit being the least significant bit. K shift processing units are concatenated in order of decreasing bit indices from K to 1, where i is an integer from 1 to K. The i-th shift processing unit checks the validity of the (i+1)-th bit in the received valid flag bit vector. The specific process of step S2 is as follows: If the (i+1)th bit is valid, the received valid flag vector and data vector are passed directly to the next shift processing unit. If the (i+1)th bit is invalid, all data from the (i+2)th bit to the most significant bit are shifted one bit to the right, and the most significant bit is automatically padded with zeros. The position of the valid flag in the valid flag bit vector is shifted to the lower bit, and the valid data unit corresponding to the valid flag in the data vector is also shifted to the lower bit.

8. A method for compactly packaging self-driven stateless pipeline data according to claim 6, characterized in that, The specific process of step S3 is as follows: At the rising edge of the clock, the valid data signal output by the last shift processing unit is directly used as the output, and then the validity of the least significant bit of the valid flag vector output by the last shift processing unit is checked. If the least significant bit is valid, then the valid flag vector and data vector output from the last shift processing unit are directly output. If the least significant bit is invalid, the valid flag vector and data vector output by the last shift processing unit are shifted one bit to the right of the least significant bit, and the most significant bit of the valid flag vector and data vector output by the last shift processing unit is cleared to zero.

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