A data synchronization method for dual-core heterogeneous communication

Abstract

The application discloses a kind of data synchronization methods of dual-core heterogeneous communication, belong to heterogeneous multicore processor communication technical field;The application designs Cache consistency strategy of dual-core heterogeneous architecture adaptation, through the operation of cache configuration or cache refresh, invalidation, completely solve the problem that heterogeneous core local cache and physical memory data are inconsistent, abandon the multi-layer redundant processing of traditional message protocol stack, greatly reduce data synchronization delay, effectively meet the real-time application scenario demand;The application adopts dynamic grading check strategy based on channel quality, combines data fragmentation, serial number and timeliness double-checking mechanism, can adjust check strength and transmission granularity according to channel interference degree, effectively avoid data transmission error, fragmentation disorder, expired data synchronization and other problems, greatly improve the integrity and accuracy of heterogeneous dual-core data synchronization.

Description

Technical Field

[0001] This invention belongs to the field of heterogeneous multi-core processor communication technology, specifically a data synchronization method for dual-core heterogeneous communication. Background Technology

[0002] With the rapid development of embedded systems and system-on-a-chip technologies, heterogeneous multi-core processor architecture has become an important technical approach to improve overall system performance. In heterogeneous multi-core processors, cores with different instruction set architectures work together to fully leverage the performance advantages of each core and meet the computing needs of complex application scenarios.

[0003] In heterogeneous multi-core processors, data synchronization between cores is a crucial step in achieving collaborative operation. Current technologies primarily employ the following solutions for data synchronization between heterogeneous cores: The first approach is a synchronization method based on a message passing interface. This approach enables data exchange between heterogeneous cores through a message passing framework. However, this approach requires processing through multiple layers of protocol stacks, including message encapsulation, queue management, and protocol parsing, resulting in significant data synchronization delays and making it difficult to meet the real-time requirements of application scenarios.

[0004] The second approach is a synchronization method based on a shared bus protocol. This approach enables data sharing between heterogeneous cores through the bus protocol. However, due to the differences in how cores with different instruction set architectures parse the bus protocol, problems such as byte order conversion errors and address alignment anomalies can easily occur during data parsing, leading to reduced synchronization reliability.

[0005] The third approach is a shared memory-based synchronization method, which achieves data exchange by dividing shared memory regions. However, existing shared memory solutions do not fully consider the cache consistency problem between heterogeneous cores. Data written to shared memory by the main core may be cached in the local cache, and when the core reads data, it still retrieves the old data from physical memory, resulting in data inconsistency. In addition, existing solutions lack effective data integrity verification mechanisms and exception handling mechanisms, and cannot correct data transmission errors in a timely manner, affecting system stability.

[0006] Therefore, there is an urgent need for a data synchronization method suitable for dual-core heterogeneous environments that can reduce synchronization latency while ensuring the integrity, reliability, and consistency of data synchronization.

[0007] Based on this, a data synchronization method for dual-core heterogeneous communication is designed. Summary of the Invention

[0008] In view of the above situation and to overcome the shortcomings of the prior art, the present invention provides a data synchronization method for dual-core heterogeneous communication, which effectively solves the problems mentioned in the background art.

[0009] To achieve the above objectives, the present invention provides the following technical solution: a data synchronization method for dual-core heterogeneous communication, comprising the following steps: S1. Initialize the dual-core heterogeneous communication environment, establish a shared memory mapping between the master core and the slave core, and configure the cache consistency strategy between the master core and the slave core. The shared memory mapping includes a write buffer, a read buffer, a flag register group, and a status synchronization register. S2. The main core obtains the data to be synchronized, encapsulates the data to be synchronized into a data packet, determines the verification strategy according to the channel quality parameters and calculates the verification value of the data packet, executes the Cache Flush operation, and writes the data packet and the verification value into the write buffer of the shared memory. S3. The main core sets the write completion flag bit in the flag register group and triggers a heterogeneous interrupt to notify the slave core. S4. From the core response to the heterogeneous interrupt, execute the Cache Invalid operation, read the data packet and check value in the write buffer of the shared memory, calculate the check value of the read data, and compare the check value of the read data with the check value carried by the data packet; S5. If the comparison result is consistent, the data packet is written from the core to the core local storage, the read completion flag bit in the flag register group is set, the heterogeneous interrupt is cleared, and the status synchronization register is updated to the synchronization completion status. S6. If the comparison result is inconsistent, a retransmission request is sent from the core to the main core. After receiving the retransmission request, the main core increments the count value of the retransmission counter by one and determines whether the count value has reached the preset retransmission threshold. S7. If the count value does not reach the preset retransmission threshold, the main core will re-execute step S2. S8. If the count value reaches the preset retransmission threshold, the main core triggers the exception handling process and updates the status synchronization register to the synchronization failure state.

[0010] Preferably, the cache consistency strategy configured between the primary and secondary cores in step S1 includes: Configure the physical address range corresponding to the shared memory mapping as non-cacheable, so that the master core and slave core can access the physical memory directly without their respective data caches when accessing the shared memory; Alternatively, configure the physical address range corresponding to the shared memory mapping as cacheable, perform a cache flush operation after the main core writes to the write buffer in step S2, and perform a cache invalid operation before reading the write buffer from the core in step S4.

[0011] Preferably, the determination of the verification strategy based on the channel quality parameters in step S2 includes: Calculate the data synchronization error rate within a preset time window; If the data synchronization error rate is lower than the first threshold, the first verification algorithm is used to calculate the verification value. If the data synchronization error rate is higher than or equal to the first threshold and lower than the second threshold, then the second verification algorithm is used to calculate the verification value, and the verification strength of the second verification algorithm is higher than that of the first verification algorithm. If the data synchronization error rate is higher than or equal to the second threshold, a third verification algorithm is used to calculate the verification value. The verification strength of the third verification algorithm is higher than that of the second verification algorithm, and the data fragment size of the data packet is reduced.

[0012] Preferably, the encapsulation of the data to be synchronized into a data packet in step S2 includes: The data to be synchronized is segmented to generate at least one data segment. The size of each data segment is determined based on the write buffer capacity of the shared memory and the verification strategy. Assign a sequence number and timestamp to each data fragment; The data fragments, the sequence number, and the timestamp are combined into the data packet.

[0013] Preferably, after reading the data packet from the core in step S4, the method further includes: The continuity of data fragments is verified from the core based on the sequence number; The timeliness of data fragments is verified from the core based on the timestamp. If the continuity check or the timeliness check fails, proceed to step S6.

[0014] Preferably, the triggering of the heterogeneous interrupt to notify the kernel in step S3 includes: The main core writes an interrupt trigger instruction to the first interrupt controller; The first interrupt controller sends an interrupt signal to the second interrupt controller through a heterogeneous interrupt channel; After receiving the interrupt signal, the second interrupt controller sends an interrupt request to the slave core processor; The main core starts a timeout timer. If it does not receive a read completion flag or retransmission request from the slave core within the preset timeout period, the main core will re-execute step S3.

[0015] Preferably, the step S6 of sending a retransmission request from the core to the main core includes: The retransmission request information is written from the core to the read buffer of the shared memory; Set the retransmission request flag bit in the flag register group from the core; A reverse heterogeneous interrupt is triggered from the core to notify the main core; The main core responds to the reverse heterogeneous interrupt, reads the retransmission request information in the read buffer, and executes step S2.

[0016] Preferably, the exception handling process in step S8 includes: The main core updates the state synchronization register to a synchronization failure state; The main core writes error codes to the flag register set; The main core triggers an error reporting interrupt to notify the upper-layer application; The main core resets the retransmission counter to zero.

[0017] Preferably, it also includes a flow control step: Before writing to the write buffer, the main core checks the remaining space in the write buffer; If the remaining space is less than the size of the data packet, the main core waits to read data from the core and release the space before performing the write operation; The main core dynamically adjusts the data fragment size based on the remaining space in the write buffer.

[0018] Preferably, the main core and the slave core are processor cores with different instruction set architectures.

[0019] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention is designed with a cache consistency strategy adapted to dual-core heterogeneous architecture. By enabling non-cache configuration or cache refresh and invalidation operations, it completely solves the problem of data inconsistency between local cache and physical memory in heterogeneous cores. It abandons the multi-layered redundant processing of traditional message protocol stacks, greatly reduces data synchronization latency, and effectively meets the needs of real-time application scenarios. 2. This invention adopts a dynamic hierarchical verification strategy based on channel quality, combined with a dual verification mechanism of data fragmentation, sequence number and timeliness. It can adaptively adjust the verification strength and transmission granularity according to the degree of channel interference, effectively avoiding problems such as data transmission errors, fragmentation disorder and expired data synchronization, and greatly improving the integrity and accuracy of heterogeneous dual-core data synchronization. 3. This invention has a complete retransmission error correction, timeout retransmission and anomaly handling mechanism. It achieves fault-tolerant transmission by retransmission threshold determination, and achieves anomaly traceability by fault reporting and status marking. At the same time, it is equipped with a buffer flow control mechanism to avoid buffer overflow and transmission deadlock, thus comprehensively improving the system's synchronization stability and anti-interference capability. 4. This invention is adaptable to dual-core heterogeneous scenarios with any instruction set architecture, has strong hardware adaptability, simple process and low overhead, and can be widely used in various scenarios such as embedded heterogeneous computing, industrial control, and smart devices, making it highly practical. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0021] In the attached diagram: Figure 1 This is a flowchart illustrating the overall process of dual-core heterogeneous communication data synchronization in this invention. Figure 2 This is a flowchart illustrating the cache consistency strategy configuration and data read / write processing of this invention. Figure 3 This is a flowchart of the dynamic verification, flow control, and abnormal retransmission processing of the present invention; Detailed Implementation

[0022] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0023] Depend on Figures 1-3 The present invention relates to a data synchronization method for dual-core heterogeneous communication, comprising the following steps: S1. Upon system power-up, initialize the dual-core heterogeneous communication environment and establish a shared memory mapping area for the master and slave cores. This area includes a write buffer, a read buffer, a flag register group, and a status synchronization register. Configure a cache consistency strategy according to the hardware architecture. If minimal operating overhead is desired, configure the shared memory physical address range as non-cacheable, allowing the dual cores to directly access physical memory. If cache access efficiency needs to be considered, configure it as cacheable and preset subsequent read and write cache operation rules.

[0024] S2. The main core collects local data to be synchronized, dynamically segments the data based on the write buffer capacity and preset verification strategy, assigns a unique sequence number and timestamp to each data segment, and combines them to generate a complete data packet; it calculates the data synchronization error rate within the recent preset time window, matches the corresponding first-level, second-level, and third-level verification algorithms according to the error rate threshold, and calculates the data packet verification value; the main core executes a Cache Flush operation to synchronously write the data packet and verification value to the shared memory write buffer.

[0025] S3. After the main core completes the data writing, it sets the write completion flag bit of the flag register group, sends an interrupt trigger instruction to the first interrupt controller, completes the two-level interrupt controller signal transmission through the heterogeneous interrupt channel, and finally sends an interrupt request to the slave core; at the same time, it starts the timeout timer. If no feedback is received from the slave core within the preset timeout period, the interrupt is re-triggered to avoid communication interruption loss.

[0026] S4. After detecting a heterogeneous interrupt request from the core, respond to the interrupt, prioritize the Cache Invalid operation, clear the old data in the local cache, and read the data packet and corresponding check value in the write buffer; recalculate the check value of the read data from the core, complete the check value comparison, and at the same time check the continuity of data fragments according to the sequence number and the timeliness of data fragments according to the timestamp.

[0027] S5. If the checksum is consistent and the fragmentation continuity and timeliness are verified, the data synchronization is determined to be valid. The data packet is stored from the core to the local storage space, the read completion flag is set, the current heterogeneous interrupt is cleared, the status synchronization register is updated to the synchronization completion status, and this round of data synchronization ends.

[0028] S6. If the checksum is inconsistent or the fragment verification fails, a retransmission request message is generated from the core, written to the shared memory read buffer, the retransmission request flag is set, and a reverse heterogeneous interrupt is triggered to notify the main core. The main core responds to the reverse interrupt, reads the retransmission request message, increments the retransmission counter value by one, and compares the current count value with the preset retransmission threshold.

[0029] S7. If the number of retransmissions does not reach the threshold, the main core will repeatedly execute the data encapsulation, verification, writing, and interrupt triggering process to complete the data retransmission.

[0030] S8. If the number of retransmissions reaches the preset threshold, the current channel is determined to be abnormal or the data transmission is faulty. The main core triggers the abnormal handling process: update the status register to synchronization failure, write the corresponding fault error code, trigger an interrupt to report the fault information to the upper layer application, and at the same time reset the retransmission counter and wait for the next round of synchronization instructions.

[0031] S9. Full-process flow control logic: Before each data write, the main core checks the remaining space in the write buffer. If the remaining space is insufficient, it waits to read the space from the core to release it. At the same time, it dynamically adjusts the data fragment size according to the free capacity of the buffer to avoid buffer overflow and data overwriting issues.

[0032] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0033] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A data synchronization method for dual-core heterogeneous communication, characterized in that, Includes the following steps: S1. Initialize the dual-core heterogeneous communication environment, establish a shared memory mapping between the master core and the slave core, and configure the cache consistency strategy between the master core and the slave core. The shared memory mapping includes a write buffer, a read buffer, a flag register group, and a status synchronization register. S2. The main core obtains the data to be synchronized, encapsulates the data to be synchronized into a data packet, determines the verification strategy according to the channel quality parameters and calculates the verification value of the data packet, executes the Cache Flush operation, and writes the data packet and the verification value into the write buffer of the shared memory. S3. The main core sets the write completion flag bit in the flag register group and triggers a heterogeneous interrupt to notify the slave core. S4. From the core response to the heterogeneous interrupt, execute the Cache Invalid operation, read the data packet and check value in the write buffer of the shared memory, calculate the check value of the read data, and compare the check value of the read data with the check value carried by the data packet; S5. If the comparison result is consistent, the data packet is written from the core to the core local storage, the read completion flag bit in the flag register group is set, the heterogeneous interrupt is cleared, and the status synchronization register is updated to the synchronization completion status. S6. If the comparison result is inconsistent, a retransmission request is sent from the core to the main core. After receiving the retransmission request, the main core increments the count value of the retransmission counter by one and determines whether the count value has reached the preset retransmission threshold. S7. If the count value does not reach the preset retransmission threshold, the main core will re-execute step S2. S8. If the count value reaches the preset retransmission threshold, the main core triggers the exception handling process and updates the status synchronization register to the synchronization failure state.

2. The data synchronization method for dual-core heterogeneous communication according to claim 1, characterized in that, The cache consistency strategy configured between the primary and secondary cores in step S1 includes: Configure the physical address range corresponding to the shared memory mapping as non-cacheable, so that the master core and slave core can access the physical memory directly without their respective data caches when accessing the shared memory; Alternatively, configure the physical address range corresponding to the shared memory mapping as cacheable, perform a cache flush operation after the main core writes to the write buffer in step S2, and perform a cache invalid operation before reading the write buffer from the core in step S4.

3. The data synchronization method for dual-core heterogeneous communication according to claim 1, characterized in that, The step S2, which involves determining the verification strategy based on channel quality parameters, includes: Calculate the data synchronization error rate within a preset time window; If the data synchronization error rate is lower than the first threshold, the first verification algorithm is used to calculate the verification value. If the data synchronization error rate is higher than or equal to the first threshold and lower than the second threshold, then the second verification algorithm is used to calculate the verification value, and the verification strength of the second verification algorithm is higher than that of the first verification algorithm. If the data synchronization error rate is higher than or equal to the second threshold, a third verification algorithm is used to calculate the verification value. The verification strength of the third verification algorithm is higher than that of the second verification algorithm, and the data fragment size of the data packet is reduced.

4. The data synchronization method for dual-core heterogeneous communication according to claim 1, characterized in that, Step S2, which involves encapsulating the data to be synchronized into a data packet, includes: The data to be synchronized is segmented to generate at least one data segment. The size of each data segment is determined based on the write buffer capacity of the shared memory and the verification strategy. Assign a sequence number and timestamp to each data fragment; The data fragments, the sequence number, and the timestamp are combined into the data packet.

5. The data synchronization method for dual-core heterogeneous communication according to claim 4, characterized in that, After reading the data packet from the core in step S4, the process also includes: The continuity of data fragments is verified from the core based on the sequence number; The timeliness of data fragments is verified from the core based on the timestamp. If the continuity check or the timeliness check fails, proceed to step S6.

6. The data synchronization method for dual-core heterogeneous communication according to claim 1, characterized in that, The step S3 of triggering a heterogeneous interrupt to notify the kernel includes: The main core writes an interrupt trigger instruction to the first interrupt controller; The first interrupt controller sends an interrupt signal to the second interrupt controller through a heterogeneous interrupt channel; After receiving the interrupt signal, the second interrupt controller sends an interrupt request to the slave core processor; The main core starts a timeout timer. If it does not receive a read completion flag or retransmission request from the slave core within the preset timeout period, the main core will re-execute step S3.

7. The data synchronization method for dual-core heterogeneous communication according to claim 1, characterized in that, The step S6, which involves sending a retransmission request from the core to the main core, includes: The retransmission request information is written from the core to the read buffer of the shared memory; Set the retransmission request flag bit in the flag register group from the core; A reverse heterogeneous interrupt is triggered from the core to notify the main core; The main core responds to the reverse heterogeneous interrupt, reads the retransmission request information in the read buffer, and executes step S2.

8. The data synchronization method for dual-core heterogeneous communication according to claim 1, characterized in that, The exception handling process described in step S8 includes: The main core updates the state synchronization register to a synchronization failure state; The main core writes error codes to the flag register set; The main core triggers an error reporting interrupt to notify the upper-layer application; The main core resets the retransmission counter to zero.

9. The data synchronization method for dual-core heterogeneous communication according to claim 1, characterized in that, It also includes flow control steps: Before writing to the write buffer, the main core checks the remaining space in the write buffer; If the remaining space is less than the size of the data packet, the main core waits to read data from the core and release the space before performing the write operation; The main core dynamically adjusts the data fragment size based on the remaining space in the write buffer.

10. A data synchronization method for dual-core heterogeneous communication according to any one of claims 1-9, characterized in that, The main core and the slave core are processor cores with different instruction set architectures.

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