Global adaptation processor architecture based on root primitive native operations

Abstract

The application discloses a global adaptive processor architecture based on Chinese character root original operation and belongs to the technical field of novel autonomous general processor architecture and computing power system. The existing processor and supercomputer cluster adopt binary von Neumann architecture, and there are generally the industry pain points of separation of storage and calculation, large data carrying capacity, complicated network protocol level, high power consumption and dependence of computing power improvement on chip stacking, and there are long-term large invalid energy consumption and link redundancy. The application discloses a novel hardware architecture of storage and calculation integration, unified addressing and direct communication, which discards the traditional binary operation logic, takes Chinese character root as a unified operation, storage and addressing unit, and constructs the novel hardware architecture. The application cancels the redundant links of binary translation, multi-layer protocol forwarding, independent file system data scheduling and the like, and greatly reduces the operation and communication overhead of the equipment. The architecture supports elastic trimming and can be integrally adapted to Internet of Things terminals, industrial edge devices and cloud supercomputer cluster full scenes. Compared with the traditional computing power scheme, the application has simpler structure, extremely low energy consumption and greatly improved computing power utilization rate, completely gets rid of the traditional chip stacking efficiency improvement mode and external instruction set dependence, realizes complete autonomous control of the underlying computing power architecture, and has high engineering practical value and industrialization popularization prospect.

Description

Technical Field

[0001] This invention belongs to the fields of general-purpose processor architecture, artificial intelligence computing power, Internet of Things communication, and in-memory computing chip technology. Specifically, it relates to a flexible and adaptable processor architecture that abandons the traditional binary von Neumann architecture, is based on native Chinese character root operations, and features unified addressing across the entire domain. It can be widely adapted to all levels of scenarios, including IoT terminals, industrial edge devices, and cloud supercomputing clusters. It is suitable for core technology scenarios such as domestically developed computing power bases, HarmonyOS unified interconnection, smart cities, industrial internet, and supercomputing centers. Background Technology

[0002] Existing commercial general-purpose processors, AI computing processors, and supercomputing cluster systems are all based on the traditional binary von Neumann architecture. Their core operates on a storage-compute separation model, requiring data to be repeatedly moved, packaged, parsed, and translated between registers, caches, memory, and external storage devices via the system bus. In deep learning operations, large-scale cluster collaboration, and cross-device data interaction scenarios, the energy consumption from data movement and protocol conversion accounts for 70%–95% of the overall system energy consumption, while effective computing energy consumption accounts for only 5%–30%. This inherent redundancy in the architecture results in significant losses and presents an insurmountable underlying efficiency bottleneck.

[0003] Currently, the mainstream domestic computing power system is represented by the Kunpeng and Ascend heterogeneous computing power clusters. Among them, the Kunpeng 920 processor is developed based on the ARMv8 architecture and relies on external instruction set licenses, which are subject to external constraints at both the technical and commercial levels. The Ascend 910 AI processor is based on the Da Vinci binary architecture, with a typical single-chip power consumption of up to 310W. The "CPU+NPU" heterogeneous system composed of these two is the core hardware foundation of the Pengcheng Cloud Brain supercomputing cluster. Pengcheng Cloud Brain II is equipped with 4,096 Ascend 910 chips, and Pengcheng Cloud Brain III expands to more than 20,000 AI chips. Through massive chip stacking, bandwidth optimization, and storage system iteration, it has achieved a breakthrough in computing power scale, with a peak computing power of up to 16,000P, representing the highest level of domestic binary computing power engineering application.

[0004] However, this type of traditional computing power system is a quantitative optimization within a binary framework, and has several inherent technical defects that cannot be eliminated through engineering optimization: First, the improvement of computing power depends entirely on the stacking of hardware chips. The scale of computing power is strongly tied to the number of hardware and power consumption costs. The energy consumption of supercomputing clusters reaches the city level, making it impossible to extend to terminal and edge lightweight scenarios. Second, the system is highly dependent on dedicated independent file systems such as SuperFS and MadFS to achieve data layered scheduling. Operational parameters, intermediate caches, and model data need to be continuously transferred and transferred across units. The storage-computing separation architecture makes it impossible to eliminate redundant overhead. Third, cross-device and cross-node interactions are based on the TCP / IP seven-layer protocol stack throughout the process. It requires multi-level gateway routing, data encapsulation and decapsulation, and protocol parsing and verification. The link layers are complex and the communication loss is extremely high. Fourth, the ARM architecture instruction set has external dependencies, and the underlying computing power system cannot achieve complete independent control.

[0005] In summary, existing binary processors and supercomputing cluster systems are still limited to the century-old traditional computing framework, and cannot fundamentally solve the industry pain points of computing power redundancy, high energy consumption, interconnection fragmentation, and insufficient autonomy. There is an urgent need for a new paradigm of processor architecture to break through traditional technical barriers and build a new generation of computing power foundation that is full-scenario, low-energy, highly autonomous, and without redundancy. Summary of the Invention

[0006] To address the technical shortcomings of existing binary von Neumann architecture computing systems, such as storage-computation separation, protocol redundancy, high energy consumption, poor scenario adaptability, and insufficient autonomy, this invention provides a fully adaptable processor architecture based on native word root operations. It completely abandons the dependence on binary operation logic and external instruction sets, reconstructs the three underlying technology systems of computing, storage, and communication, and achieves end-to-end computing power simplification, ultra-low energy consumption, direct connection to all devices, and flexible adaptation to all scenarios, filling the technical gap in the next generation of autonomous computing paradigms.

[0007] This invention breaks away from traditional bit-based binary arithmetic logic, pioneering a native computing system that uses Chinese character roots as the smallest operational, storage, and addressing units. It is paired with a self-developed Chinese character root-based native operating system (YiAn OS), achieving native matching of software and hardware instruction sets without intermediate binary translation, protocol stack redundancy, or cross-unit data transfer. The overall technical approach adopts a core solution of "single-architecture flexible tailoring, full-level homogeneous adaptation, global dictionary addressing, and integrated storage and computation parallel derivation," fundamentally reconstructing the logic of computing power operation and device interconnection.

[0008] Compared to the traditional architecture's technical path of "repeated data transfer, multi-layer protocol relay, and stacked computing power for efficiency enhancement," this invention adopts a brand-new technical path of direct transmission of character root encoding, one-time location addressing, simultaneous execution of storage and computation, and flexible kernel adaptation. This upgrades the traditional redundant iterative mode of "repeatedly transferring sand to build a building" to a highly efficient parallel mode of "precise image transmission and directional construction." The computing power utilization efficiency, energy consumption control, and interconnection speed are improved by a generation, and the overall energy efficiency ratio can reach 100 times that of the traditional architecture.

[0009] A globally adaptable processor architecture based on native radical operations is characterized by comprising: a radical operation array, a radical unified addressing bus, a direct communication interface, a parallel deduction unit, and an in-memory computing unit; the processor uses radical encoding as the sole data flow form throughout the process, eliminating the need for binary format conversion and instruction translation, and relying on a globally unified radical dictionary addressing system to achieve end-to-end protocol-free direct communication. The architecture can be flexibly scaled and expanded to cover computing power needs across all scenarios.

[0010] 1. Innovative native character root computing system: Abandoning the traditional binary bit operation logic and ARM external instruction set, it uses Chinese character roots as the native computing unit and relies on the character root parallel deduction mechanism to complete all computing tasks. It can achieve high-efficiency computing power output without the need for massive chip stacking, completely getting rid of the industry's computing power improvement mode of "stacking hardware and stacking power consumption". The single-chip computing power utilization rate far exceeds that of traditional heterogeneous processors.

[0011] 2. Innovation of the original integrated computing system: The character root has dual attributes of computing and storage. The computing unit and the storage unit are integrated into one, without the need to configure an independent file system or a massive intermediate cache. It completely eliminates 70%-95% of the ineffective energy consumption of cross-unit data reading, writing, moving and format translation in the traditional architecture, and eradicates the inherent redundancy of the storage-computing separation architecture from the source.

[0012] 3. Global radical addressing communication innovation: A standardized, globally unified radical dictionary addressing system is built. All terminals, edge devices, and cloud devices equipped with this architecture share the same radical address library, which can accurately locate the radical position of interactive devices. It completely eliminates the TCP / IP seven-layer protocol stack, multi-level routing gateways, and data encapsulation and decapsulation processes, and realizes flat direct communication between devices without communication layer loss.

[0013] 4. Integrative Hardware and Software Collaborative Innovation: The processor hardware architecture is natively adapted to the native Chinese character root operating system, with a complete instruction set match. No intermediate binary translation, multi-layer compilation, or virtual machine conversion is required. There is no adaptation redundancy across the entire input, processing, and output chain, maximizing the efficiency of hardware and software collaboration.

[0014] 5. Globally Flexible Adaptive Architecture Innovation: The core infrastructure supports stepless flexible scaling and multi-core expansion. A single architecture can be used to generate three core forms: small, medium, and large, fully covering IoT terminals, industrial edge computing, and cloud supercomputing scenarios. This solves the industry pain points of traditional chip architecture, such as single scenario, high adaptation cost, and fragmented technology.

[0015] Example 1: Small Core Terminal Architecture (Lightweight IoT Scenario) The core character root operation array is lightweighted and trimmed, retaining core functions such as basic character root operations, unified addressing, and direct communication, while drastically reducing chip size and power consumption. It is compatible with lightweight IoT terminals such as smart speakers, routers, IoT sensors, and smart home devices, and can completely replace traditional MCUs and low-end SOC chips. No complex protocol adaptation is required; devices connect and communicate instantly, effectively solving the problems of weak computing power, high latency, high power consumption, and high adaptation costs in terminal devices.

[0016] Example 2: Medium-sized core edge architecture (industrial and government scenarios) It features a balanced configuration of root word processing arrays, concurrent paths, and security verification units, enhancing multi-device collaboration, data security verification, and concurrent processing capabilities. It is compatible with edge devices such as industrial gateways, edge computing boxes, smart city nodes, and communication base stations, eliminating the need for multi-layered gateway forwarding and cross-device protocol conversion in traditional industrial equipment. This enables secure, high-speed direct connection and collaboration between industrial and government equipment, closely aligning with the Ministry of Industry and Information Technology's national industry standards for unified interconnection via open-source HarmonyOS and device security certification.

[0017] Example 3: Large-scale core-cloud architecture (supercomputing cluster scenario) Based on a basic quad-core character root computing unit, a large-scale character root parallel computing cluster is constructed through multi-level interconnection and stacking. Compared with the binary supercomputing solution of Pengcheng Cloud Brain with 4,000-level and 20,000-level chip stacks, this architecture relies on the original advantages of integrated computing and no communication redundancy. The number of chips required for the same computing power scale is greatly reduced, the overall power consumption of the cluster is reduced by orders of magnitude, and there is no need to rely on an independent storage system. It completely changes the inherent drawbacks of traditional supercomputing that "the higher the computing power, the higher the energy consumption and the higher the cost." It can fully replace the traditional CPU+GPU heterogeneous supercomputing architecture and realize a paradigm-level upgrade of domestic supercomputing.

[0018] Compared to existing binary von Neumann architecture-based Kunpeng and Ascend series processors and supercomputing clusters, this invention offers several disruptive technological advantages, achieving comprehensive breakthroughs in technical path, operational logic, and application scenarios. Specific benefits are as follows: 1. Extreme energy saving across the entire chain, and a significant improvement in computing power efficiency: This invention eliminates all redundant links such as binary format preprocessing, multi-layer protocol parsing, multi-level gateway forwarding, and cross-unit data transfer, eliminating 70%-95% of ineffective energy consumption from the source. The computing power utilization rate and computing response speed are improved by a significant margin, and the overall energy efficiency ratio reaches 100 times that of the traditional architecture, completely breaking through the energy consumption ceiling of the traditional computing power system.

[0019] 2. Universal compatibility and seamless scenario coverage: The single core architecture can be flexibly derived into three forms: lightweight, standard, and stacked, seamlessly adapting to application scenarios at all levels, including terminals, edge, and cloud. This solves the industry problems of traditional chip architectures, such as strong targeting, weak versatility, high cost of multi-scenario adaptation, and fragmented technical systems, and has extremely strong industrialization adaptation capabilities.

[0020] 3. Native hardware and software collaboration with no adaptation redundancy: The processor hardware and the root operating system instruction set are natively matched, eliminating the intermediate binary translation and multi-layered compilation adaptation process. The entire process of input, internal operation and output interaction is extremely simple, completely eliminating the computing power, time and space redundancy overhead caused by hardware and software adaptation.

[0021] 4. Completely independent at the underlying level, in line with national strategy: Completely free from the constraints of external instruction sets and technologies such as ARM architecture, relying on the independently developed character root operation, unified addressing, and direct communication system, the underlying computing power architecture is 100% independent and controllable, perfectly adapting to the national-level industrial strategy of replacing domestic independent computing power, HarmonyOS unified interconnection, and secure and controllable industrial Internet.

[0022] 5. Disrupting traditional computing power paths and reconstructing industry technology paradigms, this invention possesses exceptional uniqueness and is impossible to imitate: Existing computing power technologies all follow an additive development logic of "adding functions, stacking modules, and incremental optimization," achieving performance improvements by increasing the number of chips, optimizing protocol layers, and iterating storage systems. The industry has mature technical references and engineering workload assessment benchmarks. This invention breaks through a century-old established R&D mindset, adopting a subtractive reconstruction paradigm. It eliminates all traditionally necessary redundant links such as the binary translation layer, data transport layer, TCP / IP protocol stack, and independent file system. The core innovation challenge lies not in adding new functional modules, but in demonstrating from scratch that "after removing all redundant systems, the entire computing, storage, and communication chain remains complete, stable, and usable." This technical solution has no existing technological precedents, no mature modules that can be reused, and no traditional benchmarks to anchor it to. Those skilled in the art can only verify the self-consistency of the architectural logic and the feasibility of the technical path, but cannot assess the R&D workload and implementation path through traditional technical systems. It possesses extremely high technical uniqueness, non-obviousness, and non-replicability, completely breaking the iterative monopoly of the binary computing system and constructing the core technology foundation for next-generation general-purpose computing and the Internet of Things.

[0023] Figure 1Overall module architecture diagram of the native root processor of this invention; Figure 2 Simplified architecture diagram of a small IoT terminal; Figure 3 Standard architecture diagram for medium-sized edge industries; Figure 4 Diagram of a large-scale cloud-based multi-core stacked supercomputing architecture; Figure 5 A comparison diagram of traditional multi-level routing and forwarding links and the flattened direct-connection links of this invention.

Claims

1. A globally adaptable processor architecture based on native radical operations, characterized in that, include: The processor comprises a character root operation array, a unified character root addressing bus, a direct communication interface, a parallel deduction unit, and an integrated storage and computation unit. It uses Chinese character roots as its native operation, storage, and addressing units, employing character root encoding throughout the entire data input, computation, storage, and output process without requiring intermediate binary translation or format conversion. Relying on a globally unified character root dictionary addressing system, it achieves flat, direct communication with devices, eliminating the redundancy of multi-level TCP / IP protocol stack forwarding. The architecture is flexibly customizable and expandable with multiple cores, adapting to the computing power needs of terminals, edge computing, and cloud computing scenarios.

2. The processor architecture according to claim 1, characterized in that, The architecture can be tailored into a small core form, with a simplified root operation array, while retaining core operation and addressing functions. It is compatible with lightweight terminal devices such as smart speakers, routers, and IoT sensors, enabling ultra-low power consumption and protocol-free fast interconnection.

3. The processor architecture according to claim 1, characterized in that, The architecture can be configured as a medium-sized core, enhancing concurrent processing and security verification capabilities, and is compatible with industrial gateways, edge computing boxes, and smart city node devices, enabling high-speed and secure linkage between industrial and government equipment.

4. The processor architecture according to claim 1, characterized in that, The architecture can be expanded into a large-scale core cluster through multi-core interconnection and stacking to build a cloud-based supercomputing system. Compared with traditional binary stacked clusters, it uses fewer chips, consumes less energy, has no independent file system dependency, and has no hierarchical communication loss at the same computing power scale.

5. The processor architecture according to claim 1, characterized in that, The processor is natively adapted to the self-developed Chinese character root-based operating system with integrated hardware and software, and the instruction set is fully matched. It eliminates the need for multi-layered compilation and virtual machine conversion, thus eliminating redundant hardware and software adaptation overhead at the end of the chain.

6. The processor architecture according to claim 1, characterized in that, The in-memory computing unit relies on the dual attributes of character roots to simultaneously complete data computation and storage, completely eliminating the energy consumption of cross-unit data transfer caused by the separation of in-memory computing in the traditional von Neumann architecture.

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