A cache-based method and system for initializing RAM content
Patent Information
- Application Number
- CN202610872007.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-16
- Publication Date
- 2026-10-27
Smart Images
Figure CN122985709A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of programmable logic device technology, and in particular to a cache-based RAM content initialization method and system. Background Technology
[0002] Programmable logic devices (PLDs), as a type of semi-custom circuit in the field of application-specific integrated circuits (ASICs), offer the key advantage of allowing users to modify the circuit as needed during the design phase until they are satisfied with the design. Once the design is complete, users can immediately put it into production, simply by programming the required number of PLDs using the final software design file. RAM, as a crucial resource in programmable logic devices, allows users to modify its initial values as needed during the design phase, initializing its contents through an initialization interface.
[0003] Generally speaking, after a chip is powered on but before it is initialized, the values in RAM (Random Access Memory) are random. These random values are uncontrollable, which makes it impossible to achieve the expected results. Summary of the Invention
[0004] The main objective of this application is to propose a cache-based RAM content initialization method and system, which aims to write initialization values into RAM through caching.
[0005] To achieve the above objectives, one aspect of this application proposes a cache-based RAM content initialization method, the method comprising: The control memory interface sends RAM initialization values to a cache medium so that the cache medium stores the RAM initialization values. The memory interface is controlled to send transmission control signals to the cache interface; the transmission control signals include a clock enable signal, a write enable signal, an initialization clock signal, and a write frame address signal; The control cache interface sends the RAM initialization value in the cache medium to the RAM according to the transmission control signal, so that the RAM writes the RAM initialization value.
[0006] In some embodiments, the RAM initialization value is transmitted in frames, and the control memory interface sends the RAM initialization value to the cache medium, including: The memory interface is controlled to send the cache frame address signal to the cache medium and to send frame data of a first preset number of bits to the cache medium.
[0007] In some embodiments, sending frame data of a first preset number of bits to the buffer medium includes: The frame data of the first preset number of bits is sent to the buffer medium through the displacement register.
[0008] In some embodiments, controlling the cache interface to send the RAM initialization value in the cache medium to the RAM according to the transmission control signal includes: The cache interface is controlled to select the interface path with the RAM according to the clock enable signal, and the tri-state buffer is controlled to enter the initialization mode according to the write enable signal; The control interface determines the RAM clock signal based on the initialization clock signal, and determines the data selection signal and RAM frame address signal based on the write frame address signal; The control cache interface sends the RAM initialization value in the cache medium to the RAM according to the data selection signal, the interface path, the RAM clock signal, and the RAM frame address signal.
[0009] To achieve the above objectives, another aspect of this application proposes a cache-based RAM content initialization system, the system comprising a memory interface, a cache interface, a cache medium, and RAM; wherein, The memory interface is used to send RAM initialization values to the cache medium and send transmission control signals to the cache interface; the transmission control signals include clock enable signal, write enable signal, initialization clock signal and write frame address signal. The cache medium is used to receive and store the RAM initialization value; The cache interface is used to send the RAM initialization value in the cache medium to the RAM according to the transmission control signal; The RAM is used to receive and write RAM initialization values.
[0010] In some embodiments, the system further includes a shift register connected to the memory interface and the buffer medium, the shift register being configured to send frame data of a first preset number of bits to the buffer medium.
[0011] In some embodiments, the cache interface includes a tri-state buffer, an address generation module, and a clock generation module; wherein, The clock generation module is used to determine the RAM clock signal based on the initialization clock signal; The address generation module is used to determine the data selection signal and the RAM frame address signal based on the clock enable signal, the write enable signal, the initialization clock signal, and the write frame address signal; The tri-state buffer is used to transmit the RAM initialization value according to the write enable signal and the data selection signal.
[0012] In some embodiments, the RAM includes a data write interface, an address interface, and a clock interface; the clock interface is configured to receive the RAM clock signal, the address interface is configured to receive the RAM frame address signal, and the write interface is configured to receive the output of the tri-state buffer.
[0013] In some embodiments, the system further includes a first data selection circuit, the input of which includes the output of the tri-state buffer and externally written data, and the output of the first data selection circuit is connected to the write interface.
[0014] In some embodiments, the system further includes a second data selection circuit, the input of which includes the RAM frame address signal and the external write frame address signal, and the output of which is connected to the address interface.
[0015] In some embodiments, the system further includes a third data selection circuit, the inputs of which include the RAM clock signal and an external write clock signal, and the output of which is connected to the clock interface.
[0016] In some embodiments, the RAM includes a data read interface connected to the tri-state buffer.
[0017] The embodiments of this application include at least the following beneficial effects: This application provides a cache-based RAM content initialization method and system. In this scheme, the initialization system includes a memory interface, a cache interface, a cache medium, and RAM. The memory interface sends the RAM initialization value to the cache medium and sends a transmission control signal to the cache interface. The transmission control signal includes a clock enable signal, a write enable signal, an initialization clock signal, and a write frame address signal. The cache medium receives and stores the RAM initialization value. The cache interface sends the RAM initialization value in the cache medium to the RAM according to the transmission control signal, thereby realizing the writing of the initialization value in the RAM and controlling the writing value of the RAM to achieve the expected requirements. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the structure of a cache-based RAM content initialization system provided in an embodiment of this application; Figure 2 This is a flowchart of a cache-based RAM content initialization method provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the cache interface provided in the embodiments of this application; Figure 4 This is a schematic diagram of another cache-based RAM content initialization system provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an address generation module provided in an embodiment of this application; Figure 6 This is a timing diagram for the initialization of the cache interface provided in an embodiment of this application. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.
[0020] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”
[0021] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.
[0023] See Figure 1This application provides a cache-based RAM content initialization system. The system includes a memory interface (CMI), a shift register (shift_top), a cache interface, a cache medium (cacheram), and RAM. The memory interface writes the RAM's initialization value to the cache medium frame by frame through the shift register. After each frame is written, the memory interface sends a transmission control signal to the cache interface to control the cache interface to move the content from the cache medium into the RAM array. The transmission control signal includes, but is not limited to, a clock enable signal, a write enable signal, an initialization clock signal, and a write frame address signal.
[0024] See Figure 2 This application provides a cache-based RAM content initialization method, which includes steps S101 to S103.
[0025] Step S101: Control the memory interface to send the RAM initialization value to the cache medium so that the cache medium stores the RAM initialization value; Step S102: The control memory interface sends a transmission control signal to the cache interface; the transmission control signal includes a clock enable signal, a write enable signal, an initialization clock signal, and a write frame address signal. Step S103: The control cache interface sends the RAM initialization value in the cache medium to the RAM according to the transmission control signal, so that the RAM writes the RAM initialization value.
[0026] First, the memory interface sends the RAM initialization value to the cache medium via multiple frames of initialization data through the cache frame address signal. The cache medium receives and stores the RAM initialization value. Then, the memory interface sends transmission control signals to the cache interface. The transmission control signals include a clock enable signal, a write enable signal, an initialization clock signal, and a write frame address signal. The clock enable signal controls the validity of the clock signal, the write enable signal controls the validity of the write signal, the initialization clock signal refers to the clock signal sent by the memory interface to the cache interface, and the write frame address signal refers to the address signal sent by the memory interface to the cache interface. Finally, the cache interface sends the RAM initialization value from the cache medium to the RAM according to the clock signal, address signal, and data signal in the transmission control signals, so that the RAM writes the RAM initialization value.
[0027] In some embodiments, the RAM initialization value is transmitted in frames, and the control memory interface sends the RAM initialization value to the cache medium, including: Step S201: The control memory interface sends the cache frame address signal to the cache medium and sends the frame data of the first preset number of bits to the cache medium.
[0028] It should be noted that the number of bits in the cache frame address signal and the first preset number of bits are determined according to the actual application, and this embodiment does not impose specific restrictions. For example, the memory interface sends the cache frame address signal frame_addr[5:0] to the cache medium and sends the frame data data[251:0] of the first preset number of bits to the cache medium.
[0029] In some embodiments, sending frame data of a first preset number of bits to a buffer medium includes: Step S301: Send the frame data of the first preset number of bits to the buffer medium through the shift register.
[0030] See Figure 1 Sending the frame data of the first preset number of bits to the buffer medium through the shift register can reduce the occupation of I / O pins. For example, an 8-bit shift register can be expanded to 8 outputs with only 3 pins, saving at least 5 I / O ports. At the same time, it can also make the circuit simple, easy to expand, and have strong anti-interference ability.
[0031] In some embodiments, the control cache interface sends the RAM initialization value in the cache medium to the RAM according to the transmission control signal, including: Step S401: Control the cache interface to select the interface path with RAM according to the clock enable signal, and control the tri-state buffer to enter the initialization mode according to the write enable signal. Step S402: The control cache interface determines the RAM clock signal based on the initialization clock signal, and determines the data selection signal and RAM frame address signal based on the write frame address signal; Step S403: The control cache interface sends the RAM initialization value in the cache medium to the RAM according to the data selection signal, interface path, RAM clock signal and RAM frame address signal.
[0032] See Figure 3The transmission control signals include the clock enable signal (MCE), write enable signal (MWR), initialization clock signal (MCLK), and write frame address signal (MADF). The cache interface selects the interface path with the RAM based on the clock enable signal (MCE). The interface path includes the clock path (the path between the clock output port of the cache interface and the clock input port CLK of the RAM), the address path (the path between the address output port of the cache interface and the address input port ADDR of the RAM), and the data transmission path (the path between the data output port of the cache interface and the data input port DI of the RAM). The write enable signal controls the tri-state buffer (WR Tri_Buffer) to enter the initialization mode. The cache interface determines the RAM clock signal based on the initialization clock signal (MCLK) and determines the data select signal (MDS) and RAM frame address signal (MADB) based on the write frame address signal (MADF). Finally, the cache interface sends the RAM initialization value in the cache medium to the RAM based on the data select signal (MDS), each interface path, the RAM clock signal (MCLK), and the RAM frame address signal (MADB).
[0033] See Figure 4 This application also provides a cache-based RAM content initialization system, which includes a memory interface, a cache interface, a cache medium, and RAM; wherein, The memory interface is used to send RAM initialization values to the cache medium and send transmission control signals to the cache interface; the transmission control signals include clock enable signal, write enable signal, initialization clock signal and write frame address signal; A buffer medium used to receive and store RAM initialization values; The cache interface is used to send the RAM initialization value in the cache medium to the RAM according to the transmission control signal; RAM is used to receive and write RAM initialization values.
[0034] The memory interface is connected to the cache medium, and the cache interface is connected to the memory interface, the cache medium, and the RAM. First, the memory interface sends the RAM initialization value to the cache medium, which receives and stores the RAM initialization value. Then, the memory interface sends a transmission control signal to the cache interface. Finally, the cache interface sends the RAM initialization value from the cache medium to the RAM according to the transmission control signal, and the RAM receives and writes the RAM initialization value.
[0035] In some embodiments, the system further includes a shift register connected to a memory interface and a buffer medium, the shift register being configured to send frame data of a first preset number of bits to the buffer medium.
[0036] See Figure 1 The shift register connects the memory interface and the cache medium. The memory interface transmits multiple frames of data to the cache medium through the shift register and directly transmits the cache frame address signal to the cache medium to send all RAM initialization values to the RAM.
[0037] In some embodiments, the cache interface includes a tri-state buffer, an address generation module, and a clock generation module; wherein... The clock generation module is used to determine the RAM clock signal based on the initialization clock signal. The address generation module is used to determine the data selection signal and RAM frame address signal based on the clock enable signal, write enable signal, initialization clock signal and write frame address signal; A tri-state buffer is used to transmit RAM initialization values based on the write enable signal and the data selection signal.
[0038] See Figure 3 The cache interface includes a tri-state buffer, an address generation module (MAD GEN), and a clock generation module (CLK GEN). The clock generation module (CLK GEN) determines the RAM clock signal (MCLKA) based on the initialization clock signal (MCLK). The address generation module (MAD GEN) determines the data select signal (MDS) and the RAM frame address signal (MADB) based on the write frame address signal (MADF). The tri-state buffer (Tri-Buffer) transmits a second preset number of frame data (MDB) based on the write enable signal (MWR) and the data select signal (MDS) to transmit the complete RAM initialization value to the RAM.
[0039] See Figure 5 , Figure 5 This diagram illustrates the structure of the address generation module. MCE, MWR, and MCLK jointly control the state machine. MCE is the clock enable signal, MWR is the initialization or readback enable signal, and MCLK is the initialization clock signal. An incrementing counter counts the MCLK clock and outputs the count result to the MDS encoder. The state machine unit is configured to transition between idle, initialization, readback, and completion states based on the frame type and the direction indication of MWR. The MDS encoder output unit is configured to output MDS<2:0> based on the current state of the state machine unit to control the data selection MUX circuit (tri-state Tri-Buffer). The address assembly unit is configured to assemble the multi-cycle received write frame address signals (MADF<7:0>) into a complete memory address in the initialization state and automatically update the memory address in the initialization / readback states.
[0040] In some embodiments, the RAM includes a data write interface, an address interface, and a clock interface; the clock interface is configured to receive a RAM clock signal, the address interface is configured to receive a RAM frame address signal, and the write interface is configured to receive the output of a tri-state buffer.
[0041] In some embodiments, the RAM includes a data read interface connected to a tri-state buffer.
[0042] See Figure 3 The RAM includes a data write interface (DI), a data read interface (D0), an address interface (ADDR), and a clock interface (CLK). The cache interface writes data to the RAM through the data write interface (DI), the address interface (ADDR), and the clock interface (CLK), and the RAM outputs data from the cache interface through the data read interface (D0), the address interface (ADDR), and the clock interface (CLK).
[0043] In some embodiments, the system further includes a first data selection circuit, the input of which includes the output of a tri-state buffer and externally written data, and the output of the first data selection circuit is connected to a write interface.
[0044] See Figure 3 The inputs of the first data selection circuit include the output of the tri-state buffer (MDB) and external write data (user data). The output of the first data selection circuit is connected to the write interface. When the first data selection circuit selects the output of the tri-state buffer (MDB) to be valid, the input of RAM is the data in the buffer medium; when the first data selection circuit selects external write data (user data) to be valid, the input of RAM is the external write data.
[0045] In some embodiments, the system further includes a second data selection circuit, the inputs of which include a RAM frame address signal and an external write frame address signal, and the output of the second data selection circuit is connected to an address interface.
[0046] See Figure 3 The inputs of the second data selection circuit include the RAM frame address signal (MADB) and the external write frame address signal (user address). The output of the second data selection circuit is connected to the address interface. When the second data selection circuit selects the RAM frame address signal (MADB) to be valid, the RAM input address is determined according to the write frame address signal (MADF); when the second data selection circuit selects the external write frame address signal (user address) to be valid, the RAM input address is determined according to the external write frame address signal (user address).
[0047] In some embodiments, the system further includes a third data selection circuit, the inputs of which include a RAM clock signal and an external write clock signal, and the output of the third data selection circuit is connected to a clock interface.
[0048] See Figure 3 The inputs of the third data selection circuit include the RAM clock signal (MCLKA) and the external write clock signal (user clk). The output of the third data selection circuit is connected to the clock interface. When the third data selection circuit selects the RAM clock signal (MCLKA) as valid, the RAM clock input is the RAM clock signal (MCLKA); when the third data selection circuit selects the external write clock signal (user clk) as valid, the RAM input clock is the external write clock signal (user clk).
[0049] In one specific embodiment, see Figure 3 and Figure 6 , Figure 6 This diagram illustrates the timing sequence for cache interface initialization. First, the memory interface sends the RAM initialization value to the cache medium via a cache frame address signal, consisting of multiple frames of initialization data. The cache frame address signal is a 6-bit address [5:0], and each frame of initialization data contains [251:0]. The cache medium receives and stores the RAM initialization value. Then, the memory interface sends transmission control signals to the cache interface. These signals include a clock enable signal (MCE), a write enable signal (MWR), an initialization clock signal (MCLK), and a write frame address signal (MADF<7:0>). Then, the cache interface selects the interface path with RAM according to the clock enable signal (MCE), and controls the tri-state buffer (WR Tri_Buffer) to enter the initialization mode according to the write enable signal (MWR). The data transmission bit length between the cache interface and the cache medium is 252 bits. MDS<2:0> is the data selection signal generated by the address generation module (MAD GEN) through the initialization clock signal (MCLK). Each code pattern of MDS<2:0> selects 36 bits of data from the 252 bits of the cache medium to the RAM data input interface DI<35:0>. The address generation module (MAD GEN) outputs MADB<9:0> as the RAM address input signal ADDR<9:0> generated by MADF<7:0> and MDS<2:0>. The clock generation module (CLK GEN) inputs the initialization clock (MCLK) and outputs the RAM clock signal (MCLKA) and clock count. Finally, the cache interface sends the RAM initialization value from the cache medium to the RAM based on the data selection signal (MDS<2:0>), each interface path, the RAM clock signal (MCLKA), and the RAM frame address signal (MADB<9:0>). For example... Figure 6As shown, during each frame initialization operation, MCE is pulled high. MCLK has a total of M=7 frames. During each frame operation, the MDS<2:0> signal selects 36 bits of data from the cache and assigns them to DI<35:0>. The MDS<2:0> signal increments sequentially starting from address 0 each time; the MADB<9:0> signal increments sequentially starting from address X each time. After receiving the data, address, and clock, the RAM writes the data for the current frame into the RAM.
[0050] The embodiments of this application include at least the following beneficial effects: This application provides a cache-based RAM content initialization method and system. In this scheme, the initialization system includes a memory interface, a cache interface, a cache medium, and RAM. The memory interface sends the RAM initialization value to the cache medium and sends a transmission control signal to the cache interface. The transmission control signal includes a clock enable signal, a write enable signal, an initialization clock signal, and a write frame address signal. The cache medium receives and stores the RAM initialization value. The cache interface sends the RAM initialization value in the cache medium to the RAM according to the transmission control signal, thereby realizing the writing of the initialization value in the RAM and controlling the writing value of the RAM to achieve the expected requirements.
[0051] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0052] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.
[0053] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.
[0054] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.
[0055] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0056] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.
[0057] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0058] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0059] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0060] For example, for various devices or products applied to or integrated into the controller, each module / unit contained therein can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on the processor integrated inside the controller, and the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices or products applied to or integrated into the controller module or terminal, each module / unit contained therein can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., controller, circuit module, etc.) or different components of the controller module or terminal, or at least some modules / units can be implemented using software programs that run on the processor integrated inside the controller module or terminal, and the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0061] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0062] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.
Claims
1. A method for initializing RAM content based on caching, characterized in that, The method includes: The control memory interface sends RAM initialization values to a cache medium so that the cache medium stores the RAM initialization values. The memory interface is controlled to send transmission control signals to the cache interface; the transmission control signals include a clock enable signal, a write enable signal, an initialization clock signal, and a write frame address signal; The control cache interface sends the RAM initialization value in the cache medium to the RAM according to the transmission control signal, so that the RAM writes the RAM initialization value.
2. The method according to claim 1, characterized in that, The RAM initialization value is transmitted in frames, and the control memory interface sends the RAM initialization value to the cache medium, including: The memory interface is controlled to send the cache frame address signal to the cache medium and to send frame data of a first preset number of bits to the cache medium.
3. The method according to claim 2, characterized in that, Sending frame data of a first preset number of bits to the buffer medium includes: The frame data of the first preset number of bits is sent to the buffer medium through the displacement register.
4. The method according to claim 1, characterized in that, The control of the cache interface to send the RAM initialization value in the cache medium to the RAM according to the transmission control signal includes: The cache interface is controlled to select the interface path with the RAM according to the clock enable signal, and the tri-state buffer is controlled to enter the initialization mode according to the write enable signal; The control interface determines the RAM clock signal based on the initialization clock signal, and determines the data selection signal and RAM frame address signal based on the write frame address signal; The control cache interface sends the RAM initialization value in the cache medium to the RAM according to the data selection signal, the interface path, the RAM clock signal, and the RAM frame address signal.
5. A cache-based RAM content initialization system, characterized in that, The system includes a memory interface, a cache interface, a cache medium, and RAM; wherein, The memory interface is used to send RAM initialization values to the cache medium and send transmission control signals to the cache interface; the transmission control signals include clock enable signal, write enable signal, initialization clock signal and write frame address signal. The cache medium is used to receive and store the RAM initialization value; The cache interface is used to send the RAM initialization value in the cache medium to the RAM according to the transmission control signal; The RAM is used to receive and write RAM initialization values.
6. The system according to claim 5, characterized in that, The system also includes a shift register connected to the memory interface and the buffer medium, the shift register being configured to send frame data of a first preset number of bits to the buffer medium.
7. The system according to claim 5, characterized in that, The cache interface includes a tri-state buffer, an address generation module, and a clock generation module; wherein... The clock generation module is used to determine the RAM clock signal based on the initialization clock signal; The address generation module is used to determine the data selection signal and the RAM frame address signal based on the clock enable signal, the write enable signal, the initialization clock signal, and the write frame address signal; The tri-state buffer is used to transmit the RAM initialization value according to the write enable signal and the data selection signal.
8. The system according to claim 7, characterized in that, The RAM includes a data write interface, an address interface, and a clock interface; the clock interface is configured to receive the RAM clock signal, the address interface is configured to receive the RAM frame address signal, and the write interface is configured to receive the output of the tri-state buffer.
9. The system according to claim 8, characterized in that, The system further includes a first data selection circuit, the input of which includes the output of the tri-state buffer and externally written data, and the output of the first data selection circuit is connected to the write interface.
10. The system according to claim 8, characterized in that, The system further includes a second data selection circuit, the input of which includes the RAM frame address signal and the external write frame address signal, and the output of the second data selection circuit is connected to the address interface.
11. The system according to claim 8, characterized in that, The system also includes a third data selection circuit, the input of which includes the RAM clock signal and an external write clock signal, and the output of which is connected to the clock interface.
12. The system according to claim 8, characterized in that, The RAM includes a data read interface, which is connected to the tri-state buffer.