A flight control system testability index calculation method based on multi-layer correlation matrix

Abstract

The application provides a testability index calculation method of a flight control system based on a multi-layer correlation matrix, and relates to the technical field of testability analysis. The method is started from a hierarchical structure of system design, a fault mode correlation matrix for representing a dependency relationship between fault modes is constructed, a BIT hierarchical structure matrix for describing a transmission relationship between multi-layer BITs is constructed, and a fault mode and low-layer BIT mapping matrix for describing a corresponding relationship between fault modes and low-layer BITs is constructed, a reachability matrix for representing an overall reachable relationship between fault modes and detection means is constructed through matrix combination operation, and fault coverage and fault detection rate are calculated based on the reachability matrix. The application also proposes two system-level testability indexes of cross-device fault detection rate and detection contribution degree. The application realizes structured and decoupled expression of testability analysis input, can truly reflect actual detection capability of a complex flight control system, and has strong engineering applicability.

Description

Technical Field

[0001] This invention relates to the field of testability analysis technology, and specifically to a method for calculating testability indicators of a flight control system based on a multi-layer correlation matrix. Background Technology

[0002] Airborne equipment is a critical component for the functional realization of an aircraft, and its correctness and integrity directly affect the aircraft's safety and mission completion capabilities. To ensure that system failures can be detected and located promptly and accurately, testability analysis is typically conducted during the design phase of airborne equipment. Testability design is not only an extension of system safety analysis but also an important basis for subsequent maintainability design and health management functions. Therefore, testability design plays a crucial, bridging role throughout the entire lifecycle of airborne equipment.

[0003] Current methods for testability analysis and design of airborne equipment still have limitations. Traditional methods are mostly based on static failure mode coverage analysis, lacking a characterization of the hierarchical structure of detection methods and the coupling relationships between devices, and failing to systematically describe the correlation identification between faults. Especially for flight control systems, the number of devices is large, the coupling relationships between devices are complex, and the correlation and transmission relationships between failure modes are difficult to identify. The hierarchical BIT makes the identification of failure modes incomplete. Traditional detection rate calculation methods are difficult to effectively adapt to this hierarchical and strongly coupled complex system structure, resulting in a deviation between the detection performance evaluation results and the actual system performance. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method for calculating testability indicators of a flight control system based on a multi-level correlation matrix. This method enables testability analysis and fault detection rate calculation for complex airborne equipment, and can realize a testability indicator calculation method that considers the correlation between multi-level BIT structure and fault modes. By matrix-based expression of the correlation between multi-level BIT structure and fault modes, a quantitative evaluation of the system's testability is achieved.

[0005] This application provides the following technical solution: a method for calculating testability indicators of a flight control system based on a multi-layer correlation matrix, comprising the following steps:

[0006] S1. Based on the interface documentation and device FMEA, the fault propagation path of the fault modes is extracted, and a fault mode correlation matrix is ​​constructed to characterize the dependencies between fault modes. S2. Based on the BIT architecture design and BIT analysis documents, construct a BIT hierarchy structure matrix to describe the transmission relationship between multi-level BITs; S3. Based on the fault mode detection method in the FMEA document, construct a fault mode and underlying BIT mapping matrix; S4. Based on the fault mode correlation matrix, the BIT hierarchy structure matrix, and the fault mode-bottom BIT mapping matrix, construct an reachability matrix D to characterize the overall reachability relationship between fault modes and detection methods through matrix combination operations. S5. Based on the reachability matrix D, extract the set of detectable fault modes in each device, and calculate the fault coverage, fault detection rate, cross-device fault detection rate and fault detection contribution respectively.

[0007] According to one embodiment of this application, constructing the fault mode correlation matrix includes: Filter the failure mode candidates in the FMEA document to identify the failure mode candidates and confirm their failure propagation relationships. Divide three or more propagation links into multiple one-to-one propagation relationships to represent the failure mode propagation relationships in a matrix format.

[0008] According to one embodiment of this application, the reachability matrix D is calculated as follows:

[0009] in, The fault mode correlation matrix is... Let P be the BIT hierarchy structure matrix, P be the fault mode and bottom-level BIT mapping matrix, and I be the identity matrix.

[0010] According to one embodiment of this application, the rows and columns of the fault mode correlation matrix correspond to the system fault mode set, the columns of the BIT hierarchy structure matrix are the set low-level BITs, and the columns are the set high-level BITs. The columns of the fault mode and bottom-level BIT mapping matrix are the fault modes, and the columns are the bottom-level detection methods.

[0011] According to one embodiment of this application, the fault coverage rate is the ratio of the number of detectable fault modes to the total number of fault modes; the fault detection rate is the ratio of the sum of the failure rates of detectable fault modes to the sum of the failure rates of all fault modes.

[0012] According to one embodiment of this application, the cross-device fault detection rate is the ratio of the sum of the failure rates of fault modes in the device that can only be detected by other devices to the sum of the failure rates of all fault modes in the device.

[0013] According to one embodiment of this application, the fault detection contribution is the ratio of the sum of the failure rates of the fault modes of the device under test that can be detected by the specified device to the sum of the failure rates of all fault modes of the device under test.

[0014] According to one embodiment of this application, it further includes: when the calculation result of the fault detection rate does not reach the preset testability index, adjusting the system testability design, the adjustment content including at least one of the following: the number of faults that BIT can detect, the fault criterion threshold, the diagnostic logic, the interface information, and the division of labor of BIT hierarchy.

[0015] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least: First, this invention introduces a fault mode correlation matrix, a BIT hierarchy matrix, and a fault mode-to-bottom BIT mapping matrix to provide a unified matrix description of the highly coupled fault propagation relationships, hierarchical relationships of detection methods, and basic detection capabilities in traditional testability analysis. It also automatically generates a reachability matrix through matrix operations, avoiding the subjectivity and inconsistency issues caused by directly constructing the reachability matrix, and realizing a structured and decoupled expression of testability analysis input.

[0016] Second, the reachability matrix obtained by combining multiple matrices not only reflects whether there is a detection relationship between the fault mode and the detection method, but also reflects the redundancy of the detection path. This fully considers the impact of fault mode correlation and BIT (Built-In Test) hierarchy on the detection results, and more realistically reflects the actual detection capability of complex flight control systems.

[0017] Third, this invention proposes two new system-level testability metrics: cross-device fault detection rate and detection contribution. The cross-device fault detection rate can quantitatively characterize the degree to which devices depend on external detection methods, while the detection contribution can quantify the role and importance of different devices in system fault detection, providing clear quantitative basis for BIT architecture optimization, fault isolation design, and testability verification.

[0018] Fourth, the method of the present invention has strong engineering applicability and is suitable for test analysis scenarios of flight control systems with a large number of devices, complex coupling relationships, and obvious BIT hierarchy. It can also effectively use FMEA documents and BIT design data in the system design process. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a method for calculating test performance indicators of a flight control system based on a multi-layer correlation matrix, according to an embodiment of the present invention. Figure 2 This is a test model example diagram of an embodiment of the present invention. Detailed Implementation

[0021] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0022] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] This invention proposes a method for calculating testability indicators of flight control systems based on multi-layer correlation matrices. Starting from the hierarchical structure of the system design, it establishes three types of matrices to describe fault mode correlation, BIT hierarchical relationships, and BIT-fault mode associations. These matrices provide a unified expression of fault modes, detection methods, and their hierarchical relationships. Furthermore, based on matrix combination operations, it constructs an overall reachability relationship between fault modes and detection methods, achieving a structured expression of the system's testability characteristics and thus enabling the calculation of multi-dimensional testability indicators. Through matrix combination operations, the fault detection rate at different levels can be systematically calculated, providing a quantitative basis for testability design optimization and verification.

[0024] Specifically, the method proposed in this invention includes the following: (1) Construct a fault mode correlation matrix to characterize the dependencies between fault modes, so as to explicitly describe the fault propagation relationship of system function flow between fault modes; (2) Construct a BIT hierarchy matrix to describe the transitive relationships between multi-level BITs, so as to characterize the combination and dependency relationships between low-level BITs and high-level BITs; (3) Construct a mapping matrix between fault modes and low-level BITs to describe the correspondence between fault modes and low-level BITs, so as to characterize the system’s basic detection capability for equipment fault modes. (4) Based on the above multi-layer correlation matrix, an accessibility matrix is ​​constructed through matrix combination operations to characterize the overall accessibility relationship between fault modes and detection methods, providing a unified description of detection capabilities at the system level. Based on the accessibility matrix, fault coverage and fault detection rate are calculated to check the compliance between test requirements and test design implementation.

[0025] (5) Based on the above three matrices, two system-level testability indicators, cross-device fault detection rate and fault detection contribution, are proposed to characterize the ability of other equipment to detect the fault mode of the target equipment, thereby identifying the importance of equipment with self-detection capability or undertaking key detection functions in the system testability design, and providing a basis for subsequent fault isolation design and testability verification.

[0026] This invention derives a reachability matrix between failure modes and detection methods based on the aforementioned three matrices, thereby calculating testability metrics such as fault coverage and fault isolation rate. The proposed three matrices simplify and clarify the relationship between each part of the testability analysis input, and the hierarchical structure also facilitates the construction of new metrics to demonstrate the correctness and rationality of the testability design.

[0027] The aforementioned fault detection rate serves as a key evaluation indicator in the testability analysis and design of airborne equipment, used to measure whether the current testability scheme meets the requirements. Based on the calculation results of the fault detection rate, when the detection rate of a certain device or a certain type of fault mode fails to meet the testability indicators, the system testability design should be adjusted in a timely manner, focusing on optimizing design data directly related to detection capabilities, such as the number of faults that a BIT can detect, fault criterion thresholds, diagnostic logic, interface information, and BIT hierarchical division of labor.

[0028] The two quantitative testability indicators proposed in this invention—cross-device fault detection rate and detection contribution—can also be used to identify the importance of devices with self-testing capabilities in system fault diagnosis design, thereby providing a basis for the allocation of testing resources. Targeted improvement of the fault detection capabilities of each device based on these indicators helps in modifying BIT functions, adding test points, and optimizing the determination of detection levels, thus improving the overall testability design level of the system.

[0029] Example 1 like Figure 1 As shown, this embodiment of the invention provides a method for calculating the testability index of a flight control system based on a multi-layer correlation matrix, including the following steps: S1. Based on the interface documentation and device FMEA, the fault propagation path of the fault modes is extracted, and a fault mode correlation matrix is ​​constructed to characterize the dependencies between fault modes. S2. Based on the BIT architecture design and BIT analysis documents, construct a BIT hierarchy structure matrix to describe the transmission relationship between multi-level BITs; S3. Based on the fault mode detection method in the FMEA document, construct a fault mode and underlying BIT mapping matrix; S4. Based on the fault mode correlation matrix, the BIT hierarchy structure matrix, and the fault mode-bottom BIT mapping matrix, construct an reachability matrix D to characterize the overall reachability relationship between fault modes and detection methods through matrix combination operations. S5. Based on the reachability matrix D, extract the set of detectable fault modes in each device, and calculate the fault coverage, fault detection rate, cross-device fault detection rate and fault detection contribution respectively.

[0030] Specifically, step S1 can be divided into the following sub-steps: S1-1. Filter the failure mode candidates for the failure propagation path in the FMEA file. The selection criteria for the candidates include the following two items: failure modes related to the interface module of the component; and failures in the failure impact analysis that will cause the device to output errors or loss due to higher-level impacts or final impacts.

[0031] S1-2. Confirm the fault propagation relationship of the failure mode candidates. Determine whether a fault propagation relationship exists in the following two ways: (1) Based on the port connection between devices, confirm whether an error in the output of the transmitting end interface will cause an error in the output of the receiving end interface module (including forwarding errors to other modules inside the device and sending errors to external signals); (2) Based on the system functional flow diagram, confirm whether the failure mode has a direct impact on the downstream function.

[0032] S1-3. Simplify the fault propagation relationships between fault modes. For fault mode pairs with obvious fault propagation relationships extracted in S1-2, confirm the sending and receiving ends of the propagation relationship. All propagation relationship descriptions only consider directed one-to-one relationships. For three or more propagation links, it is necessary to divide them into multiple one-to-one propagation relationships to facilitate matrix expression. This also avoids the need for multi-level superposition of index calculations required for multi-level propagation.

[0033] S1-4. Confirm the matrix representation of the failure mode propagation relationship and construct the failure mode correlation matrix. .

[0034] Specifically, in the fault mode correlation matrix constructed in steps S1-4, It is a square matrix, where each row and column is a set of all failure modes. When the failure mode This will lead to When it happens, that is For the sending end, When acting as the receiving end, set the corresponding elements of the matrix. Otherwise, it is 0.

[0035] Specifically, in step S2, it is necessary to identify the low-level and high-level BITs in the system design. Low-level BITs generally refer to BITs that directly collect relevant parameters from sensors for logical judgment or dedicated BIT circuits built in hardware. High-level BITs refer to BITs that make comprehensive judgments based on the results of low-level BITs, supplemented by data from other sensors or calculations. High-level BITs are generally implemented in software and involve cross-device information interaction and monitoring logic. Generally, the level of BITs can be identified by analyzing the BIT output content, suppression conditions, and other information in the BIT analysis document. Based on the above relationship between high-level and low-level BITs, a BIT hierarchy structure matrix is ​​constructed. .

[0036] Specifically, the BIT hierarchical structure matrix constructed in step S2 The matrix represents lower-level bits, and the columns represent higher-level bits. When the lower-level bits... It will trigger a high-level BIT When, set the corresponding element of the matrix Otherwise, it is 0.

[0037] Specifically, in step S3, the fault mode is mapped to the underlying BIT matrix. This is a mapping of failure modes and detection methods based on the FMEA file. The matrix columns represent detection methods, including BIT (Block In-Time) and manual inspection; and behavioral failure modes. If... The corresponding fault mode of the line Can be Detection methods for columns If detected, then proceed to the elements of the matrix. Otherwise, it is 0.

[0038] Specifically, the fault coverage rate and fault detection rate calculated in step S4 can be calculated using the reachability matrix D obtained from the three matrices mentioned above. Based on these three matrices, the calculation method for matrix D can be derived as follows:

[0039] in, The fault mode correlation matrix is... Let P be the BIT hierarchy structure matrix, P be the fault mode and bottom-level BIT mapping matrix, and I be the identity matrix.

[0040] Specifically, the fault coverage rate calculated in step S5 refers to the proportion of fault modes that can be covered by different types of detection methods to the total number of fault modes.

[0041] The mathematical model expression for the fault coverage rate is:

[0042] In the formula, Num(·) is a function that takes the number of elements in the set. This refers to the set of all failure modes of device A. This refers to the set of fault modes that can be detected in device A. and It can be obtained through the D matrix.

[0043] Specifically, the fault detection rate calculated in step S5 refers to the ratio of the sum of failure rates of fault modes that can be covered by different types of detection methods to the sum of failure rates of all fault modes.

[0044] The mathematical model expression for the fault coverage rate is:

[0045] In the formula For corresponding fault modes The failure rate can be obtained from the device's FMEA file.

[0046] Specifically, the cross-device fault detection rate and fault detection contribution in step S5 need to be calculated by combining the failure rate data of the fault modes and the D matrix. The cross-device fault detection rate refers to the proportion of the failure rate of the fault modes that need to be detected by other devices to the total failure rate of the device.

[0047] The mathematical model expression for the cross-device fault detection rate is:

[0048] In the formula For the fault modes of the equipment that can only be calculated by other devices, the analysis and calculation can be performed based on the D matrix structure.

[0049] Specifically, in step S5, the fault detection contribution rate refers to the proportion of the failure rate of the tested device that can be detected by all devices capable of detecting the fault mode of the tested device to the total failure rate of the tested device.

[0050] The mathematical model expression for the contribution of fault detection is:

[0051] In the formula It refers to the set of all fault modes of device A that can be detected by device B, which can be analyzed and calculated based on the structure of matrix D.

[0052] Example 2 This embodiment, based on the method described in Embodiment 1, explains the calculation process of testability indicators in conjunction with specific flight control system structures and failure rate data.

[0053] This embodiment uses a typical flight control link as an example. The system adopts a three-level hierarchical control structure, including actuators (ACTs), secondary control units (SCUs), and a main control unit (MCU) from bottom to top. The actuators lack self-testing capabilities; the detection of all fault modes requires transmitting relevant parameters to external devices with self-testing capabilities. The secondary control units have self-testing capabilities and are equipped with some test points, mainly used to detect faults in the control unit itself and some actuator parameter inputs. The main control unit, as a system-level monitoring node, performs comprehensive fault logic detection on relevant parameters from the secondary control units and actuators, and provides detection capabilities for faults in some key actuators and communication links. The relationship diagram between fault modes and test points is shown below. Figure 2 As shown.

[0054] Define the set of fault modes for each device in the system as follows: The definitions and failure rates of each failure mode are as follows: Actuator failure, failure rate ; Actuator position output error, failure rate ; Failure rate: Actuator drive or power supply link malfunction. ; Failure rate: Actuator anti-cavitation valve closure error. ; The actuator pressure sensor is oscillating incorrectly, resulting in a failure rate. ; SCU outputs an error-driven instruction, resulting in failure rate. ; SCU actuator position acquisition error, failure rate ; SCU pressure sensor acquisition error, failure rate ; MCU output instruction error, failure rate .

[0055] MCU communication interface module received an error, failure rate .

[0056] The fault propagation relationships that exist include: lead to and , lead to , lead to , and This will lead to , lead to , lead to .

[0057] Therefore, the failure mode correlation matrix can be obtained. The expression is as follows:

[0058] Define the low-level BIT set designed in the system as follows: High-level BIT collection Its meaning is as follows: SCU actuator position monitoring (coverage) (SCU implementation) SCU pressure range monitoring (coverage) (SCU implementation) Bus monitoring from MCU to SCU (covering) , and (MCU implementation) MCU pressure sensor range detection (MCU configuration only, coverage) and (MCU implementation) MCU instruction wrap-around consistency monitoring (combined with) Information, coverage (MCU implementation) MCU unit alarm monitoring (combined with) Information, coverage (MCU implementation) Therefore, the BIT hierarchical structure matrix can be obtained. Fault Mode Mapping Matrix The expression is as follows:

[0059]

[0060] After matrix calculation, the result of matrix D is as follows:

[0061] Compared with the traditional D matrix, the D matrix obtained by calculating the product of the three types of matrices proposed in this invention has elements that are not only 0 or 1, but the element size also represents the redundancy of the detection link between the corresponding BIT and the fault mode.

[0062] Fault coverage and fault detection rate can be calculated based on the correspondence between non-zero rows and fault modes in the D matrix:

[0063]

[0064] The cross-device fault detection rate is calculated separately for ACT, SCU, and MCU. Based on the D matrix, the fault modes that require cross-device detection can be identified separately.

[0065]

[0066] The contribution of SCU and MCU to the fault mode detection capability of ACT devices is calculated based on the D matrix block division:

[0067]

[0068] Since there is an undetectable fault in the ACT, the sum of the contribution of detection capabilities is not 1. It can be seen that for actuator design, the control unit that interacts directly with it is the main means of fault detection. For some key fault modes, detection may be carried out in the higher-level MCU, which is also in line with the hierarchical design of detection capabilities in the BIT architecture design of flight control system.

[0069] This invention offers the following advantages: By introducing a fault mode correlation matrix, a BIT hierarchy matrix, and a fault mode-to-bottom BIT mapping matrix, it unifies the highly coupled fault propagation relationships, detection method hierarchical relationships, and basic detection capabilities in traditional testability analysis into a unified matrix description. Furthermore, it automatically generates a D-matrix through matrix operations, avoiding the subjectivity and inconsistencies inherent in directly constructing the D-matrix, thus achieving a structured and decoupled expression of testability analysis input. The D-matrix obtained from multi-matrix combinations not only reflects the existence of detection relationships between fault modes and detection methods but also reflects the redundancy of detection paths, thereby fully considering the impact of fault mode correlation and BIT hierarchy structure on detection results and more realistically reflecting the actual detection capabilities of complex flight control systems. This invention proposes two new system-level testability indicators: cross-device fault detection rate and detection contribution. The device fault detection rate quantitatively characterizes the degree of dependence of devices on external detection methods, while the detection contribution quantifies the role and importance of different devices in system fault detection, providing clear quantitative basis for testability verification, BIT architecture optimization, and fault isolation design. The method of this invention has strong engineering applicability and is suitable for test analysis scenarios of flight control systems with a large number of devices, complex coupling relationships, and obvious BIT hierarchy. It can also effectively utilize FMEA documents and BIT design data in the system design process.

[0070] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for calculating testability indicators of a flight control system based on a multi-layer correlation matrix, characterized in that, Includes the following steps: S1. Based on the interface documentation and device FMEA, the fault propagation path of the fault modes is extracted, and a fault mode correlation matrix is ​​constructed to characterize the dependencies between fault modes. S2. Based on the BIT architecture design and BIT analysis documents, construct a BIT hierarchy structure matrix to describe the transmission relationship between multi-level BITs; S3. Based on the fault mode detection method in the FMEA document, construct a fault mode and underlying BIT mapping matrix; S4. Based on the fault mode correlation matrix, the BIT hierarchy structure matrix, and the fault mode-bottom BIT mapping matrix, construct an reachability matrix D to characterize the overall reachability relationship between fault modes and detection methods through matrix combination operations. S5. Based on the reachability matrix D, extract the set of detectable fault modes in each device, and calculate the fault coverage, fault detection rate, cross-device fault detection rate and fault detection contribution respectively.

2. The method for calculating the testability index of a flight control system based on a multi-layer correlation matrix according to claim 1, characterized in that, Constructing the failure mode correlation matrix includes: Filter the failure mode candidates in the FMEA document to identify the failure mode candidates and confirm their failure propagation relationships. Divide three or more propagation links into multiple one-to-one propagation relationships to represent the failure mode propagation relationships in a matrix format.

3. The method for calculating the testability index of a flight control system based on a multi-layer correlation matrix according to claim 1, characterized in that, The reachability matrix D is calculated as follows: in, The fault mode correlation matrix is... Let P be the BIT hierarchy structure matrix, P be the fault mode and bottom-level BIT mapping matrix, and I be the identity matrix.

4. The method for calculating the testability index of a flight control system based on a multi-layer correlation matrix according to claim 1, characterized in that, The rows and columns of the fault mode correlation matrix correspond to the system fault mode set. The BIT hierarchy structure matrix has the lower-level BITs set as its columns and the higher-level BITs set as its columns. The fault mode to lower-level BIT mapping matrix has the fault modes set as its columns and the lower-level detection methods set as its columns.

5. The method for calculating the testability index of a flight control system based on a multi-layer correlation matrix according to claim 1, characterized in that, The fault coverage rate is the ratio of the number of detectable fault modes to the total number of fault modes; the fault detection rate is the ratio of the sum of the failure rates of detectable fault modes to the sum of the failure rates of all fault modes.

6. The method for calculating the testability index of a flight control system based on a multi-layer correlation matrix according to claim 1, characterized in that, The cross-device fault detection rate is the ratio of the sum of the failure rates of fault modes in the device that can only be detected by other devices to the sum of the failure rates of all fault modes in the device.

7. The method for calculating testability indicators of a flight control system based on a multi-layer correlation matrix according to claim 1, characterized in that, The fault detection contribution is the ratio of the sum of the failure rates of the fault modes of the tested device that can be detected by the specified equipment to the sum of the failure rates of all fault modes of the tested device.

8. The method for calculating testability indicators of a flight control system based on a multi-layer correlation matrix according to claim 1, characterized in that, Also includes: When the calculated fault detection rate does not meet the preset testability index, the system testability design is adjusted. The adjustment includes at least one of the following: the number of faults that BIT can detect, the fault criterion threshold, the diagnostic logic, the interface information, and the division of labor among BIT levels.

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