Linear solving method and device based on block LU and vectorization

Abstract

The application provides a linear solving method and device based on block LU and vectorization, and relates to the technical field of high-performance computing.The method comprises the following steps: obtaining a coefficient matrix and a right end term to be solved; reading hardware parameters of an X86 architecture processor and setting a basic block size to divide the coefficient matrix into four sub-block matrices, and ensuring that the data amount of the first sub-block matrix is not more than the L1 data cache capacity; further dividing the LU decomposition process into four sub-processes, accelerating the solving of each sub-block matrix, and stopping until the decomposition of each sub-block matrix is completed; based on the result of the LU decomposition process, performing forward substitution and backward substitution on the right end term, and outputting the solution of the linear equation group; the data amount of the first sub-block matrix matches the cache capacity of the processor, and the LU decomposition speed can be improved; the four sub-processes are respectively subjected to vectorization optimization strategies, which is helpful to improve the data reading speed and further improve the solving speed.

Description

Technical Field

[0001] This invention relates to the technical field of high-performance computing, and in particular to a linear solution method and apparatus based on block LU and vectorization. Background Technology

[0002] LU decomposition is a numerical computation method that decomposes a matrix into a lower triangular matrix L and an upper triangular matrix U, and can be viewed as the matrix form of Gaussian elimination. LU decomposition is a core foundational step in solving linear equation systems Ax=b, matrix inversion, determinant calculation, and many local block linear fitting tasks. For business scenarios such as image brightness compensation, CAE (Computer-Aided Engineering) local block solving, mesh field parameter fitting, and local linear model construction, systems often need to repeatedly perform LU decomposition on a large number of small- to medium-sized matrices; therefore, the performance of this step directly determines the overall throughput and latency.

[0003] In image processing scenarios, in typical applications of existing technologies, the input image needs to be divided into blocks, and then each block needs to be solved linearly. The entire process requires a large number of solutions, resulting in low execution efficiency. This makes execution efficiency a bottleneck in the overall system performance and makes it difficult to meet the latency requirements of real-time image processing. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a linear solution method and apparatus based on block LU and vectorization to improve image processing efficiency and thus alleviate the above-mentioned technical problems.

[0005] In a first aspect, embodiments of the present invention provide a linear solution method based on block LU and vectorization, the method comprising: obtaining the coefficient matrix to be solved and the right-hand side; reading the hardware parameters of the x86 architecture processor, wherein the hardware parameters include at least the L1 data cache capacity and the AVX instruction set types supported by the processor and the number of corresponding AVX vector registers; setting a basic block size according to the L1 data cache capacity, and dividing the coefficient matrix into four sub-block matrices according to the basic block size, denoted as the first sub-block matrix A11, the second sub-block matrix A11, etc. 12. The third sub-block matrix A21 and the fourth sub-block matrix A22 are configured such that the data size of the first sub-block matrix does not exceed the L1 data cache capacity. The LU decomposition process is divided into four sub-processes executed sequentially, and a differentiated vectorized optimization strategy is adopted for the memory access mode of each sub-process, including: Basic decomposition sub-process: Perform LU decomposition on the first sub-block matrix A11 to obtain the lower triangular matrix L11 and the upper triangular matrix U11; First solution sub-process: Solve the lower triangular matrix corresponding to the third sub-block matrix A21 according to the formula L21·U11=A21. Matrix L21; Before solving, the upper triangular matrix U11 is transposed and stored, so that the transposed upper triangular matrix U11 is arranged continuously in row order. A multi-level row direction register blocking strategy is used to load the transposed upper triangular matrix U11 into AVX vector registers in row blocks for multiplication and addition operations. The number of rows in each row block is determined by the number of AVX vector registers. Second solution sub-process: Solve for the upper triangular matrix U12 corresponding to the second sub-block matrix A12 according to the formula L11·U12=A12; without performing matrix transposition, directly arrange in row order. First, the lower triangular matrix L11 is accessed in a modular manner, and a multi-level column direction register blocking strategy is adopted to load the lower triangular matrix L11 into the AVX vector register by column and perform multiplication and addition operations; the update sub-process: the Shure complement matrix S is calculated according to the formula S = A22 - L21·U12, and a strategy combining multi-level cache block and GEMM microkernel is adopted, wherein the size of the GEMM microkernel is determined according to the AVX instruction set type; based on the result of the LU decomposition process, forward substitution and backward substitution are performed on the right-hand side terms, and the solution of the linear equation system is output.

[0006] In conjunction with the first aspect, the present invention provides a first possible implementation of the first aspect, wherein the above method further includes: if the data volume of the Schur complement matrix S is greater than the L1 data cache capacity, then the Schur complement matrix S is used as a new coefficient matrix, and the step of dividing the coefficient matrix into four sub-block matrices and four sub-processes according to the basic block size is repeatedly executed until the data volume of the Schur complement matrix S is not greater than the L1 data cache capacity.

[0007] In conjunction with the first aspect, this embodiment of the invention provides a second possible implementation of the first aspect, wherein the above method further includes: when determining the size of the GEMM microkernel according to the AVX instruction set type, when the processor supports the AVX-512 instruction set, an 8×16 microkernel is used; when the processor supports the AVX2 instruction set, a 4×8 microkernel is used.

[0008] In conjunction with the first aspect, this embodiment of the invention provides a third possible implementation of the first aspect, wherein the coefficient matrix and right-hand side are constructed based on the image to be processed, and the method further includes: acquiring the image to be processed; determining the image block size according to the processing requirements of the image to be processed; dividing the image to be processed into blocks according to the image block size to obtain multiple image blocks; extracting the pixel features of each image block; and constructing the coefficient matrix and right-hand side based on the pixel features.

[0009] In conjunction with the third possible implementation of the first aspect, this embodiment of the invention provides a fourth possible implementation of the first aspect, wherein the above method further includes: converting the coefficient matrix and the right-hand side terms into a preset data type, and smoothing the coefficient matrix.

[0010] In conjunction with the third possible implementation of the first aspect, this embodiment of the invention provides a fifth possible implementation of the first aspect, wherein the above method further includes: mapping the solution of the solved linear equation system back to the pixel values ​​of the image block; fusing the pixel values ​​of each image block to obtain the target image corresponding to the image to be processed.

[0011] In conjunction with the first aspect, the present invention provides a sixth possible implementation of the first aspect, wherein the step of dividing the coefficient matrix into four sub-block matrices according to the basic block size includes: dividing the coefficient matrix into four sub-block matrices arranged in a 2×2 pattern according to the basic block size.

[0012] Secondly, embodiments of the present invention also provide a linear solver based on block LU and vectorization, the apparatus comprising: an acquisition module for acquiring the coefficient matrix to be solved and the right-hand side terms; a parameter reading module for reading the hardware parameters of the x86 architecture processor, wherein the hardware parameters include at least the L1 data cache capacity and the AVX instruction set types supported by the processor and the number of corresponding AVX vector registers; and a block partitioning module for setting a basic block size according to the L1 data cache capacity, and dividing the coefficient matrix into four sub-block matrices according to the basic block size, denoted as the first sub-block matrix. The block matrix A11, the second sub-block matrix A12, the third sub-block matrix A21, and the fourth sub-block matrix A22 are configured such that the data size of the first sub-block matrix does not exceed the L1 data cache capacity. A decomposition module is used to divide the LU decomposition process into four sequentially executed sub-processes, and to employ differentiated vectorized optimization strategies for the memory access patterns of each sub-process. These include: a basic decomposition sub-process: performing LU decomposition on the first sub-block matrix A11 to obtain a lower triangular matrix L11 and an upper triangular matrix U11; and a first solution sub-process: solving for the third sub-block matrix according to the formula L21·U11=A21. The lower triangular matrix L21 corresponds to matrix A21; before solving, the upper triangular matrix U11 is transposed and stored, so that the transposed upper triangular matrix U11 is arranged continuously in row priority, and a multi-level row direction register blocking strategy is adopted to load the transposed upper triangular matrix U11 into AVX vector registers in row blocks and perform multiplication and addition operations, wherein the number of rows in each row block is determined according to the number of AVX vector registers; the second solution sub-process: solve the upper triangular matrix U12 corresponding to the second sub-block matrix A12 according to the formula L11·U12=A12; without performing matrix transposition, directly according to The lower triangular matrix L11 is accessed in row-first order, and a multi-level column direction register blocking strategy is used to load the lower triangular matrix L11 into the AVX vector register in column blocks for multiplication and addition operations; the update sub-process calculates the Schul complement matrix S according to the formula S = A22 - L21·U12, using a strategy combining multi-level cache blocks and a GEMM microkernel, wherein the size of the GEMM microkernel is determined according to the AVX instruction set type; the output module is used to perform forward and backward substitution on the right-hand side terms based on the results of the LU decomposition process, and output the solution of the linear equation system.

[0013] The embodiments of the present invention bring the following beneficial effects: This invention provides a linear equation solving method and apparatus based on block LU and vectorization. The method acquires the coefficient matrix and right-hand side terms to be solved; reads the hardware parameters of the x86 architecture processor and sets a basic block size to divide the coefficient matrix into four sub-block matrices, ensuring that the data size of the first sub-block matrix does not exceed the L1 data cache capacity; further divides the LU decomposition process into four sub-processes, accelerating the solution for each sub-block matrix until each sub-block matrix is ​​decomposed; based on the results of the LU decomposition process, performs forward and backward substitutions on the right-hand side terms, and outputs the solution to the linear equation system. Since the basic block size is determined based on the hardware parameters of the x86 architecture processor, the data size of the first sub-block matrix after decomposition matches the processor's cache capacity, reducing the overhead of data splitting, improving the LU decomposition speed, and eliminating the need to read data from memory; the LU decomposition process is divided into four sequentially executed sub-processes, and vectorization optimization strategies are applied to each sub-process, which helps improve data reading speed and thus the solution rate.

[0014] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0015] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 A flowchart of a linear solution method based on block LU and vectorization provided in an embodiment of the present invention; Figure 2 A schematic diagram of LU decomposition provided in an embodiment of the present invention; Figure 3 A schematic diagram of a linear solver based on block LU and vectorization provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Currently, in image processing scenarios, the typical application process of existing technologies is as follows: First, the input image is divided into blocks, usually using rectangular blocks of fixed size, such as 64×64 or 32×32. For each image block, features such as pixel grayscale values ​​and gradient information are further extracted to construct a corresponding coefficient matrix A and right-hand side B, which are used to describe the linear relationship between pixels within the image block, such as pixel value fitting in grayscale compensation and signal recovery models in denoising. Then, matrix A and vector B are converted into double-precision floating-point numbers, and a general solution function is called to perform LU decomposition and solve Ax=b to obtain the linear solution result for each image block. Finally, the results of all blocks are merged to complete the entire image processing task.

[0020] Taking local grayscale compensation in an image as an example, in existing technologies, the main program reads the image to be processed from the image file, divides it into blocks of fixed size, and constructs a system of linear equations for each block. For example, matrix A describes the grayscale correlation between pixels, and vector B is the target grayscale value. Then, a general solution function is called to perform LU decomposition and solve the equations. Subsequently, the time taken to solve a single block is counted through multiple loops to complete the compensation of the entire image. In the existing solution process, the luDecomposition function is executed first. This function typically loops mainly in the column direction. If a singularity is detected in the matrix, the decomposition fails. If it can be decomposed, the numerical stability is improved by swapping matrix rows, and Gaussian elimination is used to complete the decomposition of the L and U matrices. Afterward, in the solveLU function, the LU decomposition results are used to perform forward and backward substitutions in sequence to finally obtain the solution of the system of linear equations. The solution is then mapped back to the pixel values ​​of the image blocks to complete the local compensation.

[0021] In image processing engineering applications, the above methods are often embedded in larger business processes. For example, in image compensation or correction tasks based on local blocks, if each 64×64 data block requires a linear solution, then for a 2k×2k data object, approximately 1600 LU decompositions may be required. For medical images (such as CT and MRI images), due to higher image resolution (e.g., 4k×4k) and deeper pixel depth (16-bit grayscale), the number of image blocks to be processed can reach over 6400. Furthermore, in image processing scenarios, image blocks often exhibit strong local correlation, uneven noise distribution, and significant pixel abrupt changes in edge regions. Existing general LU decomposition processes are not optimized for these characteristics, resulting in execution efficiency often becoming a bottleneck for overall system performance, failing to meet the latency requirements of real-time image processing (such as industrial online inspection and real-time image enhancement).

[0022] Based on this, the present invention provides a linear solution method and apparatus based on block LU and vectorization, which can combine the inherent characteristics of image data to design optimization strategies, significantly improve the execution efficiency of local linear solution tasks in image processing, and can be widely applied to sub-fields of image processing such as machine vision, image enhancement, image restoration, and medical image processing.

[0023] To facilitate understanding of this embodiment, a linear solution method based on block LU and vectorization disclosed in this embodiment of the invention will first be described in detail.

[0024] In one possible implementation, embodiments of the present invention provide a linear solution method based on block LU and vectorization, specifically, as follows: Figure 1 The flowchart shown illustrates a linear solution method based on block LU and vectorization, including the following steps: Step S102: Obtain the coefficient matrix and right-hand side terms to be solved; Step S104: Read the hardware parameters of the x86 architecture processor; Among them, the hardware parameters include at least the L1 data cache capacity and the types of AVX instruction sets supported by the processor and the number of corresponding AVX vector registers; Step S106: Set the basic block size according to the L1 data cache capacity, and divide the coefficient matrix into four sub-block matrices according to the basic block size, which are respectively denoted as the first sub-block matrix A11, the second sub-block matrix A12, the third sub-block matrix A21 and the fourth sub-block matrix A22, so that the data volume of the first sub-block matrix does not exceed the L1 data cache capacity. Here, the first sub-block matrix refers to the first sub-block matrix. In this embodiment of the invention, the data of the first sub-block matrix can be placed in the processor's cache; during decomposition, the data of the first sub-block matrix can be directly read from the cache for calculation.

[0025] Step S108: Divide the LU decomposition process into four sub-processes to be executed sequentially, and adopt a differentiated vectorization optimization strategy for the memory access mode of each sub-process. Specifically, the four sub-processes include: Basic decomposition sub-process: Perform LU decomposition on the first sub-block matrix A11 to obtain the lower triangular matrix L11 and the upper triangular matrix U11; First solution sub-process: Solve for the lower triangular matrix L21 corresponding to the third sub-block matrix A21 according to the formula L21·U11=A21; before solving, transpose the upper triangular matrix U11, so that the transposed upper triangular matrix U11 is arranged continuously in row priority, and adopt a multi-level row direction register blocking strategy to load the transposed upper triangular matrix U11 into the AVX vector register in row blocks and perform multiplication and addition operations. The number of rows in each row block is determined according to the number of AVX vector registers. The second solution process: Solve the upper triangular matrix U12 corresponding to the second sub-block matrix A12 according to the formula L11·U12=A12; without performing matrix transpose, directly access the lower triangular matrix L11 in row priority mode, and use a multi-level column direction register blocking strategy to load the lower triangular matrix L11 into the AVX vector register by column block to perform multiplication and addition operations. Update sub-process: Calculate the Shure complement matrix S according to the formula S = A22 - L21·U12, and adopt a strategy that combines multi-level cache block and GEMM microkernel. The size of GEMM microkernel is determined according to AVX instruction set type. Step S110: Based on the results of the LU decomposition process, perform forward and backward substitutions on the right-hand side terms to output the solution of the linear equation system.

[0026] This invention provides a linear equation solving method based on block LU and vectorization. It obtains the coefficient matrix and right-hand side terms to be solved; reads the hardware parameters of the x86 architecture processor and sets a basic block size to divide the coefficient matrix into four sub-block matrices, ensuring that the data size of the first sub-block matrix does not exceed the L1 cache capacity; further, the LU decomposition process is divided into four sub-processes, accelerating the solution for each sub-block matrix until each sub-block matrix is ​​decomposed; based on the results of the LU decomposition process, forward and backward substitutions are performed on the right-hand side terms, outputting the solution to the linear equation system. Since the basic block size is determined based on the hardware parameters of the x86 architecture processor, the data size of the decomposed sub-block matrices matches the processor's cache capacity, reducing the overhead of data splitting and eliminating the need to read data from memory; the LU decomposition process is divided into four sequentially executed sub-processes, and vectorization optimization strategies are applied to each sub-process, which helps improve data reading speed and thus the solution rate.

[0027] In practical use, the coefficient matrix and right-hand side of the embodiments of the present invention can be derived from image local blocks, CAE local field matrices, finite element matrixes, simulation fitting matrices, or other numerical calculation tasks. Specifically, in the embodiments of the present invention, taking image local blocks as an example, the linear solution method based on block LU and vectorization provided in the embodiments of the present invention can be applied to image processing scenarios. In this image processing scenario, the coefficient matrix A and right-hand side B are constructed based on the image to be processed. Therefore, the embodiments of the present invention also include the following processes: acquiring the image to be processed; determining the image block size according to the processing requirements of the image to be processed; dividing the image to be processed into blocks according to the image block size to obtain multiple image blocks; extracting the pixel features of each image block; and constructing the coefficient matrix and right-hand side based on the pixel features. Furthermore, in the embodiments of the present invention, the coefficient matrix and right-hand side can also be converted into a preset data type, and the coefficient matrix can be smoothed.

[0028] In specific implementation, the image to be processed can be an industrial inspection image, medical image, natural image, etc. The image format includes, but is not limited to, BMP, PNG, DICOM, etc. When determining the image block size, the image processing requirements considered can be local grayscale compensation processing, noise reduction processing, image enhancement processing, etc. In addition, the image block size in the embodiments of the present invention is preferably 64×64, 32×32, etc., which are adapted to commonly used image processing block sizes. The specific size depends on the actual use, and the embodiments of the present invention do not impose any restrictions on this.

[0029] Furthermore, when dividing the image into blocks, insufficient image blocks, such as those at edges, can be padded with zero or mirror padding to ensure that each image block has a uniform size and that the corresponding constructed coefficient matrix A is a square matrix. Moreover, when constructing the coefficient matrix A and the right-hand side B, pixel features of each image block can be extracted, such as grayscale values, gradient values, and neighboring pixel correlation values, to construct the coefficient matrix A. This coefficient matrix A describes the linear correlation between pixels within an image block. For example, in grayscale compensation, the elements of the coefficient matrix A represent the influence weights of adjacent pixels, while the right-hand side B represents the target pixel value or the corrected pixel value.

[0030] The coefficient matrix A and the right-hand side B mentioned above need to be further converted into a data type suitable for numerically stable calculations, such as preferably double-precision floating-point numbers CV_64F. At the same time, in view of image noise characteristics, the coefficient matrix A can be slightly smoothed, such as neighborhood mean filtering, to avoid matrix singularity caused by noise and improve the stability of the solution.

[0031] Furthermore, for the coefficient matrix A and right-hand side B of the image patch obtained in the above construction process, the above process can be further performed. Figure 1 The process. Furthermore, each image block can perform the above... Figure 1 The process involves fusing all image patches and outputting the final processed target image.

[0032] Furthermore, the block partitioning strategy in step S106 above, which sets the basic block size based on the L1 data cache capacity, is based on the cache of the X86 architecture processor. In this embodiment of the invention, all data in the calculation process is placed in the cache for processing to improve the processing speed.

[0033] Furthermore, for the obtained sub-block matrix, its data volume does not exceed the L1 data cache capacity, so that the data volume of the sub-block matrix can be stored in the L1 data cache; and adjacent sub-block matrices are associated according to the preset local correlation, and the associated sub-block matrices are stored in the L1 data cache.

[0034] For example, if the data size of the sub-block matrix is ​​64×64, the basic block size determined based on the L1 data cache capacity can be directly set to 64×64, so that the sub-block matrix is ​​close to the capacity of an L1 cache. At the same time, using the local correlation of the image to be processed to correlate the coefficient matrices of adjacent image blocks can improve the cache hit rate, further helping to improve the data reading speed.

[0035] Furthermore, in this embodiment of the invention, if the amount of data in the Schul complement matrix S obtained in the update sub-process of step S108 is greater than the L1 data cache capacity, then the Schul complement matrix S is used as a new coefficient matrix, and the steps of dividing the coefficient matrix into four sub-block matrices and four sub-processes according to the basic block size are repeated until the amount of data in the Schul complement matrix S is not greater than the L1 data cache capacity.

[0036] For ease of understanding, Figure 2 A schematic diagram of LU decomposition is shown. In this embodiment of the invention, when the coefficient matrix is ​​divided into four sub-block matrices according to the basic block size, the coefficient matrix can be divided into four sub-block matrices arranged in a 2×2 pattern. That is, in Figure 2 In Figure (a), the coefficient matrix is ​​divided into four sub-matrices: A11, A12, A21, and A22. The above basic decomposition sub-process corresponds to... Figure 2 In (b), that is, the first sub-block matrix A11 is divided into a lower triangular matrix L11 and an upper triangular matrix U11, corresponding to the formula L11·U11=A11.

[0037] Furthermore, the first solution sub-process is the process of solving the lower triangular matrix L21 corresponding to the third sub-block matrix A21; the second solution sub-process is the process of solving the upper triangular matrix U12 corresponding to the second sub-block matrix A12; in this embodiment of the invention, the first and second solution sub-processes adopt an asymmetric optimization strategy; specifically, when executing the first solution sub-process, the upper triangular matrix U11 is transposed and stored before solving, so that the transposed upper triangular matrix U11 is arranged continuously in row priority, and a multi-level row direction register blocking strategy is adopted to continuously load the transposed upper triangular matrix U11 into AVX vector registers in row blocks. Multiplication and addition operations are performed in the memory, where the number of rows in each row block is determined by the number of AVX vector registers. For example, based on the fact that AVX2 has 16 YMM registers, various block sizes can be designed, such as 40 rows (10 YMM registers), 32 rows (8 YMM registers), 16 rows (4 YMM registers), 8 rows (2 YMM registers), and 4 rows (1 YMM register). The selection of each block size is based on the fact that 10 YMM registers × 4 doubles = 40 elements, which exactly covers a complete row block. After transposing and completing the calculation, the result is transposed back to its original position. Furthermore, in this first solution process, the continuity of cache access can be improved through matrix transposition and vectorization. Specifically, in traditional matrix operations, data is stored continuously row by row. In this embodiment of the invention, when using SIMD (Single Instruction, Multiple Data) instructions, the processor may skip data in the cache. In this embodiment of the invention, taking into account the characteristic of image data being stored row by row first, the matrix is ​​transposed and stored first, so that data can be read continuously during vectorized loading, thereby giving full play to the advantages of SIMD instructions.

[0038] Furthermore, during the execution of the second solution sub-process described above, a direct row access and multi-level column-direction register blocking strategy is adopted. That is, matrix transposition is not performed; the lower triangular matrix L11 is accessed directly in row-major order. A multi-level column-direction register blocking strategy is used to load the lower triangular matrix L11 into column blocks in the AVX vector register for multiplication and addition operations. This direct row access mode is naturally adapted to row-major storage; therefore, matrix transposition is unnecessary. For column-direction partitioning, a 40 / 32 / 16 / 8 / 4 column partitioning strategy can be used, and parallel computation is achieved through AVX2 vector accumulation. Specifically, this process corresponds to... Figure 2 In (d), the process of solving U12 based on L11 decomposed from (b) corresponds to the formula: L11 U12=A12. In specific implementation, SIMD vectorization can be used to perform multiplication, addition, and update operations; for example, considering the continuous storage characteristics of the image matrix, the loading method of vectorized instructions can be optimized, and continuous loading instructions (such as _mm512_loadu_pd) can be used to load data to reduce memory access latency; in addition, considering the characteristics of batch solving of image blocks, in this embodiment of the invention, the second solving subprocess is optimized by loop expansion to reduce the overhead of loop control.

[0039] Furthermore, in this embodiment of the invention, when executing the above-mentioned update sub-process, a strategy combining multi-level cache block partitioning and the GEMM microkernel is adopted. Multi-level cache block partitioning adapts to the processor's cache, and the GEMM microkernel enables register-level data reuse to improve performance. Specifically, in this process, the remaining sub-block A22 is updated matrix based on L21 and U12, and the corresponding formula can be expressed as: L21 U12+L22 Given U22=A22, we can deduce the formula for calculating the S matrix as: S=L22 U22=A22-L21 U12, where S matrix is ​​the Shure complement matrix S in this embodiment of the invention, and the update sub-process here can essentially be reduced to matrix multiplication and subtraction operations, implemented using a register-friendly microkernel. Specifically, if the processor supports the AVX512 instruction set architecture, an 8×16 microkernel is selected; if the processor supports the AVX2 instruction set architecture, a 4×8 microkernel is selected. If the processor does not support the AVX instruction set architecture, a block size of M=32, N=32, K=48 is used as the block size strategy for matrix block computation, so that the data blocks during the computation process are adapted to the processor's L1 cache capacity.

[0040] Furthermore, in this embodiment of the invention, corresponding optimization strategies can be designed for the different sub-processes. Specifically, the basic decomposition sub-processes that are not easy to improve can be kept stable. For the first solution sub-process, the second solution sub-process, and the update sub-process that are suitable for vectorization, AVX2 or AVX512 hardware instruction set optimization can be adopted. Especially for image processing scenarios, the vectorization optimization process of the first solution sub-process and the second solution sub-process can fully combine the continuous storage characteristics of image data, and the microkernel optimization process of the update sub-process can combine the characteristics of image batch block solving to maximize optimization benefits.

[0041] Furthermore, for the AVX2 platform, it is preferable to fully utilize the 16 YMM registers; for the AVX512 platform, it is preferable to fully utilize the 32 ZMM registers to improve instruction-level parallelism and data reuse efficiency. Considering the characteristics of batch block solving in image processing, a register reuse strategy can be designed to temporarily store intermediate calculation results of multiple image blocks in registers, reducing frequent exchanges between registers and memory and further improving efficiency. Furthermore, in this embodiment of the invention, compiler optimization options can be combined for further acceleration, including but not limited to loop unrolling options and fast math options, to reduce loop control overhead and improve floating-point computation throughput. For example, for image processing scenarios, the compiler's "data prefetch" optimization option can be enabled, taking into account the continuous storage characteristics of image data, to prefetch the subsequent image block matrix data to be processed into the cache in advance, reducing cache miss rate.

[0042] Furthermore, in this embodiment of the invention, after completing the above LU decomposition, the principal component information can be used to perform a permutation on the right-hand side B, followed by forward and backward substitutions, thereby outputting the solution of the linear equation system containing the coefficient matrix and the right-hand side terms; and, considering the characteristics of the image solution results, this embodiment of the invention can also limit the range of the solution (e.g., limit the pixel grayscale value to 0~255 or 0~65535) to avoid the solution results exceeding the reasonable range of image pixels and improve the image processing effect.

[0043] Furthermore, during the solution process, the first SIMD instruction set is typically used for the GEMM (Geometric Multiplication) stage of matrix multiplication and the TRSM (Triangular Matrix Equation Solving) stage of upper and lower triangular matrices, while the second SIMD instruction set is used for the forward and backward substitution stages, forming a hybrid instruction set scheduling strategy. The first SIMD instruction set has more registers than the second SIMD instruction set. The first SIMD instruction set is suitable for the large number of intermediate result resident registers required in the GEMM and TRSM stages, where the 16 YMM registers of AVX2 are more appropriate. The second SIMD instruction set, on the other hand, is suitable for the vector dot product reduction requirements in the forward and backward substitution stages, where the 8-element reduction of AVX512 is more efficient.

[0044] Furthermore, in this embodiment of the invention, the coefficient matrix and right-hand side obtained in step S102 typically refer to the data of one image patch in the image to be processed. However, for the entire image to be processed, there are multiple image patches. Therefore, this embodiment of the invention implements a batch task scenario, that is, for multiple image patches of multiple images to be processed, the above steps can be repeatedly called. Figure 1 The process involves writing the results back to the corresponding image block, grid block, cell block, or local region.

[0045] Furthermore, in image processing scenarios, the solutions to the linear equations obtained can be mapped back to the pixel values ​​of the image blocks; the pixel values ​​of each image block can be fused to obtain the target image corresponding to the image to be processed. For example, the solution results can be mapped back to the pixel values ​​of the corresponding image blocks, the edge padding can be de-filled, and the results of all image blocks can be fused to obtain a complete processed image. At the same time, interpolation smoothing and other processing methods can be used to eliminate stitching marks between image blocks and improve image quality.

[0046] Furthermore, for ease of understanding, the following explanation uses an industrial inspection CCD image as an example. It is assumed that the image to be processed has a resolution of 4k×4k, 8-bit grayscale, and a pixel value range of 0~255. The image to be processed also exhibits local grayscale inhomogeneity, such as areas with low grayscale caused by lighting and shadows, requiring linear grayscale compensation for each image block. Using an image block size of 64×64, approximately 6400 LU decompositions are required. In addition, the image contains slight salt-and-pepper noise (noise pixels account for approximately 2%), and there are significant abrupt changes in pixel grayscale at the edges, requiring high accuracy and stability in the solution process.

[0047] In practice, the block partitioning strategy can be determined first. Assuming that the L1 cache capacity of the processor is 32KB, the basic block size can be set to 64×64 (32768 bytes of double-precision data), which perfectly matches the image block size and reduces the overhead of data splitting and fusion. By utilizing the local correlation of the image, the blocks of adjacent image blocks are associated and scheduled, and the block data of adjacent image blocks are prefetched into the cache at the same time, thereby improving the cache hit rate.

[0048] Furthermore, the coefficient matrix A constructed for each image patch can undergo 3×3 neighborhood mean smoothing to eliminate the influence of salt-and-pepper noise. Further, during vectorization optimization, taking into account the row-first, contiguous storage characteristic of image data, the matrix is ​​transposed in the first solution process, and parallel computation is performed using AVX512 vector instructions (_mm512_loadu_pd, _mm512_fmadd_pd) to fully leverage the advantages of SIMD instructions; in the second solution process, loop unrolling optimization is enabled, with the loop step size set to 8 to reduce loop control overhead.

[0049] Furthermore, during the result fusion, the solution results for each image block are limited to a range of 0~255, the edge filling is removed, and the bilinear interpolation algorithm is used to smooth the image block stitching area to eliminate stitching marks.

[0050] Based on the above optimizations, the results show that the decomposition time of a single image block is reduced from the original 1142 microseconds to 205 microseconds, and the processing time of the entire image is reduced from 18.2 seconds to 3.1 seconds, which is about 5.87 times faster. The processed image has uniform local grayscale, clear edges, no splicing traces, and good noise suppression effect, which meets the processing requirements of industrial inspection images.

[0051] Further optimization of the microkernel is carried out. In this embodiment, the microkernel is organized around the 32 ZMM registers of the AVX512 platform, and the intermediate calculation results of multiple image blocks are temporarily stored in the registers to reduce the frequent exchange between registers and memory. In the update sub-process, the matrix multiplication and subtraction operations are optimized by drawing on the idea of ​​GEMM microkernel to improve the calculation efficiency.

[0052] In practice, high-precision floating-point calculations are used during the forward and backward replacement processes to ensure that the accuracy of the solution results meets the requirements of medical image processing.

[0053] Furthermore, the task of solving multiple image patches can be scheduled in parallel to make full use of the CPU's multi-core resources and improve batch processing efficiency; the compiler's data prefetching optimization can be enabled to prefetch the image patch matrix data to be processed later into the cache in advance, reducing the cache miss rate.

[0054] Furthermore, in this embodiment of the invention, in order to adapt to the image processing scenario, hardware matching and block selection can also be performed. For example, processors that support AVX2 and AVX512 series instructions can be matched, and the L1 cache capacity can be queried and recorded. Then, a block strategy can be determined for different image block sizes in the image processing scenario. For example, for a 64×64 image block (a commonly used size for industrial inspection images), the double-precision matrix data volume is 64×64×8=32768 bytes, which is a perfect match with the L1 cache capacity. Therefore, the basic block size is set to 64×64, so that the block data can reside in the L1 cache throughout the process, improving memory access efficiency.

[0055] Furthermore, for extended matrices of image patches, such as 175×175 or 275×275 matrices, the block partitioning strategy can better balance computational density and memory access locality, while adapting to the image patch size and reducing data splitting and fusion overhead, demonstrating excellent performance in image processing scenarios.

[0056] Furthermore, considering the row-first, contiguous storage characteristic of image data, the vectorized loading method is optimized by employing continuous loading instructions to reduce memory access latency and further improve vectorization efficiency. In the first solution subprocess, AVX512 optimization combined with transpose processing improves memory access continuity and significantly enhances performance. Simultaneously, by utilizing local image correlations, L21 solution results from adjacent blocks are reused, reducing redundant computations and improving batch processing efficiency. Moreover, the update subprocess employs a GEMM-like microkernel design to fully utilize register resources. For example, considering the characteristics of batch block solving of images, the update subprocess is scheduled in parallel to fully utilize CPU multi-core resources, further improving batch processing efficiency.

[0057] In summary, the linear solution method based on block LU and vectorization provided in this invention significantly improves the execution efficiency of LU decomposition and linear solution for small-to-medium-scale dense matrices by using a block strategy for cache matching, employing SIMD vectorization, and combining microkernel and compilation optimization. Especially considering the specific characteristics of image processing scenarios, targeted optimization strategies are designed to improve efficiency while maintaining solution accuracy and image processing quality. Specific technical effects are as follows: (1) The block-based strategy, combined with the image block size characteristics of image processing, decomposes the matrix into local sub-block matrices that are more suitable for L1 cache processing instead of performing the matrix decomposition as a whole. The basic block size matches the image block size, reducing the overhead of data splitting and fusion. At the same time, by utilizing the local correlation of images, the blocks of adjacent image blocks are correlated and scheduled, further reducing the cache miss rate. Since the hot working set is smaller, the processor can reduce the number of times it reads data from the low-level cache or main memory when performing local block operations, thus reducing the memory access wait time and significantly improving the efficiency of solving batch image blocks.

[0058] (2) After decomposing LU into four sub-processes: basic decomposition sub-process, first solution sub-process for basic decomposition sub-process, second solution sub-process for basic decomposition sub-process, and update sub-process for remaining blocks, different optimizations can be implemented according to their respective computational characteristics. At the same time, based on the characteristics of continuous storage of image data, noise distribution, and edge block mutation, targeted adjustments can be made to each sub-process. For example, for the first solution sub-process and the second solution sub-process, the vectorized loading method can be optimized based on the characteristics of continuous image storage, and the parallel scheduling of the update sub-process can be optimized based on the characteristics of batch block solving of images. This targeted optimization is more effective than uniform processing of the entire process.

[0059] (3) The processor’s microkernel organizes computation around the 16 YMM registers of the AVX2 platform and the 32 ZMM registers of the AVX512 platform. It can retain more intermediate results inside the registers, reduce repeated memory access and temporary variable write-back, thereby improving the throughput of computation. In view of the characteristics of batch block solving in image processing, the designed register reuse strategy further reduces the frequent exchange between registers and memory, and improves the efficiency of batch processing.

[0060] (4) In addition, by using loop unrolling and fast mathematical compilation options, the number of loop control instructions can be reduced, the parallelism of the floating-point pipeline can be enhanced, and the critical path time can be further compressed. The enabled data prefetch optimization, combined with the continuous storage characteristics of image data, prefetches the image block matrix data for subsequent processing into the cache in advance, further reducing the cache miss rate. While ensuring that the result error is within an acceptable range (the image processing scenario requires an error of less than 1e-6), it can meet the dual requirements of correctness and efficiency for engineering applications.

[0061] (5) Finally, the results of each image block are fused, and the solution results can be range-limited, defilled and interpolated to smooth them, eliminating image block splicing traces, improving image processing quality, and solving the problem of obvious splicing traces after solving image blocks in the prior art; the optimization of image noise and edge block features improves the stability and accuracy of the solution, ensuring that the image processing effect meets the actual application requirements.

[0062] Furthermore, test results show that in a single-process scenario with a 175×175 matrix, 1000 loops, the original latency was approximately 1142 microseconds, while the optimized latency was approximately 205 microseconds, representing a speedup of approximately 5.58 times. In a single-process scenario with a 275×275 matrix, 1000 loops, the original latency was approximately 4132 microseconds, while the optimized latency was approximately 701 microseconds, representing a speedup of approximately 5.89 times. Stable performance gains were also observed in multi-process scenarios, indicating that this invention not only improves single-task latency but also has good concurrent applicability, meeting the needs of high-resolution image batch processing.

[0063] Test results for specific image processing scenarios show that in the local grayscale compensation task of 4k×4k industrial inspection images (block size 64×64, total 6400 image blocks), the existing technology takes about 18.2 seconds, while the optimized method provided in this embodiment takes about 3.1 seconds, an acceleration of about 5.87 times. In the local enhancement task of medical images (CT images, resolution 2k×2k, block size 32×32, total 4096 image blocks), the existing technology takes about 7.6 seconds, while the optimized method in this embodiment takes about 1.3 seconds, an acceleration of about 5.85 times. Moreover, the processed image has clear edges, no stitching marks, and better noise suppression effect.

[0064] Furthermore, the linear solution method based on block LU and vectorization provided in this embodiment of the invention focuses on the general matrix decomposition and linear solution process itself, rather than specific business semantics. Therefore, it can be naturally transferred to CAE local solution, finite element level matrix processing, local fitting in simulation post-processing, industrial online correction, and other applications of solving repetitive small matrices. At the same time, the optimized design for image processing scenarios gives it more significant advantages in this field, further enhancing the application value of this embodiment of the invention.

[0065] Furthermore, based on the above embodiments, this invention also provides a linear solution device based on block LU and vectorization, such as... Figure 3 The diagram shows a structural schematic of a linear solver based on block LU and vectorization. The solver includes: Module 30 is used to obtain the coefficient matrix and right-hand side terms to be solved; The parameter reading module 32 is used to read the hardware parameters of the X86 architecture processor, wherein the hardware parameters include at least the L1 data cache capacity and the AVX instruction set types supported by the processor and the number of corresponding AVX vector registers; The block segmentation module 34 is used to set a basic block size according to the L1 data cache capacity, and divide the coefficient matrix into four sub-block matrices according to the basic block size, which are respectively denoted as the first sub-block matrix A11, the second sub-block matrix A12, the third sub-block matrix A21 and the fourth sub-block matrix A22, so that the data volume of the first sub-block matrix does not exceed the L1 data cache capacity. The decomposition module 36 is used to divide the LU decomposition process into four sub-processes that are executed sequentially, and to adopt differentiated vectorized optimization strategies for the memory access patterns of each sub-process, including: Basic decomposition sub-process: Perform LU decomposition on the first sub-block matrix A11 to obtain the lower triangular matrix L11 and the upper triangular matrix U11; First solution sub-process: Solve the lower triangular matrix L21 corresponding to the third sub-block matrix A21 according to the formula L21·U11=A21; before solving, perform transpose storage on the upper triangular matrix U11 so that the transposed upper triangular matrix U11 is arranged continuously in row priority, and adopt a multi-level row direction register blocking strategy to load the transposed upper triangular matrix U11 into the AVX vector register in row blocks and perform multiplication and addition operations, wherein the number of rows in each row block is determined according to the number of AVX vector registers; The second solution process: Solve the upper triangular matrix U12 corresponding to the second sub-block matrix A12 according to the formula L11·U12=A12; without performing matrix transpose, directly access the lower triangular matrix L11 in row priority mode, and use a multi-level column direction register blocking strategy to load the lower triangular matrix L11 into the AVX vector register by column blocks to perform multiplication and addition operations. Update sub-process: Calculate the Shure complement matrix S according to the formula S = A22 - L21·U12, and adopt a strategy that combines multi-level cache block and GEMM microkernel, wherein the size of the GEMM microkernel is determined according to the AVX instruction set type; Output module 38 is used to perform forward and backward substitutions on the right-hand side terms based on the results of the LU decomposition process, and output the solution of the linear equation system.

[0066] The linear solver based on block LU and vectorization provided in this embodiment of the invention has the same technical features as the linear solver based on block LU and vectorization provided in the above embodiment, so it can also solve the same technical problems and achieve the same technical effects.

[0067] Furthermore, embodiments of the present invention also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above method.

[0068] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the above-described method.

[0069] Furthermore, embodiments of the present invention also provide a schematic diagram of the structure of an electronic device, such as... Figure 4 The diagram shows the structure of the electronic device, which includes a processor 41 and a memory 40. The memory 40 stores computer-executable instructions that can be executed by the processor 41, and the processor 41 executes the computer-executable instructions to implement the above-described method.

[0070] exist Figure 4 In the illustrated embodiment, the electronic device further includes a bus 42 and a communication interface 43, wherein the processor 41, the communication interface 43, and the memory 40 are connected via the bus 42.

[0071] The memory 40 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 43 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 42 may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus 42 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0072] Processor 41 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 41 or by software instructions. Processor 41 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this invention can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in the memory, and the processor 41 reads the information in the memory and uses its hardware to complete the aforementioned method.

[0073] The computer program product of the linear solution method and apparatus based on block LU and vectorization provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0074] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0075] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0076] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0077] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0078] Finally, it should be noted that the above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A linear solution method based on block LU and vectorization, characterized in that, The method includes: Obtain the coefficient matrix and right-hand side terms to be solved; Read the hardware parameters of the x86 architecture processor, wherein the hardware parameters include at least the L1 data cache capacity and the AVX instruction set types supported by the processor and the number of corresponding AVX vector registers; Based on the L1 data cache capacity, the basic block size is set, and the coefficient matrix is ​​divided into four sub-block matrices according to the basic block size, which are respectively denoted as the first sub-block matrix A11, the second sub-block matrix A12, the third sub-block matrix A21 and the fourth sub-block matrix A22, so that the data volume of the first sub-block matrix does not exceed the L1 data cache capacity. The LU decomposition process is divided into four sub-processes executed sequentially, and a differentiated vectorized optimization strategy is adopted for the memory access mode of each sub-process, including: Basic decomposition sub-process: Perform LU decomposition on the first sub-block matrix A11 to obtain the lower triangular matrix L11 and the upper triangular matrix U11; First solution sub-process: Solve the lower triangular matrix L21 corresponding to the third sub-block matrix A21 according to the formula L21·U11=A21; before solving, perform transpose storage on the upper triangular matrix U11 so that the transposed upper triangular matrix U11 is arranged continuously in row priority, and adopt a multi-level row direction register blocking strategy to load the transposed upper triangular matrix U11 into the AVX vector register in row blocks and perform multiplication and addition operations, wherein the number of rows in each row block is determined according to the number of AVX vector registers; The second solution process: Solve the upper triangular matrix U12 corresponding to the second sub-block matrix A12 according to the formula L11·U12=A12; without performing matrix transpose, directly access the lower triangular matrix L11 in row priority mode, and use a multi-level column direction register blocking strategy to load the lower triangular matrix L11 into the AVX vector register by column blocks to perform multiplication and addition operations. Update sub-process: Calculate the Shure complement matrix S according to the formula S = A22 - L21·U12, and adopt a strategy that combines multi-level cache block and GEMM microkernel, wherein the size of the GEMM microkernel is determined according to the AVX instruction set type; Based on the results of the LU decomposition process, forward and backward substitutions are performed on the right-hand side terms to output the solution of the linear equation system.

2. The method according to claim 1, characterized in that, The method further includes: If the data size of the Schul complement matrix S is greater than the L1 data cache capacity, then the Schul complement matrix S is used as a new coefficient matrix, and the step of dividing the coefficient matrix into four sub-block matrices and four sub-processes according to the basic block size is repeated until the data size of the Schul complement matrix S is not greater than the L1 data cache capacity.

3. The method according to claim 1, characterized in that, The method further includes: When determining the size of the GEMM microkernel based on the AVX instruction set type, an 8×16 microkernel is used when the processor supports the AVX-512 instruction set; and a 4×8 microkernel is used when the processor supports the AVX2 instruction set.

4. The method according to claim 1, characterized in that, The coefficient matrix and right-hand side are constructed based on the image to be processed. The method further includes: Obtain the image to be processed, and determine the image block size according to the processing requirements of the image to be processed; The image to be processed is divided into blocks according to the image block size to obtain multiple image blocks; Extract the pixel features of each image block, and construct the coefficient matrix based on the pixel features.

5. The method according to claim 4, characterized in that, The method further includes: The coefficient matrix and the right-hand side are converted to a preset data type, and the coefficient matrix is ​​smoothed.

6. The method according to claim 4, characterized in that, The method further includes: The solution to the system of linear equations is mapped back to the pixel values ​​of the image block; By fusing the pixel values ​​of each image block, the target image corresponding to the image to be processed is obtained.

7. The method according to claim 1, characterized in that, The step of dividing the coefficient matrix into four sub-block matrices according to the basic block size includes: The coefficient matrix is ​​divided into four sub-block matrices arranged in a 2×2 pattern according to the basic block size.

8. A linear solver based on block LU and vectorization, characterized in that, The device includes: The acquisition module is used to obtain the coefficient matrix and right-hand side terms to be solved; The parameter reading module is used to read the hardware parameters of the x86 architecture processor, wherein the hardware parameters include at least the L1 data cache capacity and the AVX instruction set types supported by the processor and the number of corresponding AVX vector registers; The block segmentation module is used to set a basic block size according to the L1 data cache capacity, and divide the coefficient matrix into four sub-block matrices according to the basic block size, which are respectively denoted as the first sub-block matrix A11, the second sub-block matrix A12, the third sub-block matrix A21 and the fourth sub-block matrix A22, so that the data volume of the first sub-block matrix does not exceed the L1 data cache capacity. The decomposition module is used to divide the LU decomposition process into four sub-processes that are executed sequentially, and to employ differentiated vectorized optimization strategies for the memory access patterns of each sub-process, including: Basic decomposition sub-process: Perform LU decomposition on the first sub-block matrix A11 to obtain the lower triangular matrix L11 and the upper triangular matrix U11; First solution sub-process: Solve the lower triangular matrix L21 corresponding to the third sub-block matrix A21 according to the formula L21·U11=A21; before solving, perform transpose storage on the upper triangular matrix U11 so that the transposed upper triangular matrix U11 is arranged continuously in row priority, and adopt a multi-level row direction register blocking strategy to load the transposed upper triangular matrix U11 into the AVX vector register in row blocks and perform multiplication and addition operations, wherein the number of rows in each row block is determined according to the number of AVX vector registers; The second solution process: Solve the upper triangular matrix U12 corresponding to the second sub-block matrix A12 according to the formula L11·U12=A12; without performing matrix transpose, directly access the lower triangular matrix L11 in row priority mode, and use a multi-level column direction register blocking strategy to load the lower triangular matrix L11 into the AVX vector register by column blocks to perform multiplication and addition operations. Update sub-process: Calculate the Shure complement matrix S according to the formula S = A22 - L21·U12, and adopt a strategy that combines multi-level cache block and GEMM microkernel, wherein the size of the GEMM microkernel is determined according to the AVX instruction set type; The output module is used to perform forward and backward substitutions on the right-hand side terms based on the results of the LU decomposition process, and output the solution of the linear equation system.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps of the method described in any one of claims 1-7.

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