A hardware security architecture that integrates physical fuse-locking with AES-256 encrypted storage

Abstract

The application provides a kind of hardware security architecture integrating physical fuse locking and AES-256 encryption storage, belongs to integrated circuit and information security technical field, the architecture takes the security protection core in the chip independent security island as pivot, integrates encryption storage unit, fuse control unit, distributed sensor array and security management unit.Encryption storage unit carries AES-256 hardware encryption engine, adopts root key-data encryption key layered management system;Fuse control unit is physically connected with key access path, encryption engine enable end;Distributed sensor array multidimensional monitoring physical attack signal.The architecture sets two-level response mechanism of dynamic locking and physical fuse, triggers according to threat level classification, realizes temporary protection under suspicious attack and key irreversible destruction under high intensity intrusion.The application deeply couples encryption storage and physical self-destruction mechanism, builds in-depth defense system, and gives consideration to high performance and high security.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuits and information security technology, specifically to a hardware security architecture for embedded chips to protect critical data and firmware, and more particularly to a hardware security architecture that integrates a physical fuse locking mechanism and AES-256 encrypted storage. Background Technology

[0002] With the proliferation of the Internet of Things (IoT), mobile computing, and edge devices, hardware faces increasingly severe security threats, including physical attacks, side-channel attacks, and firmware tampering. Traditional software encryption schemes have shortcomings in key management and resistance to physical attacks, while single hardware encryption modules, although improving performance, still pose a risk that their stored static encrypted data can be extracted and analyzed in the face of physical disassembly or side-channel attacks.

[0003] In existing technologies, hardware security solutions employ an independent security domain (SE) within the eSIM chip for hardware isolation and tamper-proof design, with built-in sensors detecting physical attacks. Another solution utilizes a "security island" design in automotive-grade MCUs, integrating an encryption engine and an tamper-proof controller, using sensor arrays to detect anomalies and trigger data destruction. Furthermore, physical fuse technology, as a hardware-level self-destruct mechanism, can permanently damage critical circuits or erase keys upon detecting tampering, providing an extremely high level of defense. However, existing solutions often treat encrypted storage and physical fuse as independent modules, lacking a deeply collaborative and systematic architectural design, making it difficult to provide ultimate, irreversible protection against physical intrusion while ensuring high-performance encrypted storage.

[0004] Therefore, there is an urgent need for a security architecture that can deeply integrate high-strength data encryption with hardware-level physical self-destruct mechanisms to address the increasingly complex hardware security challenges. Summary of the Invention

[0005] To address the shortcomings of existing hardware security solutions in the coordination of physical protection and encrypted storage, this invention provides a hardware security architecture that integrates physical circuit breaker locking with AES-256 encrypted storage. Using the Security Protection Core (SPC) as the system hub, it deeply couples the AES-256 hardware encryption engine, hierarchical key system, physical circuit breaker array, distributed sensor array, and security management unit at the hardware level. This achieves the security goals of end-to-end encryption protection during runtime, tiered response to intrusions, and irreversible data destruction in ultimate scenarios, fundamentally enhancing the hardware device's ability to resist physical attacks and data theft.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows: This invention provides a hardware security architecture that integrates physical fuse locking and AES-256 encrypted storage, including an AES encryption module and a physical fuse unit. The hardware security architecture takes the Security Protection Core (SPC) integrated in the chip's independent security island as the system hub. The Security Protection Core (SPC) includes an encrypted storage unit, a fuse control unit, a distributed sensor array, and a Security Management Unit (SMU). The encrypted storage unit integrates an AES-256 hardware encryption engine, which is deployed between the storage controller and the physical storage medium to perform real-time encryption and decryption of sensitive data. It adopts a hierarchical key management architecture of root key-data encryption key (DEK). The fuse control unit includes one or more sets of electrically programmable non-volatile fuse arrays. The fuse arrays are physically directly connected to the key access path of the encrypted storage unit and the encryption engine enable terminal. The fuse state irreversibly determines the access permissions and key material availability of the encrypted storage unit. The distributed sensor array is deployed at key physical locations on the security island map to monitor physical attack signals in real time and output the detection data to the fault aggregation logic for processing to generate a fault state vector. The Security Management Unit (SMU) is the control center of the security protection core. It has a built-in multi-level threat judgment strategy and hardware security state machine. It is interconnected with the encrypted storage unit and the fuse control unit through a bus, and receives fault state vectors and sensor alarm signals. The hardware security architecture features a dual-modal hierarchical response mechanism of locking and circuit breaking: the first-level response is dynamic locking, whereby when the Security Management Unit (SMU) detects a suspicious attack signal, it controls the encrypted storage unit to suspend encryption and decryption operations and clear the plaintext key; the second-level response is physical circuit breaking, whereby when the Security Management Unit (SMU) confirms a high-intensity physical attack, it controls the circuit breaking control unit to burn the specified fuse, permanently cutting off the key access path or disabling the encryption engine.

[0007] As a further aspect of the present invention, the AES-256 hardware encryption engine supports AES-256-GCM and AES-256-XTS certified encryption modes, independently performing 14 rounds of encryption operations including byte substitution, row shifting, column obfuscation, and round key addition, without consuming the main CPU's computing power. The encryption engine is set to three working modes: normal encryption / decryption, dynamic locking, and debug bypass. The mode switching is controlled at the hardware level by both the Security Management Unit (SMU) instructions and the fuse status.

[0008] As a further aspect of the present invention, in the hierarchical key management architecture, the root key is generated by a physically unclonable function (PUF) during the chip manufacturing stage, permanently stored in a fuse-protected one-time programmable (OTP) area, and never leaves the security boundary in plaintext form; the data encryption key (DEK) is generated based on the HMAC key derivation function (HKDF) combined with the root key and the authorization factor, and stored in a hardware-isolated key register and protected SRAM. The root key is used to encrypt and protect the data encryption key (DEK), and the DEK is used to directly encrypt user data and firmware code.

[0009] As a further aspect of the present invention, the fuse array body is made of polycrystalline silicon material, and the critical path is equipped with aluminum / copper / nickel-chromium metal fuses for redundancy; its electrical parameters meet the following requirements: resistance is 30–200Ω when not blown, the fuse-breaking judgment resistance threshold is ≥1MΩ, the high-reliability scenario judgment threshold is ≥10MΩ, the fuse-breaking programming current is 5–20mA, it is driven by a stepped wave pulse, the programming pulse width is from several μs to hundreds of μs, and the physical structure is permanently disconnected and cannot be recovered after the fuse is blown.

[0010] As a further aspect of the present invention, the fuse array has 32 bits and is divided into three main groups: a security control group, a key destruction group, and a lifecycle group, wherein: The security control group includes the JTAG_DISABLE, ISP_DISABLE, BOOT_LOCK, ROLLBACK_DIS, and ANALOG_TEST_DIS fuse bits, which correspond to the functions of disabling debug port, disabling in-system programming, locking secure boot area, disabling firmware rollback, and disabling simulation test mode, respectively. The key destruction group includes the fuse bits KILL_PRIMARY_ROOT, KILL_SECONDARY_ROOT, KILL_SESSION_CACHE, TAMPER_EVIDENCE, and KEY_LADDER_FUSE, which correspond to the functions of primary root key destruction, secondary root key destruction, session key cache destruction, intrusion evidence marking, and key chain cascading destruction, respectively. The lifecycle group includes the LC_PSV_RMA, LC_FIELD_RET, LC_OEM_LOCK, and FIPS_COMPLIANCE fuse bits, which correspond to the after-sales repair mode, the field return analysis mode, the OEM manufacturer lock, and the mandatory compliance lock function, respectively. The remaining fuse bits are reserved for extension bits.

[0011] As a further aspect of the present invention, the fuse control unit has built-in fuse verification and fault tolerance logic, and automatically performs cyclic redundancy check (CRC) on the fuse array each time it is powered on; it supports two fuse triggering methods: one is to receive a software fuse triggering command issued by the security management unit (SMU) through the APB bus, and the other is to receive a hardware direct-connection emergency triggering signal from the encrypted storage unit side. After the fuse is triggered, the status register is automatically updated and an acknowledgment signal is returned to the security management unit (SMU).

[0012] As a further aspect of the present invention, the distributed sensor array comprises 11 independent sensor front-ends, specifically including: Four voltage sensors are deployed on the encryption engine power rail VDD_SEC_A, the SMU power rail VDD_SEC_B, the fuse charge pump power rail VDD_EFUSE, and the key cache power rail VDD_SRAM, respectively. Three temperature sensors are deployed at the heat distribution center directly above the encryption engine, next to the eFuse controller, and at the edge of the security island layout. Two light intensity sensors are deployed on the front of the chip, one below the metal shielding layer and the other directly above the key storage area. Two clock disturbance detectors are deployed at the output of the independent RC oscillator in the safety island and at the synchronization bridge between the safety island and the main system clock domain, respectively.

[0013] As a further aspect of the invention, all sensors employ a dual-level threshold mechanism of warning and lethality, including: For the safety island power supply rail, the voltage sensor has a normal range of 1.2V ± 5%, a warning threshold of below 1.08V or above 1.32V, and a fatal threshold of below 0.95V or above 1.50V; for the fuse charge pump power supply rail, the normal range is 3.3V ± 10%, the warning threshold is below 2.8V, and the fatal threshold is below 2.0V. The normal operating range of the temperature sensor is -40°C to 125°C. The warning threshold is when the temperature exceeds this range, and the fatal threshold is when the local temperature rise slope is >50°C / ms or the local temperature is >150°C. The light intensity sensor operates normally in a 0 lux dark environment, with a warning threshold of continuous light intensity greater than 10 lux and a lethal threshold of instantaneous pulse light intensity greater than 10,000 lux. The clock disturbance detector has a nominal clock frequency of 10MHz, a normal range of 10MHz ±2%, a warning threshold of frequency deviation ±5%, and a fatal threshold of frequency deviation ±15% or single-cycle width mutation >30%.

[0014] As a further aspect of the present invention, the sampling and output parameters of each sensor in the distributed sensor array satisfy the following: The voltage sensor uses a 12-bit ADC with a resolution of approximately 0.8mV / LSB and a sampling frequency of 10MSa / s. After downsampling to 1MSa / s, it is output with an on-chip digital low-pass filter and a cutoff frequency of 500kHz. The temperature sensor has a resolution of 0.0625°C / LSB, an absolute accuracy of ±2°C, a sampling frequency of 1kSa / s, and uses an 8-point moving average window filter, updating the value every 1ms. The light intensity sensor uses 10-bit quantization, a sampling frequency of 100MSa / s, edge-triggered latching without filtering, and directly outputs a hardware interrupt signal when the threshold is exceeded. The clock disturbance detector is based on TDC time-to-digital conversion with a resolution of <50ps. It monitors once per clock cycle, uses an 8-cycle sliding window to calculate the jitter variance, and outputs a 16-bit jitter statistical value and a 1-bit hardware alarm flag.

[0015] As a further embodiment of the present invention, the fault aggregation logic receives the detection data from all sensors, compares it with a preset threshold through a comparator array, and outputs an 8-bit fault state vector fault_vector[7:0] to the Safety Management Unit (SMU); where bit0 corresponds to voltage sensor warning, bit1 corresponds to voltage sensor fatal alarm, bit2 corresponds to temperature sensor warning, bit3 corresponds to temperature sensor fatal alarm, bit4 corresponds to light intensity sensor warning, bit5 corresponds to light intensity sensor fatal alarm, bit6 corresponds to clock disturbance warning, and bit7 corresponds to clock disturbance fatal alarm; the fatal alarms for light intensity and clock disturbance are simultaneously connected to the asynchronous interrupt pin of the Safety Management Unit (SMU) through a dedicated hardwired connection.

[0016] As a further embodiment of the present invention, the safety island adopts an independent clock and an independent power supply: a global clock sec_clk is provided by an independent RC oscillator, which supports dynamic switching between a 32.768kHz low-power mode and a 10MHz full-speed mode; a 1.2V / 3.3V isolated power rail VDD_SEC is provided by an independent LDO, which is physically isolated from the main system power supply and keeps it in a constantly on state.

[0017] As a further embodiment of the present invention, the security management unit (SMU), the encrypted storage unit, and the fuse control unit are all interconnected via an AMBAAPB slave interface, with an interface data width of 32 bits and a maximum operating frequency of ≤50MHz. The APB interface signals between the Security Management Unit (SMU) and the Encryption Storage Unit include paddr[7:0], pwdata[31:0], prdata[31:0], pwrite, penable, and psel, which are used to configure encryption engine parameters, read and write key storage status, and support loading of national cryptographic algorithm keys. The APB interface signals between the Safety Management Unit (SMU) and the Fuse Control Unit include f_addr[7:0], f_wdata[31:0], f_rdata[31:0], f_write, f_enable, and f_sel, which are used to issue fuse commands and read the fuse status register. The fuse operation is irreversible after it is written.

[0018] As a further aspect of the present invention, a dedicated hardware trigger signal key_kill_req and an acknowledgment signal key_kill_ack are provided between the encrypted storage unit and the circuit breaker control unit for triggering emergency circuit breaking of the hard connection in anti-tampering scenarios, asynchronously or synchronously with the 10MHz security island clock.

[0019] As a further aspect of the present invention, two types of interaction interfaces are provided between the security management unit (SMU) and the main system: The 2-bit interrupt signal sec_int[1:0], where bit0 is a recoverable alarm interrupt and bit1 is a fatal error interrupt that triggers a system reset. The interface is in asynchronous mode. The 16-bit unidirectional read-only security status bus sec_status[15:0] is synchronized with the main system clock and has a maximum frequency of ≤200MHz. It is used by the main core to read fault codes and fuse status.

[0020] As a further aspect of the present invention, the specific execution process of the dynamic locking of the first-level response is as follows: after the Security Management Unit (SMU) detects a suspicious attack signal, it sends a hardware locking command to the encrypted storage unit, suspends all encryption and decryption operations, clears the plaintext key register and operation buffer, retains only the encrypted DEK, cuts off the data path between the encrypted storage unit and the main system, and sends a recoverable alarm interrupt to the main system; after the attack is resolved and the authorization verification is passed, the system can resume normal operation.

[0021] As a further aspect of the present invention, the physical fusion of the second-order response produces two types of irreversible consequences: First, key destruction: burn the fuse corresponding to the key destruction group to permanently cut off the physical access path of the root key. At the same time, the hardware triggers the automatic erasure of the key buffer. All DEKs protected by the root key cannot be decrypted, and all encrypted data is permanently invalidated. Second, function disablement: After the corresponding fuse is burned out, the enable signal of the AES hardware encryption engine is permanently pulled low, and the encrypted storage function is completely disabled at the hardware level.

[0022] Compared with existing technologies, the hardware security architecture integrating physical fuse locking and AES-256 encrypted storage provided in this application has the following advantages: 1. A comprehensive defense-in-depth system significantly raises the attack threshold: A multi-layered threat perception system has been constructed, from software anomaly monitoring and hardware bus monitoring to physical signal perception. Coupled with a two-level response mechanism of dynamic software locking and irreversible physical circuit breaking, a defense-in-depth system has been formed, covering all scenarios of attacks from low-risk anomalies to high-intensity physical intrusions. Attackers need to break through both cryptographic and physical protection barriers at the same time, and the attack cost and technical threshold increase exponentially.

[0023] 2. Deep hardware-level linkage, mandatory security policy: The physical circuit breaker mechanism provides the ultimate means to combat physical attacks. Through direct hardware connection of signal lines and state machine logic, it realizes direct control of key access and encryption engine in the circuit breaker state without software intervention, avoiding the risk of software logic being tampered with and bypassed; sensor fatal alarms are directly connected to the circuit breaker trigger circuit through hardwire, with a response delay of microseconds, which can effectively intercept high-speed physical attacks in the nanosecond to microsecond range.

[0024] 3. High-performance encryption implementation, balancing security and operational efficiency: AES-256 encryption and decryption are executed independently by a dedicated hardware engine, supporting high-speed data storage such as AES-NI instruction set acceleration, ensuring high-performance requirements for encrypting and storing large amounts of data, with power consumption far lower than software implementation solutions, perfectly adapting to application scenarios with high real-time requirements such as industrial control and automotive electronics.

[0025] 4. Strong compliance and adaptability, covering multiple application fields: The AES-256 algorithm complies with international security standards such as NISTFIPS, and the physical circuit breaker and anti-tampering mechanism meet the hardware security compliance concept. The entire architecture can be adapted to high-security scenarios such as financial terminals, government equipment, vehicle network controllers, and industrial control chips. Attached Figure Description

[0026] Figure 1 This is a flowchart of a hardware security architecture that integrates physical fuse locking and AES-256 encrypted storage, provided by the present invention.

[0027] Figure 2 This is a schematic diagram of the encrypted storage and hierarchical key management structure in a hardware security architecture that integrates physical fuse locking and AES-256 encrypted storage, provided by the present invention.

[0028] Figure 3 This is a flowchart of the overall security threat detection and graded response in a hardware security architecture that integrates physical fuse locking and AES-256 encrypted storage, provided by the present invention.

[0029] Figure 4 This is a flowchart of the circuit breaker control execution sub-flow in a hardware security architecture that integrates physical circuit breaker locking and AES-256 encrypted storage, provided by the present invention. Detailed Implementation

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] To address the shortcomings of existing hardware security solutions in the coordination of physical protection and encrypted storage, this invention provides a hardware security architecture that integrates physical circuit breaker locking with AES-256 encrypted storage. Using the Security Protection Core (SPC) as the system hub, it deeply couples the AES-256 hardware encryption engine, hierarchical key system, physical circuit breaker array, distributed sensor array, and security management unit at the hardware level. This achieves the security goals of end-to-end encryption protection during runtime, tiered response to intrusions, and irreversible data destruction in ultimate scenarios, fundamentally enhancing the hardware device's ability to resist physical attacks and data theft.

[0033] See Figures 1 to 4 As shown, the present invention provides a hardware security architecture that integrates physical fuse locking and AES-256 encrypted storage, including an AES encryption module and a physical fuse unit. The hardware security architecture takes the Security Protection Core (SPC) integrated in the independent security island of the chip as the system hub. The Security Protection Core (SPC) includes an encrypted storage unit, a fuse control unit, a distributed sensor array, and a Security Management Unit (SMU).

[0034] The encrypted storage unit integrates an AES-256 hardware encryption engine, deployed between the storage controller and the physical storage medium, for real-time encryption and decryption of sensitive data. It adopts a hierarchical key management architecture of root key-data encryption key (DEK) to perform transparent real-time encryption and decryption of sensitive data in the off-chip Flash and on-chip secure storage areas.

[0035] In this embodiment, the AES-256 hardware encryption engine supports AES-256-GCM and AES-256-XTS authenticated encryption modes. It independently performs 14 rounds of encryption operations, including byte substitution, row shifting, column obfuscation, and round key addition. It is compatible with authenticated encryption modes such as AES-256-GCM and AES-256-XTS, while ensuring data confidentiality and integrity. The operation process is completed independently by dedicated hardware circuitry, without consuming the main CPU's computing power, meeting the performance requirements of high-throughput storage scenarios. The encryption engine has three working modes: normal encryption / decryption, dynamic locking, and debug bypass. Mode switching is controlled at the hardware level by both the Security Management Unit (SMU) instructions and fuse status.

[0036] The hierarchical key management architecture adopts a two-level key system of root key and data encryption key (DEK). The root key (also known as the hardware unique key HUK) is generated by a physically unclonable function (PUF) during the chip manufacturing stage, permanently stored in a fuse-protected OTP (one-time programmable) and never leaves the security boundary in plaintext. The root key is used to encrypt and protect the data encryption key (DEK). The data encryption key (DEK) is generated based on the HMAC key derivation function HKDF combined with the root key and the authorization factor, and is stored in a hardware-isolated key register and protected SRAM. The root key is used to encrypt and protect the data encryption key DEK, and the DEK is used to directly encrypt user data and firmware code.

[0037] The fuse control unit includes one or more arrays of electrically programmable non-volatile fuses. These fuse arrays are physically directly connected to the key access path of the encrypted storage unit and the encryption engine enable terminal. The fuse state irreversibly determines the access permissions and key material availability of the encrypted storage unit. In this embodiment, the fuse array body is made of polycrystalline silicon, with aluminum / copper / nickel-chromium metal fuses used for redundancy along the critical path. Its electrical parameters meet the following requirements: resistance of 30–200Ω when not blown, fuse-breaking threshold resistance ≥1MΩ, high-reliability scenario threshold ≥10MΩ, fuse-breaking programming current of 5–20mA, driven by a stepped-wave pulse, with a programming pulse width of several μs to hundreds of μs. After blowing, the physical structure is permanently disconnected and cannot be recovered. The fuse state directly determines the access permissions and key material availability of the encrypted storage unit. Under normal conditions, the fuse remains connected, and the system can access encrypted data normally. The fuse control unit receives trigger signals from the sensor array and the security management unit (SMU). The sensor array is integrated inside the chip or in a key package location to monitor physical attack signals in real time, including but not limited to abnormal voltage, abnormal temperature, abnormal light intensity (detecting opening of the cover), clock frequency disturbances, etc. The Security Management Unit (SMU) acts as the "brain" of the architecture, continuously receiving and analyzing sensor data, bus access monitoring signals, and software-layer anomaly reports. The SMU has preset multi-level threat judgment strategies.

[0038] In this embodiment, the fuse array has 32 bits, divided into three groups: a security control group, a key destruction group, and a lifecycle group. The security control group includes JTAG_DISABLE, ISP_DISABLE, BOOT_LOCK, ROLLBACK_DIS, and ANALOG_TEST_DIS fuse bits, corresponding to functions such as debug port shutdown, in-system programming shutdown, secure boot area locking, firmware rollback disabling, and simulation test mode shutdown, respectively. The key destruction group includes KILL_PRIMARY_ROOT, KILL_SECONDARY_ROOT, K... The ILL_SESSION_CACHE, TAMPER_EVIDENCE, and KEY_LADDER_FUSE fuse bits correspond to the functions of primary root key destruction, secondary root key destruction, session key cache destruction, intrusion evidence marking, and key chain cascading destruction, respectively. The lifecycle group includes the LC_PSV_RMA, LC_FIELD_RET, LC_OEM_LOCK, and FIPS_COMPLIANCE fuse bits, which correspond to the functions of after-sales repair mode, on-site return analysis mode, OEM manufacturer locking, and mandatory compliance locking, respectively. The remaining fuse bits are reserved for future expansion.

[0039] In this embodiment, the fuse control unit has built-in fuse verification and fault tolerance logic, and automatically performs CRC verification on the fuse array each time it is powered on; it supports two fuse triggering methods: one is to receive the software fuse triggering command issued by the security management unit (SMU) through the APB bus, and the other is to receive the hardware direct connection emergency triggering signal from the encrypted storage unit side. After the fuse is triggered, the status register is automatically updated and a confirmation signal is returned to the security management unit (SMU).

[0040] The distributed sensor array is deployed at key physical locations on the security island layout to monitor physical attack signals in real time. The output detection data is processed by the fault aggregation logic to generate a fault state vector. In this embodiment, the fault aggregation logic receives the detection data from all sensors, compares it with a preset threshold through a comparator array, and outputs an 8-bit fault state vector fault_vector[7:0] to the security management unit (SMU). Bit 0 corresponds to voltage sensor warning, bit 1 corresponds to voltage sensor fatal alarm, bit 2 corresponds to temperature sensor warning, bit 3 corresponds to temperature sensor fatal alarm, bit 4 corresponds to light intensity sensor warning, bit 5 corresponds to light intensity sensor fatal alarm, bit 6 corresponds to clock disturbance warning, and bit 7 corresponds to clock disturbance fatal alarm. The fatal alarms for light intensity and clock disturbance are simultaneously connected to the asynchronous interrupt pin of the security management unit (SMU) via a dedicated hardwired connection.

[0041] In this embodiment, the distributed sensor array comprises 11 independent sensor front-ends, specifically including: Four voltage sensors are deployed on the encryption engine power rail VDD_SEC_A, the SMU power rail VDD_SEC_B, the fuse charge pump power rail VDD_EFUSE, and the key cache power rail VDD_SRAM, respectively. Three temperature sensors are deployed at the heat distribution center directly above the encryption engine, next to the eFuse controller, and at the edge of the security island layout. Two light intensity sensors are deployed on the front of the chip, one below the metal shielding layer and the other directly above the key storage area. Two clock disturbance detectors are deployed at the output of the independent RC oscillator in the safety island and at the synchronization bridge between the safety island and the main system clock domain, respectively.

[0042] In this embodiment, the safety island adopts an independent clock and an independent power supply: a global clock sec_clk is provided by an independent RC oscillator, which supports dynamic switching between a 32.768kHz low-power mode and a 10MHz full-speed mode; a 1.2V / 3.3V isolated power rail VDD_SEC is provided by an independent LDO, which is physically isolated from the main system power supply and keeps it in a constantly on state.

[0043] In this embodiment, all sensors employ a two-tiered threshold mechanism of warning and lethality, including: For the safety island power supply rail, the voltage sensor has a normal range of 1.2V ± 5%, a warning threshold of below 1.08V or above 1.32V, and a fatal threshold of below 0.95V or above 1.50V; for the fuse charge pump power supply rail, the normal range is 3.3V ± 10%, the warning threshold is below 2.8V, and the fatal threshold is below 2.0V. The normal operating range of the temperature sensor is -40°C to 125°C. The warning threshold is when the temperature exceeds this range, and the fatal threshold is when the local temperature rise slope is >50°C / ms or the local temperature is >150°C. The light intensity sensor operates normally in a 0 lux dark environment, with a warning threshold of continuous light intensity greater than 10 lux and a lethal threshold of instantaneous pulse light intensity greater than 10,000 lux. The clock disturbance detector has a nominal clock frequency of 10MHz, a normal range of 10MHz ±2%, a warning threshold of frequency deviation ±5%, and a fatal threshold of frequency deviation ±15% or single-cycle width mutation >30%.

[0044] In this embodiment, the sampling and output parameters of each sensor in the distributed sensor array satisfy the following: The voltage sensor uses a 12-bit ADC with a resolution of approximately 0.8mV / LSB and a sampling frequency of 10MSa / s. After downsampling to 1MSa / s, it is output with an on-chip digital low-pass filter and a cutoff frequency of 500kHz. The temperature sensor has a resolution of 0.0625°C / LSB, an absolute accuracy of ±2°C, a sampling frequency of 1kSa / s, and uses an 8-point moving average window filter, updating the value every 1ms. The light intensity sensor uses 10-bit quantization, a sampling frequency of 100MSa / s, edge-triggered latching without filtering, and directly outputs a hardware interrupt signal when the threshold is exceeded. The clock disturbance detector is based on TDC time-to-digital conversion with a resolution of <50ps. It monitors once per clock cycle, uses an 8-cycle sliding window to calculate the jitter variance, and outputs a 16-bit jitter statistical value and a 1-bit hardware alarm flag.

[0045] The Security Management Unit (SMU) is the control center of the security protection core. It has a built-in multi-level threat judgment strategy and hardware security state machine. It is interconnected with the encrypted storage unit and the fuse control unit through a bus, and receives fault status vectors and sensor alarm signals. The hardware security architecture has a dual-modal hierarchical response mechanism of locking and circuit breaking: the first-level response is dynamic locking, when the security management unit (SMU) detects a suspicious attack signal, it controls the encrypted storage unit to suspend encryption and decryption operations and clear the plaintext key; the second-level response is physical circuit breaking, when the security management unit (SMU) confirms a high-intensity physical attack, it controls the circuit breaking control unit to burn the specified fuse, permanently cutting off the key access path or disabling the encryption engine.

[0046] In this embodiment, the security management unit (SMU), the encrypted storage unit, and the fuse control unit are all interconnected via the AMBAAPB slave interface. The interface data width is 32 bits, and the maximum operating frequency is ≤50MHz. The APB interface signals between the Security Management Unit (SMU) and the Encryption Storage Unit include paddr[7:0], pwdata[31:0], prdata[31:0], pwrite, penable, and psel, which are used to configure encryption engine parameters, read and write key storage status, and support loading of national cryptographic algorithm keys. The APB interface signals between the Safety Management Unit (SMU) and the Fuse Control Unit include f_addr[7:0], f_wdata[31:0], f_rdata[31:0], f_write, f_enable, and f_sel, which are used to issue fuse commands and read the fuse status register. The fuse operation is irreversible after it is written.

[0047] In this embodiment, a dedicated hardware trigger signal key_kill_req and an acknowledgment signal key_kill_ack are set between the encrypted storage unit and the fuse control unit for triggering emergency fuse breaking of the hard connection in anti-tampering scenarios, asynchronously or synchronously with the 10MHz security island clock.

[0048] In this embodiment, two types of interaction interfaces are set up between the security management unit (SMU) and the main system: The 2-bit interrupt signal sec_int[1:0], where bit0 is a recoverable alarm interrupt and bit1 is a fatal error interrupt that triggers a system reset. The interface is in asynchronous mode. The 16-bit unidirectional read-only security status bus sec_status[15:0] is synchronized with the main system clock and has a maximum frequency of ≤200MHz. It is used by the main core to read fault codes and fuse status.

[0049] In this embodiment, the specific execution process of the dynamic locking in the first-level response is as follows: After the Security Management Unit (SMU) detects a suspicious attack signal, it sends a hardware lock command to the encrypted storage unit, suspends all encryption and decryption operations, clears the plaintext key register and operation buffer, retains only the encrypted DEK, cuts off the data path between the encrypted storage unit and the main system, and sends a recoverable alarm interrupt to the main system; after the attack is resolved and the authorization verification is passed, the system can resume normal operation. Specifically, in the dynamic locking of the first-level response, when the SMU detects a suspicious but unconfirmed attack (such as a slight voltage fluctuation), it immediately sends a command to the encrypted storage unit to put it into a locked state. In this state, all encryption or decryption operations are suspended, the plaintext key in memory is cleared, only the encrypted DEK is retained, the system function is degraded but the data is not corrupted.

[0050] In this embodiment, when the SMU confirms a high-intensity physical attack, such as detecting opening the cover, voltage spike attacks, or unauthorized debugging interface access, it sends a final command to the fuse control unit. The fuse control unit immediately burns the designated physical fuse. The secondary response of the physical fuse produces two types of irreversible consequences: First, key destruction: Burning the fuse corresponding to the key destruction group permanently cuts off the physical access path to the root key. At the same time, the hardware triggers the automatic erasure of the key buffer. All DEKs protected by the root key cannot be decrypted, and all encrypted data is permanently invalidated. The consequence of this fuse breaking is key destruction. Burning the fuse can permanently cut off the access path to the root key in the PUF circuit or secure storage area, causing all DEKs protected by the root key to be unable to be decrypted, thus making all encrypted data permanently "invalid".

[0051] Second, functional disabling: After the corresponding fuse is burned, the enable signal of the AES hardware encryption engine is permanently lowered, and the encrypted storage function is completely disabled at the hardware level. The consequence of this fuse failure is functional disabling. Burning the fuse can also directly and permanently disable the enable signal of the AES hardware encryption engine, causing the encrypted storage function to fail at the hardware level. Even if an attacker obtains the storage medium, they will not be able to decrypt it using the chip's own hardware.

[0052] The hardware security architecture in this embodiment achieves end-to-end protection for sensitive data and firmware intellectual property through a deep coupling of a physical fuse locking mechanism and AES-256 hardware encrypted storage. It is adaptable to high-security scenarios such as IoT terminals, automotive controllers, industrial control equipment, and financial security chips. The enable signal of the AES hardware encryption engine disables the encrypted storage function at the hardware level, so even if an attacker obtains the storage medium, they cannot decrypt it using the chip's hardware.

[0053] The following description, with reference to the accompanying drawings, uses an embedded SoC chip integrating this architecture as an example to illustrate specific embodiments of the present invention in detail.

[0054] Example 1 This embodiment provides a security architecture integrated into a smart chessboard main control chip for data protection of embedded smart devices. The execution steps of this hardware security architecture are as follows: Step 1, Initialization: When the chip powers on, the PUF circuit generates a unique root key for the device and writes it into the security fuse protection zone. The system uses this root key to encrypt and generate a DEK, which is used to encrypt private data such as chess game records and user habits and send it to external Flash.

[0055] Step 2, Normal Operation: During gameplay, data is encrypted using an AES-256 hardware engine before storage. Upon retrieval, the hardware engine decrypts the data in real time, with the CPU processing only the plaintext.

[0056] Step 3, Encountering an Attack: If an attacker attempts to inject a fault through the power pin, the sensor array detects an abnormal voltage, the SMU initiates a Level 1 response, immediately locking the encryption engine and clearing the relevant registers.

[0057] If the attacker continues to attempt to physically open the chip and probe its internal bus, both the optical sensor and the bus monitor will trigger alarms. The SMU will determine this as a high-intensity physical intrusion and initiate a level-two response. The fuse control unit will then burn the fuse connected to the PUF access circuit within microseconds.

[0058] Step 4, Attack Result: The root key access path is permanently severed. Even if the attacker removes the Flash memory chip, they cannot decrypt the data because the key material required for decryption has been physically destroyed inside the chip.

[0059] Example 2 This embodiment provides an application of this architecture in an automotive-grade MCU that meets the ISO / SAE 21434 standard, serving as a secure boot and firmware protection mechanism for automotive-grade controllers. The execution steps of this hardware security architecture are as follows: Step 1, Secure Startup: The Bootloader code snippet and initial key are protected by an encrypted storage unit. During startup, the SMU first checks the fuse status and only allows decryption and execution of the Bootloader after confirming there is no record of physical intrusion.

[0060] Step 2, Firmware Update: The encrypted firmware package received via secure communication is decrypted by the AES-256 hardware engine and written to the code area.

[0061] Step 3, Anti-tampering: If an attacker attempts to extract memory through the debugging interface while the vehicle is running, the SMU will trigger a fuse, directly burning the fuse on the connection to the encryption engine enable end, permanently disabling the hardware encryption and decryption function, making all subsequent secure boots and firmware operation impossible, thereby protecting the deployed firmware logic from reverse engineering.

[0062] As can be seen from the above embodiments, the present invention achieves seamless collaboration between encrypted storage and physical self-destruction mechanisms through deep integration at the hardware level, providing chip-level high-strength security protection for various key hardware devices.

[0063] In summary, the hardware security architecture integrating physical circuit breaker locking and AES-256 encrypted storage provided by this invention enables a complete defense-in-depth system, significantly raising the attack threshold. It constructs a multi-layered threat perception system from software anomaly monitoring and hardware bus monitoring to physical signal sensing. Combined with a two-level response mechanism of dynamic software locking and irreversible physical circuit breaker locking, it forms a defense-in-depth system covering all attack scenarios from low-risk anomalies to high-intensity physical intrusions. Attackers must simultaneously overcome both cryptographic and physical protection barriers, resulting in an exponential increase in attack costs and technical barriers. This invention features deep hardware-level linkage, enforced security policies, and a physical circuit breaker mechanism that provides the ultimate means of combating physical attacks. Through direct hardware connection to signal lines and state machine logic, it achieves direct control of key access and encryption engine during the circuit breaker state without software intervention, avoiding the risk of software logic being tampered with or bypassed. Sensor fatal alarms are directly connected to the circuit breaker trigger circuit via hardwired connections, with a response latency down to the microsecond level, effectively intercepting high-speed physical attacks at the nanosecond to microsecond level. This invention offers a high-performance encryption implementation that balances security and operational efficiency. AES-256 encryption and decryption are executed independently by a dedicated hardware engine, supporting high-speed data storage acceleration through instruction sets such as AES-NI. This ensures high-performance requirements for encrypting and storing large amounts of data, with power consumption significantly lower than software implementations. It is perfectly suited for applications with high real-time requirements, such as industrial control and automotive electronics. This invention boasts strong compliance and adaptability, covering multiple application fields. The AES-256 algorithm complies with international security standards such as NISTFIPS, and physical circuit breaking and anti-tampering mechanisms meet hardware security compliance requirements. The entire architecture is adaptable to high-security scenarios such as financial terminals, government equipment, vehicle network controllers, and industrial control chips.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art can still combine, add, delete, or otherwise adjust the features of the various embodiments of the present invention according to the circumstances without conflict or creative effort, thereby obtaining different technical solutions that do not fundamentally depart from the concept of the present invention. These technical solutions also fall within the scope of protection of the present invention.

Claims

1. A hardware security architecture integrating physical fuse locking and AES-256 encrypted storage, characterized in that, The hardware security architecture includes an AES encryption module and a physical fuse unit. The security protection core, which is integrated into the chip's independent security island, serves as the system's central hub. The security protection core includes an encrypted storage unit, a fuse control unit, a distributed sensor array, and a security management unit. The encrypted storage unit integrates an AES-256 hardware encryption engine, which is deployed between the storage controller and the physical storage medium to perform real-time encryption and decryption of sensitive data. It adopts a hierarchical key management architecture of root key-data encryption key. The fuse control unit includes one or more sets of electrically programmable non-volatile fuse arrays. The fuse arrays are physically directly connected to the key access path of the encrypted storage unit and the encryption engine enable terminal. The fuse state irreversibly determines the access permissions and key material availability of the encrypted storage unit. The distributed sensor array is deployed at key physical locations on the security island map to monitor physical attack signals in real time and output the detection data to the fault aggregation logic for processing to generate a fault state vector. The security management unit is the control center of the security protection core. It has a built-in multi-level threat judgment strategy and hardware security state machine. It is interconnected with the encrypted storage unit and the fuse control unit through a bus, and receives fault status vectors and sensor alarm signals. The hardware security architecture has a dual-modal hierarchical response mechanism of locking and circuit breaking: the first-level response is dynamic locking, when the security management unit detects a suspicious attack signal, it controls the encrypted storage unit to suspend encryption and decryption operations and clear the plaintext key; The second-level response is physical circuit breaking. When the security management unit confirms a high-intensity physical attack, it controls the circuit breaking control unit to burn the specified fuse, permanently cutting off the key access path or disabling the encryption engine.

2. The hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, The AES-256 hardware encryption engine supports AES-256-GCM and AES-256-XTS with authentication encryption modes. It independently performs 14 rounds of encryption operations, including byte substitution, row shifting, column obfuscation, and round key addition, without consuming the main CPU's computing power. The encryption engine is set to three working modes: normal encryption / decryption, dynamic locking, and debug bypass. The mode switching is controlled at the hardware level by both the security management unit instructions and the fuse status.

3. The hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, In the hierarchical key management architecture, the root key is generated by a physically unclonable function during the chip manufacturing stage, permanently stored in a one-time programmable area protected by a fuse, and never leaves the security boundary in plaintext form; the data encryption key is generated based on the HMAC key derivation function combined with the root key and the authorization factor, and stored in a hardware-isolated key register and protected SRAM. The root key is used to encrypt and protect the data encryption key, and the data encryption key is used to directly encrypt user data and firmware code.

4. The hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, The fuse array body is made of polycrystalline silicon material, and the critical path is equipped with aluminum / copper / nickel-chromium metal fuses for redundancy. Its electrical parameters meet the following requirements: resistance is 30–200Ω when not blown, resistance threshold for blown judgment is ≥1MΩ, threshold for high reliability scenario judgment is ≥10MΩ, programming current for blown is 5–20mA, stepped wave pulse drive is used, programming pulse width is from several μs to hundreds of μs, and the physical structure is permanently disconnected and cannot be recovered after blown.

5. A hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, The fuse array has 32 bits and is divided into three main groups: security control group, key destruction group, and lifecycle group. The security control group includes the JTAG_DISABLE, ISP_DISABLE, BOOT_LOCK, ROLLBACK_DIS, and ANALOG_TEST_DIS fuse bits, which correspond to the functions of disabling debug port, disabling in-system programming, locking secure boot area, disabling firmware rollback, and disabling simulation test mode, respectively. The key destruction group includes the fuse bits KILL_PRIMARY_ROOT, KILL_SECONDARY_ROOT, KILL_SESSION_CACHE, TAMPER_EVIDENCE, and KEY_LADDER_FUSE, which correspond to the functions of primary root key destruction, secondary root key destruction, session key cache destruction, intrusion evidence marking, and key chain cascading destruction, respectively. The lifecycle group includes the LC_PSV_RMA, LC_FIELD_RET, LC_OEM_LOCK, and FIPS_COMPLIANCE fuse bits, which correspond to the after-sales repair mode, the field return analysis mode, the OEM manufacturer lock, and the mandatory compliance lock function, respectively. The remaining fuse bits are reserved for extension bits.

6. A hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, The fuse control unit has built-in fuse verification and fault tolerance logic, and automatically performs cyclic redundancy check on the fuse array every time it is powered on. It supports two fuse triggering methods: one is to receive the software fuse triggering command issued by the security management unit through the APB bus, and the other is to receive the hardware direct connection emergency triggering signal from the encrypted storage unit. After the fuse is triggered, the status register is automatically updated and an acknowledgment signal is returned to the security management unit.

7. A hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, The distributed sensor array comprises 11 independent sensor front-ends, specifically including: Four voltage sensors are deployed on the encryption engine power rail VDD_SEC_A, the SMU power rail VDD_SEC_B, the fuse charge pump power rail VDD_EFUSE, and the key cache power rail VDD_SRAM, respectively. Three temperature sensors are deployed at the heat distribution center directly above the encryption engine, next to the eFuse controller, and at the edge of the security island layout. Two light intensity sensors are deployed on the front of the chip, one below the metal shielding layer and the other directly above the key storage area. Two clock disturbance detectors are deployed at the output of the independent RC oscillator in the safety island and at the synchronization bridge between the safety island and the main system clock domain, respectively.

8. A hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, All sensors employ a two-tiered threshold mechanism with both warning and lethal thresholds, including: For the safety island power supply rail, the voltage sensor has a normal range of 1.2V ± 5%, a warning threshold of below 1.08V or above 1.32V, and a fatal threshold of below 0.95V or above 1.50V; for the fuse charge pump power supply rail, the normal range is 3.3V ± 10%, the warning threshold is below 2.8V, and the fatal threshold is below 2.0V. The normal operating range of the temperature sensor is -40°C to 125°C. The warning threshold is when the temperature exceeds this range, and the fatal threshold is when the local temperature rise slope is >50°C / ms or the local temperature is >150°C. The light intensity sensor operates normally in a 0 lux dark environment, with a warning threshold of continuous light intensity greater than 10 lux and a lethal threshold of instantaneous pulse light intensity greater than 10,000 lux. The clock disturbance detector has a nominal clock frequency of 10MHz, a normal range of 10MHz ±2%, a warning threshold of frequency deviation ±5%, and a fatal threshold of frequency deviation ±15% or single-cycle width mutation >30%.

9. A hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, The sampling and output parameters of each sensor in the distributed sensor array satisfy the following: The voltage sensor uses a 12-bit ADC with a resolution of approximately 0.8mV / LSB and a sampling frequency of 10MSa / s. After downsampling to 1MSa / s, it is output with an on-chip digital low-pass filter and a cutoff frequency of 500kHz. The temperature sensor has a resolution of 0.0625°C / LSB, an absolute accuracy of ±2°C, a sampling frequency of 1kSa / s, and uses an 8-point moving average window filter, updating the value every 1ms. The light intensity sensor uses 10-bit quantization, a sampling frequency of 100MSa / s, edge-triggered latching without filtering, and directly outputs a hardware interrupt signal when the threshold is exceeded. The clock disturbance detector is based on TDC time-to-digital conversion with a resolution of <50ps. It monitors once per clock cycle, uses an 8-cycle sliding window to calculate the jitter variance, and outputs a 16-bit jitter statistical value and a 1-bit hardware alarm flag.

10. A hardware security architecture integrating physical fuse locking and AES-256 encrypted storage as described in claim 1, characterized in that, The fault aggregation logic receives the detection data from all sensors, compares it with a preset threshold through a comparator array, and outputs an 8-bit fault state vector fault_vector[7:0] to the safety management unit; where bit0 corresponds to voltage sensor warning, bit1 corresponds to voltage sensor fatal alarm, bit2 corresponds to temperature sensor warning, bit3 corresponds to temperature sensor fatal alarm, bit4 corresponds to light intensity sensor warning, bit5 corresponds to light intensity sensor fatal alarm, bit6 corresponds to clock disturbance warning, and bit7 corresponds to clock disturbance fatal alarm. Fatal alarms for light intensity and clock disturbances are simultaneously connected to the asynchronous interrupt pin of the safety management unit via a dedicated hardwired connection.

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