Simulation optimization method, device and equipment of power distribution network and storage medium

Abstract

The application provides a simulation optimization method and device of a power distribution network, equipment and a storage medium. The method obtains an equivalent simulation model of the power distribution network, obtains voltage data of each simulation power pin through direct current simulation, and classifies the voltage data into multiple groups of power supply path regions. Overall frequency domain simulation is performed to obtain a first impedance curve. In response to the first impedance curve meeting a preset condition, frequency domain simulation is performed on each group to obtain a second impedance curve corresponding to each group. The first and second impedance curves and an impedance target value are used to determine a power supply path region to be adjusted and adjustment data, and adjustment is performed to obtain an adjusted power distribution network model, and an optimization strategy of the power distribution network is determined. Efficient and accurate optimization of the power distribution network is achieved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a simulation optimization method, apparatus, device and storage medium for power distribution networks. Background Technology

[0002] A Power Delivery Network (PDN) represents the physical path from power supply to the System-on-Chip (SoC). It typically consists of a Voltage Regulator Module (VRM), power planes / traces on a Printed Circuit Board (PCB), vias, decoupling capacitors, and chip packages. Since these components inevitably contain parasitic parameters such as parasitic resistance and inductance, voltage drops and power supply noise occur during current transmission. The main function of the PDN is to suppress the adverse effects of these parasitic parameters, providing a stable voltage to the SoC and responding quickly to changes in load current. During PDN design, the layout and parameter selection of PDN components directly determine the magnitude of parasitic parameters, thus affecting the stability of the SoC's power supply. Therefore, how to effectively regulate the PDN to ensure that the power supply requirements of the SoC are met has become a pressing technical problem. Summary of the Invention

[0003] This application provides a simulation optimization method, apparatus, device, and storage medium for power distribution networks, in order to at least solve the above-mentioned technical problems existing in the prior art.

[0004] A first aspect of this application provides a simulation optimization method for a power distribution network, the method comprising: Obtain an equivalent simulation model of the power distribution network, the equivalent simulation model including a power distribution network model and a target chip model, the target chip model being connected to the power distribution network model through multiple simulated power pins; DC simulation was performed on the equivalent simulation model to obtain voltage data at each of the simulated power supply pins. Based on the voltage data, all simulated power supply pins are classified to obtain multiple groups of pins, each group of pins corresponding to a power supply path region within the power distribution network model; The total load current configured for all simulated power supply pins is obtained. After the total load current is input to all simulated power supply pins of the equivalent simulation model, the equivalent simulation model is subjected to a first frequency domain simulation to obtain a first impedance curve. In response to the first impedance curve meeting the preset conditions, an independent load current is obtained for each group of pins. After each independent load current is input to the corresponding group of pins in the equivalent simulation model, a second frequency domain simulation is performed on the equivalent simulation model to obtain the second impedance curve of each group of pins. Based on the first impedance curve, the second impedance curve, and the preset impedance target value, the power supply path regions that need to be adjusted and the adjustment data are determined from the power supply path regions corresponding to each group of pins. Based on the adjustment data, the power supply path regions that need to be adjusted are adjusted in the power distribution network model to obtain the adjusted power distribution network model. Based on the adjusted power distribution network model, an optimization strategy for the power distribution network is determined, and the optimization strategy is used to optimize the power distribution network.

[0005] In one possible implementation, the first impedance curve meets preset conditions, including: The impedance value at a frequency point on the first impedance curve exceeds the target impedance value; or, The impedance values ​​at all frequency points on the first impedance curve are lower than the target impedance value and the impedance margin is greater than the first threshold.

[0006] In one possible implementation, determining the power supply path region requiring adjustment and the adjustment data from the power supply path regions corresponding to each group of pins, based on the first impedance curve, the second impedance curve, and a preset impedance target value, includes: Based on the first impedance curve and the target impedance value, the adjustment mode is determined.

[0007] Based on the adjustment mode, the target impedance value, and the second impedance curve of each group of pins, the power supply path area that needs to be adjusted and the adjustment data are determined from the power supply path area corresponding to each group of pins.

[0008] In one possible implementation, the adjustment mode includes a first configuration adjustment mode and a second configuration adjustment mode; determining the adjustment mode based on the first impedance curve and the target impedance value includes: In response to the impedance value at a frequency point on the first impedance curve exceeding the target impedance value, the adjustment mode is determined to be the first configuration adjustment mode; In response to the fact that the impedance values ​​at all frequency points on the first impedance curve are lower than the target impedance value and the impedance margin is greater than the first threshold, the adjustment mode is determined to be the second configuration adjustment mode. The first configuration adjustment mode is used to indicate the addition of a decoupling capacitor in the power supply path area; the second configuration adjustment mode is used to indicate the removal of a decoupling capacitor in the power supply path area.

[0009] In one possible implementation, determining the power supply path region to be adjusted and the adjustment data from the power supply path region corresponding to each group of pins, based on the adjustment mode, the target impedance value, and the second impedance curve of each group of pins, includes: In response to the adjustment mode being the first configuration adjustment mode, based on the second impedance curve of each group of pins, the power supply path region corresponding to the pin group where the frequency point impedance value exceeds the impedance target value is determined as the power supply path region that needs to be adjusted, and the frequency information of the frequency point is used as the adjustment data; In response to the adjustment mode being the second configuration adjustment mode, based on the second impedance curve of each group of pins, the power supply path area corresponding to the group or more groups of pins with the lowest impedance value is determined as the power supply path area that needs to be adjusted, and the preset removal ratio information is used as the adjustment data.

[0010] In one possible implementation, adjusting the power supply path region requiring adjustment within the power distribution network model based on the adjustment data includes: In response to the adjustment mode being the first configuration adjustment mode, a decoupling capacitor with a resonant frequency matching the frequency information is added in the power supply path area that needs to be adjusted in the power distribution network model. In response to the adjustment mode being the second configuration adjustment mode, decoupling capacitors are removed according to the removal ratio information within the power supply path area that needs to be adjusted in the power distribution network model.

[0011] In one possible implementation, the method further includes: In response to the first impedance curve of the adjusted power distribution network not meeting the second preset condition, the adjusted power distribution network is iteratively simulated in the first frequency domain and the second frequency domain to determine the power supply path region that needs to be adjusted and the adjustment data. Based on the adjustment data, the power supply path region that needs to be adjusted is adjusted in the power distribution network model until the first impedance curve meets the second preset condition. The second preset condition is that the impedance values ​​at all frequency points on the first impedance curve are lower than the target impedance value and the impedance margin is less than the first threshold.

[0012] A second aspect of this application provides a simulation optimization apparatus for a power distribution network, the apparatus comprising: The acquisition module is used to acquire the equivalent simulation model of the power distribution network. The equivalent simulation model includes a power distribution network model and a target chip model. The target chip model is connected to the power distribution network model through multiple simulated power pins. A DC simulation module is used to perform DC simulation on the equivalent simulation model to obtain voltage data at each of the simulation power supply pins. The classification module is used to classify all simulated power supply pins according to the voltage data to obtain multiple groups of pins, each group of pins corresponding to a power supply path region in the power distribution network model; The first frequency domain simulation module is used to obtain the total load current configured for all simulated power supply pins. After inputting the total load current to all simulated power supply pins of the equivalent simulation model, the first frequency domain simulation is performed on the equivalent simulation model to obtain the first impedance curve. The second frequency domain simulation module is used to obtain the independent load current configured for each group of pins in response to the first impedance curve meeting the preset conditions. After inputting each independent load current into the corresponding group of pins in the equivalent simulation model, the module performs a second frequency domain simulation on the equivalent simulation model to obtain the second impedance curve of each group of pins. The adjustment module is used to determine the power supply path region to be adjusted and the adjustment data from the power supply path region corresponding to each group of pins according to the first impedance curve, the second impedance curve and the preset impedance target value, and to adjust the power supply path region to be adjusted in the power distribution network model based on the adjustment data to obtain the adjusted power distribution network model. The determination module is used to determine the optimization strategy of the power distribution network based on the adjusted power distribution network model, and the optimization strategy is used to optimize the power distribution network.

[0013] A third aspect of this application provides an electronic device comprising: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0014] A fourth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the methods described in this application.

[0015] This application discloses a simulation optimization method, apparatus, device, and storage medium for a power distribution network. It performs DC simulation on the chip's simulated power supply pins and groups them according to voltage values, followed by two frequency domain simulations. The first simulation combines all pins into a single load terminal, obtaining the overall impedance curve. The second simulation treats each group of pins as an independent load terminal, obtaining the local impedance curves for each power supply path region. By comparing the relationship between the overall and local impedance curves and the target impedance value, the power supply path regions requiring adjustment can be accurately identified, and targeted adjustments can be performed. This efficiently and accurately optimizes the power distribution network, ensuring the chip's power supply stability and design rationality.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, wherein: In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0018] Figure 1 A schematic diagram of the equivalent circuit of a PDN is shown. Figure 2 The PDN simulation flowchart is shown; Figure 3 A schematic diagram illustrating the implementation flow of the simulation optimization method for the power distribution network provided in the embodiments of this application is shown. Figure 4 An example diagram of the pin classification operation of the simulation optimization method for the power distribution network provided in the embodiments of this application is shown; Figure 5 A schematic diagram of the equivalent structure of the power distribution network provided in an embodiment of this application is shown; Figure 6 This paper illustrates a schematic diagram of the implementation process of determining the region and adjustment data in the simulation optimization method for the power distribution network provided in an embodiment of this application. Figure 7 This illustration shows a schematic diagram of the implementation process of a specific application example of the simulation optimization method for power distribution networks provided in the embodiments of this application; Figure 8 This paper shows a schematic diagram of the composition structure of the simulation optimization device for the power distribution network provided in an embodiment of this application; Figure 9 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0019] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] First, the application scenario of this application will be described. A PDN is the physical path that transmits power to the load chip, typically including a voltage regulation module, a printed circuit board, and the chip itself. Each chip limits the range of power supply voltage fluctuations. Current flows from the power supply end to the load end through the PDN. Its main function is to provide a stable voltage to the load, respond quickly to changes in load current, and reduce switching noise.

[0021] like Figure 1 As shown, Figure 1 The diagram shows the equivalent circuit of a PDN, which can be decomposed into power paths and ground paths. Each path contains non-negligible parasitic parameters. In the PCB segment, there are parasitic inductances LPCB-power and RPCB-power for the power path, and parasitic inductances LPCB-GND and RPCB-GND for the ground path. In the package segment, there are parasitic inductances LPKG-power and RPKG-power for the power path, and parasitic inductances LPKG-GND and RPKG-GND for the ground path. In the chip segment, there are parasitic resistances RDie-power for the power path and RDie-GND for the ground path. These parasitic parameters collectively constitute the impedance of the PDN. Meanwhile, the PDN incorporates capacitors in parallel at different levels: a decoupling capacitor CPCB on the PCB, a capacitor CPKG within the package, and an on-chip capacitor COn-chip within the chip. The transient current changes of the chip itself can be equivalent to a current source Ion-chip. The Voltage Regulator is the voltage regulation module.

[0022] When the chip load current undergoes a transient change, the current flowing through the aforementioned parasitic resistance and inductance will generate a voltage drop: the parasitic resistance causes an IR voltage drop proportional to the current, while the parasitic inductance generates an induced voltage due to the rate of change of current (di / dt). These two voltage drops are superimposed, ultimately manifesting as fluctuations in the chip's supply voltage. The magnitude of these voltage fluctuations is proportional to the PDN impedance; the higher the impedance, the greater the voltage fluctuation caused by the same current change. To suppress these fluctuations, decoupling capacitors configured in the PDN, such as MLCCs (Multi-layer Ceramic Capacitors), store charge and can provide high-frequency current to the chip locally when transient load demands occur, compensating for the insufficient response of the remote power supply due to path inductance.

[0023] From an impedance perspective, the regulated power supply and decoupling capacitor form a composite power system. The design requirement for this system is that regardless of changes in the transient current of the load across the chip, the voltage across the chip must remain stable. Based on the target impedance theory, let the allowable voltage fluctuation range of the chip be... The maximum transient current change is Then the target impedance that the PDN needs to satisfy It can be defined by the following formula:

[0024] By utilizing the linearity of the Fourier transform, a quantitative relationship can be established between time-domain voltage fluctuations and frequency-domain impedance. Let the spectrum of the current be I(f), and the frequency-domain impedance of the PDN be Z(f), then the time-domain voltage fluctuation ΔV(t) can be calculated using the following formula:

[0025] IFFT, or Inverse Fast Fourier Transform, is responsible for converting frequency domain signals back to time domain signals. This is possible as long as the relation Z(f) ≤ 0 is satisfied at all frequency points. Then it must satisfy:

[0026] This shows that by controlling the impedance of the PDN at each frequency point below Z_target, the time-domain voltage fluctuation can be prevented from exceeding the limit.

[0027] To achieve impedance control, this application first provides a PDN simulation method. This method involves establishing a VRM for a specified PowerNet (power path on the PCB), modeling the capacitors on the PDN path, merging all the terminating pins (power receiving pins) of the PowerNet into a group, running the simulation, and obtaining the impedance versus frequency curve. The simulation curve is then compared with the load chip's specification and the Reference Validation Platform (RVP) simulation curve to determine impedance control. If the impedance exceeds the specification, optimization is performed. This simulation scheme is relatively basic, yielding a single curve. For cases where the powernet is relatively simple and the chip has few power-consuming pins, this method provides a straightforward way to directly optimize the capacitors.

[0028] Specifically, the process of a PDN simulation method is as follows: Figure 2 As shown, Figure 2 The PDN simulation flowchart is shown, which includes the following steps: Obtaining the impedance curve using the traditional PDN simulation method and comparing it with the specification; if the comparison result is Fail (unacceptable), meaning there are frequency points where the impedance exceeds the specification requirements, analyze the results, and for curves with AC (Alternating Current) resonance, try adding MLCCs at different locations; after adding, return to the traditional PDN simulation method to obtain the impedance curve again and compare it with the specification; if the comparison result is Pass (acceptable), meaning the impedance on all frequency bands is less than the specification, further determine if the margin is within 5%; if the impedance on all frequency bands is less than the specification and the margin is within 5%, then confirm that the simulation result is Pass at this point, and there is no DFC (Decoupling Capacitor) optimization. The process ends when the Free-Cut / DFC space is reached. If the impedance on all frequency bands is less than the spec but the margin is greater than 5%, the analysis results are analyzed. After removing about 10% of the total number of MLCCs, DFC is completed. Then, the traditional PDN simulation method is used again to obtain the impedance curve, which is compared with the spec again until the conditions are met.

[0029] The aforementioned PDN simulation method can clearly identify risks, but it has the following drawbacks: 1) AC optimization schemes require repeated trial and error. Even though the decoupling frequency reference capacitance values ​​of MLCCs decrease from large to small corresponding to low to high frequencies, factors such as planar resonance in the PCB make it impossible to quickly locate the problem and find a solution, requiring repeated attempts and wasting time; 2) If the simulation results show PASS and MLCC DFC needs to be performed, it is difficult to find the pattern, and capacitor combinations need to be combined based on experience, which is time-consuming and labor-intensive. Therefore, to solve the above problems, this application provides a simulation optimization method, device, equipment, and storage medium for power distribution networks.

[0030] Figure 3 A schematic diagram illustrating the implementation flow of the simulation optimization method for power distribution networks provided in this application embodiment is shown.

[0031] refer to Figure 3 This application provides a simulation optimization method for power distribution networks. This method can be executed by an electronic device with data processing and simulation calculation capabilities or a system running on an electronic device. The electronic device includes, but is not limited to, desktop computers, portable computers, workstations, servers, or dedicated simulation terminals. The system includes, but is not limited to, simulation systems and power distribution network analysis systems. The method includes: Operation 101: Obtain the equivalent simulation model of the power distribution network. The equivalent simulation model includes the power distribution network model and the target chip model. The target chip model is connected to the power distribution network model through multiple simulated power pins.

[0032] The power distribution network is the power supply network structure built during the PCB design phase. It mainly includes core power supply elements such as voltage regulation modules, power supply planes and traces, vias, and decoupling capacitors, used to provide stable power to the target chip. In practical applications, the target chip is divided into multiple independent power domains according to functional modules, such as the core power domain (Core Power) for core logic circuits, the IO power domain (IO Power) for input / output interfaces, and the memory power domain (Memory Power) for memory interfaces. Each power domain is configured with an independent power distribution network, and each power distribution network corresponds to the power supply requirements of a power domain, realizing independent power supply for each zone. The power distribution network in this application can be the power distribution network corresponding to any power domain of the target chip. Given that the power distribution network corresponding to the core power domain has the characteristics of a large number of power supply pins, a wide chip layout distribution, and severe transient current fluctuations, the power supply stability problem is the most prominent. Therefore, this application preferably uses the power distribution network corresponding to the Core Power as the optimization target.

[0033] During the PCB design phase, although the power distribution network has been initially planned, it does not yet meet the power supply stability requirements of the target chip. Therefore, simulation analysis is needed to debug and optimize its configuration. The purpose of this application is to optimize the power distribution network through simulation debugging to ensure it meets the power supply requirements of the target chip.

[0034] The equivalent simulation model of a power distribution network is a digital abstract representation of the physical structure of the power distribution network and serves as the basis for simulating it. Its topology is identical to that of the actual power distribution network. This equivalent simulation model can be built using Electronic Design Automation (EDA) tools (such as Cadence Sigrity, Ansys SIwave, and Keysight ADS). For example, after importing PCB design files (including circuit schematics, layout and routing, layer stack-up, and component bill of materials) into the simulation tool, the tool automatically extracts parasitic parameters based on geometric structure and material parameters to obtain the equivalent circuit model, which is the equivalent simulation model. It should be noted that the process of building the equivalent simulation model of the power distribution network can refer to existing methods for building simulation models of power distribution networks using simulation tools, and will not be elaborated upon here.

[0035] Furthermore, to distinguish between the power supply network and the load, the equivalent simulation model can be divided into two sub-models: the target chip model and the power distribution network model. The target chip model corresponds to the actual target chip and is used to simulate the power consumption behavior and internal parasitic parameters of the target chip. The power distribution network model corresponds to the remaining power distribution network after removing the target chip, including VRM, body capacitance, PCB traces and planes, package traces and planes, and all decoupling capacitors. The connection between these two models is consistent with the actual structure, and they are connected one-to-one through multiple simulated power pins. Each simulated power pin represents a power receiving pin of the actual target chip, i.e., a "power-consuming pin," responsible for transmitting the voltage and current output from the power distribution network model to the target chip model.

[0036] Operation 102: Perform DC simulation on the equivalent simulation model to obtain voltage data at each simulated power supply pin.

[0037] Specifically, voltage data can be obtained through DC simulation. A DC IR drop simulation is performed on the established equivalent simulation model. This simulation considers the parasitic resistance on the power supply path of the target chip model and the load current drawn by each simulated power supply pin (i.e., the power-carrying pin of the target chip). After the simulation is completed, the actual voltage value at each simulated power supply pin can be obtained. These voltage values ​​reflect the DC voltage drop distribution along the power supply path from the power supply terminal (VRM) to each simulated power supply pin. Simulated power supply pins with higher voltages are usually closer to the VRM, or their power supply path has lower parasitic resistance; while simulated power supply pins with lower voltages may be located at the end of the power supply path, or their power supply path has higher parasitic resistance.

[0038] DC voltage drop simulation is a common analysis method in the field of power integrity. For example, simulation tools such as Sigrity PowerDC and Ansys SIwave are used to set the VRM output voltage and the target chip load current to solve the DC voltage distribution of the power distribution network. This application will not elaborate further.

[0039] Operation 103: Classify all simulated power supply pins according to voltage data to obtain multiple groups of pins, each group of pins corresponding to a power supply path region within the power distribution network model.

[0040] After obtaining the voltage data for each simulated power supply pin, it is categorized. One specific implementation can be to sort all simulated power supply pins according to their voltage values ​​from highest to lowest or lowest to highest. Then, based on a preset number of groups or a preset voltage threshold, the sorted simulated power supply pins are divided into multiple pin groups, with each group containing one or more simulated power supply pins with similar voltage values. For example, it is possible to preset the simulated power supply pins to be divided into 3 to 5 groups, but it is recommended not to exceed 5 groups to avoid excessively long simulation times. Specifically, the top 20% of simulated power supply pins with the highest voltage values ​​can be grouped into the first group, the next 20% into the second group, and so on. Alternatively, the division can be based on voltage thresholds; for example, simulated power supply pins with voltage values ​​higher than V1 can be grouped into the first group, those with voltage values ​​between V1 and V2 into the second group, and so on.

[0041] In this embodiment of the application, each group of pins roughly corresponds to a physical region on the PCB board. This is because the return current paths of simulated power supply pins with similar voltage values ​​are relatively concentrated on the PCB, usually located in the same or similar areas of the PCB. These physical regions are mapped to the power distribution network model, corresponding to a power supply path region within the model. Multiple power supply path regions together constitute a complete power distribution network model. The physical region refers to the spatial range covered by the local power supply structure supplying power to the corresponding pin group in the PCB layout, including but not limited to the pads and vias of the pin group on the PCB, the local power plane or trace segment supplying power to the pin group, the corresponding ground plane return current region, and nearby decoupling capacitors.

[0042] To more intuitively illustrate the effect of classifying simulated power supply pins based on voltage data in this application, the following will combine... Figure 4 An example is provided. Figure 4 An example diagram of pin classification operation in the simulation optimization method for power distribution networks provided in this application embodiment is shown. Wherein, Figure 4 In the diagram, 'a' represents the voltage distribution before classification. Each point represents a simulated power supply pin, and its vertical coordinate position indicates the voltage level of that pin. Figure 4 The 'b' in the diagram represents the result of classifying the pins according to their voltage values, grouping pins with similar voltage values ​​into the same group (e.g., ...). Figure 3 (As shown by the multiple circles in b), each group of pins corresponds to a power supply path area. Figure 4 It can be clearly seen that the originally scattered simulation power supply pins have been divided into several groups according to the voltage distribution, corresponding to a physical region, which lays the foundation for subsequent refined simulation and optimization.

[0043] Operation 104 obtains the total load current configured for all simulated power supply pins. After inputting the total load current to all simulated power supply pins of the equivalent simulation model, the equivalent simulation model is subjected to the first frequency domain simulation to obtain the first impedance curve.

[0044] After classification, the first step is to perform a traditional PDN frequency domain simulation, also known as the first frequency domain simulation. Specifically, the total load current configured for all simulated power supply pins of the target chip is first obtained. This total load current can be derived from the chip datasheet or power consumption analysis. Then, this total load current is distributed to each simulated power supply pin in the equivalent simulation model (e.g., according to the power consumption ratio of each pin or evenly distributed) as the excitation source for the frequency domain simulation, thereby merging all simulated pins into a single load terminal connected to the power distribution network model. Finally, the equivalent simulation model is run for frequency domain simulation, yielding the impedance curve of the entire PDN model from the VRM to all simulated power supply pins as a function of frequency, i.e., the first impedance curve. This curve reflects the overall impedance characteristics of the power distribution network across the entire frequency domain when all simulated power supply pins of the target chip are considered as a whole load. The total load current is a unit amplitude AC current (typically 1A).

[0045] In this embodiment of the application, the first frequency domain simulation can be implemented using a conventional frequency domain simulation (also known as AC simulation) method in the art. Specifically, based on a pre-built equivalent simulation model, a VRM output impedance model is set in an EDA simulation tool (such as Cadence Sigrity, Ansys SIwave, Keysight ADS, etc.), a frequency domain model (such as SPICE model, S-parameter model, etc.) is assigned to the decoupling capacitor, and a unit AC current excitation is applied to the combined load terminal. This unit AC current is the representation of the total load current in the frequency domain simulation. The impedance curve is obtained by solving in the frequency domain. It should be noted that the above simulation method is a commonly used technique in the art, and its specific implementation details can be found in traditional PDN frequency domain simulation methods, operation guides for frequency domain simulation in EDA simulation tools, or textbooks or related literature in the field of power integrity design. This application will not elaborate further on these details.

[0046] Operation 105: In response to the first impedance curve meeting the preset conditions, an independent load current is obtained for each group of pins. After each independent load current is input to the corresponding group of pins in the equivalent simulation model, a second frequency domain simulation is performed on the equivalent simulation model to obtain the second impedance curve of each group of pins.

[0047] After obtaining the first impedance curve, it is compared with preset conditions. Preset conditions refer to the evaluation criteria for the first impedance curve, used to determine whether the current PDN design meets the expected requirements and whether further refined analysis is needed. Specifically, preset conditions can be set based on indicators such as the amplitude of the impedance curve, the degree of deviation from the desired impedance level, or the presence of abnormal resonance peaks. When the performance of the first impedance curve does not meet expectations (e.g., there is excessively high impedance at frequency points, obvious resonance peaks, etc.), or although it meets expectations, there is room for further optimization, it can be considered to meet the preset conditions, thereby triggering subsequent refined simulations.

[0048] In one embodiment of this application, the first impedance curve meeting preset conditions includes: the impedance value at a frequency point on the first impedance curve exceeds a preset impedance target value; or, the impedance values ​​at all frequency points on the first impedance curve are lower than the preset impedance target value and the impedance margin is greater than a first threshold. The impedance margin characterizes the closeness between the first impedance curve and the impedance target value, and can be specifically defined as the percentage of the difference between the impedance target value and the maximum impedance value on the first impedance curve relative to the impedance target value. The first threshold can be configured according to actual engineering needs, for example, it can be set to 5% or 10%, to determine whether the current PDN design has sufficient optimization space, such as whether decoupling capacitor reduction optimization can be performed to reduce costs.

[0049] When the first impedance curve meets the preset conditions, the second frequency domain simulation of this step is triggered. At this time, instead of merging all simulated power supply pins into a single load terminal, each pin group is independently connected to the PDN model as a load terminal according to the groups defined in step S103. Then, the equivalent simulation model is run n times (or a simulation with multiple ports set at once) to obtain n impedance curves, which are the second impedance curves corresponding to each group of pins. Connecting each pin group independently as a load terminal to the PDN model can be achieved by inputting an independent load current for each pin group. This independent load current can be obtained by allocating the total load current according to the power consumption requirements of the power supply path region corresponding to each pin group or the proportion of the number of pins.

[0050] The principle of the second frequency domain simulation is the same as that of the first frequency domain simulation. Both obtain the impedance curve by solving the frequency domain response of the power distribution network. The only difference is the configuration of the load end (the first simulation combines all simulated power supply pins into one load end, while the second simulation sets each group of pins as an independent load end). Therefore, the specific implementation method of the second frequency domain simulation can be referred to the description of the first frequency domain simulation above, and will not be repeated here.

[0051] To further illustrate the principle of the second frequency domain simulation in this application, the following will be combined with... Figure 5 Please provide an explanation. Figure 5 A schematic diagram of the equivalent structure of the power distribution network provided in an embodiment of this application is shown. Figure 5 As shown, based on the classification results of step S102, the power distribution network can conceptually be equivalent to N parallel power supply path branches, denoted as Chip_1, Chip_2, ..., Chip_n. Each branch corresponds to a set of simulated power supply pins and includes the parasitic parameters of the PCB segment, the parasitic parameters of the package segment, the parasitic resistance of the chip segment, and the transient current source corresponding to that set of pins. Each branch is coupled through a common voltage regulation module (VRM) and decoupling capacitors (C PCB, C PKG, C On-chip). During the second frequency domain simulation, based on this equivalent concept, each set of pins' corresponding Chip_n can be connected to the PDN model as an independent load in the simulation tool, thereby supporting independent simulation analysis of each power supply path region.

[0052] Operation 106: Based on the first impedance curve, the second impedance curve, and the preset impedance target value, determine the power supply path area to be adjusted and the adjustment data from the power supply path area corresponding to each group of pins, and adjust the power supply path area to be adjusted in the power distribution network model based on the adjustment data to obtain the adjusted power distribution network model.

[0053] The preset impedance target value refers to the maximum allowable impedance value that the PDN needs to meet at each frequency point to ensure the normal operation of the target chip. It is usually calculated by the chip manufacturer based on the allowable voltage fluctuation range and maximum transient current in the target chip, and is a frequency domain indicator that the PDN design must meet.

[0054] Specifically, the first impedance curve is compared with the target impedance value to preliminarily determine the overall state of the current PDN design. Based on this, the local impedance characteristics of different power supply path regions are analyzed by combining the second impedance curves of each group of pins. By comparing the relative relationship between each second impedance curve and the target impedance value, the power supply path regions requiring adjustment are identified, and the corresponding adjustment data is determined. The adjustment data refers to specific information used to guide subsequent adjustment operations, such as frequency points and location suggestions for adding decoupling capacitors, or area markers indicating where decoupling capacitors can be removed. The adjustment data can be generated based on the deviation between simulation results and the target impedance value, providing a clear basis for adjustment.

[0055] Next, based on the adjustment data, adjustment operations are performed on the power supply path regions that need adjustment within the power distribution network model. For example, decoupling capacitors are added or removed from the power supply path regions that need adjustment. After the adjustment is completed, the updated power distribution network model is obtained.

[0056] Operation 107: Based on the adjusted power distribution network model, determine the optimization strategy for the power distribution network. The optimization strategy is used to optimize the power distribution network.

[0057] The power distribution network model, after adjustments (such as adding or removing decoupling capacitors) to meet requirements, is transformed into optimization strategies that can directly guide practical engineering applications for power distribution network optimization. These optimization strategies include data on the differences between the adjusted power distribution network model and the initial unadjusted model, and may include, but are not limited to: 1) a list of decoupling capacitor changes, such as which capacitors were added (capacitance, package, location), which were removed, and which were replaced; 2) layout adjustments to the power supply path area, such as physical modifications like power plane cutting, via locations, and trace widths. This data on these differences will serve as key information guiding the implementation of the power distribution network on the PCB.

[0058] The optimization strategy can also be to directly convert the topology of the power distribution network model into the final power distribution network circuit diagram or layout guide, including but not limited to: 1) a complete power distribution network circuit diagram, marking the location, capacitance, package, and connection nodes of all decoupling capacitors, as well as the electrical connection relationships of VRM, planes, vias, and traces; 2) a PCB layout constraint diagram, indicating the recommended placement area, prohibited placement area, and via array position of decoupling capacitors in each power path area (corresponding to different pin groups); 3) a layer stack-up and plane segmentation diagram, indicating the layer allocation, cutting boundaries, and stitching via positions of the power plane and ground plane; 4) a bill of materials difference table, comparing the addition and subtraction details of components such as capacitors, inductors, and resistors between the initial design and the final design.

[0059] In one embodiment of this application, after obtaining the adjusted power distribution network model, the embodiment can first determine whether the adjusted power distribution network model meets the power supply requirements of the chip. Only if it does, the final optimization strategy is determined based on the adjusted power distribution network model for power distribution network optimization. Meeting the chip's power supply requirements can be considered as meeting a second preset condition, namely, the impedance values ​​at all frequency points on the first impedance curve are lower than a preset impedance target value, and the impedance margin is less than a first threshold.

[0060] Accordingly, if the adjusted power distribution network model does not meet the second preset condition, it indicates that it has not yet met the design requirements and needs further optimization. Specifically, after operation 106, in response to the first impedance curve of the adjusted power distribution network model, the adjusted power distribution network model is iteratively simulated in the first and second frequency domains to determine the power supply path regions that need adjustment and the adjustment data. Based on the adjustment data, the power supply path regions that need adjustment are adjusted in the power distribution network model until the first impedance curve meets the second preset condition. The power distribution network model obtained at this time can be used as the final design scheme that meets the chip power supply requirements.

[0061] Since a single adjustment to the power distribution network model may not be sufficient to achieve the ideal state, multiple "simulation-analysis-adjustment" cycles are needed to gradually approach the final goal. In each cycle, the first and second frequency domain simulations are performed again based on the currently adjusted power distribution network model. The latest simulation results are used to determine which regions still need adjustment and how, and then the adjustment operation is performed again, i.e., repeating operations 101-106. This process is repeated until a simulation result shows that the first impedance curve fully meets the second preset condition. Only then is the power distribution network model obtained the final design scheme that meets the chip power supply requirements.

[0062] Thus, this embodiment performs DC simulation on the chip's power supply pins and groups them according to voltage values, followed by two frequency domain simulations. The first simulation combines all pins into a single load terminal, obtaining the overall impedance curve. The second simulation treats each group of pins as an independent load terminal, obtaining the local impedance curves for each power supply path region. By comparing the overall and local impedance curves with the target impedance value, the power supply path regions requiring adjustment can be accurately identified, and targeted adjustments can be performed. This efficiently and accurately optimizes the power distribution network, ensuring the chip's power supply stability and design rationality. Furthermore, by integrating DC and AC simulations, the mutual influence between the two types of simulations is fully considered, enabling the frequency domain analysis to accurately reflect the effect of the voltage distribution obtained from the DC simulation on the AC resonance characteristics of each region, further improving the accuracy of the simulation analysis and the targeted nature of the optimization adjustments.

[0063] Figure 6 This illustration shows a schematic diagram of the implementation process of determining the region and adjustment data in the simulation optimization method for the power distribution network provided in this application embodiment.

[0064] refer to Figure 6 In one embodiment of this application, the above-mentioned operation 105, based on the first impedance curve, the second impedance curve, and a preset impedance target value, determines the power supply path region that needs to be adjusted and the adjustment data from the power supply path regions corresponding to each group of pins, including: Operation 201: Based on the first impedance curve and the target impedance value, determine the adjustment mode.

[0065] Operation 202: Based on the adjustment mode, the target impedance value, and the second impedance curve of each group of pins, determine the power supply path area to be adjusted and the adjustment data from the power supply path area corresponding to each group of pins.

[0066] Specifically, the first impedance curve is compared with the preset impedance target value. Based on the comparison result, the overall state of the current power distribution network model is determined, and then the corresponding adjustment mode is determined. This adjustment mode reflects the overall design adjustment direction, such as whether it is necessary to enhance decoupling capability or whether there is room for optimization. If it is necessary to increase decoupling capability, decoupling capacitors need to be added; if there is room for optimization, decoupling capacitors can be reduced to lower costs. On this basis, the local impedance characteristics of each power supply path region are analyzed by combining the relative relationship between the second impedance curve of each group of pins and the impedance target value. Regions whose impedance performance deviates from the target value or have optimization potential are identified and determined as power supply path regions that need to be adjusted. At the same time, adjustment data is generated to guide subsequent adjustment operations.

[0067] In one embodiment of this application, the adjustment mode includes a first configuration adjustment mode and a second configuration adjustment mode. The aforementioned operation 201, based on a first impedance curve and a preset impedance target value, determines the adjustment mode as follows: in response to a frequency point on the first impedance curve having an impedance value exceeding the preset impedance target value, the adjustment mode is determined to be the first configuration adjustment mode; in response to all frequency points on the first impedance curve having impedance values ​​lower than the preset impedance target value and an impedance margin greater than a first threshold, the adjustment mode is determined to be the second configuration adjustment mode. The first configuration adjustment mode is used to indicate the addition of a decoupling capacitor in the power supply path region; the second configuration adjustment mode is used to indicate the removal of a decoupling capacitor in the power supply path region.

[0068] Specifically, based on the comparison between the first impedance curve and the preset impedance target value, two different states of the current power distribution network model can be determined: one state is that the impedance at some frequency points exceeds the target value, indicating that the power distribution network model has insufficient decoupling in certain frequency bands, and the decoupling capability of these frequency bands needs to be enhanced; the other state is that the impedance at all frequency points is lower than the target value and has a certain margin, indicating that the power distribution network model meets the requirements overall but there is room for optimization. Based on the above different states, two different adjustment modes are determined accordingly, corresponding to different adjustment directions and strategies.

[0069] Furthermore, when it is determined that the current power distribution network is in the first configuration adjustment mode, it indicates that the power distribution network model has impedance over-limit problems at certain frequency points. It is necessary to add decoupling capacitors to enhance the decoupling capability of the corresponding frequency bands in order to reduce local impedance. When it is determined that the current power distribution network model is in the second configuration adjustment mode, it indicates that the overall impedance of the power distribution network model has met the requirements and has a certain margin, with room for optimization. The design can be simplified and the cost reduced by removing decoupling capacitors.

[0070] In one embodiment of this application, the above-mentioned operation 202, based on the adjustment mode, the preset impedance target value, and the second impedance curve of each group of pins, determines the power supply path area to be adjusted and the adjustment data from the power supply path area corresponding to each group of pins, including: in response to the adjustment mode being a first configuration adjustment mode, determining the power supply path area corresponding to the pin group where the frequency point impedance value exceeds the preset impedance target value as the power supply path area to be adjusted according to the second impedance curve of each group of pins, and using the frequency information of the frequency point as the adjustment data; in response to the adjustment mode being a second configuration adjustment mode, determining the power supply path area corresponding to the group or more pins with the lowest impedance value as the power supply path area to be adjusted according to the second impedance curve of each group of pins, and using the preset removal ratio information as the adjustment data.

[0071] Specifically, when the adjustment mode is set to the first configuration adjustment mode, it indicates that the current power distribution network model has impedance exceeding the standard at certain frequency points, requiring the location of the specific exceeding area. At this time, the second impedance curve of each group of pins is compared with the preset impedance target value to identify the pin groups whose frequency impedance exceeds the target value. The power supply path areas corresponding to these pin groups are the areas with insufficient decoupling capability, requiring enhancement of their decoupling capability. Simultaneously, the frequency information of the exceeding frequency points is recorded as adjustment data. This frequency information can be used to guide the subsequent addition of decoupling capacitors matching the resonant frequency of that frequency point in that area.

[0072] When the adjustment mode is the second configuration adjustment mode, it indicates that the overall impedance of the current power distribution network model meets the requirements and has a certain margin, providing room for optimization. At this time, analyze the second impedance curves of each group of pins to find one or more groups of pins with the lowest impedance value (i.e., the largest margin). The power supply path area corresponding to these pin groups is the area with excessive decoupling capability, and decoupling capacitors can be removed to simplify the design and reduce costs. At the same time, the preset removal ratio information is recorded as adjustment data. This ratio information can be used to guide the subsequent proportional removal of decoupling capacitors in this area. The preset removal ratio information can be preset according to engineering experience or design requirements. For example, it can be configured to remove 10% of the total number of decoupling capacitors in the corresponding power supply path area. The specific value can be adjusted according to the actual margin size, cost target, and other factors, and this application does not limit it.

[0073] In one embodiment of this application, the above operation 106, which adjusts the power supply path region that needs to be adjusted in the power distribution network model based on adjustment data, includes: in response to the adjustment mode being a first configuration adjustment mode, adding a decoupling capacitor whose resonant frequency matches the frequency information in the power supply path region that needs to be adjusted in the power distribution network model; and in response to the adjustment mode being a second configuration adjustment mode, removing the decoupling capacitor in the power supply path region that needs to be adjusted in the power distribution network model according to the removal ratio information.

[0074] Specifically, when the adjustment mode is the first configuration adjustment mode, it indicates that the identified power supply path area requiring adjustment has a frequency impedance exceeding the standard, and its decoupling capability needs to be enhanced. At this time, based on the frequency information of the exceeding frequency point recorded in the adjustment data, a decoupling capacitor with a resonant frequency matching that frequency point is added to this area. The low impedance characteristics of the capacitor in the corresponding frequency band are used to reduce the local impedance peak, thereby solving the impedance exceeding the standard problem in this area.

[0075] When the adjustment mode is set to the second configuration adjustment mode, it indicates that the identified power supply path area requiring adjustment has excessive decoupling capacity, leaving room for optimization. In this case, based on the removal ratio information recorded in the adjustment data, decoupling capacitors are removed from this area according to a preset ratio. For example, 10% of the total number of decoupling capacitors in this area can be removed. By removing redundant capacitors, the design can be simplified and costs reduced while ensuring power supply requirements are met.

[0076] To facilitate understanding of the solutions in the embodiments of this application, a specific application example is provided below.

[0077] refer to Figure 7 , Figure 7 This illustration shows a schematic diagram of the implementation process of a specific application example of the simulation optimization method for power distribution networks provided in this application. In this specific application example, the simulation optimization method for power distribution networks, also known as a novel simulation method for optimizing Core Power PDN resonance using IR Drop subdivision sink, adds DC subdivision sink and multi-sink simulation PDN methods to the traditional power distribution network simulation process. This significantly improves optimization efficiency, directly and quickly locates the failure point, provides effective data guidance for DFC, and greatly reduces the number of iterations. The specific process is as follows: DC simulation is used to obtain the voltage value of each pin of the simulation object (i.e., the target chip). Then, the pins are classified according to the obtained voltage values ​​and assigned the names Chip_1, Chip_2, ..., Chip_n.

[0078] The impedance curve is obtained using the traditional PDN simulation method. The result is compared with the Spec (i.e., the preset impedance target value) to determine whether the simulation result is PASS or Fail.

[0079] If the simulation result is PASS, further determine whether the impedance on all frequency bands is less than the spec and the margin is within 5%. If yes, then the simulation result is confirmed to be PASS, and there is no DFC space, and the process ends. If no, then a new PDN simulation method is used. Pins are classified according to the DC classification voltage value, and Chip_1, Chip_2, ..., Chip_n are located. Different sinks are set up, and n PDN simulation curves are generated. The results are analyzed to locate the curve with the lowest AC impedance. At the corresponding chip, about 10% of the total number of MLCCs are removed to complete DFC. After adding, return to the step "Use the traditional PDN simulation method to obtain the impedance curve and compare it with the spec" to re-evaluate.

[0080] If the simulation result is Fail, the novel PDN simulation method is directly adopted. Pins are classified according to the DC voltage value, identifying Chip_1, Chip_2, ..., Chip_n. Different sinks are set up, and n PDN simulation curves are generated. The results are analyzed, and for curves showing AC resonance, the corresponding chip is located, and the corresponding MLCC is added based on the resonant frequency. After adding the MLCC, the process returns to the step of "obtaining the impedance curve using the traditional PDN simulation method and comparing it with the specification" to re-evaluate the result.

[0081] The above process is iterated repeatedly until the condition that "the impedance on all frequency bands is less than the spec and the margin is within 5%" is met after a certain iteration. The simulation result is confirmed to be PASS and there is no DFC space, and the process ends.

[0082] It should be noted that the parameter values ​​involved in this specific application example (such as no more than 5 groups, margin threshold of 5%, and removal ratio of 10%) are only specific examples given for ease of understanding. In actual applications, they can be adjusted according to specific design requirements, and this application does not limit them.

[0083] Thus, this specific application example of the present application fully integrates the advantages of DC analysis and AC simulation by first performing DC simulation to obtain the voltage values ​​of each power supply receiving pin and classifying them accordingly, and then combining overall and zoned frequency domain simulation analysis. On the one hand, the voltage distribution obtained from DC simulation is used to guide the zone setting in AC simulation, enabling frequency domain analysis to truly reflect the local resonance characteristics of different power supply path regions; on the other hand, the zoned simulation results can quickly locate the specific regions where AC resonance exists, improving the efficiency of problem troubleshooting; at the same time, when optimizing decoupling capacitor reduction, the optimization space can be judged according to the margin of each region, and regions with large margins can prioritize the removal of decoupling capacitors, providing effective guidance for obtaining the optimal design scheme.

[0084] Figure 8 A schematic diagram of the composition structure of the simulation optimization device for the power distribution network provided in the embodiments of this application is shown.

[0085] refer to Figure 8 This application also provides a simulation optimization device for power distribution networks, the device comprising: The acquisition module 301 is used to acquire the equivalent simulation model of the power distribution network. The equivalent simulation model includes the power distribution network model and the target chip model. The target chip model is connected to the power distribution network model through multiple simulated power pins. The DC simulation module 302 is used to perform DC simulation on the equivalent simulation model and obtain voltage data at each simulation power supply pin. The classification module 303 is used to classify all simulated power supply pins according to voltage data to obtain multiple groups of pins, each group of pins corresponding to a power supply path region in the power distribution network model; The first frequency domain simulation module 304 is used to obtain the total load current configured for all simulation power supply pins. After inputting the total load current to all simulation power supply pins of the equivalent simulation model, the first frequency domain simulation is performed on the equivalent simulation model to obtain the first impedance curve. The second frequency domain simulation module 305 is used to obtain the independent load current configured for each group of pins in response to the first impedance curve meeting the preset conditions. After inputting each independent load current into the corresponding group of pins in the equivalent simulation model, the second frequency domain simulation is performed on the equivalent simulation model to obtain the second impedance curve of each group of pins. The adjustment module 306 is used to determine the power supply path area to be adjusted and the adjustment data from the power supply path area corresponding to each group of pins according to the first impedance curve, the second impedance curve and the preset impedance target value, and adjust the power supply path area to be adjusted in the power distribution network model based on the adjustment data to obtain the adjusted power distribution network model. The determination module 307 is used to determine the optimization strategy of the power distribution network based on the adjusted power distribution network model. The optimization strategy is used to optimize the power distribution network.

[0086] It should be noted that the description of the apparatus in this application embodiment is similar to the description of the method embodiment above, and has similar beneficial effects as the method embodiment, therefore it will not be repeated. For any technical details not covered in the power distribution network simulation optimization apparatus provided in this application embodiment, please refer to... Figures 1 to 7 The meaning is understood in accordance with the description of any of the accompanying drawings.

[0087] According to embodiments of this application, this application also provides an electronic device and a readable storage medium.

[0088] Figure 9 A schematic block diagram of an example electronic device 400 that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0089] like Figure 9 As shown, the electronic device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. The RAM 403 may also store various programs and data required for the operation of the electronic device 400. The computing unit 401, ROM 402, and RAM 403 are interconnected via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0090] Multiple components in electronic device 400 are connected to I / O interface 405, including: input unit 406, such as keyboard, mouse, etc.; output unit 407, such as various types of displays, speakers, etc.; storage unit 408, such as disk, optical disk, etc.; and communication unit 409, such as network card, modem, wireless transceiver, etc. Communication unit 409 allows electronic device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0091] The computing unit 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the various methods and processes described above, such as the simulation optimization method for a power distribution network. For example, in some embodiments, the simulation optimization method for a power distribution network can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 408. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 400 via ROM 402 and / or communication unit 409. When the computer program is loaded into RAM 403 and executed by the computing unit 401, one or more steps of the simulation optimization method for a power distribution network described above can be performed. Alternatively, in other embodiments, computing unit 401 may be configured by any other suitable means (e.g., by means of firmware) to perform a simulation optimization method for power distribution networks.

[0092] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0093] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0094] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0095] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0096] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0097] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0098] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0099] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A simulation optimization method for power distribution networks, characterized in that, The method includes: Obtain an equivalent simulation model of the power distribution network, the equivalent simulation model including a power distribution network model and a target chip model, the target chip model being connected to the power distribution network model through multiple simulated power pins; DC simulation was performed on the equivalent simulation model to obtain voltage data at each of the simulated power supply pins. Based on the voltage data, all simulated power supply pins are classified to obtain multiple groups of pins, each group of pins corresponding to a power supply path region within the power distribution network model; The total load current configured for all simulated power supply pins is obtained. After the total load current is input to all simulated power supply pins of the equivalent simulation model, the equivalent simulation model is subjected to a first frequency domain simulation to obtain a first impedance curve. In response to the first impedance curve meeting the preset conditions, an independent load current is obtained for each group of pins. After each independent load current is input to the corresponding group of pins in the equivalent simulation model, a second frequency domain simulation is performed on the equivalent simulation model to obtain the second impedance curve of each group of pins. Based on the first impedance curve, the second impedance curve, and the preset impedance target value, the power supply path regions that need to be adjusted and the adjustment data are determined from the power supply path regions corresponding to each group of pins. Based on the adjustment data, the power supply path regions that need to be adjusted are adjusted in the power distribution network model to obtain the adjusted power distribution network model. Based on the adjusted power distribution network model, an optimization strategy for the power distribution network is determined, and the optimization strategy is used to optimize the power distribution network.

2. The method according to claim 1, characterized in that, The first impedance curve meets the following preset conditions: The impedance value at a frequency point on the first impedance curve exceeds the target impedance value; or, The impedance values ​​at all frequency points on the first impedance curve are lower than the target impedance value and the impedance margin is greater than the first threshold.

3. The method according to claim 1, characterized in that, The step of determining the power supply path region requiring adjustment and the adjustment data from the power supply path regions corresponding to each group of pins, based on the first impedance curve, the second impedance curve, and the preset impedance target value, includes: Based on the first impedance curve and the target impedance value, the adjustment mode is determined; Based on the adjustment mode, the target impedance value, and the second impedance curve of each group of pins, the power supply path area that needs to be adjusted and the adjustment data are determined from the power supply path area corresponding to each group of pins.

4. The method according to claim 3, characterized in that, The adjustment mode includes a first configuration adjustment mode and a second configuration adjustment mode; determining the adjustment mode based on the first impedance curve and the target impedance value includes: In response to the impedance value at a frequency point on the first impedance curve exceeding the target impedance value, the adjustment mode is determined to be the first configuration adjustment mode; In response to the fact that the impedance values ​​at all frequency points on the first impedance curve are lower than the target impedance value and the impedance margin is greater than the first threshold, the adjustment mode is determined to be the second configuration adjustment mode. The first configuration adjustment mode is used to indicate the addition of a decoupling capacitor in the power supply path area; the second configuration adjustment mode is used to indicate the removal of a decoupling capacitor in the power supply path area.

5. The method according to claim 4, characterized in that, Based on the adjustment mode, the target impedance value, and the second impedance curve of each group of pins, the power supply path region to be adjusted and the adjustment data are determined from the power supply path region corresponding to each group of pins, including: In response to the adjustment mode being the first configuration adjustment mode, based on the second impedance curve of each group of pins, the power supply path region corresponding to the pin group where the frequency point impedance value exceeds the impedance target value is determined as the power supply path region that needs to be adjusted, and the frequency information of the frequency point is used as the adjustment data; In response to the adjustment mode being the second configuration adjustment mode, based on the second impedance curve of each group of pins, the power supply path area corresponding to the group or more groups of pins with the lowest impedance value is determined as the power supply path area that needs to be adjusted, and the preset removal ratio information is used as the adjustment data.

6. The method according to claim 5, characterized in that, The adjustment of the power supply path region requiring adjustment in the power distribution network model based on the adjustment data includes: In response to the adjustment mode being the first configuration adjustment mode, a decoupling capacitor with a resonant frequency matching the frequency information is added in the power supply path area that needs to be adjusted in the power distribution network model. In response to the adjustment mode being the second configuration adjustment mode, decoupling capacitors are removed according to the removal ratio information within the power supply path area that needs to be adjusted in the power distribution network model.

7. The method according to claim 1, characterized in that, The method further includes: In response to the first impedance curve of the adjusted power distribution network not meeting the second preset condition, the adjusted power distribution network is iteratively simulated in the first frequency domain and the second frequency domain to determine the power supply path region that needs to be adjusted and the adjustment data. Based on the adjustment data, the power supply path region that needs to be adjusted is adjusted in the power distribution network model until the first impedance curve meets the second preset condition. The second preset condition is that the impedance values ​​at all frequency points on the first impedance curve are lower than the target impedance value and the impedance margin is less than the first threshold.

8. A simulation and optimization device for a power distribution network, characterized in that, The device includes: The acquisition module is used to acquire the equivalent simulation model of the power distribution network. The equivalent simulation model includes a power distribution network model and a target chip model. The target chip model is connected to the power distribution network model through multiple simulated power pins. A DC simulation module is used to perform DC simulation on the equivalent simulation model to obtain voltage data at each of the simulation power supply pins. The classification module is used to classify all simulated power supply pins according to the voltage data to obtain multiple groups of pins, each group of pins corresponding to a power supply path region in the power distribution network model; The first frequency domain simulation module is used to obtain the total load current configured for all simulated power supply pins. After inputting the total load current to all simulated power supply pins of the equivalent simulation model, the first frequency domain simulation is performed on the equivalent simulation model to obtain the first impedance curve. The second frequency domain simulation module is used to obtain the independent load current configured for each group of pins in response to the first impedance curve meeting the preset conditions. After inputting each independent load current into the corresponding group of pins in the equivalent simulation model, the module performs a second frequency domain simulation on the equivalent simulation model to obtain the second impedance curve of each group of pins. The adjustment module is used to determine the power supply path region to be adjusted and the adjustment data from the power supply path region corresponding to each group of pins according to the first impedance curve, the second impedance curve and the preset impedance target value, and to adjust the power supply path region to be adjusted in the power distribution network model based on the adjustment data to obtain the adjusted power distribution network model. The determination module is used to determine the optimization strategy of the power distribution network based on the adjusted power distribution network model, and the optimization strategy is used to optimize the power distribution network.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-7.

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