SELL-C32 directed connection slice storage and traversal based reservoir connection map gpu organization method and system

Abstract

The application relates to the field of oil and gas reservoir numerical simulation calculation, and discloses a GPU organization method and system for oil reservoir connection graph based on SELL-C32 directed connection slice storage and traversal, which comprises the following steps: reading an oil reservoir model active grid set and an original grid connection set; expanding each original grid connection into two directed connection records according to two active grids at the connection ends; constructing a SELL-C32 slice according to the active grid sequence every 32 continuous active grids; counting the number of adjacent records of the active grids in each slice and storing the position according to the maximum adjacent record number in the slice; binding the connection number, the grid number, the opposite grid number, the connection side identifier, the effective flag and the matrix writing index for each effective rule storage position; traversing the directed connection records according to the rule storage position and the thread bundle mapping relationship on the GPU side; and outputting the GPU side connection graph data source for flux calculation of an oil reservoir equation, residual assembly or Jacobian matrix assembly reading.

Description

Technical Field

[0001] This invention relates to the fields of reservoir numerical simulation, high-performance computing, GPU parallel computing, and sparse connectivity graph data structure technology, and in particular to a GPU organization method and system for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal. Background Technology

[0002] Numerical simulations of oil reservoirs typically discretize subsurface reservoirs into a large number of active grids and construct connectivity graphs based on the flow relationships between the grids. In fully implicit numerical simulations of oil reservoirs, each Newton iteration within a time step requires calculating phase potential difference, windward direction, phase flux, component flux, and flux-related matrix contributions along the connectivity graph. The organization of the connectivity graph not only affects the efficiency of a single traversal but also influences subsequent matrix block positioning, right-hand side assembly, and GPU data residency. With the increasing demand for developing complex offshore oil reservoirs, the scale of actual oil reservoir models is constantly expanding. Millions of active grids have become common in engineering applications, and models with tens of millions of grids are gradually entering the high-performance computing verification stage. For such models, the number of connections typically reaches millions to tens of millions, and the overhead of connection traversal and the memory access efficiency issues caused by connection traversal significantly affect the overall performance of the simulation software.

[0003] Common storage formats for sparse graphs or sparse matrices include CSR, COO, ELLPACK, SELL-P, and SELL-C-sigma. CSR format is convenient for compressing rows of varying lengths, but when traversing rows on a GPU, the number of adjacent records for different threads within the same thread bundle may differ, easily causing thread bundle branch divergence. COO format is simple to express, but it lacks sufficient support for mesh-merging assembly processes. ELLPACK format has good rule-based access characteristics, but it requires padding based on the global maximum adjacency, which may lead to excessive padding when dealing with complex local connections and non-adjacent connections in reservoir models. SELL-P or SELL-C-sigma formats reduce the padding overhead of ELLPACK through fragmentation, but the general SELL format is mainly geared towards sparse matrix vector multiplication or general linear algebra calculations, and does not fully consider the engineering characteristics of reservoir connectivity maps, such as bilateral connections, connection side identification, matrix off-diagonal block writing direction, windward direction, and mesh flux assembly. If only the general SELL format is used for reservoir connection diagrams, an additional structure is still needed to store connection numbers, opposing grids, write indexes, and connection side information, resulting in a secondary conversion between connection diagram traversal and matrix assembly.

[0004] Reservoir connectivity maps also exhibit significant engineering characteristics. Regular corner grids typically have adjacent connections in the I, J, and K directions. Fault crossings, local densification, non-adjacent connections (NNC), and well-near grid densification all contribute to changes in adjacency. The flux contribution directions of the same connection to the grids on either side are opposite, but they correspond to different off-diagonal blocks during matrix assembly. Traditional connection-based traversal methods often require writing back to both ends of the grid after a connection calculation is completed, which can easily lead to write conflicts or require additional merging.

[0005] With the gradual introduction of GPU linear solvers and GPU matrix assembly into reservoir numerical simulation software, connectivity graphs are no longer just pre-processing structures on the CPU side, but need to become long-term data sources resident on the GPU side. In existing solutions, connectivity relationships, matrix write indices, and the assembly order of right-hand items are often organized separately by different modules, resulting in inconsistent data structures, complex transformation paths, and significant debugging difficulties. Furthermore, this is not conducive to the subsequent formation of a fully GPU-resident assembly and solution process. Summary of the Invention

[0006] To address the aforementioned problems, the purpose of this invention is to provide a GPU organization method and system for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal. By using directed connectivity records and SELL-C32 structured storage, it can explicitly expand connectivity contributions, reduce filler waste, reuse indexes, and simplify GPU branches, while providing a unified and efficient data source for throughput calculation, residual assembly, Jacobian assembly, and linear solutions.

[0007] To achieve the above objectives, in a first aspect, the technical solution adopted by the present invention is as follows: a GPU organization method for reservoir connectivity maps based on SELL-C32 directed connection slice storage and traversal, comprising: obtaining the active mesh set and the original mesh connection set of the reservoir model, wherein the original mesh connection is an undirected connection connecting two active meshes; splitting each original mesh connection into two directed connection records according to the active meshes at both ends, each directed connection record taking one active mesh as its belonging mesh and the other active mesh as its opposing mesh, and associating the two directed connection records corresponding to the same original mesh connection with different connection side identifiers; constructing a SELL-C32 slice for every 32 consecutive active meshes according to the arrangement order of the active meshes, counting the number of directed connection records of each active mesh in each slice, and generating a regular storage location based on the maximum number of directed connection records in the slice; binding connections at each regular storage location. For active grids with fewer directed connection records than the maximum number of directed connection records in a slice, invalid fill records are written at missing locations. The connection graph field includes connection number, grid number, opposing grid number, connection side identifier, validity flag, and matrix write index. On the GPU, directed connection records are traversed according to rule storage locations and thread bundle mapping relationships. All bound rule storage locations are stored in GPU memory as an array, forming a unified connection graph data source for direct GPU reading. On the GPU, each thread within a thread bundle is mapped one-to-one with each active grid row in the same adjacent layer within the slice. The connection graph field at each valid rule storage location is read according to the rule storage location. Based on the read connection number, grid number, opposing grid number, connection side identifier, and matrix write index, a GPU-side connection graph data source is output for reservoir equation flux calculation, residual assembly, or Jacobi matrix assembly.

[0008] Furthermore, each original mesh connection is split into two directed connection records based on the active meshes at both ends, specifically: For any original mesh connection Cij, where i and j are the active meshes connected to the two ends of the connection, the following are generated: The first directed connection record, with active grid i as the belonging grid and active grid j as the opposing grid, is used to characterize the directional flow relationship from the belonging grid i to the opposing grid j, and is associated with the first connection side identifier; The second directed connection record, with active grid j as the belonging grid and active grid i as the opposing grid, is used to characterize the directional flow relationship from the belonging grid j to the opposing grid i, and is associated with the second connection side identifier; The first directed connection record and the second directed connection record share the same original connection number, and the first connection side identifier and the second connection side identifier are used to distinguish the non-diagonal block write directions corresponding to the two ends of the same original connection.

[0009] Furthermore, a SELL-C32 slice is constructed for every 32 consecutive active grids, including: The active grids are arranged sequentially according to the row order of the Jacobian matrix. Starting from the beginning of the arrangement, the grids are divided into slices of 32 consecutive active grids to obtain several SELL-C32 slices. Each complete slice contains 32 rows of active grids. For slices with fewer than 32 active grids at the tail, the following method is used for processing: Method 1: Store according to the actual number of active grid rows of the tail slice; Method 2: Fill the tail slice to 32 rows, and mark the rows that exceed the actual active grid as invalid rows.

[0010] Furthermore, on the GPU side, the 32 threads within the same thread bundle correspond to 32 active grid rows in a complete SELL-C32 slice. When there are fewer than 32 rows at the end, the threads that exceed the actual grid read invalid fill records and skip them, so that the effective rule storage locations of the same adjacent layer are arranged continuously in the GPU memory.

[0011] Furthermore, the arrangement order of the active grids is the original active grid numbering order of the reservoir model active grids, the rearranged active grid numbering order, or the active grid numbering order consistent with the matrix assembly order.

[0012] Furthermore, on the GPU side, the directed connection records are traversed according to the storage location and thread bundle mapping relationship according to the rules, including: During GPU traversal, thread bundles are used as execution units. The 32 threads in the same thread bundle correspond one-to-one with the 32 active grid rows on the same adjacent layer index k in the same SELL-C32 slice. Each thread reads the connection number, opposite grid number, connection side identifier and matrix write index at the corresponding rule storage location according to the rule storage location. If the read connection number is negative, the rule storage location is an invalid fill record, and the current thread skips this location and does not perform subsequent calculations; If the read connection number is non-negative, the rule storage location is a valid directed connection record. The current thread will pass the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier, and the matrix write index to the GPU for flux calculation, residual assembly, or Jacobian matrix assembly, for reservoir equation calculation.

[0013] Furthermore, the storage locations of all bound rules are stored in the GPU memory as an array, forming a unified connection graph data source that can be directly read by the GPU, including: All rules after binding the connection graph field are stored in the GPU memory in the following order: connection number array, opposite grid number array, connection side identifier array, valid flag array, and non-diagonal block write index array. At the same time, the starting position and row number of each slice are stored in the slice starting position array and slice row number array, respectively, forming a unified connection graph data source that can be directly read by the GPU. In this system, each array in the unified connection graph data source resides in the GPU memory for a long time. When the active grid set or the original grid connection set of the reservoir model does not change, the data source can be reused between time steps without repeated construction.

[0014] Secondly, the technical solution adopted by this invention is: a reservoir connectivity graph GPU organization system based on SELL-C32 directed connectivity slice storage and traversal, comprising: The set acquisition module acquires the active mesh set and the original mesh connection set of the reservoir model, where the original mesh connection is an undirected connection connecting two active meshes; The mesh splitting module splits each original mesh connection into two directed connection records based on the active meshes at both ends. Each directed connection record uses one active mesh as its parent mesh and the other active mesh as its counterpart mesh. The two directed connection records corresponding to the same original mesh connection are associated with different connection side identifiers. The SELL-C32 slice construction module constructs a SELL-C32 slice for every 32 consecutive active grids according to the arrangement order of the active grids. It counts the number of directed connection records in each active grid within each slice and generates a rule storage location based on the maximum number of directed connection records within the slice. The connection graph field binding module binds connection graph fields at each rule storage location. For active grids with fewer directed connection records than the maximum number of directed connection records in a slice, invalid fill records are written at the missing locations. The connection graph fields include connection number, grid number, opposing grid number, connection side identifier, validity flag, and matrix write index. The GPU thread mapping module traverses the directed connection records on the GPU side according to the rule storage location and thread bundle mapping relationship, and stores all the bound rule storage locations into the GPU video memory in the form of an array, forming a unified connection graph data source that can be directly read by the GPU side. The data source output module, on the GPU side, maps each thread in the thread bundle to each active grid row in the same adjacent layer of the slice, reads the connection graph field at each valid rule storage location according to the rule storage location, and outputs the GPU-side connection graph data source for reservoir equation flux calculation, residual assembly or Jacobian matrix assembly based on the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier and the matrix write index.

[0015] Thirdly, the technical solution adopted by the present invention is: a computer-readable storage medium for storing one or more programs, wherein the one or more programs include instructions, which, when executed by a computing device, cause the computing device to perform any of the methods described above.

[0016] Fourthly, the technical solution adopted by the present invention is as follows: a computing device, comprising: one or more processors, a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for performing any of the methods described above.

[0017] The present invention has the following advantages due to the adoption of the above technical solutions: 1. This invention explicitly expands the contributions on both sides of the connection through directed connection records, so that a one-to-one correspondence is formed between traversing the grid to which it belongs and writing the matrix block.

[0018] 2. This invention reduces storage waste caused by global padding through the SELL-C32 slicing structure, while maintaining regularity suitable for thread bundle access.

[0019] 3. This invention reduces the overhead of repeatedly constructing indexes in the subsequent matrix assembly stage by binding connection fields and writing indexes through rule storage location.

[0020] 4. This invention simplifies GPU-side branch judgment by using invalid record negative value identifiers and thread bundle lane mapping.

[0021] 5. This invention can serve as a unified connection graph data source for throughput calculation, residual assembly, Jacobian matrix assembly, and GPU linear solution. Attached Figure Description

[0022] Figure 1 This is a flowchart of the overall process of the reservoir connection map GPU organization method in this embodiment of the invention, which shows the complete process from reading the active grid and original connections, expanding the directed connections, constructing SELL-C32 slices, binding the regular positions to the GPU-side traversal output; Figure 2 This is an expanded schematic diagram of an undirected connection to two directed connection records in an embodiment of the present invention. It shows that the same original connection forms records of its own grid and opposite grid under the active grids on both sides. Each record synchronously saves the connection number, opposite grid, connection side identifier, valid flag and write index, which is convenient for direct access by the GPU. Figure 3This is a schematic diagram of the SELL-C32 slice and regular storage location construction in an embodiment of the present invention, showing the relationship between adjacent layers, lanes, invalid fill records and regular location formulas within a slice. Taking 8 rows as an example, the actual complete slice is 32 rows, and the same adjacent layer k is arranged continuously in memory. Figure 4 This is a schematic diagram of the mapping relationship between GPU thread bundles and SELL-C32 slices in an embodiment of the present invention. It shows the correspondence between thread lanes and slice row lanes, as well as the continuous reading method of the same adjacent layer. The consistency between thread lanes and slice row lanes reduces branch judgment and increases the probability of global memory merging access. Figure 5 This is an embodiment of the invention showing the SPE10 connection graph scale and SELL-C32 fill statistics, illustrating the active equation rows, number of grid connections, number of directed connection records, number of rule storage locations, and fill ratio. Detailed Implementation

[0023] To address the following issues in existing technologies: First, to resolve the problems of poor memory access continuity and excessive branch divergence in thread bundles when traversing reservoir connectivity maps on GPUs using irregular structures such as CSRs; Second, to resolve the issue that general sparse matrix storage formats cannot simultaneously express reservoir connectivity numbers, opposing grids, connectivity side identifiers, and matrix write positions; Third, to resolve the issues of structural conversion and inconsistent write paths between connectivity traversal and grid assembly; Fourth, to resolve the issues of long-term GPU residency of connectivity maps at grid scales of millions to tens of millions and inconsistent subsequent matrix assembly read interfaces. This invention provides a GPU organization method and system for reservoir connectivity maps based on SELL-C32 directed connectivity slice storage and traversal. It decomposes the original undirected connections into directed connection records expanded according to their respective grids, and performs regular slice storage in a manner suitable for GPU thread bundle access. This binds the connectivity number, opposing grid, connectivity side identifier, validity flag, and matrix write index to the same regular position, thereby providing a unified data entry point for subsequent reservoir equation calculations.

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary embodiments of the present invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof. For example, the core of this invention is not simply the adoption of a particular general sparse matrix format, but rather a proposed method of combining directed connection records with SELL-C32 slices to address the coupling relationship between the contributions of both sides of the connection in the reservoir connection diagram, the direction of the off-diagonal blocks of the matrix, and GPU thread beam access. In this invention, SELL-C32 primarily emphasizes matching the complete slice with the GPU thread beam width, and does not limit the underlying array name or specific programming language. Implementation using CUDA, HIP, SYCL, or other GPU parallel programming models, as long as it slices according to a fixed number of rows, pads according to the maximum adjacent record within the slice, and generates positions according to the adjacent layer and lane rules, falls within the scope of the technical concept of this invention. The "directed connectivity record" in this invention does not alter the physical connectivity of the reservoir, but rather changes how the connectivity graph is represented in computer memory. The original connectivity still represents the flow channel between two active grids; the directed unrolling is only used to explicitly bind the belonging grid, opposing grid, connectivity side, and matrix write direction on the GPU. The terminology involved in this invention is explained as follows: Active grid refers to the grid cell that participates in solving the reservoir equations and corresponds to a matrix row; original connection refers to the undirected flow channel between two active grids; directed connection record refers to a directional connection record with one active grid as its parent grid and the other end as the opposing grid; SELL-C32 slice refers to a slice-type regular storage unit with 32 active grid rows as a group; adjacency layer k refers to the layer where the k-th adjacency record of each grid in the same slice is located; lane refers to the row number of the active grid in the slice, which can also correspond to the line program number in the thread bundle; regular storage location refers to the array position determined by sliceBase, k, sliceRows, and lane; fill ratio refers to the ratio between the number of regular storage locations and the number of effective directed connection records; right-hand side refers to the unbalanced quantity of the current nonlinear equation, which, together with the Jacobian matrix, constitutes the linear equation system. These terms are used only to limit the engineering meaning of this invention.

[0026] In one embodiment of the present invention, a GPU organization method for reservoir connectivity maps based on SELL-C32 directed connectivity slice storage and traversal is provided. This method is geared towards data organization of connectivity maps in reservoir numerical simulations. The present invention can be applied to black oil models, component models, chemical flooding models, thermal recovery models, and other reservoir simulation software that uses the finite volume method for mesh discretization. It can serve as a prerequisite data organization foundation for flux calculation, residual assembly, Jacobian matrix assembly, linear equation system packaging, and GPU parallel solution. In this embodiment, the method can be executed after reservoir model reading, active mesh identification, and connectivity establishment, or it can be executed during the matrix structure initialization stage, such as... Figure 1 As shown, the method includes the following steps: 1) Obtain the active mesh set and the original mesh connection set of the reservoir model, where the original mesh connection is an undirected connection connecting two active meshes.

[0027] 2) Split each original mesh connection into two directed connection records based on the active meshes at both ends. Each directed connection record uses one active mesh as its parent mesh and the other active mesh as its counterpart mesh. Associate the two directed connection records corresponding to the same original mesh connection with different connection side identifiers.

[0028] 3) According to the arrangement order of the active grids, construct a SELL-C32 slice for every 32 consecutive active grids, count the number of directed connection records of each active grid in each slice, and generate the rule storage location based on the maximum number of directed connection records in the slice.

[0029] 4) Bind the connection graph field at each rule storage location. For active grids with fewer directed connection records than the maximum number of directed connection records in a slice, write invalid fill records at the missing locations. The connection graph field includes the connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier, the valid flag, and the matrix write index.

[0030] 5) On the GPU side, traverse the directed connection records according to the rule storage location and thread bundle mapping relationship, and store all the bound rule storage locations into the GPU video memory in the form of an array to form a unified connection graph data source that can be directly read by the GPU side.

[0031] 6) On the GPU side, each thread in the thread bundle is matched one-to-one with each active grid row in the same adjacent layer in the slice. The connection graph field at each valid rule storage location is read according to the rule storage location. Based on the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier, and the matrix write index, the GPU-side connection graph data source is output for reservoir equation flux calculation, residual assembly, or Jacobi matrix assembly.

[0032] In step 1) above, the active mesh number mapping, connection conductivity index, and connection-side information required for subsequent matrix assembly are also obtained. The original mesh connection set can be derived from regular surface adjacent connections, fault bridging connections, non-adjacent connections (NNC), or engineering-added connections.

[0033] In step 2) above, if Figure 2 As shown, a bidirectional unrolling is performed on each original mesh connection, generating directed connection records from the first active mesh to the second active mesh, and from the second active mesh to the first active mesh. Specifically, each original mesh connection is split into two directed connection records based on its two active meshes. The implementation method is as follows: For any original mesh connection Cij, where i and j are the active meshes connected to the two ends of the connection, the following are generated: The first directed connection record Rij, with active grid i as the belonging grid and active grid j as the opposing grid, is used to represent the directional flow relationship from the belonging grid i to the opposing grid j, and is associated with the first connection side identifier. The first directed connection record Rij includes the belonging grid number i, the opposing grid number j, the original connection number Cij, the connection side identifier side=0, the adjacent layer number k, the validity flag valid=1, and the first side non-diagonal block write index.

[0034] The second directed connection record Rji, with active grid j as the belonging grid and active grid i as the opposing grid, is used to represent the directional flow relationship from the belonging grid j to the opposing grid i, and is associated with the second connection side identifier. The second directed connection record Rji includes: belonging grid number i, opposing grid number j, original connection number Cij, connection side identifier side=0, adjacent layer number k, validity flag valid=1, and the first side non-diagonal block write index. The second directed connection record Rji includes: belonging grid number j, opposing grid number i, original connection number Cij, connection side identifier side=1, adjacent layer number k, validity flag valid=1, and the second side non-diagonal block write index.

[0035] The first directed connection record and the second directed connection record share the same original connection number, and the first connection side identifier and the second connection side identifier are used to distinguish the write direction of the off-diagonal blocks corresponding to the two ends of the same original connection. The first directed connection record is written to the first side off-diagonal block index, and the second directed connection record is written to the second side off-diagonal block index.

[0036] In this embodiment, a flowable channel exists between active grid i and active grid j. Traditional connection-based traversal methods typically consider the contributions of both i and j when processing Cij. However, this embodiment splits the connection into two directed records originating from their respective grids. Through this directed connection unrolling, subsequent GPU threads can traverse according to their grid affiliation, with each thread only responsible for the adjacent records corresponding to its own grid. This avoids complex write control of two grids simultaneously within a single undirected connection. This structure is particularly suitable for the assembly process in reservoir equations where diagonal blocks are merged according to their grid affiliation, and off-diagonal blocks are written according to the connection side direction.

[0037] In this embodiment, the fields stored in the directed connectivity record can also be expanded according to the specific reservoir simulation software, such as adding connectivity conductivity indexes, connectivity direction categories, NNC markers, lithological zoning markers, or boundary type markers. These expanded fields do not affect the directed connectivity unfolding, SELL-C32 slicing, and regular location construction mechanisms of this invention.

[0038] In step 3) above, a SELL-C32 slice is constructed for every 32 consecutive active grids. The specific construction method is as follows: Assume the number of active grids is N. Arrange the active grids sequentially according to the row order of the Jacobian matrix. Starting from the beginning of the arrangement, divide the slice into several SELL-C32 slices with every 32 consecutive active grids. Each complete slice contains 32 rows of active grids. For example, the first slice contains active grids 0 to 31, the second slice contains active grids 32 to 63, and so on.

[0039] For each slice, the number of directed connections in each active grid within the slice is counted, denoted as deg(row). The slice width is determined by the maximum deg(row) within the slice, rather than by the global maximum adjacency. Therefore, compared to the global ELLPACK format, this embodiment can reduce the global padding overhead caused by abnormally high local adjacency.

[0040] For slices with fewer than 32 active grids at the tail, the following method is used for processing: Method 1: Store according to the actual number of active grid rows of the tail slice; in this case, sliceRows in the rule position formula is the actual number of rows.

[0041] Method 2: Pad the tail slice to 32 rows, mark rows exceeding the actual active grid as invalid rows, and allocate corresponding invalid padding records for invalid rows in the rule storage location. The GPU skips invalid padding records during traversal. Neither of these methods changes the core idea of ​​organizing directed connection records by slice and adjacent layer in this invention.

[0042] In this embodiment, the arrangement order of the active grids is the original active grid numbering order of the reservoir model active grids, the rearranged active grid numbering order, or the active grid numbering order consistent with the matrix assembly order.

[0043] In this embodiment, the 32 in SELL-C32 is a preferred value that matches the GPU thread bundle width. Equivalent fixed-row slices, such as 16, 32, or 64 rows, can also be used on different hardware platforms or with different thread organization methods. The core of this invention lies in slicing with a fixed number of rows, padding according to the maximum number of adjacent records within the slice, and generating positions according to adjacent layers and lane rules.

[0044] In step 4) above, on the GPU side, the 32 threads in the same thread bundle correspond to 32 active grid rows in a complete SELL-C32 slice. When there are less than 32 rows at the end, the threads that exceed the actual grid read invalid fill records and skip them, so that the effective rule storage locations of the same adjacent layer are arranged continuously in the GPU memory.

[0045] In this embodiment, as Figure 3 As shown, a regular position formula is used to arrange records corresponding to multiple consecutive lanes under the same adjacent layer k consecutively in memory. The regular position formula pos is: pos = sliceBase[sliceId] + k × sliceRows + lane; Where sliceId represents the slice number, sliceBase[sliceId] represents the starting address of the slice in the rule storage location array, k represents the adjacent layer number, sliceRows represents the number of slice rows, and lane represents the row number of the active mesh within the slice.

[0046] When threads lane0 to lane31 in a GPU thread bundle read records from the same k-layer, the thread access addresses are continuous or nearly continuous, which helps improve the efficiency of video memory access.

[0047] If the number of directed connection records in an active grid is less than the maximum number of adjacent records in a slice, an invalid padding record is written at the missing location. The connection number, opposite grid number, connection side identifier, and off-diagonal block write index of the invalid padding record are all set to -1. After the GPU reads a certain rule location, if the connection number is less than 0, the location is skipped directly and not proceeded to subsequent throughput or matrix calculations.

[0048] In step 5) above, the directed connection records are traversed on the GPU side according to the rules of storage location and thread bundle mapping relationship, including the following steps: 5.1) During GPU traversal, each thread bundle is used as the execution unit. The 32 threads in the same thread bundle are matched one-to-one with the 32 active grid rows on the same adjacent layer index k in the same SELL-C32 slice. Each thread reads the connection number, opposite grid number, connection side identifier and matrix write index at the corresponding rule storage location according to the rule storage location. 5.2) If the read connection number is negative, the storage location of this rule is an invalid fill record, and the current thread skips this location and does not perform subsequent calculations; 5.3) If the read connection number is non-negative, the rule storage location is a valid directed connection record. The current thread will pass the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier, and the matrix write index to the GPU for flux calculation, residual assembly, or Jacobian matrix assembly, for reservoir equation calculation.

[0049] Specifically, in this embodiment, as Figure 4 As shown, the same GPU thread bundle corresponds to 32 possible records of a SELL-C32 slice on a certain adjacent layer k. The thread lane within the thread bundle is consistent with the slice row lane. In a complete slice, the 32 threads correspond to 32 active grids; when there are fewer than 32 rows at the end, threads exceeding the actual grid read invalid records and skip them.

[0050] During GPU traversal, sliceBase and sliceRows are first obtained based on the slice number; then, the rule position pos corresponding to each thread is calculated for the adjacent layer k; next, the connection number, the opposing grid number, and the connection side identifier are read. If the position is valid, the read result is passed to the subsequent calculation module; if the position is invalid, the thread ends the processing of the current adjacent layer.

[0051] In this embodiment, since records within the same adjacent layer are arranged consecutively in memory along lanes, this traversal method can improve the continuity of memory access within a thread bundle. Compared to the CSR format where different threads access along different rowPtr intervals, this embodiment reduces branch divergence caused by differences in access length within a thread bundle.

[0052] In step 5) above, all the bound rule storage locations are stored in the GPU memory in the form of an array to form a unified connection graph data source that can be directly read by the GPU. Specifically, all the rule storage locations after binding the connection graph fields are stored in the GPU memory in the form of connection number array, opposite grid number array, connection side identifier array, valid flag array and non-diagonal block write index array. At the same time, the starting position and row number of each slice are stored in the slice starting position array and slice row number array respectively to form a unified connection graph data source that can be directly read by the GPU.

[0053] In this system, each array in the unified connection graph data source resides in the GPU memory for a long time. When the active grid set or the original grid connection set of the reservoir model does not change, the data source can be reused between time steps without repeated construction.

[0054] In step 6) above, the output GPU-side connection graph data source can be used as a unified input for the subsequent matrix assembly module. For flux right-hand side calculation, the calculation thread can obtain the flow direction and connection number after reading the belonging grid and the opposing grid; for pressure column Jacobi and state column Jacobi assembly, the calculation thread can directly locate the target matrix block based on the connection side identifier and the off-diagonal block write index.

[0055] In a preferred embodiment, the matrix diagonal blocks are located according to their respective grid numbers, while the first and second side off-diagonal block arrays are both located according to their original connection numbers. The connection side identifier in the directed connection record determines whether to write to the first or second side off-diagonal block. This method avoids the GPU repeatedly searching for the correspondence between the two ends of the connection and the off-diagonal blocks.

[0056] This invention does not limit the specific algorithm of the subsequent linear solver. This connection graph data source can be used in the matrix assembly stage of iterative solvers such as GMRES and BiCGSTAB, and can also serve the matrix structure generation required by preprocessors such as CPR, AMG, and ILU.

[0057] In step 6) above, the GPU-side connection graph data source can be saved in two ways: a structured array or an array structure. Considering that continuous reading of the same field is common on the GPU side, the array structure method is preferred, that is, saving arrays such as connId, oppCell, sideFlag, validFlag, offdiagIndex, sliceBase, and sliceRows respectively.

[0058] The `connId` array stores the original connection number; the `oppCell` array stores the opposite active grid number; the `sideFlag` array stores the connection side identifier; `validFlag` can be implicitly represented by whether the connection number is negative, or it can be stored as a separate array; the `offdiagIndex` array stores the subsequent off-diagonal block write index.

[0059] The `sliceBase` array stores the starting position of each slice, and the `sliceRows` array stores the actual number of rows in each slice. For a complete slice, `sliceRows` is 32; for the tail slice, `sliceRows` can be the actual number of rows, or it can be 32 combined with an invalid row indicator.

[0060] In the above embodiments, the present invention further includes a step of SPE10 scale verification: such as Figure 5 As shown, the connection graph organization method of the present invention is verified using the SPE10 large-scale test case. Table 1 lists the key connection graph sizes in the SPE10 test case. The number of directed connection records in Table 1 is twice the original number of connections, and the number of SELL-C32 rule storage locations includes valid records and invalid padding records within slices.

[0061] Table 1

[0062] The model has a grid size of 60×220×85, approximately 1,094,421 active equation lines, approximately 3,067,313 grid connections, approximately 6,134,626 directed connection records, a maximum adjacency of 6, and an average adjacency of 5.61.

[0063] After adopting the SELL-C32 regular location organization, the number of regular storage locations is approximately 6,532,820, with a fill factor of 1.065x. This result demonstrates that in typical million-level reservoir examples, slice storage in 32-row units maintains the regularity of GPU access while introducing only low fill overhead.

[0064] The above results demonstrate the engineering feasibility of this invention at the scale of millions of active grids. For even larger models, this invention can still construct and upload data in segments according to slices, and the data source structure of the connected graph remains unchanged as the model size increases.

[0065] In the above embodiments, the present invention further includes steps for processing non-adjacent connections, fault connections, and locally refined connections. In addition to the adjacent connections along the I, J, and K directions, the reservoir model may also contain fault-crossing connections, non-adjacent connections (NNC), locally refined mesh connections, and engineered additional connections. The present invention does not limit the source of the connection; as long as the connection can be represented as a flow channel between two active meshes, it can be expanded into two directed connection records in the same manner.

[0066] For NNC or tomographic connections, the connection number in the directed connection record still points to the original connection number, and the connection-side identifier is still used to distinguish the write direction at both ends. If it is necessary to distinguish the connection type in subsequent throughput calculations, extended fields such as dirType, nncFlag, or transIndex can be added to the directed record.

[0067] For locally encrypted regions, some grids may have higher adjacency than regular grids. SELL-C32 uses the maximum number of adjacent records within a slice as the slice width, which can limit the filling caused by high local adjacency to within the slice itself, without spreading to all active grids.

[0068] Therefore, this invention is applicable not only to regular corner mesh models, but also to engineering reservoir models that include faults, NNCs, local densification, and complex boundaries.

[0069] In summary, this invention pertains to a connectivity graph organization method and does not limit the specific physical model of the subsequent reservoir equations. In black oil models, connectivity traversal is typically used for calculating oil, water, and gas phase fluxes; in component models, connectivity traversal can be used for multi-component mass flux calculations; and in thermal recovery models, connectivity traversal can also be used for calculating flux or heat conduction terms in the energy equation. Different physical models may have different unknown block sizes, equation components, and physical property parameters, but they all share the common characteristic of requiring the reading of the associated grid, opposing grid, connectivity number, and flow direction information along the grid connections. The directed connectivity data source output by this invention is designed precisely to meet this common requirement. When the model variable set changes, the connectivity graph data source can remain unchanged; the matrix assembly module only needs to change the calculation function corresponding to each rule position and the number of columns written to the matrix block. Therefore, this invention is beneficial for extending different reservoir physical models within the same GPU connectivity traversal framework.

[0070] To ensure the correct organization of the GPU-side connection graph, a consistency check can be performed after construction. The check includes: whether the number of valid directed connection records is equal to twice the number of original connections; whether each original connection corresponds to two directed records in opposite directions; whether invalid fill records are all marked with negative connection numbers; and whether the number of rule storage locations for each slice is equal to the number of slice rows multiplied by the maximum number of adjacent layers of the slice. The number of directed records in each active grid can also be counted and compared grid-by-grid with the adjacency in the original connection graph. Inconsistencies indicate omissions in the connection unrolling or slice writing phases. On the GPU side, connection numbers, opposing grid numbers, and connection-side identifiers can be sampled and read back for comparison with the CPU-side connection graph. While these checks are not essential steps in this invention, they are beneficial for debugging and regression testing during engineering implementation.

[0071] In engineering applications, this invention can be deployed in the data preparation stage of reservoir simulation software. After the geological model, grid system, and connectivity relationships are read in, active grid filtering and connectivity normalization can be performed first, and then the method of this invention can be called to generate a GPU-side connectivity graph data source. This data source is subsequently reused by the flow term calculation, matrix assembly, and solver packaging modules. This invention can still be used in single-machine multi-GPU or multi-node GPU scenarios. Each subdomain can independently construct its own active grid's SELL-C32 directed connectivity slice; cross-subdomain connections can be saved as boundary connections or external connections and participate in traversal after the opposing grid data is updated at the communication layer. During software version iteration, this invention can also be used to unify the connectivity graph source for CPU paths and GPU paths. The CPU side can retain the original connectivity structure for comparison and verification, while the GPU side uses the structure of this invention for assembly. The two paths share the original connectivity numbers, facilitating the location of differences and regression testing.

[0072] For engineering reservoir models, this invention is particularly suitable for scenarios with a large number of connections, numerous NNCs, significant local densification regions, or where the matrix assembly stage has become a computational bottleneck. By pre-binding write positions at the data structure level, the complexity of subsequent assembly functions can be reduced.

[0073] In one embodiment of the present invention, a reservoir connectivity graph GPU organization system based on SELL-C32 directed connectivity slice storage and traversal is provided, comprising: The set acquisition module acquires the active mesh set and the original mesh connection set of the reservoir model, where the original mesh connection is an undirected connection connecting two active meshes; The mesh splitting module splits each original mesh connection into two directed connection records based on the active meshes at both ends. Each directed connection record uses one active mesh as its parent mesh and the other active mesh as its counterpart mesh. The two directed connection records corresponding to the same original mesh connection are associated with different connection side identifiers. The SELL-C32 slice construction module constructs a SELL-C32 slice for every 32 consecutive active grids according to the arrangement order of the active grids. It counts the number of directed connection records in each active grid within each slice and generates a rule storage location based on the maximum number of directed connection records within the slice. The connection graph field binding module binds connection graph fields at each rule storage location. For active grids with fewer directed connection records than the maximum number of directed connection records in a slice, invalid fill records are written at the missing locations. The connection graph fields include connection number, grid number, opposing grid number, connection side identifier, validity flag, and matrix write index. The GPU thread mapping module traverses the directed connection records on the GPU side according to the rule storage location and thread bundle mapping relationship, and stores all the bound rule storage locations into the GPU video memory in the form of an array, forming a unified connection graph data source that can be directly read by the GPU side. The data source output module, on the GPU side, maps each thread in the thread bundle to each active grid row in the same adjacent layer of the slice, reads the connection graph field at each valid rule storage location according to the rule storage location, and outputs the GPU-side connection graph data source for reservoir equation flux calculation, residual assembly or Jacobian matrix assembly based on the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier and the matrix write index.

[0074] In the above embodiment, each original mesh connection is split into two directed connection records based on the active meshes at both ends, specifically: For any original mesh connection Cij, where i and j are the active meshes connected to the two ends of the connection, the following are generated: The first directed connection record, with active grid i as the belonging grid and active grid j as the opposing grid, is used to characterize the directional flow relationship from the belonging grid i to the opposing grid j, and is associated with the first connection side identifier; The second directed connection record, with active grid j as the belonging grid and active grid i as the opposing grid, is used to characterize the directional flow relationship from the belonging grid j to the opposing grid i, and is associated with the second connection side identifier; The first directed connection record and the second directed connection record share the same original connection number, and the first connection side identifier and the second connection side identifier are used to distinguish the non-diagonal block write directions corresponding to the two ends of the same original connection.

[0075] In the above embodiment, a SELL-C32 slice is constructed for every 32 consecutive active grids, including: The active grids are arranged sequentially according to the row order of the matrix. Starting from the beginning of the arrangement, the matrix is ​​divided into slices of 32 consecutive active grids to obtain several SELL-C32 slices. Each complete slice contains 32 rows of active grids. For slices with fewer than 32 active grids at the tail, the following method is used for processing: Method 1: Store according to the actual number of active grid rows of the tail slice; Method 2: Fill the tail slice to 32 rows, and mark the rows that exceed the actual active grid as invalid rows.

[0076] In the above embodiments, on the GPU side, the 32 threads in the same thread bundle correspond to 32 active grid rows in a complete SELL-C32 slice. When there are less than 32 rows at the end, the threads that exceed the actual grid read invalid fill records and skip them, so that the effective rule storage locations of the same adjacent layer are arranged continuously in the GPU memory.

[0077] In the above embodiments, the arrangement order of the active grids is the original active grid numbering order of the reservoir model active grids, the rearranged active grid numbering order, or the active grid numbering order consistent with the matrix assembly order.

[0078] In the above embodiments, traversing the directed connection records on the GPU side according to the rule storage location and thread bundle mapping relationship includes: During GPU traversal, thread bundles are used as execution units. The 32 threads in the same thread bundle correspond one-to-one with the 32 active grid rows on the same adjacent layer index k in the same SELL-C32 slice. Each thread reads the connection number, opposite grid number, connection side identifier and matrix write index at the corresponding rule storage location according to the rule storage location. If the read connection number is negative, the rule storage location is an invalid fill record, and the current thread skips this location and does not perform subsequent calculations; If the read connection number is non-negative, the rule storage location is a valid directed connection record. The current thread will pass the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier, and the matrix write index to the GPU for flux calculation, residual assembly, or Jacobian matrix assembly, for reservoir equation calculation.

[0079] In the above embodiments, all the bound rule storage locations are stored in the GPU memory in array form, forming a unified connection graph data source that can be directly read by the GPU, including: All rules after binding the connection graph field are stored in the GPU memory in the following order: connection number array, opposite grid number array, connection side identifier array, valid flag array, and non-diagonal block write index array. At the same time, the starting position and row number of each slice are stored in the slice starting position array and slice row number array, respectively, forming a unified connection graph data source that can be directly read by the GPU. In this system, each array in the unified connection graph data source resides in the GPU memory for a long time. When the active grid set or the original grid connection set of the reservoir model does not change, the data source can be reused between time steps without repeated construction.

[0080] The system provided in this embodiment is used to execute the above-described method embodiments. For specific processes and details, please refer to the above embodiments, which will not be repeated here.

[0081] In one embodiment of the present invention, a computing device is provided, which may be a terminal and may include: one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, and the one or more programs include instructions for performing any of the methods in the above embodiments.

[0082] Furthermore, when the aforementioned instructions can be implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0083] In one embodiment of the present invention, a computer program product is provided, the computer program product including a computer program stored on a non-transitory computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by a computer, the computer is able to perform the methods provided in the above-described method embodiments.

[0084] In one embodiment of the present invention, a non-transitory computer-readable storage medium is provided, which stores server instructions that cause a computer to perform the methods provided in the above embodiments.

[0085] The computer-readable storage medium provided in the above embodiments has a similar implementation principle and technical effect to the above method embodiments, and will not be described again here.

[0086] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0087] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0088] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GPU organization method for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal, characterized in that, include: Obtain the active mesh set and the original mesh connection set of the reservoir model, where the original mesh connection is an undirected connection connecting two active meshes; Each original mesh connection is split into two directed connection records based on the active meshes at both ends. Each directed connection record uses one active mesh as its parent mesh and the other active mesh as its counterpart mesh. The two directed connection records corresponding to the same original mesh connection are associated with different connection side identifiers. According to the arrangement order of the active grids, a SELL-C32 slice is constructed for every 32 consecutive active grids. The number of directed connection records of each active grid in each slice is counted, and the rule storage location is generated based on the maximum number of directed connection records in the slice. Bind a connection graph field at each rule storage location. For active grids with fewer directed connection records than the maximum number of directed connection records in a slice, write invalid fill records at the missing locations. The connection graph field includes connection number, grid number, opposing grid number, connection side identifier, valid flag, and matrix write index. On the GPU side, the directed connection records are traversed according to the rule storage location and thread bundle mapping relationship. All the bound rule storage locations are stored in the GPU video memory in the form of an array to form a unified connection graph data source that can be directly read by the GPU side. On the GPU side, each thread within a thread bundle is mapped one-to-one with each active grid row in the same adjacent layer within a slice. The connection graph fields at each valid rule storage location are read according to the rule storage location. Based on the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier, and the matrix write index, the GPU-side connection graph data source is output for reservoir equation flux calculation, residual assembly, or Jacobi matrix assembly.

2. The GPU organization method for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal as described in claim 1, characterized in that, Each original mesh connection is split into two directed connection records based on the active meshes at both ends, specifically: For any original mesh connection Cij, where i and j are the active meshes connected to the two ends of the connection, the following are generated: The first directed connection record, with active grid i as the belonging grid and active grid j as the opposing grid, is used to characterize the directional flow relationship from the belonging grid i to the opposing grid j, and is associated with the first connection side identifier; The second directed connection record, with active grid j as the belonging grid and active grid i as the opposing grid, is used to characterize the directional flow relationship from the belonging grid j to the opposing grid i, and is associated with the second connection side identifier; The first directed connection record and the second directed connection record share the same original connection number, and the first connection side identifier and the second connection side identifier are used to distinguish the non-diagonal block write directions corresponding to the two ends of the same original connection.

3. The GPU organization method for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal as described in claim 1, characterized in that, A SELL-C32 slice is constructed for every 32 consecutive active grids, including: The active grids are arranged sequentially according to the row order of the Jacobian matrix. Starting from the beginning of the arrangement, the grids are divided into slices of 32 consecutive active grids to obtain several SELL-C32 slices. Each complete slice contains 32 rows of active grids. For slices with fewer than 32 active grids at the tail, the following method is used for processing: Method 1: Store according to the actual number of active grid rows of the tail slice; Method 2: Fill the tail slice to 32 rows, and mark the rows that exceed the actual active grid as invalid rows.

4. The GPU organization method for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal as described in claim 3, characterized in that, On the GPU side, the 32 threads in the same thread bundle correspond to 32 active grid rows in a complete SELL-C32 slice. When there are fewer than 32 rows at the end, the threads that exceed the actual grid read invalid padding records and skip them, so that the valid rule storage locations of the same adjacent layer are arranged continuously in the GPU memory.

5. The GPU organization method for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal as described in claim 1, characterized in that, The active grids are arranged in the order of their original active grid numbers, the rearranged active grid numbers, or the active grid number order consistent with the matrix assembly order.

6. The GPU organization method for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal as described in claim 1, characterized in that, On the GPU side, the directed connection records are traversed according to the rules of storage location and thread bundle mapping relationship, including: During GPU traversal, thread bundles are used as execution units. The 32 threads in the same thread bundle correspond one-to-one with the 32 active grid rows on the same adjacent layer index k in the same SELL-C32 slice. Each thread reads the connection number, opposite grid number, connection side identifier and matrix write index at the corresponding rule storage location according to the rule storage location. If the read connection number is negative, the rule storage location is an invalid fill record, and the current thread skips this location and does not perform subsequent calculations; If the read connection number is non-negative, the rule storage location is a valid directed connection record. The current thread will pass the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier, and the matrix write index to the GPU for flux calculation, residual assembly, or Jacobian matrix assembly, for reservoir equation calculation.

7. The GPU organization method for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal as described in claim 1, characterized in that, All bound rules are stored in the GPU memory as an array, forming a unified connection graph data source that can be directly read by the GPU, including: All rules after binding the connection graph field are stored in the GPU memory in the following order: connection number array, opposite grid number array, connection side identifier array, valid flag array, and non-diagonal block write index array. At the same time, the starting position and row number of each slice are stored in the slice starting position array and slice row number array, respectively, forming a unified connection graph data source that can be directly read by the GPU. In this system, each array in the unified connection graph data source resides in the GPU memory for a long time. When the active grid set or the original grid connection set of the reservoir model does not change, the data source can be reused between time steps without repeated construction.

8. A GPU organization system for reservoir connectivity graphs based on SELL-C32 directed connectivity slice storage and traversal, characterized in that, include: The set acquisition module acquires the active mesh set and the original mesh connection set of the reservoir model, where the original mesh connection is an undirected connection connecting two active meshes; The mesh splitting module splits each original mesh connection into two directed connection records based on the active meshes at both ends. Each directed connection record uses one active mesh as its parent mesh and the other active mesh as its counterpart mesh. The two directed connection records corresponding to the same original mesh connection are associated with different connection side identifiers. The SELL-C32 slice construction module constructs a SELL-C32 slice for every 32 consecutive active grids according to the arrangement order of the active grids. It counts the number of directed connection records in each active grid within each slice and generates a rule storage location based on the maximum number of directed connection records within the slice. The connection graph field binding module binds connection graph fields at each rule storage location. For active grids with fewer directed connection records than the maximum number of directed connection records in a slice, invalid fill records are written at the missing locations. The connection graph fields include connection number, grid number, opposing grid number, connection side identifier, validity flag, and matrix write index. The GPU thread mapping module traverses the directed connection records on the GPU side according to the rule storage location and thread bundle mapping relationship, and stores all the bound rule storage locations into the GPU video memory in the form of an array, forming a unified connection graph data source that can be directly read by the GPU side. The data source output module, on the GPU side, maps each thread in the thread bundle to each active grid row in the same adjacent layer of the slice, reads the connection graph field at each valid rule storage location according to the rule storage location, and outputs the GPU-side connection graph data source for reservoir equation flux calculation, residual assembly or Jacobian matrix assembly based on the read connection number, the grid number to which it belongs, the opposing grid number, the connection side identifier and the matrix write index.

9. A computer-readable storage medium for storing one or more programs, characterized in that, The one or more programs include instructions that, when executed by a computing device, cause the computing device to perform any of the methods described in claims 1 to 7.

10. A computing device, characterized in that, include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the methods described in claims 1 to 7.

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