A processor microarchitecture design space exploration method and related apparatus

Abstract

The application discloses a processor micro-architecture design space exploration method and related devices, the method comprises the following steps: generating a plurality of initial candidate designs for different target preferences by using a large language model according to a design space, and taking each initial candidate design as a child node of a virtual root node of a Monte Carlo tree; calling a real performance evaluation environment to perform real performance evaluation on the child node of the virtual root node, and constructing a Pareto archive using a hyper-volume measure quality according to a real performance evaluation result; performing iterative search until a preset iteration termination condition is reached, and taking one or more candidate designs in the Pareto archive constructed in the last iteration as a final design; wherein the process of each search is as follows: determining a to-be-expanded child node by using a Pareto-aware tree strategy, performing local optimization expansion and differentiated exploration expansion on the to-be-expanded child node by using a large language model, and generating child nodes of the to-be-expanded child node; wherein the child nodes of the to-be-expanded child node are new candidate designs; calling a real performance evaluation environment to perform real performance evaluation on the child nodes of the to-be-expanded child node, and constructing a Pareto archive according to a real performance evaluation result. The application generates a more reasonable candidate design through a large language model, preferentially expands a more potential word node through a Pareto-aware tree strategy, and makes real simulation budget more concentrated on high-value candidates, so that the search sample efficiency can be improved under a limited simulation budget.

Description

Technical Field

[0001] This invention relates to a method and related apparatus for exploring the design space of processor microarchitecture, belonging to the fields of electronic design automation, computer architecture optimization, and artificial intelligence-aided design technology. Background Technology

[0002] As processor design evolves from general-purpose architectures to customized architectures oriented towards workload characteristics, the selection of microarchitecture parameters has become a crucial factor determining processor performance, power consumption, and area. A typical processor exhibits complex coupling relationships among its front-end fetch width, decode width, renaming resources, reorder buffer size, number of integer / floating-point / vector physical registers, execution queue size, load / memory queues, cache capacity and associativity, branch prediction structure, TLB (Translation Lookaside Buffer), and memory access buffer structure. Changes in any parameter can affect pipeline congestion, memory hit rate, out-of-order window utilization, front-end bandwidth matching, and area and power consumption overhead. Therefore, the processor microarchitecture design space typically exhibits high dimensionality, discreteness, non-smoothness, and strong correlation. Existing methods for exploring the processor microarchitecture design space rely on random mutation, surrogate model prediction, or single-round large model sampling, which easily wastes a large number of real evaluation attempts in low-quality regions, resulting in low sample search efficiency under limited simulation budgets. Summary of the Invention

[0003] This invention provides a method and related apparatus for exploring the design space of processor microarchitecture, which solves the problems disclosed in the background art.

[0004] According to one aspect of this application, a method for exploring the design space of a processor microarchitecture is provided, comprising: Based on the design space, a large language model is used to generate multiple initial candidate designs for different target preferences, and each initial candidate design is used as a child node of the virtual root node of the Monte Carlo tree. The real performance evaluation environment is invoked to perform real performance evaluation on the child nodes of the virtual root node, and a Pareto profile using hypervolume to measure quality is constructed based on the real performance evaluation results. Perform iterative search until the preset iteration termination condition is met, and take one or more candidate designs from the Pareto profile built in the last iteration as the final design; The process of each search is as follows: The Pareto perceptual tree strategy is used to determine the child nodes to be expanded. A large language model is used to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded, generating child nodes of the child nodes to be expanded. Among them, the child nodes of the child nodes to be expanded are the generated new candidate designs. The Pareto perceptual tree strategy is a child node selection strategy that considers the hypervolume gain of the child nodes to the Pareto front, the sparsity of the distribution of the true performance evaluation results of the child nodes in the target space, the number of visits to the child nodes and the number of visits to the parent nodes. The system invokes a real performance evaluation environment to perform real performance evaluations on the child nodes of the child nodes to be expanded, and constructs a Pareto profile based on the real performance evaluation results.

[0005] Furthermore, the Pareto perceptual tree strategy is used to determine the child nodes to be expanded, including: Based on the hypervolume gain of the child node to the Pareto front, the sparsity of the distribution of the child node's true performance evaluation results in the target space, the number of visits to the child node, and the number of visits to the parent node, a selection score is calculated for each child node. The child node with the highest selection score is selected as the child node to be expanded. The selection score is the sum of the Pareto quality term, the diversity term weighted by the first weighting coefficient, and the exploration term weighted by the second weighting coefficient. The Pareto quality term is the hypervolume gain brought by the child node, the diversity term is the sparsity of the distribution of the child node's true performance evaluation results in the target space, and the exploration term is positively correlated with the logarithm of the number of visits to the parent node and negatively correlated with the number of visits to the child node.

[0006] Furthermore, the method also includes an information feedback step, which includes: After each real performance evaluation, the reward value for this child node expansion is determined based on the evaluation results, and the access count and value of each child node along the path from the child node to the virtual root node are updated.

[0007] Furthermore, a large language model is used to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded, including: The local optimization expansion takes the historical extended knowledge sampled from the extended knowledge memory, the control instructions corresponding to the state of the large language model, the child nodes to be expanded, and the real performance evaluation results and Pareto front analysis results corresponding to the child nodes to be expanded as inputs, and uses the large language model to perform local optimization expansion on the child nodes to be expanded. The differentiation exploration is extended to take the child node to be expanded and its corresponding real performance evaluation results, as well as the sibling child node and its real performance evaluation results, as inputs. A large language model is used to perform local optimization expansion on the child node to be expanded; where the sibling child node is the child node under the same parent node.

[0008] Furthermore, the method also includes a step of expanding knowledge accumulation, which includes: After each real performance evaluation, if the real performance evaluation results of the child node determine that the child node causes a positive gain in the supervolume or improves the performance of the child node relative to the parent node in at least one objective, then based on the changes between the parent and child nodes, the changes in the real performance evaluation, and the overall distribution of the Pareto front, the large oracle model is used to extract extended knowledge, and the extended knowledge is added to the extended knowledge memory.

[0009] Furthermore, the extended knowledge includes Pareto analysis knowledge and parent-child difference knowledge; Pareto analysis knowledge is to summarize the recurring or consistent variational patterns of microarchitectural parameter combinations and the target areas that are not yet fully covered from multiple non-dominated candidate designs located at different objectives; among them, non-dominated candidate designs are candidate designs that are not simultaneously dominated by other candidate designs among all candidate designs that have completed real performance evaluation up to the current iteration. Parent-child difference knowledge is a reusable adjustment principle that is effective for improving a certain type of target, extracted from the changes between parent and child nodes and the changes in actual performance evaluation.

[0010] Furthermore, the method also includes a step of controlling the state switching of a large language model, which includes: The state switching of the large language model is controlled based on the supervolume gain effect of the most recent N consecutive iterations and the supervolume gain effect of the most recent child node expansion; where N is a preset value.

[0011] According to another aspect of this application, a processor microarchitecture design space exploration device is provided, comprising: The initial generation module, based on the design space, uses a large language model to generate multiple initial candidate designs oriented towards different target preferences, and treats each initial candidate design as a child node of the virtual root node of the Monte Carlo tree; The initial evaluation module calls the real performance evaluation environment to perform real performance evaluation on the child nodes of the virtual root node, and constructs a Pareto profile that uses hypervolume to measure quality based on the real performance evaluation results. The iteration module performs iterative searches until the preset iteration termination condition is met, and takes one or more candidate designs from the Pareto profile built in the last iteration as the final design. The process of each search is as follows: The Pareto perceptual tree strategy is used to determine the child nodes to be expanded. A large language model is used to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded, generating child nodes of the child nodes to be expanded. Among them, the child nodes of the child nodes to be expanded are the generated new candidate designs. The Pareto perceptual tree strategy is a child node selection strategy that considers the hypervolume gain of the child nodes to the Pareto front, the sparsity of the distribution of the true performance evaluation results of the child nodes in the target space, the number of visits to the child nodes and the number of visits to the parent nodes. The system invokes a real performance evaluation environment to perform real performance evaluations on the child nodes of the child nodes to be expanded, and constructs a Pareto profile based on the real performance evaluation results.

[0012] According to another aspect of this application, a computer-readable storage medium is provided that stores one or more programs, the one or more programs including instructions that, when executed by a computing device, cause the computing device to perform a processor microarchitecture design space exploration method.

[0013] According to another aspect of this application, a computer device is provided, including one or more processors and one or more memories, wherein one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for performing a processor microarchitecture design space exploration method.

[0014] The beneficial effects achieved by this invention are as follows: 1. This invention generates candidate designs with more reasonable structures through a large language model and prioritizes the expansion of more promising byte points through a Pareto perceptual tree strategy, making the real simulation budget more focused on high-value candidates, thereby improving the efficiency of search samples under a limited simulation budget; 2. This invention introduces hypervolume gain, crowding distance or sparsity of the target space, and access count when determining the child nodes to be expanded, while taking into account both Pareto front quality and front coverage diversity, making it more suitable for multi-objective processor design optimization; 3. This invention uses two expansion operators during expansion, taking into account both local optimization expansion and global differential exploration expansion, and global differential exploration expansion can enhance the ability to escape local optima; 4. This invention also accumulates expansion knowledge for the local optimization expansion of subsequent child nodes, thereby continuously accumulating interpretable optimization experience during the search process, realizing continuous learning and explicit knowledge reuse capabilities, thus efficiently approximating the Pareto optimal solution set under a limited simulation budget. Attached Figure Description

[0015] Figure 1 A flowchart illustrating a method for exploring space design for processor microarchitecture; Figure 2 A flowchart for the iterative search; Figure 3 This is a flowchart of the state transition; Figure 4 A block diagram of a space exploration device designed for a processor microarchitecture. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0017] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application.

[0018] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0019] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0020] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0021] It should be noted that similar symbols and letters in the accompanying drawings represent similar items; therefore, once an item is defined in one accompanying drawing, it does not need to be discussed further in subsequent accompanying drawings.

[0022] Large language models are a type of deep learning-based artificial intelligence technology and a core research area in natural language processing. Their core principle is to train models using large-scale datasets, enabling them to generate natural language text or understand the meaning of spoken text. These models learn and simulate the complex rules of human language through layered neural network structures, achieving near-human-level text generation capabilities. Large language models employ a similar Transformer architecture and pre-training objectives to small models; the main difference lies in the increased model size, training data, and computational resources. Compared to traditional natural language processing models, large language models can better understand and generate natural text, while also exhibiting a certain degree of logical thinking and reasoning ability.

[0023] Monte Carlo tree search is a heuristic search algorithm for decision-making processes, particularly suitable for problems that are difficult to solve precisely using traditional methods. The Monte Carlo tree search algorithm searches by representing the problem space as a tree, where each node represents a decision point or state, and edges represent actions or decisions that transition from one state to another. Monte Carlo tree search has wide applications in game AI, optimization problems, and uncertain decision-making, and it is especially suitable for problems where it is difficult to manually design evaluation functions or where the search space is enormous.

[0024] This application provides a method for exploring the microarchitecture design space of a processor based on large language models and Monte Carlo tree search technology. This exploration method can be executed by an exploration device, which can be a terminal device or a server. The terminal device can include, but is not limited to, mobile phones, computers, etc. The server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, big data, and artificial intelligence platforms. Optionally, this exploration method can also be executed collaboratively by multiple electronic devices with computing power. For ease of explanation, subsequent embodiments will be described as being executed by an exploration device.

[0025] See Figure 1 , Figure 1 This is a flowchart of a processor microarchitecture design space exploration method provided in an embodiment of this application. The exploration method can be executed by an exploration device and may include at least the following steps: Step 1: Based on the design space, use a large language model to generate multiple initial candidate designs for different target preferences, and treat each initial candidate design as a child node of the virtual root node of the Monte Carlo tree.

[0026] It should be noted that the design space is the microarchitecture design space of the target processor. This design space can be given in advance by the designer and contains a set of discrete parameters under multiple functional domains. These parameters may include relevant parameters from the front-end instruction fetch module, decoding and renaming module, execution resource module, memory access module, caching module, and branch prediction module. These parameters are expanded into configuration vectors in a fixed order, and a mapping table is established between parameter names and candidate value sets.

[0027] In this example, the design space can be expanded into flat feature columns in the format "module name.parameter name". Examples include IFU.FetchWidth, IFU.fetchQueueSize, IDU.DecodeWidth, IDU.RenameWidth, IDU.ROBSize, EXE-type queue parameters, LSU-type queue parameters, Cache.ICacheSize, Cache.DCacheSize, and BPU-related BTB and RAS parameters. At startup, the design space file is read, parameter order is preserved, and a list of valid candidate values ​​is saved for each dimension of the parameter.

[0028] To enhance the usability of subsequent large language model outputs, parameter value validation functions can be built for the outputs. For ordinary integer or floating-point parameters, if the model outputs an invalid value, it is mapped to the nearest valid candidate value. For capacity-type parameters, such as "16 kB", "32 kB", and "64 kB", the string can be parsed into a uniform capacity unit before mapping to the nearest valid candidate value. If unparseable text, missing fields, or inconsistent lengths are encountered, the candidate configuration is directly determined to be invalid. Validation ensures that the output of the large language model can be reliably integrated into the simulation toolchain.

[0029] It should be noted that the large language model can be provided with design space and initialization instructions for different target preferences, thereby obtaining multiple initial candidate designs with different target preferences (performance-power-area trade-offs). Multiple initial candidate designs serve as the starting point for subsequent searches, and a wider range of trade-offs can be obtained in the early stages of the search. Among them, different target preferences include, but are not limited to: aggressive solutions that prioritize the highest performance, conservative solutions that prioritize reducing power consumption and area, balanced solutions that take into account both performance and cost, performance-biased solutions that compromise between high performance and high cost, and energy-efficiency-biased solutions that avoid serious bottlenecks under low power consumption and low area conditions.

[0030] In this example, five initial candidate designs are generated, corresponding to five preferences: high performance, high energy efficiency, balanced, performance-skewed, and power / area-skewed. To this end, the design space and several general microarchitectural heuristics (i.e., initialization instructions) can be input into the large language model, such as "front-end bandwidth and execution bandwidth need to be coordinated," "caching and buffer expansion are only effective when real bottlenecks exist," and "balanced resource configuration is often more robust than single-point extreme expansion." Based on this, the large language model outputs five distinct initial candidate designs. This step improves the quality of the initial samples and allows the search tree to expand simultaneously from multiple structural patterns, rather than being limited to a single initial point.

[0031] Step 2: Call the real performance evaluation environment to perform real performance evaluation on the child nodes of the virtual root node, and construct a Pareto profile that uses hypervolume to measure quality based on the real performance evaluation results.

[0032] It should be noted that the evaluation environment can include cycle-level processor simulators and power-area assessment tools. For example, performance metrics can be obtained using gem5 or other cycle-accurate simulators, and area and power-area metrics can be obtained using McPAT or other modeling tools. To enhance the robustness of the evaluation, when performing a true performance evaluation on each child node, it is preferable to execute simulations on multiple benchmark programs and aggregate the child node's overall performance, overall power consumption, and overall area using methods such as geometric averaging. Subsequently, a Pareto profile is constructed based on non-dominant relationships, and the quality of the Pareto profile is measured by hypervolume.

[0033] Step 3, perform iterative search (see...) Figure 2 (This continues until a preset iteration termination condition is met, at which point one or more candidate designs from the Pareto profile built in the last iteration are selected as the final design; the search process for each iteration is as follows:) 1) The Pareto perceptual tree strategy is used to determine the child nodes to be expanded. The large language model is used to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded, generating the child nodes of the child nodes to be expanded. Among them, the child nodes of the child nodes to be expanded are the newly generated candidate designs. The Pareto perceptual tree strategy is a child node selection strategy that considers the hypervolume gain of the child node to the Pareto front, the sparsity of the distribution of the true performance evaluation results of the child node in the target space, the number of visits to the child node and the number of visits to the parent node.

[0034] In some embodiments, a Pareto perceptual tree strategy is used to determine the child nodes to be expanded. The specific process may include: calculating the selection score of each child node based on the hypervolume gain of the child node to the Pareto front, the sparsity of the distribution of the child node's true performance evaluation results in the target space, the number of visits to the child node and the number of visits to the parent node, and selecting the child node with the highest score as the child node to be expanded.

[0035] The selection score is the sum of the Pareto quality term, the diversity term weighted by a first weighting coefficient, and the exploration term weighted by a second weighting coefficient. The first weighting coefficient is used to adjust the influence of the diversity term on the selection score and can be preset according to the normalization range of each target value and the search diversity requirements. In one specific embodiment, the first weighting coefficient is set to 0.05. The second weighting coefficient can be set to decrease dynamically with the iteration progress, so that the coverage of different target regions is expanded first in the early stage of the search, and the nodes to be expanded are selected more based on the Pareto quality and distribution diversity of the nodes in the later stage of the search.

[0036] The Pareto mass term is the hypervolume gain brought by the child nodes, used to reflect the Pareto mass.

[0037] The diversity term represents the sparsity of the distribution of the true performance evaluation results of child nodes in the target space. In other words, the true performance evaluation results of child nodes are mapped to a point in the target space, and the diversity term represents the sparsity of that point's distribution in the target space. For example, it could be the crowding distance between the child node and its sibling nodes in the target space (the current set of non-dominated candidate designs selected from all candidate designs that have completed true performance evaluations in the entire Monte Carlo search tree up to the current iteration). This encourages coverage of areas that have not yet been fully explored, reflecting diversity.

[0038] The number of explorations is positively correlated with the logarithm of the number of visits to the parent node and negatively correlated with the number of visits to the child node. This is used to preserve the opportunity to continue trying in uncertain areas, that is, to give nodes that are visited less but have potential value the opportunity to expand.

[0039] In the specific code implementation, to accommodate the order-of-magnitude differences in the three objectives of performance, area, and power consumption, the target values ​​(which are the values ​​of various optimization indicators obtained through real performance evaluation of each candidate design, including performance indicators, power consumption indicators, and area indicators) can be logarithmically taken and normalized before calculating the crowding distance and hypervolume. Compared to simply selecting points based on average reward, this implementation method is better able to avoid premature clustering in local areas.

[0040] Unlike traditional UCT strategies that only use a single reward and confidence upper bound, this approach introduces supervolume gain, target space distribution sparsity, and access count when determining the child nodes to be expanded. It also takes into account Pareto front quality and front coverage diversity, making it more suitable for multi-target processor design optimization.

[0041] In some embodiments, employing a large language model to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded may include: A. The large language model is used to perform local optimization expansion on the child nodes to be expanded, taking the historical extended knowledge sampled from the extended knowledge memory, the control instructions corresponding to the state of the large language model (utilization-oriented control instructions, balanced control instructions, or exploration-oriented control instructions), the child nodes to be expanded, and the actual performance evaluation results and Pareto front analysis results corresponding to the child nodes to be expanded as inputs.

[0042] B. Using the sibling child nodes of the child node to be expanded and their actual performance evaluation results as input, a large language model is used to perform local optimization expansion on the child node to be expanded; where sibling child nodes are child nodes under the same parent node.

[0043] Two types of extension operators driven by large language models are designed here, as follows: The first type is the knowledge fine-tuning operator, whose inputs include historical extended knowledge, control instructions corresponding to the state of the large language model, the child nodes to be extended, and the actual performance evaluation results and Pareto front analysis results corresponding to the child nodes to be extended; this operator is used to make local but structurally coordinated improvements around the child nodes to be extended.

[0044] For example, when improving a specific target, the coupled buffer, queue, bandwidth, and register resources should be considered simultaneously to avoid invalid or conflicting parameter adjustments. Specifically, if the child node to be expanded already has strong front-end bandwidth but high power consumption, the model can be guided to consider reducing certain area-sensitive structures while maintaining critical throughput resources; if the child node to be expanded lags behind in performance, the model can be guided to prioritize optimizing pipeline bottlenecks rather than blindly expanding all caches. The second type is the pattern exploration operator, whose input includes the child node to be expanded and the actual performance evaluation results corresponding to the child node to be expanded, the sibling child node to be expanded and the actual performance evaluation results of the sibling child node, which are used to identify the currently explored structural patterns and generate new candidate designs (i.e. child nodes) that are significantly different from the existing patterns, thereby escaping the local optimum region.

[0045] The second type enables large language models to recognize designs that have already been tried under the same parent node. The model's task is not to make minor tweaks near the current point, but to generate new candidate designs that are significantly different from the current one. For example, after exploring the "wide emission + large cache" pattern, the model might propose an alternative pattern of "moderate front-end + more aggressive branch prediction + lightweight cache" to cover the potential optimal range under different workloads.

[0046] Unlike large language model methods that rely solely on local fine-tuning and are prone to repeated patching around a few successful patterns, or methods that rely solely on random jumps and may lose structural rationality, this approach employs two extension operators that take into account both local optimization extension and global differential exploration extension. Furthermore, the global differential exploration extension can enhance the ability to escape local optima.

[0047] 2) Call the real performance evaluation environment to perform real performance evaluation on the child nodes of the child nodes to be expanded, and construct the Pareto profile based on the real performance evaluation results.

[0048] The actual performance evaluation here is the same as the actual performance evaluation in step 2, so I won't repeat it here.

[0049] It should be noted that, in some embodiments, after each real performance evaluation, the reward value for this child node expansion is determined based on the evaluation results, and the access count and child node value of each child node on the path from the child node to the virtual root node are updated.

[0050] The reward values ​​mentioned above include positive rewards and negative rewards (i.e., penalties). If a child node can increase the hypervolume (i.e., positive gain), the hypervolume increment is normalized and mapped to a positive reward. If a child node does not enter the Pareto front, a certain penalty is applied based on its distance to the current Pareto front. Through "backpropagation" in Monte Carlo tree search, the statistical information of the entire search tree is updated, providing a statistical basis for subsequent Pareto-aware tree strategies.

[0051] It should be noted that, in some embodiments, after each real performance evaluation, if it is determined that the child node causes a positive gain in the supervolume (e.g., the Pareto front supervolume growth exceeds 1% of the current overall supervolume) or achieves improvement relative to the parent node in at least one objective (e.g., the performance improvement ratio, area reduction ratio, or power consumption reduction ratio exceeds 10% relative to the parent node), based on the changes between the parent and child nodes, the changes in real performance evaluation, and the overall distribution of the Pareto front, the large oracle model is used to extract extended knowledge, and the extended knowledge is added to the extended knowledge memory, thereby achieving the accumulation of extended knowledge, which can be used for the local optimization extension of subsequent child nodes. Thus, interpretable optimization experience can be continuously accumulated during the search process, realizing continuous learning and explicit knowledge reuse capabilities, thereby efficiently approximating the Pareto optimal solution set under a limited simulation budget.

[0052] Extended knowledge is extracted at two levels, specifically including Pareto analysis knowledge and parent-child difference knowledge: Pareto analysis provides knowledge by summarizing recurring microarchitectural parameter combination patterns or those with consistent variation relationships from multiple non-dominated candidate designs located at different objectives, as well as target regions that are not yet fully covered (target regions that are not yet fully covered refer to areas in the target space where there are few existing candidate designs, large crowding distances, or significant gaps between current Pareto fronts), providing macro-level direction for subsequent searches. Among these, non-dominated candidate designs are those that, up to the current iteration, are not simultaneously dominated by other candidate designs among all candidate designs that have completed real performance evaluation.

[0053] Parent-child difference knowledge is a reusable adjustment principle that is effective for improving a certain type of target, extracted from the changes between parent and child nodes and the changes in actual performance evaluation.

[0054] The extended knowledge mentioned above is not a fixed parameter value, but rather a short knowledge phrase. This can enhance the ability to reuse across states and reduce the sensitivity to single simulation errors.

[0055] The above-mentioned extraction process can transform the current set of non-dominated candidate designs into a structured summary of "candidate design-evaluation results," requiring the large language model to summarize: which structural combinations are repeatedly effective in different trade-off regions; which intermediate regions or special trade-off regions are missing in the current Pareto front; and what direction should be prioritized for the next search. Secondly, parent-child difference knowledge extraction can input the parent node, child node, and their actual performance evaluation results into the large language model, asking it to generate a reusable design principle based solely on the current parameter differences and target changes, such as "In power-constrained scenarios, prioritizing the compression of storage levels and register resources is more effective than reducing critical execution bandwidth." The resulting knowledge sentence is both more abstract than the original numerical results and closer to the current design space than pure textbook knowledge.

[0056] It should be noted that when constructing the extended knowledge memory, information such as text content, creation time, number of uses, cumulative volume gain, and recent consecutive success count are recorded for each extended knowledge entry. To avoid redundancy and knowledge pollution, when adding new extended knowledge, text embedding similarity can be used for deduplication. That is, the cosine similarity with existing knowledge entries is calculated using a text embedding model. If the similarity is higher than 75%, it is determined to be duplicate knowledge and discarded; if it is not duplicated, a new entry is created and metadata such as source, creation time, number of uses, and cumulative gains are recorded.

[0057] To ensure that the most valuable extended knowledge is retrieved during expansion, a knowledge scoring function can be established, comprehensively considering the cumulative benefit of extended knowledge (the benefit of extended knowledge comes from the hypervolume gain brought by the generated candidate designs after the knowledge is actually used to guide the candidate design generation), usage penalties, and recent consecutive effective rewards. Extended knowledge that brings significant cumulative hypervolume gain receives higher scores, frequently used extended knowledge is penalized due to declining marginal returns, and extended knowledge that has achieved positive effects recently receives additional points. Before each round of expansion, samples are taken from the highest-scoring extended knowledge to enhance the quality of subsequent prompts.

[0058] To further improve the balance between exploration and utilization during the search process, in some embodiments, the above method also includes a step of controlling the state switching of the large language model. This step includes: controlling the state switching of the large language model based on the supervolume gain effect of the most recent N consecutive iterations and the supervolume gain effect of the most recent child node expansion; where N is a preset value, typically 3.

[0059] See also Figure 3Specifically, a stagnation counter can be used to count how many consecutive rounds have passed without a significant increase in supervolume. Simultaneously, the recent effects of the knowledge fine-tuning operator and the pattern exploration operator can be statistically analyzed, specifically whether the best supervolume gain in the most recently generated child nodes by the knowledge fine-tuning operator and the pattern exploration operator exceeds a threshold. In a particular embodiment, if three consecutive rounds of expansion iterations fail to achieve an improvement of 1% of the current overall supervolume, the state is considered stagnant, and the supervolume improvement threshold corresponding to the expansion operation is also set to 1% of the overall supervolume. Based on these two signals, switching between three states is performed.

[0060] It should be noted that the first type of signal is a global stagnation signal, which counts the number of consecutive evaluations or iterations that have failed to achieve a hypervolume gain exceeding a threshold. It only determines whether the entire search has stagnated, without distinguishing which operator generated the candidate design. The second type of signal is an operator effectiveness signal, which separately counts the hypervolume gain of candidate designs generated by the knowledge fine-tuning operator and the pattern exploration operator within a preset recent window. It is used to compare whether local optimization or structure exploration is more suitable at the current stage. The three states are: utilization-biased, equilibrium, and exploration-biased. The utilization-biased state is suitable for situations with low stagnation and good recent performance of the knowledge fine-tuning operator. In this state, the prompts instruct the model to "make local optimizations around the current effective configuration" and "maintain the stability of the main structure pattern." The equilibrium state is suitable for situations where the search continues but there is no obvious unilateral advantage. In this state, the model is prompted to make moderate adjustments while preserving structural coordination. The exploration-biased state is suitable for situations with high stagnation counts, insufficient current regional gains, or a more advantageous pattern exploration operator. In this state, the model is prompted to avoid making only minor modifications and instead perform pattern-level transformations and cross-regional searches for uncovered Pareto regions.

[0061] Specifically, when local improvements are detected to be consistently effective and stagnation is low, a biased utilization state is preferred, guiding the large language model to perform small but high-quality local optimizations. When the overall search progresses smoothly, a balanced state is preferred, making moderate modifications while maintaining structural consistency. When the stagnation count exceeds 3, or the current region clearly lacks global gain, a biased exploration state is preferred, encouraging the large language model to perform pattern-level reconstruction and cross-regional jumps. This state information is directly injected as a natural language instruction, forming soft control over the generative behavior of the large language model.

[0062] It should be noted that the iteration termination condition is reaching the preset number of real performance evaluations, i.e., the simulation budget is exhausted. Of course, the termination condition can also be one or more of the following: 1. The hypervolume of the current Pareto profile reaches the preset hypervolume threshold; 2. A candidate design that meets the preset performance, power consumption and area constraints appears in the current Pareto profile; 3. The hypervolume gain of the current Pareto profile is lower than the preset gain threshold after a preset number of iterations; 4. The distance between the current Pareto front and the preset reference front is lower than the preset distance threshold.

[0063] The above methods enhance the interpretability of the search process through knowledge text, Pareto front analysis, state-aware instructions, and node selection records. They can answer questions such as "Why are these parameter changes recommended in this round?", "What type of trade-off design is currently lacking?", and "Which experience has been most effective recently?", helping engineers understand the optimization process rather than just receiving black-box output.

[0064] The above method generates candidate designs with more reasonable structures through a large language model and prioritizes the expansion of more promising byte points through the Pareto perceptual tree strategy, so that the real simulation budget is more focused on high-value candidates, thereby improving the efficiency of search samples under a limited simulation budget.

[0065] The above method forms a complete closed loop of "design space modeling - multi-starting point initialization - Pareto-aware node selection - dual operator expansion - real performance evaluation - knowledge extraction and memory - state-aware control - result output". It is not only applicable to relatively simplified out-of-order processors, but can also be extended to industrial-grade processor design spaces that include complex branch prediction, cache hierarchy and multiple types of execution resources. Moreover, it does not require complete reliance on training a specific agent model and can be directly interfaced with existing simulation toolchains. At the same time, through mechanisms such as configuration legality verification, result file parsing and benchmark program set aggregation, it is easy to implement in actual EDA processes.

[0066] See Figure 4 , Figure 4 This is a block diagram of a processor microarchitecture design space exploration device provided in an embodiment of this application. The device is a virtual device that can be loaded and executed by a computer device, which may include the aforementioned exploration device. Figure 4 The apparatus may include an initial generation module, an initial evaluation module, and an iteration module, which, when used to execute the above-described exploration method, can: The initial generation module generates multiple initial candidate designs for different target preferences based on the design space and using a large language model. Each initial candidate design is then used as a child node of the virtual root node of the Monte Carlo tree.

[0067] The initial evaluation module calls the real performance evaluation environment to perform real performance evaluation on the child nodes of the virtual root node, and constructs a Pareto profile that uses hypervolume to measure quality based on the real performance evaluation results.

[0068] The iteration module performs iterative searches until the preset iteration termination condition is met, and takes one or more candidate designs from the Pareto profile built in the last iteration as the final design. The process of each search is as follows: The Pareto perceptual tree strategy is used to determine the child nodes to be expanded. A large language model is used to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded, generating child nodes of the child nodes to be expanded. Among them, the child nodes of the child nodes to be expanded are the generated new candidate designs. The Pareto perceptual tree strategy is a child node selection strategy that considers the hypervolume gain of the child node to the Pareto front, the sparsity of the distribution of the actual performance evaluation results of the child node in the target space, the number of visits to the child node and the number of visits to the parent node.

[0069] The system invokes a real performance evaluation environment to perform real performance evaluations on the child nodes of the child nodes to be expanded, and constructs a Pareto profile based on the real performance evaluation results.

[0070] The aforementioned device generates candidate designs with more reasonable structures through a large language model and prioritizes the expansion of more promising byte points through a Pareto perceptual tree strategy, so that the real simulation budget is more focused on high-value candidates, thereby improving the efficiency of search samples under a limited simulation budget.

[0071] This application also relates to a computer-readable storage medium that stores one or more programs, the one or more programs including instructions that, when executed by a computing device, cause the computing device to perform a processor microarchitecture design space exploration method.

[0072] This application also relates to a computer device including one or more processors and one or more memories, wherein one or more programs are stored in the one or more memories and configured to be executed by the one or more processors, and the one or more programs include instructions for performing a processor microarchitecture design space exploration method.

[0073] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0074] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0075] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0076] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0077] The above are merely embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of the claims of the present invention pending approval.

Claims

1. A method for exploring the design space of a processor microarchitecture, characterized in that, include: Based on the design space, a large language model is used to generate multiple initial candidate designs for different target preferences, and each initial candidate design is used as a child node of the virtual root node of the Monte Carlo tree. The real performance evaluation environment is invoked to perform real performance evaluation on the child nodes of the virtual root node, and a Pareto profile using hypervolume to measure quality is constructed based on the real performance evaluation results. Perform iterative search until the preset iteration termination condition is met, and take one or more candidate designs from the Pareto profile built in the last iteration as the final design; The process of each search is as follows: The Pareto perceptual tree strategy is used to determine the child nodes to be expanded. A large language model is used to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded, generating child nodes of the child nodes to be expanded. Among them, the child nodes of the child nodes to be expanded are the generated new candidate designs. The Pareto perceptual tree strategy is a child node selection strategy that considers the hypervolume gain of the child nodes to the Pareto front, the sparsity of the distribution of the true performance evaluation results of the child nodes in the target space, the number of visits to the child nodes and the number of visits to the parent nodes. The system invokes a real performance evaluation environment to perform real performance evaluations on the child nodes of the child nodes to be expanded, and constructs a Pareto profile based on the real performance evaluation results.

2. The method according to claim 1, characterized in that, The Pareto perceptual tree strategy is used to determine the child nodes to be expanded, including: Based on the hypervolume gain of the child node to the Pareto front, the sparsity of the distribution of the child node's true performance evaluation results in the target space, the number of visits to the child node, and the number of visits to the parent node, a selection score is calculated for each child node. The child node with the highest selection score is selected as the child node to be expanded. The selection score is the sum of the Pareto quality term, the diversity term weighted by the first weighting coefficient, and the exploration term weighted by the second weighting coefficient. The Pareto quality term is the hypervolume gain brought by the child node, the diversity term is the sparsity of the distribution of the child node's true performance evaluation results in the target space, and the exploration term is positively correlated with the logarithm of the number of visits to the parent node and negatively correlated with the number of visits to the child node.

3. The method according to claim 1, characterized in that, The method further includes an information feedback step, which includes: After each real performance evaluation, the reward value for this child node expansion is determined based on the evaluation results, and the access count and value of each child node along the path from the child node to the virtual root node are updated.

4. The method according to claim 1, characterized in that, The large language model is used to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded, including: The local optimization expansion takes the historical extended knowledge sampled from the extended knowledge memory, the control instructions corresponding to the state of the large language model, the child nodes to be expanded, and the real performance evaluation results and Pareto front analysis results corresponding to the child nodes to be expanded as inputs, and uses the large language model to perform local optimization expansion on the child nodes to be expanded. The differentiation exploration is extended to take the child node to be expanded and its corresponding real performance evaluation results, as well as the sibling child node and its real performance evaluation results, as inputs. A large language model is used to perform local optimization expansion on the child node to be expanded; where the sibling child node is the child node under the same parent node.

5. The method according to claim 1, characterized in that, The method also includes a step of expanding knowledge accumulation, which includes: After each real performance evaluation, if the real performance evaluation results of the child node determine that the child node causes a positive gain in the supervolume or improves the performance of the child node relative to the parent node in at least one objective, then based on the changes between the parent and child nodes, the changes in the real performance evaluation, and the overall distribution of the Pareto front, the large oracle model is used to extract extended knowledge, and the extended knowledge is added to the extended knowledge memory.

6. The method according to claim 5, characterized in that, Extended knowledge includes Pareto analysis and parent-child difference knowledge; Pareto analysis knowledge is to summarize the recurring or consistent variational patterns of microarchitectural parameter combinations and the target areas that are not yet fully covered from multiple non-dominated candidate designs located at different objectives; among them, non-dominated candidate designs are candidate designs that are not simultaneously dominated by other candidate designs among all candidate designs that have completed real performance evaluation up to the current iteration. Parent-child difference knowledge is a reusable adjustment principle that is effective for improving a certain type of target, extracted from the changes between parent and child nodes and the changes in actual performance evaluation.

7. The method according to claim 1, characterized in that, The method further includes a step of controlling the state switching of a large language model, which includes: The state switching of the large language model is controlled based on the supervolume gain effect of the most recent N consecutive iterations and the supervolume gain effect of the most recent child node expansion; where N is a preset value.

8. A space exploration device for processor microarchitecture design, characterized in that, include: The initial generation module, based on the design space, uses a large language model to generate multiple initial candidate designs oriented towards different target preferences, and treats each initial candidate design as a child node of the virtual root node of the Monte Carlo tree; The initial evaluation module calls the real performance evaluation environment to perform real performance evaluation on the child nodes of the virtual root node, and constructs a Pareto profile that uses hypervolume to measure quality based on the real performance evaluation results. The iteration module performs iterative searches until the preset iteration termination condition is met, and takes one or more candidate designs from the Pareto profile built in the last iteration as the final design. The process of each search is as follows: The Pareto perceptual tree strategy is used to determine the child nodes to be expanded. A large language model is used to perform local optimization expansion and differential exploration expansion on the child nodes to be expanded, generating child nodes of the child nodes to be expanded. Among them, the child nodes of the child nodes to be expanded are the generated new candidate designs. The Pareto perceptual tree strategy is a child node selection strategy that considers the hypervolume gain of the child nodes to the Pareto front, the sparsity of the distribution of the true performance evaluation results of the child nodes in the target space, the number of visits to the child nodes and the number of visits to the parent nodes. The system invokes a real performance evaluation environment to perform real performance evaluations on the child nodes of the child nodes to be expanded, and constructs a Pareto profile based on the real performance evaluation results.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, the one or more programs including instructions that, when executed by a computing device, cause the computing device to perform the method of any one of claims 1 to 7.

10. A computer device, characterized in that, include: One or more processors and one or more memories, one or more programs stored in one or more memories and configured to be executed by one or more processors, the one or more programs including instructions for performing the method of any one of claims 1 to 7.

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