A method for suppressing self-heating effect of MOS transistor for advanced process

Abstract

The application discloses a kind of MOS transistor self-heating effect inhibition methods for advanced process, it is related to MOS transistor technical field, and its technical solution points include the following steps: obtaining the layout and high-power heat main area of target MOS transistor, and marking reference thermal detection point on the active region boundary of target MOS transistor;The reference junction temperature value is obtained by detecting high-power heat main area;The geometric size of active region, reference thermal detection point and temperature difference difference value are processed and analyzed to obtain thermal decay correlation factor;According to junction temperature peak value and heat frequency per unit time, the comprehensive self-heating damage factor is obtained, and the current device loss prediction value is evaluated based on the comprehensive self-heating damage factor and reference device loss database;If current device loss prediction value exceeds preset threshold, the effect is to automatically issue early warning and match corresponding optimized heat dissipation layout scheme.

Description

Technical Field

[0001] This invention relates to the field of MOS transistor technology, and more specifically, to a method for suppressing the self-heating effect of MOS transistors for advanced manufacturing processes. Background Technology

[0002] As the integration density of power integrated circuits continues to increase, the current density of high-power MOS transistors continues to rise. During frequent switching operations, the active region of these devices continuously generates a large amount of Joule heat, causing a sharp increase in the temperature of local hot spots. Current chip thermal detection methods can only acquire temperature data at the surface boundary of the transistor, making it difficult to directly capture the peak junction temperature of the tiny heat-generating core inside the active region. The channel size of the active region has shrunk to the micrometer level, making it difficult for thermal imaging equipment to directly target and measure the internal heat-generating points. It can only acquire temperature data from the edge areas of the device, failing to directly obtain the highest temperature at the channel center, directly limiting the accuracy of thermal damage assessment.

[0003] Current assessment methods rely on single-point temperature values ​​to determine the degree of device aging, ignoring the periodic thermal shocks caused by repeated switching of transistors. In actual operating conditions, MOS devices undergo heating and cooling cycles. Simply relying on instantaneous peak temperatures cannot quantify the aging losses accumulated from multiple thermal cycles. The assessment results deviate significantly from the actual lifespan of the device, making it difficult to predict the risk of self-heating failure under long-term operation. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a method for suppressing the self-heating effect of MOS transistors for advanced manufacturing processes.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A method for suppressing self-heating effects in MOS transistors for advanced manufacturing processes includes the following steps:

[0007] Obtain the layout of the target MOS transistor and the main high-power heat generation region, and mark reference thermal detection points at the active region boundary of the target MOS transistor;

[0008] A reference junction temperature value was obtained by detecting the high-power heat-generating main region.

[0009] The thermal attenuation correlation factor is obtained by processing and analyzing the geometric dimensions of the active region, the reference thermal detection point, and the temperature difference.

[0010] Locate the target heating region within the active region, and obtain the peak junction temperature of the target heating region by combining the reference junction temperature value, thermal attenuation correlation factor and thermal conduction distance.

[0011] A comprehensive self-heating damage factor is obtained based on the junction temperature peak and the heating frequency per unit time. The current device loss prediction value is evaluated based on the comprehensive self-heating damage factor and the reference device loss database.

[0012] If the current device loss prediction value exceeds the preset threshold, an early warning message will be generated and an optimized heat dissipation layout scheme will be matched.

[0013] Preferably, a reference thermal detection point is marked at the boundary of the active region of the target MOS transistor, specifically including the following steps:

[0014] The source and drain boundaries at both ends of the active region of the target MOS transistor are marked as the first thermal detection point and the second thermal detection point, respectively.

[0015] Preferably, the thermal attenuation correlation factor is obtained by processing and analyzing the geometric dimensions of the active region, the reference thermal detection point, and the temperature difference, specifically including the following steps:

[0016] The thermal sensing points are determined based on the geometric dimensions of the active region and the reference thermal detection points.

[0017] Determine the heat conduction distance between the heat sensing points, and obtain the heat attenuation correlation factor based on the temperature difference and the heat conduction distance.

[0018] Preferably, the thermal sensing points are determined based on the geometric dimensions of the active region and the reference thermal detection points, specifically including the following steps:

[0019] The geometric dimensions of the active region include the total width of the active region and the total length of the gate stack;

[0020] Thermal sensing points are divided within the active area based on the first thermal detection point, the second thermal detection point, and the geometric dimensions.

[0021] Preferably, the thermal attenuation correlation factor is obtained based on the temperature difference and the thermal conduction distance, specifically including the following steps:

[0022] Calculate the temperature difference between adjacent thermal sensing points;

[0023] The ratio of the temperature difference to the heat conduction distance is used to obtain the heat attenuation ratio to be measured.

[0024] The thermal decay correlation factor is obtained by averaging all ratios.

[0025] Preferably, the peak junction temperature of the target heating region is obtained by combining the reference junction temperature value, the thermal attenuation correlation factor, and the thermal conduction spacing, specifically including the following steps:

[0026] The target heat-generating area of ​​the active region of the target high-power MOS transistor is taken as the target thermal sensing point;

[0027] Determine the first heat transfer distance between the target thermal sensing point and the first thermal detection point;

[0028] Determine the second heat transfer distance between the target thermal sensing point and the second thermal detection point;

[0029] The predicted peak value of the first junction temperature is obtained based on the first heat transfer distance, the reference junction temperature value, and the pre-treated heat transfer factor.

[0030] The predicted peak value of the second junction temperature is obtained based on the second heat transfer distance, the reference junction temperature value, and the pretreated heat transfer factor.

[0031] Preferably, the comprehensive self-heating damage factor is obtained based on the junction temperature peak and the frequency of heating per unit time, specifically including the following steps:

[0032] The heating frequency per unit time at the first thermal detection point is used as the pre-processing heating frequency.

[0033] The first self-heating damage factor is obtained based on the first predicted junction temperature peak value and the pretreatment heating frequency; the second self-heating damage factor is obtained based on the second predicted junction temperature peak value and the pretreatment heating frequency.

[0034] The comprehensive self-heating damage factor is obtained based on the first self-heating damage factor and the second self-heating damage factor.

[0035] Preferably, the current device loss prediction value is evaluated based on the comprehensive self-heating damage factor and the reference device loss database, specifically including the following steps:

[0036] The comprehensive self-heating damage factor is matched with the reference device loss database to output the corresponding current device loss prediction value.

[0037] Preferably, the optimized heat dissipation layout scheme includes:

[0038] Search for optimized heat dissipation layout schemes corresponding to the target MOS transistor layout and form an optimized heat dissipation layout set.

[0039] The thermal conductivity efficiency and perforation density of the auxiliary heat dissipation channels in the optimized heat dissipation layout set are tested to obtain the optimized heat dissipation layout scheme.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] This invention sets two reference thermal detection points at the boundary of the active region to lock the temperature acquisition boundary, and then performs temperature acquisition on the main heat-generating area to obtain the reference junction temperature value. This avoids data distortion caused by invalid temperature measurement points and significantly improves the acquisition accuracy of the original temperature data. Based on the geometric dimensions of the active region and the temperature difference between the reference measurement points and adjacent points, a thermal attenuation correlation factor is calculated to quantify the temperature drop per unit length inside the semiconductor channel, thus reconstructing the temperature attenuation law of the entire active channel. Relying on this factor and the heat transfer distance, the peak junction temperature of the target heat-generating area is inversely deduced, significantly reducing the accuracy threshold of thermal imaging equipment and improving the accuracy of high-temperature core junction temperature measurement.

[0042] A comprehensive self-heating damage factor is obtained based on the junction temperature peak and the frequency of heating per unit time. A reference device loss database is then used for numerical matching, converting instantaneous high-temperature parameters into predicted device aging losses due to long-term repeated thermal shocks. When the predicted device loss exceeds a preset threshold, an automatic warning is issued, and a corresponding optimized heat dissipation layout is matched. Heat dissipation layout optimization is completed before chip fabrication, reducing the probability of thermal failure during long-term operation and effectively improving the reliability and lifespan of power semiconductor devices. Attached Figure Description

[0043] Figure 1 This is a flowchart illustrating a method for suppressing the self-heating effect of MOS transistors in advanced manufacturing processes, as provided in this embodiment of the invention.

[0044] Figure 2 This invention provides a schematic flowchart of obtaining the thermal decay correlation factor in a method for suppressing the self-heating effect of MOS transistors for advanced processes. Detailed Implementation

[0045] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0046] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0047] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0048] Reference Figures 1-2 As shown.

[0049] The embodiments further illustrate the self-heating effect suppression method for MOS transistors in advanced manufacturing processes proposed in this invention.

[0050] A method for suppressing self-heating effects in MOS transistors for advanced manufacturing processes includes the following steps:

[0051] Obtain the layout of the target MOS transistor and the main high-power heat generation region, and mark reference thermal detection points at the active region boundary of the target MOS transistor;

[0052] A reference junction temperature value was obtained by detecting the high-power heat-generating main region.

[0053] The thermal attenuation correlation factor is obtained by processing and analyzing the geometric dimensions of the active region, the reference thermal detection point, and the temperature difference.

[0054] Locate the target heating region within the active region, and obtain the peak junction temperature of the target heating region by combining the reference junction temperature value, thermal attenuation correlation factor and thermal conduction distance.

[0055] A comprehensive self-heating damage factor is obtained based on the junction temperature peak and the heating frequency per unit time. The current device loss prediction value is evaluated based on the comprehensive self-heating damage factor and the reference device loss database.

[0056] If the current device loss prediction value exceeds the preset threshold, an early warning message will be generated and an optimized heat dissipation layout scheme will be matched.

[0057] Marking reference thermal detection points at the active region boundary of the target MOS transistor involves the following steps:

[0058] The source and drain boundaries at both ends of the active region of the target MOS transistor are marked as the first thermal detection point and the second thermal detection point, respectively.

[0059] For the target MOS transistor, a corresponding temperature acquisition location is defined. The active region is the core area in the MOS transistor where charge carriers complete their conductive movement. Current flows continuously from the source to the drain in this region, generating Joule heating. The active region has two end boundaries along the channel length: one end is the source boundary where the source region connects to the channel, and the other end is the drain boundary where the drain region connects to the channel. The source-drain boundary at one end of the active region is designated as the first thermal detection point, and the corresponding source-drain boundary at the other end of the active region is designated as the second thermal detection point.

[0060] The thermal attenuation correlation factor is obtained by processing and analyzing the geometric dimensions of the active region, the reference thermal detection point, and the temperature difference. The specific steps include:

[0061] The thermal sensing points are determined based on the geometric dimensions of the active region and the reference thermal detection points.

[0062] Determine the heat conduction distance between the heat sensing points, and obtain the heat attenuation correlation factor based on the temperature difference and the heat conduction distance.

[0063] The geometric dimensions of the active region of the target MOS transistor are extracted. These dimensions include the total length of the active region along the channel length direction and the total width of the active region along the channel width direction. Two reference thermal detection points serve as the starting and ending points of the division, and several thermal sensing points are evenly divided along the direction of the active region channel. The entire active region is segmented at intervals, and the active region between the two reference thermal detection points is divided into an equal number of small segments. Each segment's endpoint corresponds to a thermal sensing point. These thermal sensing points are evenly distributed along the channel path of the active region, ensuring that each heat conduction path is within the same semiconductor medium, preventing deviations in heat transfer due to differences in the medium. For example, when the total channel length of the active region is 10 micrometers, and the two reference thermal detection points are located at the two endpoints of the channel, this channel is divided into 5 segments, resulting in 6 thermal sensing points with a uniform distribution.

[0064] The heat conduction spacing between two adjacent heat sensing points is determined. This spacing is the straight-line distance between two adjacent points along the channel's extension direction, and it should be consistent with the interval between the active area segments. For example, if the total channel length is 10 micrometers, divided into 5 equal segments, the heat conduction spacing between adjacent points is 10 ÷ 5 = 2 micrometers. Maintaining the same fixed value for the heat conduction spacing between all adjacent points ensures that the length of each heat conduction path is exactly the same, thus eliminating temperature variation interference caused by inconsistent distances.

[0065] Real-time temperature values ​​are collected for each thermal sensing point. The temperature difference between adjacent points is calculated sequentially. The temperature of the preceding point is denoted as temperature value A, and the temperature of the following point is denoted as temperature value B. The temperature difference between the two points is equal to temperature value A minus temperature value B. During the process of heat conduction from the high-temperature region to the low-temperature region along the channel, the temperature decreases at a fixed ratio after each fixed-length heat conduction path. The heat attenuation correlation factor = temperature difference ÷ heat conduction distance.

[0066] For example, if the temperature value of the first adjacent point A is 85 degrees Celsius and the temperature value of the second adjacent point B is 83 degrees Celsius, the temperature difference between them is 85 - 83 = 2 degrees Celsius. The heat conduction distance between the adjacent points is 2 micrometers. Substituting these values ​​into the formula, we get the thermal decay correlation factor = 2 ÷ 2 = 1 degree Celsius per micrometer. The thermal decay correlation factor represents the temperature drop corresponding to each unit length of heat transfer within the active semiconductor material.

[0067] The thermal sensing points are determined based on the geometric dimensions of the active region and the reference thermal detection points, specifically including the following steps:

[0068] The geometry of the active region includes the total width of the active region and the total length of the gate stack;

[0069] Thermal sensing points are divided within the active area based on the first thermal detection point, the second thermal detection point, and the geometric dimensions.

[0070] The geometric dimensions of the active region are clearly defined. The first geometric dimension is the total width of the active region, which corresponds to the lateral extension width of the MOS transistor channel and determines the coverage area of ​​the lateral conductive region of the active region. The second geometric dimension is the total length of the gate stack, which corresponds to the longitudinal length of the gate polysilicon along the channel current flow direction, that is, the longitudinal straight-line distance between the two reference thermal detection points. These two dimensions together define the length and width boundaries of the rectangular active region, providing precise spatial boundary conditions for point division. For example, setting the total width of the active region to 6 micrometers and the total length of the gate stack to 12 micrometers determines the boundary range of the entire rectangular active region.

[0071] Using the first and second thermal detection points as the two endpoints of the entire segmentation path, each point corresponds to one of the two end boundaries along the length of the gate stack. Continuously distributed thermal sensing points are then defined within the active region along the current conduction path corresponding to the total length of the gate stack. The point segmentation uses the two reference measurement points as the starting and ending boundaries, uniformly dividing the longitudinal segment corresponding to the total length of the gate stack into several equal-length intervals. A thermal sensing point is generated at the division position of each interval. All thermal sensing points are arranged along the center line connecting the two reference measurement points, ensuring that all points fall within the center path of the active channel through which the current flows, preventing point deviation from the conductive area and thus avoiding temperature acquisition failure. For example, if the total length of the gate stack is 12 micrometers, the entire segment is uniformly divided into four equal-length intervals, with each interval length being 12 ÷ 4 = 3 micrometers. After interval segmentation, five thermal sensing points are obtained. The first point corresponds to the first thermal detection point, the last point corresponds to the second thermal detection point, and the remaining three points are evenly distributed between the two reference measurement points, with a longitudinal spacing of 3 micrometers between adjacent points.

[0072] The thermal attenuation correlation factor is obtained based on the temperature difference and the heat conduction distance, specifically including the following steps:

[0073] Calculate the temperature difference between adjacent thermal sensing points;

[0074] The ratio of the temperature difference to the heat conduction distance is used to obtain the heat attenuation ratio to be measured.

[0075] The thermal decay correlation factor is obtained by averaging all ratios.

[0076] Calculate the temperature difference between each pair of adjacent thermal detection points sequentially. Read the temperature values ​​of the preceding and following points along the direction of heat conduction. Subtract the temperature of the following point from the temperature of the preceding point to obtain the temperature difference for this path segment. Each pair of adjacent points generates an independent temperature difference value. When there are 4 pairs of adjacent points arranged in the active area, the temperature of the preceding point in the first pair is 76 degrees Celsius, and the temperature of the following point is 74 degrees Celsius. The temperature difference for this pair is 76 - 74 = 2 degrees Celsius. The temperature difference for the second pair... The temperature difference between the preceding and following points in the first group is 74 degrees Celsius and 72.5 degrees Celsius, respectively. The temperature difference in this group is 74 - 72.5 = 1.5 degrees Celsius. In the third group, the temperature difference between the preceding and following points is 72.5 degrees Celsius and 71 degrees Celsius, respectively. The temperature difference in this group is 72.5 - 71 = 1.5 degrees Celsius. In the fourth group, the temperature difference between the preceding and following points is 71 degrees Celsius and 70 degrees Celsius, respectively. The temperature difference in this group is 71 - 70 = 1 degree Celsius.

[0077] The ratio of each temperature difference to the corresponding heat conduction distance is calculated to obtain the measured heat attenuation ratio for each path segment. Measured heat attenuation ratio = Temperature difference ÷ Heat conduction distance. For example, assuming the heat conduction distance between all adjacent points is 2 micrometers, substituting the values ​​into the formula sequentially, the measured heat attenuation ratio for the first path segment is 2 ÷ 2 = 1 degree Celsius per micrometer; for the second path segment, it is 1.5 ÷ 2 = 0.75 degrees Celsius per micrometer; for the third path segment, it is 1.5 ÷ 2 = 0.75 degrees Celsius per micrometer; and for the fourth path segment, it is 1 ÷ 2 = 0.5 degrees Celsius per micrometer. Each independent conduction path generates a corresponding measured heat attenuation ratio, which reflects the rate of temperature decrease during heat transfer within that small semiconductor path segment.

[0078] The arithmetic mean of all ratios is calculated, and the final result is the thermal attenuation correlation factor corresponding to the entire active channel. Thermal attenuation correlation factor = sum of all measured thermal attenuation ratios ÷ total number of measured thermal attenuation ratios. First, the sum of all ratios is calculated: sum = 1 + 0.75 + 0.75 + 0.5 = 3. The total number of ratios is 4. Substituting these values ​​into the formula, we get the thermal attenuation correlation factor = 3 ÷ 4 = 0.75 degrees Celsius per micrometer. Averaging the ratios across multiple paths eliminates fluctuations caused by local measurement noise and avoids distortion caused by random errors in single paths, ultimately yielding a stable parameter that represents the overall thermal conductivity characteristics of the semiconductor dielectric in the entire active region.

[0079] The peak junction temperature of the target heating region is obtained by combining the reference junction temperature, thermal attenuation correlation factor, and thermal conduction spacing, specifically including the following steps:

[0080] The target heat-generating area of ​​the active region of the target high-power MOS transistor is taken as the target thermal sensing point;

[0081] Determine the first heat transfer distance between the target thermal sensing point and the first thermal detection point;

[0082] Determine the second heat transfer distance between the target thermal sensing point and the second thermal detection point;

[0083] The predicted peak value of the first junction temperature is obtained based on the first heat transfer distance, the reference junction temperature value, and the pre-treated heat transfer factor.

[0084] The predicted peak value of the second junction temperature is obtained based on the second heat transfer distance, the reference junction temperature value, and the pretreated heat transfer factor.

[0085] The target heat-generating area that generates the most Joule heat inside the active region of the target high-power MOS transistor is set as the target heat-sensing point, which corresponds to the location where power consumption is concentrated inside the transistor channel.

[0086] The straight-line lengths from the target thermal sensing point to two reference measuring points are measured separately. First, the spatial length between the target thermal sensing point and the first thermal detection point is calculated. This path represents the physical path of heat transfer from the core heating point to the first thermal detection point, and this length is the first heat transfer distance. Then, the spatial length between the target thermal sensing point and the second thermal detection point is calculated. This path represents the physical path of heat transfer from the core heating point to the second thermal detection point, and this length is the second heat transfer distance. For example, if the straight-line length from the first thermal detection point to the target thermal sensing point is set to 4 micrometers (meaning the first heat transfer distance is 4 micrometers), and the straight-line length from the second thermal detection point to the target thermal sensing point is set to 6 micrometers (meaning the second heat transfer distance is 6 micrometers), both heat transfer paths are located within the same semiconductor silicon dielectric, ensuring consistent thermal conductivity of the material.

[0087] As heat is transferred from the high-temperature target thermal sensing point to the reference measuring point, it gradually cools down along the path. The temperature decay rate = first heat transfer distance × pre-processed thermal conductivity factor. The predicted peak value of the first junction temperature = reference junction temperature + first heat transfer distance × pre-processed thermal conductivity factor. For example, if the reference junction temperature is set to 70 degrees Celsius and the pre-processed thermal conductivity factor is set to 2 degrees Celsius per micrometer, the predicted peak value of the first junction temperature = 70 + 4 × 2 = 78 degrees Celsius.

[0088] The second predicted peak junction temperature = reference junction temperature + second heat transfer distance × pre-processed thermal conductivity factor, so the second predicted peak junction temperature = 70 + 6 × 2 = 82 degrees Celsius. By reverse-engineering the temperature of the heat source through two different heat transfer paths, two sets of junction temperature prediction results are obtained. Subsequently, the two sets of prediction values ​​can be compared and verified, effectively reducing the error caused by a single temperature measurement and restoring the true level of the highest junction temperature inside the active region of the high-power MOS transistor.

[0089] The comprehensive self-heating damage factor is obtained based on the peak junction temperature and the frequency of heating per unit time, specifically including the following steps:

[0090] The heating frequency per unit time at the first thermal detection point is used as the pre-processing heating frequency.

[0091] The first self-heating damage factor is obtained based on the first predicted junction temperature peak value and the pretreatment heating frequency; the second self-heating damage factor is obtained based on the second predicted junction temperature peak value and the pretreatment heating frequency.

[0092] The comprehensive self-heating damage factor is obtained based on the first self-heating damage factor and the second self-heating damage factor.

[0093] The temperature fluctuation data of the first thermal detection point is collected during the continuous working period. The number of times the heating peak occurs at this point per unit time is counted. The statistical value is set as the pre-processing heating frequency, which reflects the number of times the target MOS transistor repeatedly experiences high temperature shocks within a unit time. For example, if the statistical time is set to 60 seconds and 12 heating peaks are captured within this time, then the pre-processing heating frequency is equal to 12 times every 60 seconds, that is, the pre-processing heating frequency is equal to 0.2 times per second.

[0094] Thermal damage to transistor semiconductor structures is determined by both peak temperature and the number of repeated heating cycles. Higher temperatures and more heating cycles result in more severe device aging damage. Using the predicted peak junction temperature as the base temperature parameter, and substituting the obtained pre-processing heating frequency, the first self-heating damage factor is calculated as: First Predicted Peak Junction Temperature × Pre-processing Heating Frequency. For example, if the predicted peak junction temperature is 78 degrees Celsius and the pre-processing heating frequency is 0.2 cycles per second, substituting these values ​​into the formula yields: First Self-Heating Damage Factor = 78 × 0.2 = 15.6. The second self-heating damage factor is calculated as: Second Predicted Peak Junction Temperature × Pre-processing Heating Frequency. If the predicted peak junction temperature is 82 degrees Celsius, substituting these values ​​yields: Second Self-Heating Damage Factor = 82 × 0.2 = 16.4. These two damage factors correspond to the thermal damage levels obtained from the two heat transfer paths, allowing for the verification of the high-temperature damage degree at the heat source.

[0095] The first and second self-heating damage factors are integrated to obtain a comprehensive self-heating damage factor, which is calculated as (first self-heating damage factor + second self-heating damage factor) ÷ 2, resulting in a comprehensive self-heating damage factor of 32 ÷ 2 = 16. By averaging the two sets of damage results corresponding to the two measurement points, the random errors caused by temperature measurement and distance calculation can be further reduced, resulting in a comprehensive evaluation parameter that more closely reflects the actual aging level of the device. This allows for a quantitative assessment of the degree of self-heating damage in the active region of high-power MOS transistors.

[0096] The current device loss prediction value is evaluated based on the comprehensive self-heating damage factor and the reference device loss database, specifically including the following steps:

[0097] The comprehensive self-heating damage factor is matched with the reference device loss database to output the corresponding current device loss prediction value.

[0098] The reference device loss database pre-stores a large amount of data corresponding to MOS devices of the same model calibrated through accelerated aging tests under different self-heating damage conditions. The database stores each set of self-heating damage factors and their corresponding device loss values, forming a continuous numerical mapping relationship to establish a correlation between damage level and device aging loss. Using the currently calculated comprehensive self-heating damage factor as a search keyword, the database is compared against existing damage factor entries to find the reference entry closest to the current value. If the current comprehensive self-heating damage factor falls between two reference data entries, linear interpolation is used to calculate the corresponding loss value. The corresponding interpolation formula is: Current device loss prediction = Loss value of the first entry + (Current comprehensive self-heating damage factor - Damage factor of the first entry) × (Loss value of the second entry - Loss value of the first entry) ÷ (Damage factor of the second entry - Damage factor of the first entry). Assuming the current comprehensive self-heating damage factor is 16, the damage factor of the first entry in the database is 15, corresponding to a loss value of 6%, and the damage factor of the last entry is 17, corresponding to a loss value of 8%, the current device loss prediction value = 6 + (16-15) × (8-6) ÷ (17-15) = 7, ultimately yielding a current device loss prediction value of 7%. After completing the data retrieval and interpolation calculations, this matching result is output, which is the current device loss prediction value corresponding to the target high-power MOS transistor.

[0099] Matching and optimizing the heat dissipation layout solution, specifically including:

[0100] Search for optimized heat dissipation layout schemes corresponding to the target MOS transistor layout and form an optimized heat dissipation layout set.

[0101] The thermal conductivity efficiency and perforation density of the auxiliary heat dissipation channels in the optimized heat dissipation layout set are tested to obtain the optimized heat dissipation layout scheme.

[0102] All optimized heat dissipation layout schemes that meet the layout size constraints are retrieved, and the complete wiring and via arrangements are compiled into a complete optimized heat dissipation layout set. This set includes multiple heat dissipation channel designs with different structures. Each scheme differs in metal trace routing, heat dissipation metal area, and via arrangement. All schemes match the layout boundaries of the target transistor's active area, preventing layout size issues that exceed process allowances.

[0103] For each scheme within the optimized heat dissipation layout set, two key parameters were tested: the thermal conductivity of the auxiliary heat dissipation channels and the via density. Thermal conductivity measures the ability of the metal heat dissipation channels to conduct heat from the active area; thermal conductivity = heat transferred ÷ temperature difference ÷ conduction time. Via density represents the number of vertically arranged heat-conducting vias per unit area; via density = total number of vias ÷ total heat dissipation area. For example, selecting one scheme from the set for testing, with a total heat dissipation area of ​​200 square micrometers and 40 heat-conducting vias, the via density is calculated as 40 ÷ 200 = 0.2 vias per square micrometer. Simultaneously, under a 10-degree Celsius temperature difference and a duration of 10 seconds, the total heat transferred is 200 joules; the thermal conductivity is calculated as 200 ÷ 10 ÷ 10 = 2 joules per degree Celsius per second.

[0104] A comprehensive evaluation and selection process was conducted for various parameters to identify the design with the highest thermal conductivity and via density that met process cost constraints. This optimal design was then chosen as the final optimized heat dissipation layout. High thermal conductivity ensures rapid heat dissipation from the active region, reducing the peak junction temperature of the channel. A reasonable via density balances heat dissipation performance with chip manufacturing costs, avoiding the waste of lithography resources caused by excessive via density. From multiple alternative designs, a layout that balances heat dissipation capacity and production cost was selected to optimize the heat dissipation structure of the target MOS transistor.

[0105] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0106] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0107] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for suppressing self-heating effects in MOS transistors for advanced manufacturing processes, characterized in that, Includes the following steps: Obtain the layout of the target MOS transistor and the main high-power heat generation region, and mark reference thermal detection points at the active region boundary of the target MOS transistor; A reference junction temperature value was obtained by detecting the high-power heat-generating main region. The thermal attenuation correlation factor is obtained by processing and analyzing the geometric dimensions of the active region, the reference thermal detection point, and the temperature difference. Locate the target heating region within the active region, and obtain the peak junction temperature of the target heating region by combining the reference junction temperature value, thermal attenuation correlation factor and thermal conduction distance. A comprehensive self-heating damage factor is obtained based on the junction temperature peak and the heating frequency per unit time. The current device loss prediction value is evaluated based on the comprehensive self-heating damage factor and the reference device loss database. If the current device loss prediction value exceeds the preset threshold, an early warning message will be generated and an optimized heat dissipation layout scheme will be matched.

2. The method for suppressing self-heating effects of MOS transistors for advanced manufacturing processes according to claim 1, characterized in that, Marking reference thermal detection points at the active region boundary of the target MOS transistor involves the following steps: The source and drain boundaries at both ends of the active region of the target MOS transistor are marked as the first thermal detection point and the second thermal detection point, respectively.

3. The method for suppressing self-heating effects of MOS transistors for advanced manufacturing processes according to claim 2, characterized in that, The thermal attenuation correlation factor is obtained by processing and analyzing the geometric dimensions of the active region, the reference thermal detection point, and the temperature difference. The specific steps include: The thermal sensing points are determined based on the geometric dimensions of the active region and the reference thermal detection points. Determine the heat conduction distance between the heat sensing points, and obtain the heat attenuation correlation factor based on the temperature difference and the heat conduction distance.

4. The method for suppressing self-heating effects of MOS transistors for advanced manufacturing processes according to claim 3, characterized in that, The thermal sensing points are determined based on the geometric dimensions of the active region and the reference thermal detection points, specifically including the following steps: The geometric dimensions of the active region include the total width of the active region and the total length of the gate stack; Thermal sensing points are divided within the active area based on the first thermal detection point, the second thermal detection point, and the geometric dimensions.

5. A method for suppressing self-heating effects in MOS transistors for advanced manufacturing processes according to claim 4, characterized in that, The thermal attenuation correlation factor is obtained based on the temperature difference and the heat conduction distance, specifically including the following steps: Calculate the temperature difference between adjacent thermal sensing points; The ratio of the temperature difference to the heat conduction distance is used to obtain the heat attenuation ratio to be measured. The thermal decay correlation factor is obtained by averaging all ratios.

6. The method for suppressing self-heating effects of MOS transistors for advanced manufacturing processes according to claim 5, characterized in that, The peak junction temperature of the target heating region is obtained by combining the reference junction temperature, thermal attenuation correlation factor, and thermal conduction spacing, specifically including the following steps: The target heat-generating area of ​​the active region of the target high-power MOS transistor is taken as the target thermal sensing point; Determine the first heat transfer distance between the target thermal sensing point and the first thermal detection point; Determine the second heat transfer distance between the target thermal sensing point and the second thermal detection point; The predicted peak value of the first junction temperature is obtained based on the first heat transfer distance, the reference junction temperature value, and the pre-treated heat transfer factor. The predicted peak value of the second junction temperature is obtained based on the second heat transfer distance, the reference junction temperature value, and the pretreated heat transfer factor.

7. A method for suppressing self-heating effects in MOS transistors for advanced manufacturing processes according to claim 6, characterized in that, The comprehensive self-heating damage factor is obtained based on the peak junction temperature and the frequency of heating per unit time, specifically including the following steps: The heating frequency per unit time at the first thermal detection point is used as the pre-processing heating frequency. The first self-heating damage factor is obtained based on the first predicted junction temperature peak value and the pretreatment heating frequency; the second self-heating damage factor is obtained based on the second predicted junction temperature peak value and the pretreatment heating frequency. The comprehensive self-heating damage factor is obtained based on the first self-heating damage factor and the second self-heating damage factor.

8. A method for suppressing self-heating effects in MOS transistors for advanced manufacturing processes according to claim 7, characterized in that, The current device loss prediction value is evaluated based on the comprehensive self-heating damage factor and the reference device loss database, specifically including the following steps: The comprehensive self-heating damage factor is matched with the reference device loss database to output the corresponding current device loss prediction value.

9. A method for suppressing self-heating effects in MOS transistors for advanced manufacturing processes according to claim 8, characterized in that, Matching and optimizing the heat dissipation layout solution, specifically including: Search for optimized heat dissipation layout schemes corresponding to the target MOS transistor layout and form an optimized heat dissipation layout set. The thermal conductivity efficiency and perforation density of the auxiliary heat dissipation channels in the optimized heat dissipation layout set are tested to obtain the optimized heat dissipation layout scheme.

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