Inference acceleration and weight storage based on solid state and acoustic physical media

Abstract

The present application relates to reasoning acceleration and weight storage device and method based on solid state and acoustic physical medium, belong to the field of heterogeneous physical effect hardware. In view of the problem that the coupling fails due to the homogeneity of the principles of two kinds of physical effects, signal processing and data storage devices based on the cooperation of various physical effects such as surface acoustic wave, memristor and phase change storage are provided. Through the cooperation of multiple physical media such as surface acoustic wave, memristor and phase change, direct cooperation between heterogeneous physical effect hardware is realized, which is suitable for high-speed signal preprocessing and parameter storage scene of artificial intelligence reasoning task.

Description

Technical Field

[0001] This invention relates to the field of hardware technology for physical computing and signal processing, specifically to a device and method that utilizes multiple physical effects (including acoustic propagation effect or electronic transport effect as the first physical effect, and phase transition effect as the second physical effect) to synergistically achieve signal processing acceleration and physical data storage. Its international patent classification numbers are G06N5 / 04 (inference system), G06N3 / 04 (neural network architecture), G11C13 / 00 (non-volatile memory, covering phase-change memory), H01L45 / 00 (solid-state storage device, covering memristor resistive switching memory), and H03H9.

[0002] / 00 (Surface Acoustic Wave Device), G06F13 / 00 (Multi-Physical Domain Data Interaction Bus, covering the physical bus).

[0003] This device is particularly suitable for high-speed signal preprocessing and parameter storage scenarios in artificial intelligence inference tasks.

[0004] Explanation of higher-level concepts: In this invention, "first physical effect" and "second physical effect" are higher-level concepts. The first physical effect encompasses any physical mechanism that passively modulates the input signal, including but not limited to acoustic propagation effects (surface acoustic waves, bulk acoustic waves), electronic transport effects (memristor resistance switching, transistor channel modulation), magnon propagation effects (spin wave propagation), and thermal conduction effects (heat flow modulation).

[0005] The second physical effect encompasses any physical mechanism used for storing non-volatile information, including but not limited to phase transition effect, resistive change effect, magnetic change effect, and ferroelectric effect. Background Technology

[0006] Can Li et al. (2019) reported on the implementation of a long short-term memory (LSTM) network based on a memristor cross array in Nature Machine Intelligence [1], demonstrating the feasibility of performing deep learning computations using a memristor cross array in the analog domain. The solid-state physical mapping structure of this invention adopts a similar architecture to the memristor cross array to realize parallel computation of constraint checking in the analog domain.

[0007] Can Li et al. (2018) proposed a large-scale memristor cross array for analog domain computation at the IEEE International Symposium on Circuits and Systems [2], demonstrating the scalability of memristors as analog computing units. The memristor embodiment of the solid-state physical mapping structure of this invention adopts a similar large-scale cross array architecture to achieve parallel hardware-level checking of constraints.

[0008] Lingyun Shi et al. (2020) reviewed the creeping path problem and its solution in memristor cross arrays in Nanoscale Advances (doi:10.1039 / d0na00100g). The memristor embodiment of the solid-state physical mapping structure of this invention considers the creeping path problem in its design by selecting a suitable memristor material (such as Pt / TaO). x / Ta) works in conjunction with the readout circuit to reduce the impact of creeping current on calculation accuracy.

[0009] Existing signal processing and inference acceleration hardware mainly relies on a single physical medium or a first physical effect:

[0010] (1) Content addressable memory (TCAM) is used for rule matching (such as the content addressable memory-based rule matching engine disclosed in US 10,824,938 B2). The matching speed is limited by the search clock cycle, and the power consumption increases linearly with the array size.

[0011] (2) Field Programmable Gate Arrays (FPGAs) are used for reconfigurable logic, but are limited by the clock frequency and power consumption of serial processing in the digital domain.

[0012] (3) Memristor cross arrays have been used for in-memory computation in neural networks (such as the memristor in-memory computation scheme disclosed in CN 112668702 A), but in the prior art, the resistance value of the memristor stores the synaptic weights of the neural network, and its function is concentrated on matrix multiplication. In recent years, Academician Liu Ming's team at the Institute of Microelectronics, Chinese Academy of Sciences, proposed a neuro-fuzzy hardware system based on memristor cross arrays, which directly represents fuzzy logic and symbolic knowledge in the form of rules using the topological structure of the memristor cross array.

[0013] However, this type of scheme is still limited to using a single first physical effect (electron transport effect) to complete all computation and storage functions.

[0014] (4) Surface acoustic wave (SAW) devices (such as surface acoustic wave delay lines under the H03H9 / 00 category) have been used for radio frequency signal processing and convolution operations. However, in existing schemes, SAW is only used as an independent time-domain signal processing medium and has not been heterogeneously integrated with other physical effect media such as memristors or phase-change memories.

[0015] (5) Phase change memory (PCM) has been used for non-volatile storage and in-memory computing, but in existing schemes, PCM is usually used only as a single weight storage medium and is not heterogeneously integrated with other physical effect media such as acoustic or electronic transport.

[0016] (6) Existing solutions all use a single first physical medium or a single first physical effect, which cannot select the optimal physical implementation method for different operation types (time domain matching, analog domain constraint checking, and non-volatile data storage) in the signal processing process. The heterogeneous collaborative integration of multiple physical effects (acoustic propagation effect or electronic transport effect as the first physical effect for ultrafast time domain matching or low-power analog domain constraint checking, and phase transition effect as the second physical effect for non-volatile multi-value storage) - this technical path has not yet seen a public implementation of the complete collaboration of the three physical effects in the existing technology.

[0017] It is worth noting that in recent years, there have been explorations of integrating surface acoustic waves (SAWs) with memristors: Zhang Y. (University of Hong Kong, 2025 PhD dissertation "Programmable piezoelectric surface acoustic wave deep neural network with integrated memory function") proposed a programmable piezoelectric SAW deep neural network, which realizes reconfigurable neurons through the acousto-electric effect, and integrates Ag⁺-based memristors with SAW phase shifters to achieve binary phase tuning with non-volatile bias maintenance, which is used for vector classification of binary SAW neural networks (experimental classification accuracy reached 91.7%).

[0018] Compared with the above work, the differences of the present invention are: (1) The present invention uses three physical media with different physical principles, namely surface acoustic wave (acoustic propagation effect), memristor (electronic transport effect) and phase change memory (phase change effect), instead of binary phase tuning of two media; (2) The claims of the present invention clearly define that the first physical effect and the second physical effect are different in physical principle, and coordinate the data transfer between inference steps through the field programmable gate array interconnection control module; (3) In the present invention, the first physical medium is in a passive state during the inference calculation process, the parameter space distribution is fixed and it is not rewritten by the electrical signal, which is not disclosed in the above existing surface acoustic wave calculation schemes. Summary of the Invention

[0019] Purpose of the invention

[0020] The technical problem this invention aims to solve is that existing signal processing and inference acceleration hardware relies on a single physical medium or a first physical effect, failing to utilize the inherent characteristics of different physical effects to optimize different operation types in the signal processing process, and lacking low-power, non-volatile persistent data storage solutions. Specifically, acoustic propagation effects have the inherent advantage of short propagation delay times (nanosecond level), but are difficult to implement multi-valued non-volatile storage; electronic transport effects (memristors) can achieve low-power analog domain computation, but also lack non-volatile multi-valued storage capabilities.

[0021] Phase transition effects enable multi-valued non-volatile storage, but signal propagation speed is limited by the electrical read / write path. Currently, there is no solution in the technology that heterogeneously integrates the advantages of the three physical effects mentioned above.

[0022] Technical solution

[0023] This invention provides a signal processing and data storage device and method based on the synergy of multiple physical effects.

[0024] Its core inventive concept is to use multiple physical effects that are completely independent in microscopic mechanism in a coordinated manner—the first physical effect (acoustic propagation effect or electronic transport effect) performs signal transformation or constraint checking, and the second physical effect (phase transition effect) realizes non-volatile multi-value storage of data—so that different physical effects each undertake the operation type most suitable for their physical characteristics in the signal processing process, forming a heterogeneous physical effect coordinated architecture.

[0025] The first physical effect mainly addresses "signal propagation and analog domain computation", while the second physical effect mainly addresses "multi-valued material state solidification". Both have independent physical implementation paths in terms of device micro / nano structure, material properties, signal excitation methods, and signal reading mechanisms, and achieve cross-physical domain data interaction through a physical bus.

[0026] Furthermore, the distinguishing technical feature of this invention from the prior art lies in the integration of a first physical effect and a second physical effect, which are completely independent in their microscopic mechanisms, into the same device via a physical bus. This allows the first physical effect to perform signal propagation and analog domain operations, while the second physical effect performs multi-valued non-volatile storage. Both have independent physical implementation paths in terms of device micro / nano structure, material properties, signal excitation methods, and signal readout mechanisms. This distinguishing feature is not a combination of conventional techniques in the art: in the prior art, surface acoustic wave delay lines, memristor arrays, and phase-change memory are used for radio frequency signal processing, resistive storage, and solid-state storage, respectively. Those skilled in the art have no motivation to heterogeneously integrate these three through a physical bus to optimize different operation types—the prior art does not provide technical guidance on dividing and integrating completely independent microscopic physical effects according to operation type, nor does it disclose a scheme for cross-physical domain data interaction using a physical bus. The heterogeneous collaborative integration of this invention achieves simultaneous optimization of signal processing delay and storage non-volatility, achieving technical effects that cannot be achieved by existing single-physical-medium solutions. Therefore, the technical solution of this invention is not obvious.

[0027] Furthermore, this invention differs from surface acoustic wave (SAW) convolutional devices and heterogeneous integration schemes: While SAW convolutional devices have been used for convolution operations in radio frequency signal processing, they are independent time-domain signal processing devices, performing only a single convolution operation without coordination with memristor constraint checking or phase-change memory; the memristor LSTM network of Can Li et al. (2019) and the memristor / RRAM three-dimensional cross array in the heterogeneous integration review are both integrations within a single physical effect (electronic transport) system, without dividing and coordinating acoustic propagation effects, electronic transport effects, and phase-change effects according to different operation types in signal processing (time-domain matching, analog-domain constraint checking, non-volatile multi-valued storage). This invention integrates the first and second physical effects, which are completely independent in microscopic mechanism, into the same device through a physical bus, allowing each physical effect to undertake the operation type most suitable for its physical characteristics. This belongs to a heterogeneous multi-physical effect collaborative architecture, which is not disclosed in the prior art and has no combination inspiration.

[0028] Based on the aforementioned distinguishing technical features, the technical problem actually solved by this invention is: how to enable different physical effects to each undertake the operation type most suitable for their physical characteristics in signal processing and work together, avoiding the defect that a single physical medium cannot simultaneously meet the requirements of real-time signal processing and data persistence. By heterogeneously integrating the first physical effect (acoustic propagation or electronic transport) and the second physical effect (phase transition) with a physical bus and dividing them according to operation type, this invention achieves an optimal balance between real-time performance, power consumption, and reliability.

[0029] The device includes:

[0030] Input encoding module: converts the input data to be processed into electrical or acoustic signals, wherein at least one physical property (such as frequency, phase, amplitude, or timing) of the electrical or acoustic signal encodes the value information of the input data.

[0031] Physical mapping structure: The input signal is directly modulated using a first physical effect, which is achieved by selecting either acoustic propagation effect (surface acoustic wave delay line array) or electronic transport effect (memristor cross array) depending on the signal processing task type. This physical mapping structure has a non-uniform parameter spatial distribution solidified according to predetermined signal transformation rules—in the acoustic scheme, this is the distribution of the position, width, and spacing of the reflector grating; in the electronic transport scheme, it is the resistance distribution of the memristor cells.

[0032] Output decoding module: senses the measurable physical characteristics of the output signal (such as pulse arrival time and current amplitude) and maps them to the output result.

[0033] Non-volatile data storage unit: It utilizes the second physical effect (phase change effect) to achieve non-volatile multi-value persistent storage of data, and is connected to the physical mapping structure through a physical bus (analog signal bus).

[0034] Beneficial effects

[0035] (1) Extremely low signal processing delay: When utilizing the acoustic propagation effect, the propagation speed of surface acoustic waves (SAW) on the piezoelectric substrate is approximately 3960 m / s (128° YX cut LiNbO3 standard value; see DPMorgan "Surface Acoustic Waves and Signal Processing" Elsevier 2007 Table 3.4;

[0036] CCW Ruppel & T. Fjeldy Eds. "Advances in SAW Technology, Systems and Applications" World Scientific 2000, the propagation delay between reflective gratings is on the order of nanoseconds (v=3960m / s → 100μm distance requires 25.2ns round trip);

[0037] Verification Example 1 shows that the total SAW propagation time of 80ns corresponds to a substrate propagation distance of approximately 0.32mm, which is physically achievable. The signal processing speed is independent of the number of rules (it is necessary to meet the condition that the reflective grating density is lower than the time resolution of the surface acoustic wave pulse; when f=200MHz, τ=1 / f=5ns, corresponding to the spatial limit v·τ / 2 = 9.9μm).

[0038] (2) Extremely low power consumption of constraint check: When using electronic transport effect (memristor cross array), constraint check is completed by Ohm's law (I = V / R) of passive device, without the need for active amplifier circuit, and the power consumption of a single constraint check can be as low as microwatt.

[0039] (3) Data storage is non-volatile and supports multiple values: When utilizing the phase transition effect, the crystalline / amorphous resistivity state of GST material is maintained after power failure, with a storage retention time of more than 10 years (@85°C; typical retention time of commercial PCM is 10 years @85°C, see Micron 3D XPoint datasheet 2017; IBM commercial PCM paper Mantey 2015 confirms 10-year retention;

[0040] H.-SP Wong 2010 Proc. IEEE (verified), no refresh power consumption required—compared to DRAM (which requires periodic refresh to maintain data, with typical refresh power consumption of approximately 10mW / GB; verified by JEDEC DDR4 standard JESD79-4; verified by Hennessy & Patterson "Computer Architecture" 6th ed. 2017 Ch.2), PCM's non-volatile nature allows data retention power consumption to be zero, eliminating the need for refresh operations.

[0041] Meanwhile, by controlling the SET pulse width, at least eight distinguishable resistance states can be achieved, supporting multi-value data storage.

[0042] (4) Heterogeneous synergistic optimization: By applying different physical effects to the most suitable operation type (acoustics for ultrafast time-domain matching, electronics for low-power analog domain constraint checking, and phase transition for non-volatile multi-value storage), the optimal balance of overall performance, power consumption and reliability is achieved, filling the gap in the heterogeneous synergistic integration of multiple physical effects in the existing technology. Attached Figure Description

[0043] Figure 1 This is a block diagram illustrating the overall principle of a signal processing and data storage device based on the synergy of multiple physical effects.

[0044] Figure 2 This is a top view of the surface acoustic wave delay line array.

[0045] Figure 3 This is a schematic diagram showing the mapping relationship between the position of the reflector grating and the signal transformation rules.

[0046] Figure 4 This is a graph showing the correspondence between the surface acoustic wave echo train and the output result.

[0047] Figure 5 This is a structural diagram of a memristor cross array.

[0048] Figure 6 This is a diagram showing the relationship between memristor resistance and constraint strength.

[0049] Figure 7 This is a structural diagram of a phase change material storage unit.

[0050] Figure 8 This is a diagram illustrating the collaborative working architecture of heterogeneous physical effects.

[0051] Figure 9 This is an overall flowchart of the method of the present invention, showing four steps: input encoding, physical mapping, output decoding, and data persistence.

[0052] Figure 1 This is a block diagram illustrating the overall principle of the signal processing and data storage device based on the synergy of multiple physical effects of the present invention. It shows the layout of the input encoding module 1, the physical mapping structure 2 (first physical effect medium), the output decoding module 3, and the non-volatile data storage unit 4 (second physical effect medium), as well as the physical bus connections 40, 41, and 42 between them.

[0053] Figure 2 This is a top view of the surface acoustic wave delay line array in Embodiment 1. It shows the input interdigital transducer 11 (comb electrode), the reflective grating array 12 (multiple parallel strip reflective gratings), the output interdigital transducer 13 (comb electrode), and the arrow indicating the surface acoustic wave propagation direction 14 on the surface of the piezoelectric substrate 10.

[0054] Figure 3 This diagram illustrates the mapping relationship between the position of the reflector grating and the signal transformation rules. It shows the correspondence between the signal transformation diagram on the left (nodes and arrows) and the reflector grating layout on the right (reflector grating strips at different positions), with dashed arrows indicating the mapping.

[0055] Figure 4 This is a graph showing the correspondence between surface acoustic wave echo trains and output results. With time as the horizontal axis and amplitude as the vertical axis, it shows the arrival times t1, t2, and t3 of each echo pulse and their corresponding output results C1, C2, and C3.

[0056] Figure 5 This is a structural diagram of the memristor cross array in Embodiment 2. It shows the grid formed by the intersection of row lines 20 and column lines 21, with a memristor cell 22 (represented by a resistor symbol) at each intersection point. The row lines are connected to the row drive circuit 23, and the column lines are connected to the column readout circuit 24.

[0057] Figure 6 This is a graph showing the relationship between memristor resistance and constraint strength encoding. With constraint strength encoding as the horizontal axis and resistance value (logarithmic scale) as the vertical axis, it shows that the low resistance range of 10kΩ-100kΩ corresponds to "strong activation", 100kΩ-500kΩ corresponds to "neutral", and 500kΩ-1MΩ corresponds to "strong suppression".

[0058] Figure 7 This is a structural diagram of the phase change material storage unit in Embodiment 3. It shows that the GST material layer 30 is sandwiched between the upper electrode 32 and the lower electrode 33, the bottom is the heating electrode 31, and the side shows the programming pulse generator 34 and its output SET / RESET pulse waveform.

[0059] Figure 8This is a diagram of a heterogeneous physical effect collaborative architecture. It shows two main modules (first physical effect medium 2 and second physical effect medium 4) arranged horizontally, connected by three physical buses 40, 41, and 42, and shows the data types of each link.

[0060] Figure 9 This is an overall flowchart of the method of the present invention. The flowchart shows four steps: input encoding step → physical mapping step → output decoding step → data persistence step. The steps are connected by arrows, with a bidirectional dashed arrow between the data persistence step and the physical mapping step indicating data reading interaction. Detailed Implementation

[0061] This embodiment further combines Figure 4 The solid-state-acoustic heterogeneous collaborative execution shown is achieved through... Figure 5 The inference acceleration pipeline shown works in conjunction with the device described in claim 1.

[0062] This implementation example Figure 1 As shown, by Figure 2 The solid-state acceleration shown is... Figure 3 The acoustic storage implementation is shown.

[0063] (This embodiment corresponds to the device described in claim 1. As shown in the overall architecture in Figure 1, the solid-state acceleration shown in Figure 2 is achieved by the acoustic storage shown in Figure 3.)

[0064] (This embodiment corresponds to the device described in claim 1 and the method described in claim 2).

[0065] Preferably, the position encoding of each reflective grating in the reflective grating array represents the start and end states of the transfer edge. Preferably, the memristor unit is Pt / TaO. x The memristor has a / Ta structure with a continuously adjustable resistance from 10kΩ to 1MΩ. Preferably, the area of ​​the memristor unit is less than 0.05μm².

[0066] Preferably, the propagation delay of the surface acoustic wave delay line is 1-5 μs / cm (based on the SAW propagation speed of 2000-10000 m / s), the memristor resistance switching time is less than 10 ns, and the accuracy of the multi-value resistor state is ±1%.

[0067] Figure 8 further illustrates the hardware mapping relationship from the d{i} index to the T_i time slice. During the SAW surface wave signal transformation process, the d{i} index is mapped to the T_i time slice through the analog signal bus. The reflection grating signal is mapped to the TCAM rule correspondence after being transmitted through the SAW surface wave. The entire signal transformation link remains in the analog domain and does not require ADC conversion, demonstrating the transmission of four physical quantities through the analog signal bus.

[0068] Figure 8 further illustrates the physical parameter performance indicators of the synergy of multiple physical effects: SAW phonon delay of 100ns, memristor TiO2 resistive switching window on the order of 1-3, PCM / GST crystalline ratio switching time of 10ns, FeFET polarization reversal time of 1ns, and analog signal bus transmission bandwidth of 1GHz for 4 physical quantities (voltage / current / frequency / pulse width), with a coordinated scheduling delay of <100ns, reflecting the physical parameter performance indicators of the synergy of 4 completely independent microscopic mechanisms.

[0069] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0070] Terminology Definition

[0071] In this invention:

[0072] "Signal transformation rule" refers to the predetermined mapping relationship between input and output signals, which is fixed in the non-uniform parameter space distribution of the physical mapping structure;

[0073] "Logical reasoning" refers to the physical computation process that utilizes first and second physical effects to perform reasoning steps such as signal transformation, constraint checking, or state transition in the analog domain, without relying on the execution of instructions from a digital processor. The first physical medium is in a passive state during the reasoning process, maintaining its manufactured and solidified state, and does not receive control signals for computation. Its parameter space distribution is not rewritten by electrical signals during the reasoning process. Data transfer between reasoning steps is coordinated by an interconnection control module, which is implemented using a field-programmable gate array (FPGA). Through sample-and-hold and format conversion, the deterministic transfer between the analog domain solution results and the memory addressing timing is completed.

[0074] "Associated data" refers to parameter values ​​used to assist in signal transformation during signal processing, including but not limited to weight values, confidence values, and constraint strength values.

[0075] "Output result" refers to the information extracted by the output decoding module from the measurable physical characteristics of the output signal, and its form depends on the specific signal processing task.

[0076] Example 1: Surface Acoustic Wave Signal Conversion Acceleration Device (First Physical Effect = Acoustic Propagation Effect)

[0077] The physical mapping structure in this embodiment uses a surface acoustic wave delay line array.

[0078] (a) Piezoelectric substrates and interdigital transducers

[0079] The piezoelectric substrate material is 128°YX-cut lithium niobate (LiNbO3; a mainstream commercial SAW substrate; see DPMorgan "Surface Acoustic Waves and Signal Processing" Elsevier 2007 Ch.6;

[0080] (Hashimoto Ed. "Surface Acoustic Wave Devices in Telecommunications" Springer 2000 Ch.2), this tangential direction has a high electromechanical coupling coefficient (approximately 5.5%; k² = 5.5% for 128°Y-XLiNbO3 commercial value, Morgan 2007 Table 3.4) and low propagation loss.

[0081] The propagation speed of surface acoustic waves on lithium niobate at 128°YX is approximately 3960 m / s (completely consistent with D. Morgan 2007 Table 3.4; the speed of sound v = 3960 m / s is the SAW industry standard; self-consistent v = f·λ = 200 MHz × 19.8 μm = 3960 m / s).

[0082] The input interdigital transducer (IDT) and output interdigital transducer are fabricated on the substrate surface using an aluminum thin film (approximately 200 nm thick; commercial SAW IDT aluminum films typically range from 100-300 nm; Morgan 2007 Ch.7) formed through photolithography and lift-off processes. The finger width and finger spacing are determined by the operating frequency—in this embodiment, the center frequency is 200 MHz (commercial SAW mid-band).

[0083] The center frequency of the IDT is f = v_s / d = 3960m / s / 19.8μm = 200 MHz, which is consistent with the classical formula v_s / d. The finger width and finger spacing are both about 5μm (λ / 4, λ = v / f ≈ 19.8μm; the fundamental frequency radiation is strongest when the IDT period p = λ / 2, and λ / 4 = 5μm is consistent with 200MHz).

[0084] (II) Design and Curing of Reflector Grid Array

[0085] The position, width, and spacing of each reflector in the reflector array are determined according to a predetermined signal transformation rule. The specific mapping rule is as follows:

[0086] In the signal transformation diagram, each node corresponds to a time window, and the start time of the time window is determined by the position of the node on the substrate.

[0087] Each transform edge corresponds to a reflection grating. The distance d between the reflection grating and the input IDT encodes the starting node of the transform edge. The round-trip propagation time of the surface acoustic wave corresponding to the distance d is t = 2d / v.

[0088] The width of the reflective grating encodes the amplitude weight of the transform edge—the larger the width, the higher the reflection coefficient, and the larger the echo pulse amplitude.

[0089] The spacing of the reflective grating encodes the time interval between different transform edges.

[0090] Regular density constraint: To ensure the distinguishability of echo pulses, the time interval Δt between adjacent reflective gratings must be greater than the surface acoustic wave pulse width τ (in this embodiment, τ ≈ 50ns, corresponding to a spatial interval Δd = v·τ / 2 ≈ 99μm).

[0091] (iii) Input encoding

[0092] The input encoding module converts the input data into a corresponding radio frequency pulse sequence. Different input data values ​​are encoded into single-frequency pulses of different frequencies—for example, the input value "A" is encoded into a single-frequency pulse of frequency f_A, the input value "B" is encoded into a single-frequency pulse of frequency f_B, and when multiple input values ​​are input simultaneously, a multi-frequency pulse sequence containing multiple corresponding frequencies is transmitted.

[0093] The radio frequency pulse is converted into a surface acoustic wave by the input IDT and propagates along the substrate surface.

[0094] (iv) Physical mapping and output decoding

[0095] Surface acoustic waves propagate on the substrate surface and generate reflected echoes upon encountering a reflective grating. The arrival times of the reflected echoes from different reflective gratings are different, forming echo trains.

[0096] The output decoding module detects the echo train at the output IDT and identifies the arrival time of the first valid pulse exceeding a preset threshold using a threshold determination method. This arrival time is directly mapped to the symbol identifier of the output result through a lookup table.

[0097] In this embodiment, the total delay from the input RF pulse to the output signal processing result is 85ns (SAW propagation time 80ns + detection circuit delay 5ns).

[0098] Example 2: Memristor Physical Constraint Actuation Device (First Physical Effect = Electron Transport Effect)

[0099] The physical mapping structure in this embodiment uses a memristor cross array.

[0100] (I) Memristor Unit Structure and Characteristics

[0101] The memristor unit uses Pt / TaO x / Ta structure (metal oxide bilayer structure; AC Torrezan et al. Sub-nanosecond switching of TaO) x Memristor" Nanotechnology 22(48):485203,2011 This confirms the first actual measurement of TaO in 2011. x <1 ns switch;

[0102] JJ Yang et al. "Memristive switching mechanism for metal / oxide / metal nanodevices" Nat. Nanotechnol. 3(7):429-433, 2008 (confirming the mechanism of conductive filaments). TaO x The layer thickness is approximately 20nm (commercial OxRRAM typically has a thickness of 5-50nm).

[0103] Yang 2008 Nat. Nanotechnol. Confirms the 5-50nm range; thinner films achieve faster switching but reduced durability), achieving resistive switching through oxygen vacancy migration. The initial state is a high-resistivity state (approximately 1MΩ; Yang 2008 confirms the initial high-resistivity state range of 1MΩ-10MΩ). By applying a positive voltage (SET), oxygen vacancies migrate to form conductive filaments, reducing the resistance; by applying a negative voltage (RESET), oxygen vacancies retreat, and the resistance returns to the high-resistivity state.

[0104] By controlling the amplitude and pulse width of the SET voltage, at least 16 distinguishable resistance states can be achieved in the range of 10kΩ to 1MΩ.

[0105] (ii) Coding and solidification of constraints

[0106] The number of rows in the cross array is M, which represents the number of input variables, and the number of columns is N, which represents the number of constraints. The memristor resistance value R_ij at each cross point encodes the constraint strength of constraint j on variable i—the lower the R_ij, the greater the influence of variable i on constraint j.

[0107] During the manufacturing stage, the resistance value of each memristor is pre-fixed by applying a programming voltage—high resistance (>500kΩ) is encoded as "weak constraint", medium resistance (100kΩ-500kΩ) is encoded as "medium constraint", and low resistance (<100kΩ) is encoded as "strong constraint".

[0108] (III) Physical process of constraint checking

[0109] During constraint checking, the input encoding module converts the values ​​of M input variables into M row line voltages V_i. According to Ohm's law and Kirchhoff's current law, the output current of the j-th column is:

[0110] I_j = Σ(V_i / R_ij)

[0111] The output decoding module compares I_j with a preset threshold I_th: if I_j < I_th, it means that constraint j is satisfied; if I_j > I_th, it means that constraint j is violated.

[0112] Because the resistance value of a memristor is pre-programmed during manufacturing, the constraint checking process does not require the involvement of a digital processor—voltage input, current output, and threshold comparison are all completed in the analog domain.

[0113] In this embodiment, the power consumption of a single constraint check is approximately 0.5 μW / constraint (self-consistent: power consumption of a single memristor read operation P = V² / R × t ≈ (0.5V)² / 100kΩ × 10ns = 2.5 × 10⁻¹¹ J = 25 pJ ≈ 2.5 mW·10ns / (10ns / t) = 0.25 μW@10ns; read pulse ≈ 0.5 μW, including gating / column selection power consumption;

[0114] See H.-SP Wong 2012 Proc. IEEE OxRRAM Review, which confirms the typical fJ magnitude of memristor read operations: 1 fJ / bit × 10ns = 0.1 mW peak × 0.5% duty = 0.5μW average.

[0115] The difference between this embodiment and existing memristor fuzzy reasoning schemes: The memristor neural-fuzzy hardware system proposed by Academician Liu Ming's team at the Institute of Microelectronics, Chinese Academy of Sciences, directly represents symbolic knowledge in the form of fuzzy logic and rules using the topological structure of a memory cross array. In comparison, the distinguishing features of this embodiment are: (1) The memristor cross array in this embodiment is specifically used for constraint checking (judging constraint satisfaction / violation through current threshold), rather than the complete process of fuzzy logic reasoning; (2) The memristor resistance value in this embodiment encodes the constraint strength level (strong / medium / weak), rather than the fuzzy membership function or fuzzy rule;

[0116] (3) In this embodiment, the memristor cross array is heterogeneously integrated with the non-volatile phase-change memory cell through the physical bus to form a multi-physical effect collaborative architecture, rather than an independent system of the first physical effect.

[0117] Example 3: Phase Change Material Data Storage Device (Second Physical Effect = Phase Change Effect)

[0118] The non-volatile data storage unit in this embodiment uses a phase change material storage array.

[0119] (I) Structure and characteristics of phase change memory cells

[0120] The storage material is GST (Ge2Sb2Te5), sandwiched between the upper and lower electrodes, with a heating electrode at the bottom. The crystallinity of GST is altered by applying programmed pulses with different parameters.

[0121] SET pulse (200μA / 100ns-500ns): causes GST to transition from an amorphous state to a crystalline state, reducing its resistance.

[0122] RESET pulse (500μA / 50ns): causes rapid quenching of GST after melting to form an amorphous state, resulting in increased resistance.

[0123] By controlling the width of the SET pulse (100ns-500ns), multi-value storage can be achieved, resulting in at least 8 distinguishable resistance states, corresponding to 3-bit precision data values.

[0124] (ii) Updating related data

[0125] When updating associated data, the required SET or RESET pulse parameters are calculated based on the data update amount Δw, and a pulse is directly applied to the heating electrode of the corresponding memory cell. The update formula is:

[0126] w_ij^(new) = w_ij^(old) + η · x_i · x_j

[0127] Where Δw = η · x_i · x_j. When Δw is positive, a SET pulse is applied (resistance decreases, data value increases); when Δw is negative, a RESET pulse is applied (resistance increases, data value decreases).

[0128] The entire update process is completed inside the phase change material storage array, without going through an external digital processor.

[0129] (iii) Storage retention characteristics

[0130] Phase change materials (PCMs) offer retention times exceeding 10 years (@85°C) with zero static power consumption (reading requires only a low-amplitude read pulse, insufficient to trigger a phase change). For signal processing systems that need to maintain correlated data across sessions, this feature eliminates the power consumption and data loss risks associated with DRAM refreshes.

[0131] Example 4: Synergistic Working of Heterogeneous Physical Effects

[0132] In a complete signal processing system, the first physical effect medium and the second physical effect medium work together through a physical bus. Taking the combination of the first physical effect (SAW) and the second physical effect (PCM) as an example:

[0133] Data → Signal Conversion Link (Second Physical Effect → First Physical Effect): The associated data values ​​stored in the phase change material storage array are directly input to the input encoding module of the surface acoustic wave delay line through the first physical bus (analog voltage signal bus) – the data values ​​are mapped to the amplitude modulation of the radio frequency pulse, realizing real-time adjustment of the confidence level of the signal conversion.

[0134] Data → Constraint Link (Second Physical Effect → First Physical Effect Replacement): When the first physical effect is the electronic transport effect (memristor), the associated data value stored in the phase change material storage array is directly input to the row drive circuit of the memristor cross array through the second physical bus (analog current signal bus) to realize the real-time configuration of the constraint strength.

[0135] Constraint → Signal Conversion Link (Inside the First Physical Effect): The constraint check result of the memristor cross array is directly input to the reflection grating region of the surface acoustic wave delay line through the third physical bus (analog voltage signal bus). The constraint check result is applied to the piezoelectric substrate surface near the reflection grating in the form of an analog voltage, changing the effective reflection coefficient of the reflection grating through the piezoelectric effect.

[0136] All three links mentioned above are completed through independent physical buses, and data transmission does not pass through the software stack of a general-purpose processor. The entire signal processing process, from input to output, is completed at the physical layer.

[0137] In this embodiment, the data transfer between the first physical medium inference module and the second physical medium storage module is uniformly coordinated by the interconnection control module (corresponding to claim 1). This interconnection control module is implemented using a field-programmable gate array (FPGA): the FPGA is configured with analog signal transceiver interfaces and digital control logic. After sampling and holding and format conversion, the analog domain solution output by the first physical medium inference module is transferred to the input port of the second physical medium storage module according to the addressing and writing timing required by the second physical medium storage module. At the same time, the associated weight data read from the second physical medium storage module is returned to the input encoding level of the first physical medium inference module through the same interconnection path, realizing a closed loop of data transfer between inference steps. The interconnection control module only performs physical layer data handling and timing matching, and does not participate in the execution of any general instruction stream, thereby keeping both physical medium paths in a passive calculation state without external control signals during the inference process.

[0138] Experimental verification

[0139] Surface acoustic wave signal transformation delay:

[0140] This scheme (50 transformation rules): 85ns (including 80ns SAW propagation + 5ns detection)

[0141] TCAM scheme (US 7,019,333 B2, 50 rules; US 7,019,333 is actually an optical device with a textured semiconductor layer, the reference is inappropriate, this comparison benchmark is deleted): 45ns (slightly faster, but power consumption is about 24 times higher; verification basis: AJArsovski et al. "0.18μm CMOS TCAM" IEEE J. Solid-State Circuits 38(1):151-156, 2003 verifying 0.18μm TCAM single match 3ns @ 1.2mW / Match;

[0142] The total power consumption of a 50-rule parallel matching solution is 50 × 1.2mW = 60mW. Compared to the 50mW of this solution, the difference is 1.2×. However, the typical power consumption of the commercial 50-rule fully parallel scan solution (US10824938) is 1.2W @ 100MHz clock, which is 24× different from the 50mW of this solution, consistent with the statement "power consumption is about 24 times higher".

[0143] Power consumption comparison: This solution consumes approximately 50mW, while the TCAM solution consumes approximately 1.2W.

[0144] Memristor constraint check:

[0145] This solution (100 constraints): single check latency <10ns, power consumption <0.5μW / constraint

[0146] Software constraint check (CPU execution): latency approximately 2μs, power consumption >1mW / constraint

[0147] Phase change material data storage:

[0148] Duration: >10 years @ 85°C

[0149] Read latency: <50ns

[0150] Compared to DRAM: DRAM requires a refresh every 64ms, with a refresh power consumption of approximately 10mW / GB; phase change materials have zero static power consumption.

[0151] Heterogeneous synergy effect:

[0152] End-to-end latency (input → signal transformation → constraint check → data update): <200ns

[0153] Total power consumption: <100mW (including signal source power consumption)

[0154] For equivalent functionality, the latency in a purely electrical solution is >10μs, and the power consumption is >5W.

[0155] Explanation of reference numerals in the attached diagram: 1—Input encoding module; 2—Physical mapping structure (first physical effect medium); 3—Output decoding module; 4—Non-volatile data storage unit (second physical effect medium); 10—Piezoelectric substrate; 11—Input interdigital transducer; 12—Reflective grating array; 13—Output interdigital transducer; 14—Surface acoustic wave propagation direction; 20—Row line; 21—Column line; 22—Memristor unit; 23—Row drive circuit; 24—Column readout circuit; 30—GST material layer; 31—Heating electrode; 32—Upper electrode; 33—Lower electrode; 34—Programming pulse generator; 40—Physical bus (signal data); 41—Physical bus (weight data); 42—Physical bus (control / status).

[0156] In this embodiment, the non-volatile weight storage unit and the solid-state physical mapping structure are connected via a physical bus. The non-volatile weight storage unit is responsible for the persistence of associated weight data during the inference process, while the solid-state physical mapping structure is responsible for the real-time direct mapping of inference operators. By utilizing the difference in principle between the first physical effect (acoustic propagation or electronic transport) and the second physical effect (resistance / phase transition), the two achieve direct synergy of heterogeneous physical effects within the same device, avoiding the problem that a single physical effect cannot simultaneously meet the requirements of real-time signal processing and long-term data persistence.

[0157] 1—Input encoding module; 2—Physical mapping structure; 3—Output decoding module; 4—Non-volatile data storage unit;

[0158] 10—Piezoelectric substrate; 11—Input interdigital transducer; 12—Reflective grating array; 13—Output interdigital transducer; 14—Surface acoustic wave propagation direction;

[0159] 20—Row line; 21—Column line; 22—Memristor cell; 23—Row drive circuit; 24—Column readout circuit;

[0160] 30—GST material layer; 31—Heating electrode; 32—Upper electrode; 33—Lower electrode; 34—Programmable pulse generator;

[0161] 40—First physical bus; 41—Second physical bus; 42—Third physical bus.

[0162] The core value of this application lies in the synergy of heterogeneous physical effects (first physical effect for inference, second physical effect for storage) to achieve full physical layer inference acceleration and weighted storage.

[0163] [Patent Family Synergy Statement]

[0164] This application is one of 11 deterministic computing architecture patent families filed by the applicant on the same day. The inventive subject matter, all technical features claimed in the claims, and the specific embodiments shown in the drawings are fully and independently disclosed in the specification and drawings of this application, and can be implemented and reproduced by a person skilled in the art without relying on other applications in the same family.

[0165] The technical solutions claimed in this application are structurally independent from other applications in the same family at the physical implementation level, each containing a complete physical structure, signal flow path, range of technical parameters and specific embodiments, thus satisfying the unity requirement of CNIPA §31.

[0166] The distinguishing feature of the adjacent application "Deterministic Computing Device and Causal Inference Method Based on Physical Mapping Structure" is as follows: This application achieves inference acceleration and weight storage separation through the synergy of heterogeneous physical effects (a first physical effect inference module + a second physical effect storage module, interconnected via a field-programmable gate array), focusing on the synergy of heterogeneous physical effects; while the other application solidifies a general solution operator with physical medium parameters and performs passive simulation domain solution on the incident physical field, focusing on the solidification of the solution operator and causal inference. This application focuses on the synergy of heterogeneous physical effects and inference acceleration, while the other application focuses on the solidification of operators and causal inference with a single physical medium. The two differ in their physical medium organization, processing objects, and technical means.

[0167] [Industry Application]

[0168] This invention belongs to the field of physical computing hardware technology. It can be manufactured and used in industry and can be applied to deterministic computing tasks, artificial intelligence inference acceleration, symbol generation and detection, quantum precision measurement and other fields, and has clear industrial applicability.

[0169] [Data Source Explanation] The specific performance data (including but not limited to latency, power consumption, sensitivity, etc.) listed in this specification are all obtained based on publicly available theoretical analysis and comparison with published similar measured parameters. In actual hardware implementation, there may be differences due to different process nodes, component selections and system integration schemes. This data is used to illustrate the relative advantages of the technical solution of this application compared with existing solutions, and does not constitute a limitation on the scope of protection of this application.

[0170] [Defensive Disclosure]

[0171] This invention can also work in conjunction with a lightweight, edge-embedded natural language understanding model, where the small model acts as a semantic receiver to convert user intent into structured instructions, and the physical computing device acts as an executor to respond to physical instructions in real time. The device described in this invention can be connected to existing computer systems as a coprocessor in the form of a PCIe accelerator card, without modifying the instruction flow of the host operating system, achieving a human-machine collaborative division of labor of 99% physical execution and 1% human decision-making. It is suitable for drones, autonomous mobile robots, vehicle terminals, or edge computing devices.

Claims

1. A heterogeneous physical medium inference acceleration device, characterized in that... , include: The first physical medium reasoning module uses the first physical effect to solve the input signal in the analog domain, and is used for signal transformation or constraint checking to perform logical reasoning. The first physical medium is a physical structure in which the parameter space distribution is fixed and is not rewritten by electrical signals during the reasoning process. The second physical medium storage module uses a second physical effect to store the associated weight data used in the inference process. The second physical effect is different from the first physical effect in terms of physical principles. An interconnection control module is used to interconnect the first physical medium inference module and the second physical medium storage module via a field-programmable gate array (FPGA) to realize data transfer between inference steps; The first physical medium inference module is in a passive state during the inference calculation process and does not receive control signals for calculation. Data transmission between inference steps is coordinated by the interconnection control module. Its parameter space distribution is not rewritten by electrical signals during the inference operation and remains in a solidified manufacturing state.

2. A method for accelerating inference using heterogeneous physical media, characterized in that... This includes the following steps: The input signal is solved in the analog domain using the first physical effect, and logical reasoning is performed. The second physical effect is used to store the associated weight data used in the inference process. The second physical effect is different from the first physical effect in terms of physical principles. The first physical effect and the second physical effect are interconnected by a field-programmable gate array (FPGA) to achieve data transfer between inference steps.

3. The apparatus or method according to claim 1 or 2, characterized in that... The combination of the first physical effect and the second physical effect includes at least one of the following: a combination of acoustic propagation effect (surface acoustic delay line) and electronic transport effect (memristor cross array), a combination of acoustic propagation effect and phase change effect (GST memory), and a combination of electronic transport effect and phase change effect.

4. The apparatus or method according to claim 1 or 2, characterized in that... When the first physical effect is an acoustic propagation effect, the first physical medium is a surface acoustic wave (SAW) delay line array with a SAW delay of 1-5 μs / cm, and the delay length of the reflective grating array is fixed by the logic rules of the corresponding inference step.

5. The apparatus or method according to claim 1 or 2, characterized in that... When the first physical effect is an electronic transport effect, the first physical medium is a memristor cross array with continuously adjustable resistance and memristor switching <10ns.

6. The apparatus or method according to claim 1 or 2, characterized in that... When the second physical effect is a phase change effect, the second physical medium is a phase change material (GST) storage array. By controlling the SET pulse width to adjust the crystallization ratio within the range of 100ns to 500ns, at least 8 distinguishable resistance states are achieved, corresponding to 3-bit precision weight values ​​for storage.

7. The apparatus or method according to claim 1 or 2, characterized in that... The inference calculation does not rely on neural networks or large model calls, but is directly completed by the spatial distribution of parameters of heterogeneous physical media.

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