Quantum circuit block splicing method and device, equipment, medium and program product

Abstract

The application relates to a quantum circuit block splicing method and device, equipment, medium and program product, which comprises the following steps: determining the current state and target state of each physical node; performing node layering preprocessing on the hardware topology graph corresponding to each physical node to generate each node layer; sequentially processing each physical node in each node layer according to the order of the node layering; for the current physical node, if the current state of the current physical node is inconsistent with the target state, the source physical node corresponding to the target state is located, a path from the source physical node to the current physical node is searched on the hardware topology graph, a swap operation sequence is generated based on the path, the current state of each physical node is updated based on the swap operation sequence, and the current physical node and the associated edge of the current physical node are deleted from the hardware topology graph; and a block splicing quantum circuit segment is generated based on the swap operation sequence. The method can improve the accuracy of block splicing.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, device, medium, and program product for splicing quantum circuit blocks. Background Technology

[0002] Quantum computing holds great promise for applications such as materials simulation, drug discovery, and cryptography due to its potential for supercomputing power. However, current noisy medium-scale quantum (NISQ) devices are limited by the number of physical qubits, connectivity, and high error rates. To run quantum algorithms on hardware, the compilation process needs to solve the qubit mapping and routing problem: mapping the logical qubits in the abstract algorithm to specific physical qubits, and inserting SWAP gates (routing) to ensure that all two-qubit gate operations can be executed on the nearest neighbor connections allowed by the hardware.

[0003] For large-scale quantum circuits, direct global routing optimization faces problems such as search space explosion and excessively long compilation times. An effective strategy is "divide and conquer," which involves cutting long quantum circuits into multiple contiguous, shorter-depth "blocks" (or "layers") and then independently mapping and optimizing the routing for each block. This method significantly reduces the complexity of a single optimization and facilitates parallel processing. However, this method introduces a new key challenge: the inter-block splicing problem. That is, after routing the previous block, the physical location distribution of the qubits (called the "end configuration") may not satisfy the expected mapping (called the "start configuration") when the next block begins execution. Therefore, a series of SWAP gates need to be inserted between the two blocks to convert the end configuration to the start configuration; this process is called "splicing."

[0004] In traditional techniques, inter-block splicing is often simplified to a single, graph-based "token swapping" or "piece rearrangement" problem. The closest approximation is to model it as finding the minimum sequence of SWAP gates from the "end configuration" to the "start configuration." For example, a shortest-path-based greedy swapping approach: for each logical qubit that needs to be moved in the next block, calculate the shortest path from its current position to the target position on the coupled graph and sequentially insert SWAP gates along that path. This method is simple to implement, but it doesn't consider the mutual interference between different bit movement paths, which can lead to collisions and additional SWAP gate insertions, and it is not globally optimal. Summary of the Invention

[0005] Therefore, it is necessary to provide a quantum circuit inter-block splicing method, apparatus, equipment, medium, and program product that can improve the accuracy of inter-block splicing in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides a method for splicing quantum circuit blocks, the method comprising:

[0007] The current state of each physical node is determined based on the termination physical configuration of the previous quantum logic block, and the target state of each physical node is determined based on the starting physical configuration of the current quantum logic block.

[0008] Based on the hardware topology diagram corresponding to each physical node, node layering preprocessing is performed to generate each node layer. The hardware topology diagram is a complete copy of the hardware topology corresponding to each physical node.

[0009] Each physical node in each node layer is processed sequentially according to the order of the node layering. For the current physical node, if the current state of the current physical node is inconsistent with the target state, the source physical node corresponding to the target state is located, a path from the source physical node to the current physical node is searched on the hardware topology graph, a swap operation sequence is generated based on the path, the current state of each physical node is updated based on the swap operation sequence, and the current physical node and its associated edge are deleted from the hardware topology graph.

[0010] Based on the exchange operation sequence, inter-block splicing quantum circuit segments are generated.

[0011] In some alternative embodiments, the method further includes:

[0012] If the current state of the current physical node is consistent with the target state, the current physical node and its associated edges are deleted from the hardware topology graph.

[0013] In some optional embodiments, the node hierarchical preprocessing based on the hardware topology graph corresponding to each physical node to generate each node hierarchy includes:

[0014] A temporary copy is generated based on the hardware topology corresponding to each physical node;

[0015] Candidate physical nodes are determined based on the degree of each physical node in the temporary replica;

[0016] Candidate physical nodes in the temporary copy that satisfy the condition of unchanged connectivity after deletion are determined as target physical nodes. The condition of unchanged connectivity after deletion means that after deleting the candidate physical node and the edge corresponding to the candidate physical node from the temporary copy, the temporary copy remains connected. The current node hierarchy is generated based on each target physical node.

[0017] Remove each target physical node and the edge corresponding to each target physical node from the temporary copy, and continue to execute the step of determining candidate physical nodes based on the degree of each physical node in the temporary copy until the temporary copy is empty, and then generate each node layer.

[0018] In some optional embodiments, determining candidate physical nodes based on the degree of each physical node of the temporary replica includes:

[0019] Calculate the number of edges currently connected to each physical node in the temporary replica;

[0020] The number of each edge is taken as the degree of each physical node;

[0021] The physical node with the smallest degree is determined as the candidate physical node.

[0022] In some optional embodiments, the step of searching for a path from the source physical node to the current physical node on the hardware topology graph and generating a sequence of switching operations based on the path includes:

[0023] Starting from the source physical node and ending at the current physical node, a breadth-first search is performed on the hardware topology graph to obtain the path from the source physical node to the current physical node.

[0024] According to the path from the starting point to the ending point, the logical bits on each pair of adjacent physical nodes in the path are swapped in sequence. After each pair of physical nodes is swapped, the pair of physical nodes is recorded in the swap operation sequence.

[0025] In some optional embodiments, before determining the current state of each physical node based on the termination physical configuration of the previous quantum logic block, and determining the target state of each physical node based on the starting physical configuration of the current quantum logic block, the process includes:

[0026] The quantum circuit is divided into multiple consecutive logic blocks in chronological order, and each logic block is a sub-circuit containing a series of quantum gate operations;

[0027] Perform qubit mapping and routing optimization on each of the logic blocks, and assign an initial physical configuration to each of the logic blocks;

[0028] By inserting swap gates into each of the logic blocks, the two-qubit gates in each logic block satisfy the nearest neighbor constraint of the hardware topology graph, thereby obtaining an executable physical circuit and the termination physical configuration after each logic block is executed.

[0029] Secondly, this application also provides a quantum circuit block splicing device, the device comprising:

[0030] The state acquisition module is used to determine the current state of each physical node based on the termination physical configuration of the previous quantum logic block, and to determine the target state of each physical node based on the starting physical configuration of the current quantum logic block.

[0031] The layering module is used to perform node layering preprocessing based on the hardware topology diagram corresponding to each physical node, and generate each node layer. The hardware topology diagram is a complete copy of the hardware topology corresponding to each physical node.

[0032] The switching module is used to process each physical node in each node layer in the order of the node layering. For the current physical node, if the current state of the current physical node is inconsistent with the target state, the source physical node corresponding to the target state is located, a path from the source physical node to the current physical node is searched on the hardware topology graph, a switching operation sequence is generated based on the path, the current state of each physical node is updated based on the switching operation sequence, and the current physical node and its associated edge are deleted from the hardware topology graph.

[0033] The inter-block circuit generation module is used to generate inter-block spliced ​​quantum circuit segments based on the exchange operation sequence.

[0034] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the above embodiments.

[0035] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0036] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0037] The aforementioned quantum circuit block splicing method, apparatus, device, medium, and program product determine the current state of each physical node based on the termination physical configuration of the previous quantum logic block, and determine the target state of each physical node based on the starting physical configuration of the current quantum logic block; perform node layering preprocessing based on the hardware topology graph corresponding to each physical node to generate each node layer, wherein the hardware topology graph is a complete copy based on the hardware topology corresponding to each physical node; process each physical node in each node layer sequentially according to the node layering order, wherein for the current physical node, the current state and the target state of the current physical node are different. In the case of a conflict, the source physical node corresponding to the target state is located, and a path from the source physical node to the current physical node is searched on the hardware topology graph. After generating a swap operation sequence based on the path, the current state of each physical node is updated based on the swap operation sequence, and the current physical node and its associated edges are deleted from the hardware topology graph. Based on the swap operation sequence, inter-block splicing quantum circuit segments are generated. In this way, the movement sequence is planned from a global perspective, the peripheral nodes are fixed securely first, and clear paths are made for the movement of internal bits, so as to obtain a splicing scheme that is logically correct, has few swap conflicts, and does not fall into deadlock. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a flowchart illustrating a method for splicing quantum circuit blocks in one embodiment;

[0040] Figure 2 This is a flowchart of the layering steps in one embodiment;

[0041] Figure 3 This is a structural block diagram of a quantum circuit block splicing device in one embodiment;

[0042] Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0045] Before providing a detailed introduction to this application, the following explanations will be given regarding the terms used in this application:

[0046] Quantum circuitry: A computational flowchart consisting of a series of logic gates (such as single-bit gates, two-bit CNOT gates, etc.) acting on qubits in a specific order, used to describe quantum algorithms.

[0047] Quantum bit mapping: The process of assigning logical qubits in a quantum algorithm to specific physical qubits on a physical quantum chip.

[0048] Quantum routing: In quantum circuit compilation, by inserting operations such as SWAP gates, the positions of logical qubits on physical qubits are adjusted to meet the hardware nearest neighbor constraint required by two-qubit gates.

[0049] Coupled graph: An undirected graph G=(V, E), where vertex V represents a physical qubit and edge E represents a two-qubit gate (such as a CNOT gate) that can be directly executed between two physical qubits.

[0050] Logical Block / Physical Block: A long quantum circuit is divided into several sub-circuit modules according to the execution order, which are called "logic blocks". Before each logical block is executed, its logical qubits are mapped to a set of physical qubits, which is called a "physical block configuration".

[0051] Inter-block concatenation: In a block-based routing strategy, after completing internal routing for a logical block, it is necessary to convert the physical block configuration at the end of the block into the starting physical block configuration required by the next logical block. This process is typically achieved by inserting additional SWAP gate sequences.

[0052] SWAP gate: A basic two-qubit logic gate used to swap the quantum states of two qubits.

[0053] In one embodiment, such as Figure 1As shown, a method for splicing quantum circuit blocks is provided. This embodiment illustrates the application of this method to a terminal. It is understood that this method can also be applied to a server, and further to a system including both a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0054] S102: Determine the current state of each physical node based on the termination physical configuration of the previous quantum logic block, and determine the target state of each physical node based on the starting physical configuration of the current quantum logic block.

[0055] In this step, the terminal first obtains the two input configurations necessary for the splicing operation. Specifically, for two adjacent quantum logic blocks that need to be spliced, the first block is designated as block t, and the second block as block t+1. The terminal reads the termination physical configuration after the execution of the first quantum logic block (block t), and the starting physical configuration required before the execution of the current quantum logic block (block t+1) begins.

[0056] A physical configuration refers to a mapping from a set of logical qubits to a set of physical qubits. For example, on a chip containing N physical qubits, a physical configuration π can be represented as π: → ,in Represents the logical qubits in the algorithm. This represents the physical qubits on the chip. This mapping indicates which physical qubit each logical qubit is currently mapped to.

[0057] For logic blocks that need to be connected and The terminal receives the termination physical configuration generated by its internal routing optimization. With the initial physical configuration Based on this, the current state vector is defined. , of which components Represents physical bits The current logical bit, and based on Initialization, i.e. (This means that for any physical node i, its current state is determined based on the initial physical configuration), thus obtaining the current state of each physical node. Simultaneously, a target state vector is defined. ,in This means determining the target state of each physical node. The algorithm initializes the hardware topology. Hardware topology A complete copy is used as the basis for subsequent pathfinding.

[0058] Through this step, the terminal concretizes the abstract configuration transformation problem into a clear and quantifiable state transformation problem, namely, finding a series of operations that make the current state vector... Final and target state vector Totally consistent.

[0059] S104: Perform node layering preprocessing based on the hardware topology diagram corresponding to each physical node to generate each node layer. The hardware topology diagram is a complete copy of the hardware topology corresponding to each physical node.

[0060] After determining the initial and target states, the terminal does not directly perform random swap operations, but instead executes a crucial preprocessing step. The terminal acquires the hardware topology of the target quantum chip, which consists of an undirected connected graph. =(Vphy, Ephy) represents the set of all physical qubits on the chip, while Ephy represents all physical connections (i.e., edges) on the chip that can directly execute two-qubit gates.

[0061] The purpose of this step is to, based on this static hardware topology Generate a hardware topology diagram Then based on the hardware topology diagram A priority order for processing each physical node is pre-calculated. This order is organized into multiple "node hierarchies," for example... These layers are determined layer by layer from the periphery of the topology graph (usually nodes with lower degrees) inwards.

[0062] To generate these layers, the terminal employs a connectivity-protected strategy. When determining each layer, a simulated deletion operation is performed, checking whether deleting the node would disrupt the connectivity of the remaining topology. Only nodes whose deletion would not cause the remaining graph to split are added to the current outermost layer. This process is repeated until all nodes are layered, ultimately generating an ordered list of node layers. This list ensures that when processing a node, its external nodes have been removed, thus creating clear paths for operations on internal nodes and guaranteeing that the logic of the entire layering is globally solvable.

[0063] S106: Process each physical node in each node layer in the order of node layering. For the current physical node, if the current state of the current physical node is inconsistent with the target state, locate the source physical node corresponding to the target state, search for the path from the source physical node to the current physical node on the hardware topology graph, generate a swap operation sequence based on the path, update the current state of each physical node based on the swap operation sequence, and delete the current physical node and its associated edges from the hardware topology graph.

[0064] After obtaining the node hierarchy list, the terminal enters the core exchange sequence generation phase. The terminal will strictly follow the sequence starting from the outermost layer. To the innermost layer The process is carried out in sequence, layer by layer and node by node.

[0065] When processing the current physical node v, the terminal first checks whether the current physical node v is already in place. That is, it determines the current state vector. Is it equal to the target state vector? .

[0066] If the determination result is inconsistent, meaning the logical bit currently located on the current physical node v is not the final logical bit it needs, the terminal needs to perform a move operation. First, the terminal will locate the source physical node, denoted as u. The source physical node u refers to the node currently carrying the target logical bit. = That physical node, that is, satisfying The terminal performs a path search on a specific hardware topology graph after determining the source physical node u and the current physical node v. It is important to emphasize that this hardware topology graph is not the original hardware topology. Instead, it's a dynamic graph that continuously updates and shrinks as the algorithm executes. In other words, the path needs to meet two conditions: first, it must be the shortest path; second, it cannot traverse fixed physical nodes (those that have already been processed and satisfy the condition). The physical nodes are those that are already fixed. The terminal uses algorithms such as Breadth-First Search (BFS) on this dynamic graph to find the shortest path from u to v. .

[0067] After finding a path, the terminal generates a sequence of swap operations along that path. Specifically, starting from the path's starting point u, it swaps the tokens of each pair of adjacent nodes along the path in sequence. For example, it first swaps the tokens of nodes u and u. The logical bits on the top, then swapped and On top, and so on, until the target token is obtained. Finally, the process moves to node v. Each swap operation (e.g., swapping the contents of nodes a and b) is recorded as a SWAP gate operation (a, b) and appended to the total swap operation sequence S. After performing all swaps along the path, the current state vector... It is also updated to reflect the latest logical bit distribution.

[0068] Whether the node is in place after being moved as described above, or it was already in place during the previous check, once the logical bits on the current physical node v are in their target positions, the terminal considers the current physical node v to be fixed. At this point, the terminal will formally remove the current physical node v from the currently operating dynamic hardware topology graph. This removal operation is permanent, meaning that the current physical node v and all its associated edges will no longer participate in any subsequent path searches. This simulates the physical reality that the position has been permanently occupied on the physical hardware.

[0069] S108: Generate inter-block splicing quantum circuit segments based on the exchange operation sequence.

[0070] Step S106 is executed continuously until all physical nodes have been processed according to the hierarchical list. At this point, all nodes are fixed, and the current state vector... It must be related to the target state vector Completely identical. All the SWAP gate operations generated in step S106, arranged in the order they were appended, constitute the complete sequence S of swap operations.

[0071] Finally, the terminal packages the operation sequence S to generate an independent inter-block splicing quantum circuit segment. This segment is a sub-circuit consisting of a series of SWAP gates, which can be directly executed on the target quantum hardware. The terminal outputs this segment, which is inserted between the executable physical circuit of the previous quantum logic block and the beginning of the next quantum logic block, thus smoothly and correctly connecting the two independently routed segments to form a complete, executable full circuit.

[0072] The above-described quantum circuit block splicing method determines the current state of each physical node based on the termination physical configuration of the previous quantum logic block and the target state of each physical node based on the starting physical configuration of the current quantum logic block. It performs node layering preprocessing based on the hardware topology graph corresponding to each physical node, generating each node layer. The hardware topology graph is a complete copy of the hardware topology corresponding to each physical node. Each physical node in each node layer is processed sequentially according to the node layering order. For the current physical node, if the current state of the current physical node is inconsistent with the target state, the source physical node corresponding to the target state is located. A path from the source physical node to the current physical node is searched on the hardware topology graph. After generating a swap operation sequence based on the path, the current state of each physical node is updated based on the swap operation sequence, and the current physical node and its associated edges are deleted from the hardware topology graph. The inter-block splicing quantum circuit segment is generated based on the swap operation sequence. This method plans the movement sequence from a global perspective, prioritizing the safe fixing of peripheral nodes and creating clear paths for the movement of internal bits, thus obtaining a logically correct splicing scheme with few swap conflicts and no deadlock.

[0073] In some optional embodiments, the method further includes: removing the current physical node and its associated edges from the hardware topology graph if the current state of the current physical node is consistent with the target state.

[0074] Specifically, when the terminal is processing a current physical node When the condition is met, it first performs a check. This means the target logical bit is now located on the correct physical node. At this point, the terminal does not need to perform any additional movement operations for that node, nor will it generate any new SWAP gates. The node is directly marked as either in place or fixed.

[0075] Subsequently, the terminal will immediately perform a deletion operation. This deletion operation is exactly the same as the deletion operation performed after the move is completed in Embodiment 1. That is, the terminal will delete the current physical node. From the current dynamic hardware topology graph used for pathfinding The node has been officially removed. The removal operation includes removing the current physical node. itself and all physical nodes Connected edges from the hardware topology diagram Remove from the set of nodes and the set of edges.

[0076] Through the current physical node Once in place, it is deleted immediately; this embodiment allows for earlier shrinking of the search space. This is because the current physical node... The connections they occupy no longer contribute to subsequent path searches. Removing them in advance can prevent subsequent search algorithms from mistakenly using these fixed nodes as intermediate jump points or target points when processing innermost nodes, thereby further simplifying the search graph and improving search efficiency and accuracy.

[0077] This embodiment further optimizes the algorithm's execution efficiency. By identifying and immediately fixing nodes already at the target position, the algorithm can process these nodes and shrink the topology graph in advance without any additional operations. This strategy of fixing and shrinking early minimizes the scale of subsequent path searches, reduces unnecessary computational overhead, and avoids including fixed nodes in subsequent path planning, thereby ensuring the uniqueness and stability of the splicing scheme.

[0078] In some alternative embodiments, combined with Figure 2 As shown, Figure 2 This is a flowchart of a layering step in one embodiment. This layering step, namely, performing node layering preprocessing based on the hardware topology diagram corresponding to each physical node to generate each node layer, includes:

[0079] S202: Generate a temporary copy based on the hardware topology diagram corresponding to each physical node.

[0080] First, read the complete hardware topology of the target quantum chip. To perform layered preprocessing calculations and avoid polluting the dynamic topology graph used during actual algorithm execution, the compilation server creates a separate copy of the graph in memory, denoted as a temporary copy. This temporary copy contains information related to the hardware topology. The set of nodes and edges is exactly the same. All subsequent layered calculations and simulated deletion operations will be performed on this temporary copy.

[0081] S204: Determine candidate physical nodes based on the degree of each physical node in the temporary replica.

[0082] The build server begins iteratively building each layer. First, the build server computes the current temporary copy. The degree of each physical node in the system.

[0083] In a topological graph, the degree of a node refers to the number of edges directly connected to that node. For example, in a 2D mesh chip, corner nodes have a degree of 2, edge nodes (excluding corner nodes) have a degree of 3, and interior nodes have a degree of 4.

[0084] In some optional embodiments, determining candidate physical nodes based on the degree of each physical node in the temporary replica includes: calculating the number of edges currently connected to each physical node in the temporary replica; using the number of edges as the degree of each physical node; and determining the physical node with the smallest degree as a candidate physical node.

[0085] Specifically, the compilation server traverses the current temporary topology graph. The compiler process involves all nodes in the graph. For each node, the compiler retrieves its adjacency list or adjacency matrix to count the total number of edges directly connected to that node. This process is the most basic degree calculation operation in graph theory. The compiler then defines the number of edges directly connected to each node, calculated in the previous step, as the degree of that physical node. After calculating the degree of all nodes, the compiler sorts or compares these degrees to find the minimum value, d_min. Then, the compiler iterates through all nodes again, selecting all nodes with a degree equal to d_min to form a candidate set. These nodes are the outermost nodes in the current topology.

[0086] After calculating the degree of all nodes, the compilation server identifies all nodes with the minimum degree. These nodes with the minimum degree are grouped into a candidate set, denoted as . These nodes are usually located on the periphery of the current remaining topology and are theoretically nodes that should be processed first.

[0087] S206: Determine the candidate physical nodes in the temporary replica that satisfy the condition of unchanged connectivity after deletion as target physical nodes. The condition of unchanged connectivity after deletion is that the temporary replica remains connected after deleting the candidate physical nodes and the edges corresponding to the candidate physical nodes. Generate the current node hierarchy based on each target physical node.

[0088] This step is the core of the layered approach: connectivity protection checking. The compilation server iterates through the candidate set. For each current physical node v, the compilation server performs a simulation operation: it attempts to move node v and all its associated edges from the temporary copy. Delete it. After deletion, the compilation server checks whether the remaining graph is still connected. Determining whether a graph is connected is a classic algorithmic problem that can be completed in O(n) time using breadth-first search or depth-first search.

[0089] If the remaining graph remains connected after the current physical node v, this means that the current physical node v is not a critical bridge node connecting two or more internal regions. In this case, the current physical node v is safe and can be assigned to the current layer. The compilation server will formally add the current physical node v to the node set of the current layer. middle.

[0090] If deleting the current physical node v results in the remaining graph becoming disconnected (i.e., splitting into two or more unconnected subgraphs), then the current physical node v is a critical cut point. Prematurely fixing such a node would prevent subsequent nodes in different subgraphs from communicating and moving. Therefore, the compilation server will skip this current physical node v and not include it in the current layer. They also did not delete it.

[0091] S208: Delete each target physical node and the edge corresponding to each target physical node from the temporary replica, and continue to execute the step of determining candidate physical nodes based on the degree of each physical node in the temporary replica until the temporary replica is empty, and generate each node layer.

[0092] When the compilation server has finished compiling the candidate set After traversing all nodes in the current layer, The construction is now complete. At this point, the compilation server will... All nodes that are determined to be safe, and all their associated edges, from the temporary copy. The temporary copy was officially and permanently deleted. This is used for the next round of hierarchical calculations.

[0093] Subsequently, the compilation server increments the layer number l, that is... And determine the updated temporary copy. Is it empty? If it's a temporary copy. If nodes still exist in the process, return to step S204 to create a new, smaller temporary copy. Repeat the above process to begin building the next layer. If a temporary copy... If the value is already empty, it means that all nodes have been layered, and the loop ends.

[0094] Finally, the compilation server combines all the built layers in sequence and outputs an ordered list of layered results. This list represents the node hierarchy to be generated in step S104.

[0095] This embodiment provides a deterministic node layering method with strong logical guarantees. By introducing a connectivity protection check, this embodiment ensures the rationality of the layering result, fundamentally avoiding the situation where subsequent problems become unsolvable due to incorrectly fixing key cut points in advance. This makes the solution space of the entire splicing algorithm complete and solvable, guaranteeing the convergence of the algorithm and the feasibility of the final generated solution. At the same time, the idea of ​​layering on the periphery naturally aligns with the outside-in splicing strategy, which helps to reduce the overall number of swap operations.

[0096] In some optional embodiments, a path from the source physical node to the current physical node is searched on the hardware topology graph, and a sequence of swap operations is generated based on the path. This includes: performing a breadth-first search on the hardware topology graph with the source physical node as the starting point and the current physical node as the ending point to obtain the path from the source physical node to the current physical node; and sequentially swapping the logical bits on each pair of adjacent physical nodes in the path in the order from the starting point to the ending point. After each pair of physical nodes is swapped, the pair of physical nodes is recorded in the swap operation sequence.

[0097] Once the compilation server determines the source physical node u and the current physical node v, it will update the current dynamic hardware topology graph. Perform a breadth-first search (BFS) on the current graph. BFS is a classic graph search algorithm. Its characteristic is that when it starts searching from the starting point u, once it reaches the destination v for the first time, the recorded path is always the shortest of all possible paths (i.e., the path with the fewest edges).

[0098] During the search process, the compilation server records the predecessor node of each node so that after a successful search, it can trace back from the endpoint v to the starting point u to reconstruct the complete path. This path can be represented as... .

[0099] After obtaining the shortest path, the compilation server begins the actual token movement. It starts from the first node of the path (source node u) and continues until the second-to-last node (the node preceding the target node v).

[0100] In each step, the compilation server swaps the logical bits of the current node and its next node in the path. For example, the first step swaps u and... The logical bits on the first step; the second step is to swap them. and The logical bits on nk and v are swapped in the final step. After each swap, the compilation server records the operation in memory, for example, as a tuple (a, b), indicating that a SWAP gate was inserted between physical nodes a and b. This tuple is then appended sequentially to the end of the total swap operation sequence S. Simultaneously, the compilation server updates the current state vector in real time. The new mapping after the exchange is recorded to maintain the consistency of the state data.

[0101] This embodiment uses the BFS algorithm to ensure that each time a single target token is moved, the path taken is the shortest path under the current dynamic topology, achieving local optimization. Furthermore, the sequential swapping operation along the path is simple, direct, and effective, accurately moving the target token from the source node to the current node while maintaining the relative order of other tokens along the path. The logic is clear, and it is easy to implement and verify.

[0102] In some optional embodiments, before determining the current state of each physical node based on the termination physical configuration of the previous quantum logic block and the target state of each physical node based on the starting physical configuration of the current quantum logic block, the process includes: dividing the quantum circuit into multiple consecutive logic blocks in chronological order, each logic block being a sub-circuit containing a series of quantum gate operations; performing qubit mapping and routing optimization on each logic block, and assigning an initial physical configuration to each logic block; and obtaining an executable physical circuit and the termination physical configuration after each logic block is executed by inserting swap gates in each logic block to ensure that the two-qubit gates in each logic block satisfy the nearest neighbor constraint of the hardware topology graph.

[0103] The physical quantum chip's topology consists of an undirected connected graph (coupling graph), i.e., the hardware topology. It means that among them represent A physical quantum bit, edge This indicates that a two-qubit gate (such as a CNOT gate) can be directly executed between two qubits.

[0104] Then execute quantum circuitry and block decomposition: given a set of... 1 logical qubit Quantum circuits Divide it into time (depth) order. A series of consecutive logical blocks, denoted as Each logical block It is a sub-circuit containing a series of quantum gate operations.

[0105] Internal routing within each logical block: For each logical block Independently perform qubit mapping and routing optimization. This process is... Allocate an initial physical block configuration and through in Insert a SWAP gate to ensure that all two-qubit gates satisfy the hardware topology. By applying nearest-neighbor constraints, an executable, extended physical circuit is obtained. After optimization, the logic block There is a termination physical block configuration ,express After execution, the position of each logic bit on the physical chip.

[0106] Input: logic block Hardware topology Output: Executable physical circuitry and initial and termination configurations The internal routing can be implemented using existing arbitrary qubit mapping algorithms (such as SABRE, Monte Carlo tree search-based methods, etc.), with the goal of minimizing... The depth or number of SWAP gates.

[0107] For ease of understanding, a detailed embodiment is provided, specifically including:

[0108] In block routing, the previous logical block Termination configuration , and the next logic block Initial configuration They are usually inconsistent. The goal of inter-block splicing is to find a short sequence consisting of SWAP gates. This makes it possible for us to Functions in configuration At that time, configuration can be obtained Mathematically, this can be expressed as:

[0109]

[0110] in, Indicates sequential application The final mapping obtained after all SWAP gates. The complete circuit after splicing is: .

[0111] Perform problem transformation (token exchange on the diagram): For each physical qubit... View as a diagram A node. At time... (Block-to-block), node A "token" was placed on it, its number being a logical qubit. The target pattern is to make the node... The token on it becomes Each operation allows swapping tokens between two adjacent nodes. The goal is to find the minimum sequence of adjacent swaps that transforms the current token distribution into the target distribution. This is a classic graph token swapping problem, and finding the optimal solution on a general graph is NP-hard.

[0112] To address the aforementioned NP-hard problem, this application proposes an efficient heuristic algorithm. The idea is to mimic the "peeling an onion" process, starting from the periphery of the coupled graph (low-degree nodes), gradually moving tokens to their target positions. Each time a node is fixed, it is removed from the current problem, dynamically simplifying the topology of subsequent problems.

[0113] Step (1): Problem initialization and state representation.

[0114] This step aims to establish an accurate mathematical model for the inter-block splicing problem. For the logical blocks that need to be connected... and The algorithm receives the termination configuration generated by its internal routing optimization. With initial configuration Based on this, the current state vector is defined. , of which components Represents physical bits The current logical bit, and based on Initialization, i.e. At the same time, define the target state vector. ,in Algorithm initialization master dynamic coupling diagram Hardware topology A complete copy is used as the basis for subsequent pathfinding. An empty set of processed tags is initialized. This set is used to record the physical bit nodes where the logical bits are in place and their positions need to be fixed. This set will dynamically constrain the search space. Finally, an empty list is initialized. Used to store the sequence of swap operations.

[0115] Step (2): Node hierarchies based on dynamic topology.

[0116] This step is a separate preprocessing stage designed to pre-determine the priority order of processing nodes without modifying the main dynamic hardware topology. and set The algorithm starts from the layer number. Begin and create the initial hardware topology. A temporary copy Used for hierarchical computation. Then it enters the main loop: in each round, when... At this time, the algorithm first finds the current temporary topology. The candidate set is composed of all nodes with the smallest degree. and make the current layer Next, regarding Each node in Perform a critical "connectivity protection check": determine the source of the temporary topology. Delete node After checking all its associated edges, is the remaining part still a connected graph? If the check passes, then... Join the current layer, that is, let and in the temporary topology Perform a deletion operation and update to a temporary topology. Otherwise, skip. After completing the traversal, the set... The nodes in the array are marked as belonging to the first... Layers. Layer numbers increment. The loop continues. Finally, the algorithm outputs an ordered list of hierarchical results. ,in It includes the outermost node, which can be fixed first without affecting connectivity.

[0117] Step (3): Generation of hierarchical guided exchange sequences and dynamic constraint update.

[0118] This step is the execution phase of the algorithm. It processes nodes sequentially based on the static hierarchical list generated in step (2) and dynamically updates the search constraints. The outer loop of the algorithm follows the sequence from... arrive The nodes at each level are traversed sequentially. For each node in the current level... Determine whether the token on the node is already at the target location, i.e., condition. Is it true? If true, then directly add the node. Add to collection To fix, that is Then the node and its neighboring edges from the hardware topology graph The node will be officially removed (subsequent path searches will no longer traverse this node). If this does not work, the target token needs to be removed. Move here. The algorithm first locates... The current source node That is, satisfying of Then, a constrained shortest path search function is called. This function is used in dynamic hardware topology graphs. Run a breadth-first search (BFS) to find a path from... arrive Effective shortest path Next, the algorithm swaps tokens on adjacent nodes along this path in turn: for arrive ,make , Perform the exchange That is, exchanging state vectors In position and The elements. And the operations. Append to sequence When the target token is moved to the node After that, immediately Add to processed set and nodes and its neighboring edges from the hardware topology graph It was officially removed from the Chinese website.

[0119] Step (4): Generation and verification of spliced ​​lines.

[0120] The algorithm will terminate once all nodes have been processed in hierarchical order, and the current state vector will then be... With the target state vector Completely identical, that is At this point, the algorithm outputs a sequence of swap operations. This is the desired inter-block splicing route. This sequence can be directly inserted into the route following the previous logical block. The starting line of the next logic block This ensures that the entire quantum program can be executed correctly and coherently on actual hardware.

[0121] In the above embodiments, a globally coordinated and robust optimization is achieved, effectively avoiding invalid operations and path deadlock. Compared with the traditional greedy method based on single-bit shortest path, the core innovation of this application lies in the introduction of a hierarchical processing mechanism with connectivity protection. In step (2), the algorithm not only filters the candidate set according to the node degree, but also... More importantly, for each candidate node Perform "connectivity protection check" only when delete Only when the remaining part is still connected will it be included in the current layer. This mechanism ensures the robustness of the hierarchical order, preventing serious problems such as prematurely "fixing" a node that is actually a critical bridge, leading to subsequent graph splitting and the inability to find effective paths for internal nodes. In step (3), this robust hierarchical list is strictly followed. Sequential processing, combined with the hardware topology diagram. The operation of removing fixed nodes in the middle section achieves a true and controllable shrinkage of the search space. This plans the movement sequence from a global perspective, prioritizing the safe fixing of peripheral nodes and making clear paths for the movement of internal bits, thereby obtaining a logically correct splicing scheme with few swapping conflicts and without deadlock.

[0122] Second, while ensuring solution quality and robustness, computational efficiency is significantly improved by dynamically shrinking the search space. Compared to the global static graph... The search is performed using a global permutation search algorithm with extremely high complexity. This application uses step (3) to "process the nodes". and its neighboring sides from The "removal" operation in the Chinese version makes the path search function... The calls are always within a continuously decreasing dynamic graph. This proactive topology simplification strategy drastically reduces the scope of the subsequent breadth-first search (BFS), lowering the average search complexity from... The computational efficiency continues to decrease, resulting in higher overall computational efficiency than traditional methods based on static full graph search. The algorithm maintains polynomial time complexity while offering both high-quality solutions and scalable practical performance.

[0123] Third, this application innovatively decouples and tightly integrates "layered preprocessing" and "dynamic topology maintenance," making the algorithm logic clear and easy to extend. This application clearly distinguishes between static layered analysis (step (2), in (on) and dynamically execute updates (step (3), in The process is divided into two phases (upper and lower). This design makes the priority order calculation independent of the actual state movement, resulting in clearer logic. Simultaneously, during the dynamic execution phase, adjustments are made in real time. The removal of nodes reflects the physical constraint that "a position has been permanently occupied," ensuring that the algorithm model perfectly matches the physical reality of quantum hardware where a physical bit can only carry one logical bit at a time. This architecture provides a natural interface for integrating more hardware-aware optimizations; for example, it allows for optimization during initialization. Known error bits or low-fidelity links can be directly masked, thus ensuring that the generated splicing scheme is not only logically correct but also physically more reliable.

[0124] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0125] Based on the same inventive concept, this application also provides a quantum circuit block splicing device for implementing the above-described quantum circuit block splicing method. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations of the one or more quantum circuit block splicing device embodiments provided below can be found in the limitations of the quantum circuit block splicing method described above, and will not be repeated here.

[0126] In one exemplary embodiment, such as Figure 3 As shown, a quantum circuit inter-block splicing device is provided, including: a state acquisition module 301, a layering module 302, an exchange module 303, and an inter-block circuit generation module 304, wherein:

[0127] The state acquisition module 301 is used to determine the current state of each physical node based on the termination physical configuration of the previous quantum logic block, and to determine the target state of each physical node based on the starting physical configuration of the current quantum logic block.

[0128] The layering module 302 is used to perform node layering preprocessing based on the hardware topology diagram corresponding to each physical node, and generate each node layer. The hardware topology diagram is a complete copy of the hardware topology corresponding to each physical node.

[0129] The switching module 303 is used to process each physical node in each node layer in the order of node layering. For the current physical node, if the current state of the current physical node is inconsistent with the target state, the source physical node corresponding to the target state is located, the path from the source physical node to the current physical node is searched on the hardware topology graph, the switching operation sequence is generated based on the path, the current state of each physical node is updated based on the switching operation sequence, and the current physical node and its associated edges are deleted from the hardware topology graph.

[0130] Inter-block circuit generation module 304 is used to generate inter-block spliced ​​quantum circuit segments based on the exchange operation sequence.

[0131] In some optional embodiments, the above-mentioned exchange module 303 is further configured to delete the current physical node and its associated edges from the hardware topology graph when the current state of the current physical node is consistent with the target state.

[0132] In some optional embodiments, the layering module 302 is further configured to generate temporary copies based on the hardware topology corresponding to each physical node; determine candidate physical nodes based on the degree of each physical node in the temporary copy; determine the candidate physical nodes in the temporary copy that satisfy the condition of unchanged connectivity after deletion as target physical nodes, wherein the condition of unchanged connectivity after deletion is that the temporary copy remains connected after deleting the candidate physical nodes and the edges corresponding to the candidate physical nodes; generate the current node layering based on each target physical node; delete each target physical node and the edges corresponding to each target physical node in the current node layering from the temporary copy, and continue to execute the step of determining candidate physical nodes based on the degree of each physical node in the temporary copy, until the temporary copy is empty, and generate each node layering.

[0133] In some optional embodiments, the layering module 302 is further configured to calculate the number of edges currently connected to each physical node in the temporary replica; use the number of edges as the degree of each physical node; and determine the physical node with the smallest degree as a candidate physical node.

[0134] In some optional embodiments, the above-mentioned switching module 303 is further configured to perform a breadth-first search on the hardware topology graph with the source physical node as the starting point and the current physical node as the ending point to obtain the path from the source physical node to the current physical node; and to sequentially exchange the logical bits on each pair of adjacent physical nodes in the path in the order from the starting point to the ending point, and to record the pair of physical nodes in the switching operation sequence after each pair of physical nodes is exchanged.

[0135] In some optional embodiments, the above apparatus further includes: a configuration module for dividing the quantum circuit into multiple consecutive logic blocks in chronological order, each logic block being a sub-circuit containing a series of quantum gate operations; performing quantum bit mapping and routing optimization on each logic block, and assigning an initial physical configuration to each logic block; and obtaining an executable physical circuit and a termination physical configuration after each logic block is executed by inserting swap gates in each logic block to make the two-qubit gates in each logic block satisfy the nearest neighbor constraint of the hardware topology graph.

[0136] Each module in the aforementioned quantum circuit block splicing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0137] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When executed by the processor, the computer program implements a quantum circuit block splicing method. The display unit is used to form a visually visible image and can be a display screen, projection device, or virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0138] Those skilled in the art will understand that Figure 4The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0139] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0140] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0141] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0142] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0143] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0144] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0145] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for splicing quantum circuit blocks, characterized in that, The method includes: The current state of each physical node is determined based on the termination physical configuration of the previous quantum logic block, and the target state of each physical node is determined based on the starting physical configuration of the current quantum logic block. Based on the hardware topology diagram corresponding to each physical node, node layering preprocessing is performed to generate each node layer. The hardware topology diagram is a complete copy of the hardware topology corresponding to each physical node. Each physical node in each node layer is processed sequentially according to the order of the node layering. For the current physical node, if the current state of the current physical node is inconsistent with the target state, the source physical node corresponding to the target state is located, a path from the source physical node to the current physical node is searched on the hardware topology graph, a swap operation sequence is generated based on the path, the current state of each physical node is updated based on the swap operation sequence, and the current physical node and its associated edge are deleted from the hardware topology graph. Based on the exchange operation sequence, inter-block splicing quantum circuit segments are generated.

2. The method according to claim 1, characterized in that, The method further includes: If the current state of the current physical node is consistent with the target state, the current physical node and its associated edges are deleted from the hardware topology graph.

3. The method according to claim 1, characterized in that, The node layering preprocessing based on the hardware topology diagram corresponding to each physical node to generate each node layer includes: A temporary copy is generated based on the hardware topology corresponding to each physical node; Candidate physical nodes are determined based on the degree of each physical node in the temporary replica; Candidate physical nodes in the temporary copy that satisfy the condition of unchanged connectivity after deletion are determined as target physical nodes. The condition of unchanged connectivity after deletion means that after deleting the candidate physical node and the edge corresponding to the candidate physical node from the temporary copy, the temporary copy remains connected. The current node hierarchy is generated based on each target physical node. Remove each target physical node and the edge corresponding to each target physical node from the temporary copy, and continue to execute the step of determining candidate physical nodes based on the degree of each physical node in the temporary copy until the temporary copy is empty, and generate each node layer.

4. The method according to claim 3, characterized in that, The process of determining candidate physical nodes based on the degree of each physical node in the temporary replica includes: Calculate the number of edges currently connected to each physical node in the temporary replica; The number of each edge is taken as the degree of each physical node; The physical node with the smallest degree is determined as the candidate physical node.

5. The method according to any one of claims 1 to 4, characterized in that, The step of searching for a path from the source physical node to the current physical node on the hardware topology graph and generating a sequence of switching operations based on the path includes: Starting from the source physical node and ending at the current physical node, a breadth-first search is performed on the hardware topology graph to obtain the path from the source physical node to the current physical node. According to the path from the starting point to the ending point, the logical bits on each pair of adjacent physical nodes in the path are swapped in sequence. After each pair of physical nodes is swapped, the pair of physical nodes is recorded in the swap operation sequence.

6. The method according to any one of claims 1 to 4, characterized in that, Before determining the current state of each physical node based on the termination physical configuration of the previous quantum logic block, and determining the target state of each physical node based on the starting physical configuration of the current quantum logic block, the process includes: The quantum circuit is divided into multiple consecutive logic blocks in chronological order, and each logic block is a sub-circuit containing a series of quantum gate operations; Perform qubit mapping and routing optimization on each of the logic blocks, and assign an initial physical configuration to each of the logic blocks; By inserting swap gates into each of the logic blocks, the two-qubit gates in each logic block satisfy the nearest neighbor constraint of the hardware topology graph, thereby obtaining an executable physical circuit and the termination physical configuration after each logic block is executed.

7. A quantum circuit block splicing device, characterized in that, The device includes: The state acquisition module is used to determine the current state of each physical node based on the termination physical configuration of the previous quantum logic block, and to determine the target state of each physical node based on the starting physical configuration of the current quantum logic block. The layering module is used to perform node layering preprocessing based on the hardware topology diagram corresponding to each physical node, and generate each node layer. The hardware topology diagram is a complete copy of the hardware topology corresponding to each physical node. The switching module is used to process each physical node in each node layer in the order of the node layering. For the current physical node, if the current state of the current physical node is inconsistent with the target state, the source physical node corresponding to the target state is located, a path from the source physical node to the current physical node is searched on the hardware topology graph, a switching operation sequence is generated based on the path, the current state of each physical node is updated based on the switching operation sequence, and the current physical node and its associated edge are deleted from the hardware topology graph. The inter-block circuit generation module is used to generate inter-block spliced ​​quantum circuit segments based on the exchange operation sequence.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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