Real-time online identification method of pixel detector cluster response

Abstract

The application provides a pixel detector cluster response real-time online identification method, which comprises receiving a pixel data stream, assigning a current frame to an idle core in a plurality of parallel processing cores; in the assigned core, performing background suppression, connected marking with a stroke as a granularity and temporary label assignment on the pixel data stream of the current frame, and performing label merging and compression to generate cluster data; arbitrating and merging the cluster data output by each core and outputting after bit width conversion; when any core completes the processing of the current frame and the output cache queue is empty, if there is unaligned residual data in the bit width conversion, the unaligned residual data is aligned to the target bit width by zero padding and then output. Thus, under the condition of not relying on external memory for whole frame buffering, high frame rate real-time processing is realized, and problems such as large label propagation overhead, limited throughput, high output bandwidth, easy tail misalignment or arbitration waiting deadlock in multi-core output integration, and the like, of pixel-level connected marking under complex target shape are solved.

Description

Technical Field

[0001] This invention relates to the field of high-speed image data stream processing technology, and in particular to a real-time online identification method for pixel detector cluster response. Background Technology

[0002] In applications such as high-energy physics detection, radiation imaging, time projection chamber readout, X-ray / gamma-ray imaging, and industrial non-destructive testing, pixel detectors typically output two-dimensional array pixel data at high frame rates. In practical applications, the detection signal often manifests as several spatially adjacent or connected pixel clusters. However, background noise, dark current, readout noise, and channel gain differences introduce a large number of low-amplitude pixels, resulting in a large amount of data per frame and a low proportion of effective information.

[0003] Existing cluster recognition schemes mostly employ software-based batch processing or general image connected component algorithms. Typical problems include: large processing latency under high-speed continuous frame input conditions, making it difficult to achieve online triggering; high computational complexity and storage overhead due to pixel-by-pixel scanning and connected component merging of the entire frame; and problems such as limited throughput or packet errors and loss at the end of the data when parallel processing is required. Summary of the Invention

[0004] This invention provides a real-time online identification method for pixel detector cluster response, which solves the problem that the existing technology cannot achieve real-time online cluster identification and compression output of high-speed frame data streams under the premise of controllable hardware resources, and cannot improve the data link load and meet the requirements of online processing and real-time triggering.

[0005] This invention provides a real-time online identification method for pixel detector cluster response, comprising: Receives a pixel data stream synchronized frame by frame, and allocates the current frame to one of the idle cores among multiple parallel processing cores in units of complete frames; Within the allocated core, background suppression, run-length granularity of connectivity markers and temporary labels are assigned to the pixel data stream of the current frame, and label-based merging and compression are performed to generate clustered data. Each core is configured with an independent output buffer queue. The cluster data output by each core is arbitrated, merged, and converted in bit width before being output. When any core finishes processing the current frame and the output buffer queue is empty, if there is unaligned residual data in the bit width conversion, it is padded with zeros to align to the target bit width before being output.

[0006] According to the present invention, a real-time online identification method for pixel detector cluster response is provided, wherein the background suppression includes: Generate a memory read address based on the row and column coordinates of the current pixel, and read the corresponding background statistics parameters from the pre-stored background statistics parameter memory; The background statistical parameters are combined with configurable coefficients to generate an adaptive threshold; If the current pixel value exceeds the adaptive threshold, the current pixel value and address information are output as valid pixels to form a sparse pixel stream.

[0007] The real-time online identification method for pixel detector cluster response provided by the present invention further includes using two row buffers with a capacity of N pixels for ping-pong switching: The sparse pixel stream is written into the first row buffer, and the complete pixel data of the previous row is read out from the second row buffer in column order to form a continuous row pixel stream; When the column count reaches N-1, the current row is written and the buffer is switched. The second row buffer is controlled to write the current row, and the first row buffer reads the next row.

[0008] According to the pixel detector cluster response real-time online identification method provided by the present invention, before the connectivity marker with travel granularity, it further includes: The valid pixels in the continuous row pixel stream are detected using a finite state machine; When a non-zero pixel is detected, the system enters the travel state and records the starting column coordinates; When a zero-value pixel or the end of a row is detected, the coordinates of the end column are recorded, and the output is a valid travel object including the row number, the coordinates of the start column, and the coordinates of the end column.

[0009] According to the present invention, a real-time online identification method for pixel detector cluster response is provided, wherein the tag-based merging and compression includes: Expand the run objects with assigned temporary labels into a labeled pixel stream by the start and end column coordinates; Pixels with the same label and consecutive column coordinates in the same row number in the labeled pixel stream are merged to generate a compressed coordinate segment. The compressed coordinate segment includes at least the starting column coordinates, the ending column coordinates, the row number, and the segment length.

[0010] According to the pixel detector cluster response real-time online identification method provided by the present invention, before the zero-padding and alignment to the target bit width and output, the method further includes: Latch the frame processing completion signals of each core; After the signal latch is completed, the output buffer queue corresponding to the core is checked for empty queue. When it is determined that the output buffer queue is empty and there is still unaligned residual data in the bit-width splicing buffer, zeros are padded to the bit-width splicing buffer to the target bit width before splicing output is triggered.

[0011] According to the present invention, a real-time online identification method for pixel detector cluster response is provided, wherein allocating the current frame to an idle core among multiple parallel processing cores on a complete frame basis includes: After detecting the frame header, a core that is currently idle is selected by polling based on the busy / idle status of each parallel processing core. If there are no free cores, the current frame is discarded and a frame drop flag and / or a statistical count are output.

[0012] According to the present invention, a real-time online identification method for pixel detector cluster response is provided, wherein the cluster data is encapsulated in a structured data packet, and the data packet includes at least a frame header, a cluster data area, a connectivity record area, and a frame tail; The frame header includes a synchronization word and a frame sequence number; the cluster data area includes labels, coordinate segments, and energy information for one or more clusters; the connectivity record area includes connectivity records; and the frame tail contains an end marker.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the real-time online identification method for pixel detector cluster response as described above.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the real-time online identification method for pixel detector cluster response as described above.

[0015] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the real-time online identification method for pixel detector cluster response as described above.

[0016] This invention provides a real-time online identification method for pixel detector cluster response. By allocating complete frames to different cores for parallel processing through frame-level multi-core scheduling, it ensures consistency in intra-frame cluster identification. An independent output buffer queue is set up for each core, and a zero-padding alignment mechanism ensures that the output data packets of each core end completely at word boundaries, fundamentally avoiding tail misalignment and arbitration deadlock during multi-core output integration, significantly improving system stability and throughput. Within a single core, connected component analysis is performed at the run-length level, avoiding the logical complexity caused by pixel-level label propagation. Combined with background suppression and coordinate compression, it effectively reduces output data bandwidth, meeting the real-time online processing requirements of the pixel detector front-end. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the real-time online identification method for pixel detector cluster response provided by the present invention; Figure 2 This is a structural diagram of the background suppression and line-by-line output module provided by the present invention; Figure 3 This is a diagram illustrating the travel coding data structure and coding example provided by the present invention; Figure 4 This is a flowchart of the inter-line connectivity determination and label allocation provided by the present invention; Figure 5 This is a schematic diagram of the label equivalence relation processing provided by the present invention; Figure 6 This is a flowchart of the stroke expansion and cluster coordinate compression provided by the present invention; Figure 7 This is a hierarchical diagram of the cluster data packet encapsulation and transmission structure provided by the present invention; Figure 8 This is a schematic diagram of multi-core parallel frame-level scheduling and output integration provided by the present invention; Figure 9 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0020] Example like Figure 1 and Figure 8As shown in the figure, this embodiment provides a real-time online clustering response method for pixel detectors. Facing the frame-synchronized two-dimensional array pixel data stream output by the pixel detector, background suppression, run-length encoding, connectivity marking, compression and packaging, multi-core scheduling, and output integration are performed in a streaming manner on an FPGA (Field Programmable Gate Array). No external memory is required for full-frame buffering, enabling high-frame-rate real-time clustering recognition. The method mainly includes the following steps: 101. Receive the pixel data stream synchronized frame by frame, and allocate the current frame to one of the idle cores among multiple parallel processing cores in units of complete frames.

[0021] Specifically, the system receives the frame-by-frame synchronized pixel data stream output by the pixel detector. Using the complete frame as the smallest allocation unit, after detecting the frame header flag, it queries the busy / idle status of multiple parallel processing cores and allocates the entire current frame to an idle core. Throughout frame processing, splitting the same frame data into different cores is prohibited to ensure consistency between intra-frame cluster identification and label relationships. This avoids cluster breakage and label misalignment caused by cross-core processing of intra-frame data, ensuring the integrity of cluster identification.

[0022] 102. Within the allocated core, perform background suppression, assign connectivity markers and temporary labels at the run-length granularity, and merge and compress the pixel data stream of the current frame to generate clustered data.

[0023] Specifically, the core of the allocated frame performs background suppression, allocates connectivity markers and temporary labels at the run-length level, and merges and compresses the current frame's pixel data stream using a pipelined streaming process throughout, eliminating the overhead of whole-frame buffering and ultimately generating standardized clustered data. Single-core streaming processing reduces hardware resource consumption and ensures real-time processing of single frames.

[0024] 103. Configure an independent output buffer queue for each core, and perform arbitration merging and bit-width conversion on the cluster data output by each core before outputting.

[0025] Specifically, such as Figure 8 As shown, each parallel processing core is configured with an independent output buffer queue, such as a FIFO. Clustered data processed by each core is first written to its own buffer to avoid output interference between cores. A round-robin arbitration method is used to merge the output buffer queues of multiple cores, with configurable output time slices and maximum consecutive output word limits, achieving orderly integration of multi-core output. Independent caching avoids data conflicts, and round-robin arbitration improves output throughput efficiency.

[0026] When any core completes the processing of the current frame and the output buffer queue is empty, if there is unaligned residual data in the bit width conversion, it is padded with zeros to align to the target bit width before output.

[0027] like Figure 8 As shown, the clustered data after arbitration and merging undergoes bit-width conversion. When any core completes processing the current frame and the output buffer queue is empty, if there is unaligned residual data in the bit-width conversion module, it is directly padded with zeros to align to the target bit width and then output immediately. The integrated output data packet is further marked with validity information and generated with verification information before being output to the downstream interface or storage module. This fundamentally avoids the problems of data packet tail misalignment and arbitration state machine deadlock during multi-core output integration, thus improving system stability.

[0028] Example 2 Furthermore, based on the above embodiments, background suppression in this embodiment includes: generating a memory read address based on the row and column coordinates of the current pixel, reading the corresponding background statistical parameters from the pre-stored background statistical parameter memory; combining the background statistical parameters with configurable coefficients to generate an adaptive threshold; if the current pixel value exceeds the adaptive threshold, outputting the current pixel value and address information as a valid pixel to form a sparse pixel stream.

[0029] Specifically, such as Figure 2 As shown, the figure includes a frame synchronization input interface module 201, a background parameter storage module 202, an adaptive threshold suppression module 203, and a row-by-row recombination and row buffering module 204. Based on the row and column coordinates of the current input pixel, the read address of the background statistical parameter memory is generated according to formula (1): addr = row × N + col (1) Where row is the row number, col is the column number, and N is the number of columns in the pixel array.

[0030] The background statistical parameters corresponding to the pixel location are read from the pre-stored dual-port background statistical parameter memory, including at least the background mean μ(x,y), background standard deviation σ(x,y), or equivalent discrete statistics. The dual-port memory supports writing during the background acquisition stage and reading during the processing stage without read / write conflicts, ensuring stable parameter reading timing, accurately matching the background parameters of each pixel, and providing a data foundation for adaptive thresholding.

[0031] The adaptive threshold suppression module 203 combines the read background statistical parameters with the configurable multiplier coefficient K to generate a pixel-level adaptive threshold according to formula (2): T(x,y)=μ(x,y)+K·σ(x,y) (2) Where K is a configurable multiplier, μ(x,y) is the background mean, and σ(x,y) is the background standard deviation.

[0032] The adaptive threshold can be flexibly configured with coefficient K according to the application scenario. The adaptive threshold can replace the fixed threshold and adaptively suppress background noise, dark current and readout noise at different pixel positions.

[0033] Compare the current pixel value P(x,y) with the adaptive threshold T(x,y): If P(x,y)>T(x,y), it is determined to be a valid pixel, and the pixel value and row and column address information are output.

[0034] If P(x,y)≤T(x,y), it is determined to be background noise, zero value is output and valid flags are masked, and finally a sparse pixel stream containing only valid signals is formed.

[0035] Adaptive threshold suppression employs a three-stage pipeline structure: address generation and read request, background parameter reading and pixel alignment buffering, and threshold calculation and comparison output. It processes one pixel per clock cycle, maintaining alignment between the output valid flag and the pixel data. By eliminating invalid background data, it significantly reduces the amount of data and bandwidth pressure in subsequent processing.

[0036] Example 3 Furthermore, based on the above embodiments, this embodiment also includes ping-pong switching using two row buffers with a capacity of N pixels: the sparse pixel stream is written to the first row buffer, and the complete pixel data of the previous row is read from the second row buffer in column order to form a continuous row pixel stream; when the column count reaches N-1, the current row is written and the buffer is switched, the second row buffer is controlled to write the current row, and the first row buffer reads the next row.

[0037] Specifically, such as Figure 2 As shown, the row-by-row recombination and row buffering module 204 employs two row buffers, each with a capacity of N (the total number of pixels in a single column), forming a ping-pong buffer structure. The two buffers are read and written independently without interference. The generated sparse pixel stream is written to the first row buffer, while simultaneously, the complete pixel data of the previous row is read from the second row buffer sequentially from column addresses 0 to N-1, forming a continuous row pixel stream. When the column count reaches N-1, it is determined that the current row has been written, and the read / write states of the two buffers are immediately switched. The first row buffer, which was previously writing, becomes the read state, and the second row buffer, which was previously reading, becomes the write state. This cycle continues, providing stable row-by-row output without interrupting input, providing a continuous row pixel stream for run-length encoding and inter-row connectivity determination, without input interruption.

[0038] Example 4 Furthermore, based on the above embodiments, this embodiment further includes the following steps before the connectivity marker with travel granularity: detecting valid pixels in a continuous row pixel stream using a finite state machine; entering a travel state and recording the starting column coordinates when a non-zero pixel is detected; recording the ending column coordinates when a zero-value pixel or the end of a row is detected, and outputting a valid travel object including the row number, starting column coordinates, and ending column coordinates.

[0039] Specifically, such as Figure 3 As shown, a finite state machine is used to perform travel encoding. The state machine includes at least two working states: an idle state and a travel state. The state machine performs real-time detection on the output continuous row pixel stream. When a non-zero valid pixel is detected, the state machine switches from the idle state to the travel state and records the starting column coordinates of the current valid pixel. When an invalid pixel with a zero value or a row end marker is detected, record the coordinates of the last column. The state machine switches back to idle and outputs a valid travel object. A valid travel object must contain at least the row number *r* and the starting column coordinate. End column coordinates The validity flag is set, and a label field can be reserved for later assignment. By compressing consecutive valid pixels into a run-length object, the processing is changed from pixel-level to run-length-level, reducing the complexity of connectivity determination.

[0040] Example 5 Furthermore, based on the above embodiments, this embodiment assigns connectivity markers and temporary labels at the process level, including: performing inter-process connectivity judgment on the process object of the current line and the cached upstream process object; if the current process is not connected to any process in the previous line, then assigning a new label; if the current process is only connected to a single process in the previous line, then inheriting the label of the single process in the previous line; if the current process is connected to multiple processes with different labels in the previous line, then assigning a representative label to the current process and outputting the connectivity relationship record between the representative label and the connected label.

[0041] Specifically, such as Figure 4 The diagram shown is a flowchart of the interline connectivity determination and label assignment process. Figure 5 The diagram illustrates the label equivalence relation processing. All valid process objects and label information from the previous row are cached. The process objects in the current row are compared with those in the previous row using a process interval-level inter-row connectivity check, without performing pixel-level point-by-point label propagation, thus reducing logical complexity and storage access overhead. Based on the connectivity check result, temporary labels are allocated in three ways: (a) The current trip is not connected to any trips in the previous row, so assign a new label to the current trip; (b) The current trip is connected to only one trip in the previous row, and the current trip inherits the tag of that trip; (c) The current process is connected to multiple processes with different labels in the previous line. Assign a representative label to the current process, selecting it according to the label number priority or arrival order priority. At the same time, output the connection relationship record between the representative label and each connected label, that is, the equivalent label pair in the form of a tuple [label_a, label_b].

[0042] The connectivity record is output uniformly before the end of the frame in the form of a data stream. Path compression or root tag mapping table generation is not performed within the FPGA; instead, the receiving end performs a lookup and merging process. Run-time tag allocation avoids the logical and timing pressure of pixel-level tag propagation, and the connectivity record provides the basis for tag merging.

[0043] Example 6 Furthermore, based on the above embodiments, this embodiment performs inter-row connectivity determination, including: under the four-connectivity criterion, when the column interval of the current journey overlaps with the column interval of the previous row journey, it is determined to be connected; or, under the eight-connectivity criterion, when the column interval of the current journey overlaps with or is adjacent to the column interval of the previous row journey, it is determined to be connected.

[0044] Specifically, such as Figure 4 As shown, connectivity criterion 401 offers two selection methods: 4-connectivity criterion and 8-connectivity criterion. The appropriate method can be chosen based on the application scenario. Four-connectivity criterion: such as Figure 4 As shown, the current travel column range [ , [and the previous travel interval] , ]satisfy ≤ and ≥ When intervals overlap, the area is considered connected. Eight-connectivity criterion: such as Figure 4 As shown, the current travel column range [ , [and the previous travel interval] , ]satisfy ≤ +1 and +1≥ When intervals overlap or are adjacent, they are considered connected.

[0045] Two connectivity rules are adapted to pixel clusters of different shapes, improving the applicability of cluster recognition.

[0046] Example 7 Furthermore, based on the above embodiments, this embodiment of merging and compressing by label includes: expanding the run objects with assigned temporary labels into a labeled pixel stream according to the start and end column coordinates; merging pixels with the same label and consecutive column coordinates in the same row number in the labeled pixel stream to generate a compressed coordinate segment, wherein the compressed coordinate segment includes at least the segment start column coordinate, the segment end column coordinate, the row number, and the segment length.

[0047] Specifically, such as Figure 6The diagram shows the flowchart for runout and cluster coordinate compression. A dual-buffer structure is used to synchronously store row pixel data and runout information. The row buffer stores pixel data, and the runout FIFO stores runout objects sequentially. After synchronous pairing by row number, the runout objects with assigned temporary tags are then sorted according to their starting column coordinates. End column coordinates Expand point by point, restoring a labeled pixel stream. Run-time expansion uses column counter streaming control, initialized to [value missing]. It outputs one pixel per clock cycle and increments the counter until... The process concludes without any risk of buffer overflow. Each pixel carries a cluster label, row and column coordinates, and pixel energy information; only valid pixels are output.

[0048] When merging and compressing within a row: group by label, use label switching as the cluster boundary, use a temporary storage mechanism to prevent the loss of the first pixel when switching labels, and classify pixels with the same label; for coordinate compression, merge pixels with the same label, the same row number, and consecutive column coordinates to generate compressed coordinate segments, and calculate the segment length according to formula (3); len=end_col-start_col+1 (3) The compressed coordinate segment must include at least the starting column coordinates, ending column coordinates, row number, and segment length, eliminating the need to output coordinates pixel by pixel; the energy sequence is packaged, and if the total number of energy sequences is even, it is output directly, while if it is odd, the last energy is padded with 0; it is implemented in a pipelined manner, with the compression detection completing the continuity judgment of one pixel every clock cycle, reducing the pressure on the critical path.

[0049] By using run-length expansion and inline merging compression, the amount of cluster coordinate data is significantly reduced, output bandwidth is decreased, and downstream modules can easily parse the data.

[0050] Example 8 Furthermore, based on the above embodiments, this embodiment further includes the following steps before outputting after zero-padding and alignment to the target bit width: latching the frame processing completion signal of each core; after latching the completion signal, performing an empty queue determination on the output buffer queue corresponding to the core; when it is determined that the output buffer queue is empty and there is still unaligned residual data in the bit width splicing buffer, zero-padding is performed on the bit width splicing buffer to the target bit width before triggering splicing output.

[0051] Specifically, such as Figure 8As shown, the output integration and bit-width conversion module monitors the working status of each parallel processing core in real time, latches the frame processing completion signal of each core, and marks the end of the current frame processing for the core. After the completion signal is latched, the output buffer queue corresponding to the core is immediately checked for emptiness to confirm that there is no data to be output in the queue. The bit-width splicing buffer output trigger conditions are: splicing to the target bit width, detecting the end of data packet marker, or the output buffer queue is empty and the completion signal has been latched. When it is determined that the output buffer queue is empty and there is still unaligned residual data in the bit-width splicing buffer, zeros are padded to the bit-width splicing buffer to the target bit width, and splicing output is immediately triggered to ensure that the data packet ends at the word boundary.

[0052] By precisely triggering the zero-padding operation, arbitration deadlocks and data packet misalignment caused by residual data are completely avoided.

[0053] Example 9 Furthermore, based on the above embodiments, this embodiment allocates the current frame to one of the multiple parallel processing cores as a whole frame, including: after detecting the frame header, selecting a currently idle core in a polling manner according to the busy / idle status of each parallel processing core; if there is no idle core, the current frame is discarded as a whole and a frame dropping flag and / or a statistical count is output.

[0054] Specifically, such as Figure 8 As shown, using a multi-core frame-level scheduling module, after detecting the frame header flag, the system polls the busy / idle status of all parallel processing cores, prioritizing the currently idle core to receive the current frame. If no idle core is found after polling, the system discards the entire frame, simultaneously outputting a dropped frame flag and / or a dropped frame count, without affecting the normal processing of subsequent frames. Polling scheduling balances the multi-core load, and whole-frame discarding avoids system stuttering caused by core blockage.

[0055] Example 10 Furthermore, based on the above embodiments, in this embodiment, the cluster data is encapsulated in a structured data packet, which includes at least a frame header, a cluster data area, a connectivity record area, and a frame tail; wherein, the frame header includes a synchronization word and a frame sequence number, the cluster data area includes labels, coordinate segments, and energy information of one or more clusters, the connectivity record area includes connectivity records, and the frame tail contains an end marker.

[0056] Specifically, such as Figure 7 The diagram shows the hierarchical structure of clustered data packet encapsulation and transmission. Clustered data generated by single-core processing is encapsulated in structured data packets, which contain four parts in a fixed order: Frame header: Contains synchronization word, frame sequence number or timestamp, used for downstream module unpacking and synchronization.

[0057] Cluster data area: encapsulated as [identifier header, tag number, number of run segments M, M] {segment start column coordinates, segment end column coordinates, row number, segment length}, M [len corresponding pixel energy sequences], where the energy sequence is defined as: The sequence 0:E0,0...len-1, sequence 1:E1,0...len-1... and sequence M-1:E0,0...len-1 contain the labels, compressed coordinate segments, and pixel energy information of one or more clusters, and are the core data of the clusters.

[0058] Connectivity record area: includes a list of equivalent label pairs / connected edges, for downstream modules to perform label merging and remarking.

[0059] End of frame: Contains a frame end identifier, marking the end of a single frame of data.

[0060] This solution is adaptable to different pixel widths, image dimensions, connectivity options, maximum number of runs per line, maximum number of clusters, and number of parallel cores. Background parameters can be provided by an external module and written to memory. The data packet format can be adjusted according to the downstream link protocol, including frame headers and trailers, field arrangement, and data bit width. The standardized data packet format facilitates downstream interface parsing, and connectivity records ensure the final accuracy of cluster tags, making it suitable for various application scenarios.

[0061] The scheme of this invention obtains pixel and row / column indices through frame synchronization input, reads pixel-level background statistical parameters and performs adaptive threshold suppression, and reassembles and buffers the output by row. Run-length encoding is performed on each row of valid pixels, and run-length granularity connectivity judgment and temporary label allocation are realized based on the overlap of adjacent run-length intervals, and label equivalence relation records are output. The run-length is expanded and continuous coordinates of the same label, row, and column are merged into compressed segments to generate cluster coordinates and energy statistics. Multi-core frame-level scheduling is used for parallel processing, and the output is integrated through FIFO. The cluster data is encapsulated into frame header—cluster data area—connectivity relation record area—frame tail, and the data packets output by each core are width-converted and integrated for output.

[0062] Background adaptive threshold suppression and sparsity are implemented in a streaming manner on FPGA to reduce the processing and output burden caused by invalid data; interline connectivity judgment and label assignment are performed at the granularity of run objects to avoid the logical and timing pressure caused by the point-to-point propagation of labels in pixel windows, which is suitable for complex shaped targets; output bandwidth is reduced and downstream parsing is facilitated by inline compression and structured data packet encapsulation; high-throughput parallel processing is achieved by using frame-level multi-core scheduling and configuring independent output buffer queues; bit-width splicing and zero-padding alignment mechanisms ensure that data packets end at word boundaries, avoiding deadlocks caused by tail misalignment and arbitration waiting, thereby improving system stability and engineering feasibility.

[0063] Figure 9 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 9 As shown, the electronic device may include: a processor 910, a communication interface 920, a memory 930, and a communication bus 940, wherein the processor 910, the communication interface 920, and the memory 930 communicate with each other through the communication bus 940. The processor 910 can call logical instructions in the memory 930 to execute a real-time online identification method for pixel detector cluster response. The method includes: receiving a pixel data stream synchronized frame by frame; allocating the current frame to an idle core among multiple parallel processing cores in units of complete frames; within the allocated core, performing background suppression, allocation of connectivity markers and temporary tags at the run-length granularity, and merging and compressing by tag on the pixel data stream of the current frame to generate cluster data; configuring an independent output buffer queue for each core, and arbitrarily merging and converting the cluster data output by each core before outputting it; wherein, when any core completes the processing of the current frame and the output buffer queue is empty, if there is unaligned residual data in the bit-width conversion, it is padded with zeros to align to the target bit width before outputting.

[0064] Furthermore, the logical instructions in the aforementioned memory 930 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0065] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the pixel detector cluster response real-time online identification method provided by the above methods. The method includes: receiving a pixel data stream synchronized frame by frame; allocating the current frame to an idle core among multiple parallel processing cores in units of complete frames; within the allocated core, performing background suppression, allocation of connectivity markers and temporary labels at the run-length granularity, and merging and compression by label on the pixel data stream of the current frame to generate cluster data; configuring an independent output buffer queue for each core, and arbitrarily merging and converting the cluster data output by each core before outputting it; wherein, when any core completes the processing of the current frame and the output buffer queue is empty, if there is unaligned residual data in the bit-width conversion, it is zeroed and aligned to the target bit width before outputting.

[0066] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements a real-time online identification method for pixel detector cluster response provided by the above methods. The method includes: receiving a pixel data stream synchronized frame by frame; allocating the current frame to an idle core among multiple parallel processing cores in units of complete frames; within the allocated core, performing background suppression, allocation of connectivity markers and temporary labels at the run-length granularity, and merging and compression by label on the pixel data stream of the current frame to generate cluster data; configuring an independent output buffer queue for each core, and arbitrarily merging and converting the cluster data output by each core before outputting it; wherein, when any core completes the processing of the current frame and the output buffer queue is empty, if there is unaligned residual data in the bit-width conversion, it is zero-padded and aligned to the target bit width before outputting.

[0067] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0068] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A real-time online identification method for pixel detector cluster response, characterized in that, include: Receives a pixel data stream synchronized frame by frame, and allocates the current frame to one of the idle cores among multiple parallel processing cores in units of complete frames; Within the allocated core, background suppression, run-length granularity of connectivity markers and temporary labels are assigned to the pixel data stream of the current frame, and label-based merging and compression are performed to generate clustered data. Each core is configured with an independent output buffer queue. The cluster data output by each core is arbitrated, merged, and converted in bit width before being output. When any core finishes processing the current frame and the output buffer queue is empty, if there is unaligned residual data in the bit width conversion, it is padded with zeros to align to the target bit width before being output.

2. The real-time online identification method for pixel detector cluster response according to claim 1, characterized in that, The background suppression includes: Generate a memory read address based on the row and column coordinates of the current pixel, and read the corresponding background statistics parameters from the pre-stored background statistics parameter memory; The background statistical parameters are combined with configurable coefficients to generate an adaptive threshold; If the current pixel value exceeds the adaptive threshold, the current pixel value and address information are output as valid pixels to form a sparse pixel stream.

3. The real-time online identification method for pixel detector cluster response according to claim 2, characterized in that, It also includes using two row buffers with a capacity of N pixels for ping-pong switching: The sparse pixel stream is written into the first row buffer, and the complete pixel data of the previous row is read out from the second row buffer in column order to form a continuous row pixel stream; When the column count reaches N-1, the current row is written and the buffer is switched. The second row buffer is controlled to write the current row, and the first row buffer reads the next row.

4. The real-time online identification method for pixel detector cluster response according to claim 3, characterized in that, Before the connectivity markers at the travel-level granularity, the following are also included: The valid pixels in the continuous row pixel stream are detected using a finite state machine; When a non-zero pixel is detected, the system enters the travel state and records the starting column coordinates; When a zero-value pixel or the end of a row is detected, the coordinates of the end column are recorded, and the output is a valid travel object including the row number, the coordinates of the start column, and the coordinates of the end column.

5. The real-time online identification method for pixel detector cluster response according to claim 1, characterized in that, The tag-based merging and compression includes: Expand the run objects with assigned temporary labels into a labeled pixel stream by the start and end column coordinates; Pixels with the same label and consecutive column coordinates in the same row number in the labeled pixel stream are merged to generate a compressed coordinate segment. The compressed coordinate segment includes at least the starting column coordinates, the ending column coordinates, the row number, and the segment length.

6. The real-time online identification method for pixel detector cluster response according to claim 1, characterized in that, Before the zero-padding and alignment to the target bit width are output, the process also includes: Latch the frame processing completion signals of each core; After the signal latch is completed, the output buffer queue corresponding to the core is checked for empty queue. When it is determined that the output buffer queue is empty and there is still unaligned residual data in the bit-width splicing buffer, zeros are padded to the bit-width splicing buffer to the target bit width before splicing output is triggered.

7. The real-time online identification method for pixel detector cluster response according to claim 1, characterized in that, The method of allocating the current frame to an idle core among multiple parallel processing cores on a complete frame basis includes: After detecting the frame header, a core that is currently idle is selected by polling based on the busy / idle status of each parallel processing core. If there are no free cores, the current frame is discarded and a frame drop flag and / or a statistical count are output.

8. The real-time online identification method for pixel detector cluster response according to any one of claims 1-7, characterized in that, The cluster data is encapsulated in structured data packets, which include at least a frame header, a cluster data area, a connectivity record area, and a frame tail. The frame header includes a synchronization word and a frame sequence number; the cluster data area includes labels, coordinate segments, and energy information for one or more clusters; the connectivity record area includes connectivity records; and the frame tail contains an end marker.

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