A PCB defect detection method, medium and system

Abstract

The application discloses a PCB defect detection method, medium and system, relates to the technical field of PCB defect detection, and comprises the following steps: acquiring PCB images and PCB three-dimensional coordinate data of a plurality of visual angles; generating a warping degree three-dimensional model based on the PCB three-dimensional coordinate data; correcting warping area images of the PCB images of the plurality of visual angles based on the warping degree three-dimensional model; fusing the corrected images to obtain a PCB three-dimensional visual image; performing preliminary inspection by adopting a target detection algorithm; if unqualified, outputting a preliminary inspection defect list; if qualified, performing internal defect and electrical performance collaborative detection to output a collaborative detection defect list; and rechecking each defect in the defect list to output a final detection result. The application eliminates the influence of plate deformation, and realizes high-precision full-coverage detection of surface defects, internal defects and electrical defects.

Description

Technical Field

[0001] This application relates to the field of PCB defect detection, and in particular to a PCB defect detection method, medium, and system. Background Technology

[0002] Printed Circuit Boards (PCBs) are core components of electronic products, and their quality directly determines the reliability, lifespan, and safety of the product. They are widely used in high-end fields such as 5G, artificial intelligence, new energy vehicles, and aerospace. With the iterative upgrading of related industries, PCBs continue to develop towards miniaturization, multilayering, and high density. Line widths and spacing have decreased from the 100μm level to the 10μm level, the number of layers has increased to over 20, and the minimum via diameter has decreased to 0.05mm. This development trend places extremely high demands on the accuracy, integrity, and stability of PCB defect detection.

[0003] Existing PCB defect detection technologies typically employ methods such as Automatic Optical Inspection (AOI) or X-ray inspection. However, in actual production, PCB boards often exhibit varying degrees of warping. Current technologies lack effective three-dimensional deformation compensation mechanisms when dealing with warped boards, leading to image stitching misalignment and distorted feature extraction, resulting in missed or false detections of minute defects. Furthermore, single-function surface optical inspection struggles to cover hidden defects such as internal delamination and missing copper in holes, while purely electrical testing cannot locate external flaws. There is a lack of a comprehensive inspection solution that spatially aligns and collaboratively determines surface optical information, internal structural information, and electrical performance information, resulting in insufficient inspection coverage and delayed feedback. Summary of the Invention

[0004] The purpose of this application is to provide a PCB defect detection method, medium, and system that can achieve full coverage detection of PCB surface, internal, and electrical performance defects through multi-view image acquisition and three-dimensional warp modeling. It solves the detection error problem caused by PCB deformation through three-dimensional warp modeling and geometric correction, reduces the false negative and false positive rates to extremely low levels through target detection and electrical dual verification, and achieves closed-loop production control through real-time result feedback.

[0005] To achieve the above objectives, this application provides the following solution: Firstly, this application provides a PCB defect detection method, including: Acquire PCB images and PCB 3D coordinate data from several perspectives; Based on the PCB three-dimensional coordinate data, a three-dimensional model of warpage is generated; Based on the aforementioned three-dimensional warp model, the warp region images of the PCB images from several viewpoints are corrected. The PCB images from several corrected perspectives are fused to obtain a 3D visualization image of the PCB. The PCB 3D visualization image is used to perform a preliminary inspection of the PCB appearance. If the preliminary inspection fails, a preliminary defect list is output. If the preliminary inspection passes, the PCB internal defects and electrical performance are jointly inspected, and a joint inspection defect list is output. Each defect in the initial defect list and the collaborative defect list is reviewed, and the final detection result is output.

[0006] Optionally, a three-dimensional model of warpage is generated based on the PCB three-dimensional coordinate data, specifically as follows: The PCB is divided into several grids; the PCB three-dimensional coordinate data includes the planar coordinates of each grid and the height data of each grid. Based on the planar coordinates of each grid on the PCB and the height data of the sampling points within each grid, a bicubic polynomial surface equation is constructed. The correction coefficients are obtained by solving the bicubic polynomial surface equation using the least squares method. Based on the correction coefficients, a continuous surface height field within the corresponding grid is generated by fitting a bicubic polynomial surface equation. By stitching together the continuous surface height fields of all meshes, the final three-dimensional model of warpage is obtained.

[0007] Optionally, the warped region images of the PCB images from the plurality of viewpoints are corrected, specifically as follows: For each viewpoint of the PCB image, based on the correction coefficients, the sub-pixel coordinates of the original distorted image are calculated using a pre-constructed set of bidirectional distortion mapping equations, using the reference plane pixel coordinates and corresponding height data of the PCB image. Bilinear interpolation is used to assign grayscale weighted values ​​to the original pixels surrounding the subpixel coordinates of the original distorted image, generating PCB images from several corrected perspectives.

[0008] Optionally, the expression for the bidirectional distortion mapping equation set is: in, The x-coordinate of the reference plane pixel coordinates of the PCB image; The ordinate of the reference plane pixel coordinates of the PCB image; Representing coordinates Corresponding height data; The x-coordinate represents the subpixel coordinates of the original distorted image; The ordinate represents the subpixel coordinates of the original distorted image; , , , , , and as well as , , , , , and All of these are correction coefficients.

[0009] Optionally, the fusion of the corrected PCB images from several viewpoints specifically involves: The PCB feature map is obtained by fusing features from several corrected PCB images from different viewpoints using an improved SIFT feature point matching algorithm. The PCB feature map is subjected to a weighted average fusion algorithm to perform pixel-by-pixel weighted fusion, resulting in a 3D visualization image of the PCB.

[0010] Optionally, the target detection algorithm employs an improved YOLOv8 model; the improved YOLOv8 model includes a backbone network, a feature enhancement module, and a detection layer; The backbone network includes Conv2Former modules and C2f modules; the Conv2Former modules and C2f modules are connected in series and stacked. The feature enhancement module is connected in series with the backbone network, and the feature enhancement module adopts dual-channel SimAM; The detection layer is connected in series with the feature enhancement module; the detection layer includes several detection heads of different sizes.

[0011] Optionally, the joint inspection of internal defects and electrical performance of the PCB specifically includes: The internal three-dimensional volume data of the PCB is reconstructed from the 3D visualization image of the PCB that has passed the initial inspection by using a filtered back projection algorithm to identify internal defects. The electrical characteristics of the PCB are tested using flying probes, and the flying probe test results are output. By aligning and fusing the internal defects with the results of the flying probe test in spatial coordinates, a collaborative defect detection list is obtained.

[0012] Optionally, each defect in the initial defect list and the collaborative defect list is reviewed, specifically as follows: For each defect in the initial defect list and the collaborative defect list, multi-dimensional features are extracted to generate a multi-dimensional feature vector; the multi-dimensional feature vector includes geometric features, texture features, grayscale features, edge gradient features, and frequency domain features; The multi-dimensional feature vectors are used to perform defect identification using a CNN model, and the defect type and verification confidence level are output. The defect type and verification confidence level are determined using the IPC standard, and the final detection result is output.

[0013] Secondly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the PCB defect detection method described in any one of the above descriptions.

[0014] Thirdly, this application provides a PCB defect detection system, comprising: The data acquisition module is used to acquire PCB images and PCB 3D coordinate data from several perspectives. The warpage model construction module generates a three-dimensional warpage model based on the PCB three-dimensional coordinate data. The warpage correction module is used to correct the warpage region images of the PCB images from several viewpoints based on the warpage three-dimensional model. The image fusion module is used to fuse PCB images from several corrected perspectives to obtain a 3D visualization image of the PCB. The defect detection module is used to perform a preliminary inspection of the PCB 3D visualization image using a target detection algorithm. If the preliminary inspection fails, a preliminary defect list is output; if the preliminary inspection passes, the PCB undergoes a collaborative inspection of internal defects and electrical performance, and a collaborative defect list is output. The defect verification module is used to verify each defect in the initial inspection defect list and the collaborative detection defect list, and output the final detection result.

[0015] According to the specific embodiments provided in this application, the following technical effects are disclosed: This application provides a PCB defect detection method, medium, and system. The method generates a 3D warpage model using PCB 3D coordinate data, accurately describing the 3D deformation characteristics of the PCB surface. Based on this model, it performs targeted correction on warped areas in multi-view images, effectively eliminating the interference of image distortion caused by PCB surface warping on the detection results. This correction process avoids missed and false detections of defects caused by surface deformation in traditional 2D inspection, significantly improving the quality of input images in subsequent inspection stages and laying a data foundation for high-precision defect identification.

[0016] By fusing PCB images corrected from several perspectives, the resulting 3D visualization image of the PCB contains more complete structural information about the PCB surface and interior. Multi-view fusion avoids the blind spots present in single-view inspection, allowing image information from different areas of the PCB to complement each other. This effectively solves the problem of missing local information caused by factors such as component occlusion and uneven lighting, thereby improving the coverage and comprehensiveness of the inspection.

[0017] A target detection algorithm is used to perform an initial inspection of the PCB's 3D visualization image, which can quickly screen out obvious surface visual defects and achieve preliminary defect location and classification. If the initial inspection is satisfactory, further collaborative inspection of internal defects and electrical performance is triggered, compensating for the limitations of pure visual inspection in detecting defects buried within the PCB (such as delamination, voids, cracks, etc.) and abnormal electrical performance (such as impedance deviation, poor continuity, etc.). This two-level architecture design balances inspection efficiency and inspection depth, avoiding the resource waste caused by performing complex inspection processes on all PCBs while ensuring comprehensive quality inspection of PCBs with high performance requirements.

[0018] After initial and collaborative inspections, each detected defect undergoes a further verification process. This verification mechanism can reconfirm suspected defect areas, eliminate false defects caused by image noise, algorithm misjudgments, and other factors, and supplement the identification of defects that may have been missed in the initial inspection. Through this verification process, the accuracy and reliability of the inspection results are significantly improved, the workload of manual review is reduced, and the overall level of PCB quality control is enhanced. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is an application environment diagram of a PCB defect detection method according to an embodiment of this application; Figure 2 This is a flowchart illustrating a PCB defect detection method according to an embodiment of this application. Figure 3 This is a schematic diagram of an improved YOLOv8 model structure according to an embodiment of this application; Figure 4 This is a flowchart illustrating the defect review and classification process according to an embodiment of this application; Figure 5 This is a schematic diagram of the architecture of a PCB defect detection system according to an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] The PCB defect detection method provided in this application embodiment can be applied to, for example... Figure 1In the application environment shown, terminal 102 (such as an industrial control computer, embedded vision inspection equipment, or intelligent inspection terminal) communicates with server 104 via a network. The data storage system can store the data that server 104 needs to process, such as historical inspection reports, 3D warpage models, defect review results, and production linkage feedback data. The data storage system can be set up independently, integrated into server 104, or placed in the cloud or on other servers. The inspection terminal 102 can send multi-view images and laser ranging data of the PCB to be inspected to the server 104. After receiving the multi-view images and laser ranging data of the PCB to be inspected, the server 104 performs geometric correction on the warped areas of the multi-view images based on the warp 3D model, and fuses the corrected multi-view images to obtain a 3D visualization image of the PCB. Then, the server uses an improved YOLOv8 model to perform preliminary defect inspection on the 3D visualization image of the PCB. If the preliminary inspection fails, a preliminary defect list is output. If the preliminary inspection passes, a collaborative inspection process of micro-focus X-ray inspection and flying probe testing is initiated, and a collaborative inspection defect list is output. Finally, a triple verification (multi-feature fusion, lightweight CNN verification, and IPC standard comparison) is performed on each defect in the preliminary inspection defect list and the collaborative inspection defect list, and the final inspection result is output. The server 104 can feed back the final inspection result to the inspection terminal 102, and simultaneously feed back the defect type, defect location, defect severity, and suggested process parameter adjustment values ​​to the production equipment in real time through the industrial Ethernet protocol to achieve production linkage control. In addition, in some embodiments, the PCB defect detection method can also be implemented by the server 104 or the detection terminal 102 alone. For example, the detection terminal 102 can directly perform multi-view image acquisition and warpage modeling on the PCB to be detected, thereby completing defect detection and verification processing. Alternatively, the server 104 can obtain multi-view images and laser ranging data of the PCB to be detected from the data storage system, and perform defect detection and verification processing on the PCB to be detected.

[0024] The inspection terminal 102 can be, but is not limited to, various industrial control computers, embedded vision inspection equipment, intelligent inspection terminals, desktop computers, laptops, industrial control computers, edge computing devices, etc. The server 104 can be implemented using a standalone server or a server cluster composed of multiple servers, or it can be a cloud server. The data storage system can be a relational database or a non-relational database, used to store data such as PCB numbers, production batch numbers, 3D warpage models, defect candidate lists, collaborative inspection defect lists, standardized inspection reports, and process parameter adjustment records.

[0025] In one exemplary embodiment, such as Figure 2As shown, a PCB defect detection method is provided. This method is executed by a computer device, specifically by a terminal or server alone, or by both a terminal and a server. In this embodiment, the method is applied to... Figure 1 Taking server 104 as an example, the explanation includes the following steps S1 to S6. Wherein: S1: Acquire PCB images and PCB 3D coordinate data from several perspectives.

[0026] In this step, the PCB to be inspected is fixed onto the vacuum adsorption stage of the inspection platform. The surface of the vacuum adsorption stage has adsorption holes; a vacuum pump generates negative pressure to adsorb and fix the PCB onto the stage surface, preventing displacement during inspection. PCB positioning can be achieved using a combination of visual positioning, mechanical positioning, and vacuum adsorption positioning. Visual positioning uses a positioning camera to collect edge feature points and positioning hole features of the PCB, calculating the PCB's rotation angle and translation. Mechanical positioning uses adjustable positioning pins that engage with the PCB's positioning holes to achieve precise positioning. Vacuum adsorption positioning uses the vacuum adsorption stage to firmly adhere the PCB to the stage surface, achieving final overall positioning.

[0027] After PCB positioning is completed, images of the PCB from several perspectives are acquired using a multi-view image acquisition module. This module may include at least four high-resolution CMOS industrial cameras, positioned at the top, left, right, and bottom of the PCB, respectively. Each camera is equipped with a telecentric lens and a ring-shaped shadowless light source. All cameras are simultaneously exposed via an external hardware-triggered synchronous trigger signal, enabling synchronized acquisition of multi-view images. Uniform illumination is provided by the ring-shaped shadowless light source to eliminate the impact of shadows on image quality.

[0028] Simultaneously, 3D coordinate data of the PCB is acquired via a laser rangefinder array. The laser rangefinder array consists of multiple phase-type laser rangefinders arranged in a grid above the PCB. Each laser rangefinder shares a hardware synchronization trigger signal with the CMOS industrial camera, achieving microsecond-level timing synchronization accuracy. The laser rangefinder array uses the vacuum adsorption stage plane as a unified XY reference plane, synchronously acquiring the coordinates of each grid on the PCB surface. Corresponding Z-axis height value Output discrete 3D height point cloud dataset P={( By pre-establishing the mapping relationship between image pixel coordinates and physical coordinates through camera calibration, the height value corresponding to each pixel is obtained by interpolation from the laser ranging data, and a three-dimensional imaging dataset containing RGB image and depth information is constructed.

[0029] Before image acquisition, a three-in-one dust removal device can optionally be used to clean the PCB surface to remove surface impurities that could interfere with detection. This device includes a high-pressure airflow nozzle, an electrostatic dust removal roller, and an ionizing air bar. The high-pressure airflow uses a pulsed blowing mode to blow large dust particles away from the PCB surface, the electrostatic dust removal roller removes fine dust particles through electrostatic adsorption, and the ionizing air bar generates positive and negative ions to neutralize the static electricity on the PCB surface, preventing secondary adsorption. Simultaneously, a semiconductor thermostat module can optionally control the PCB surface temperature to eliminate the impact of thermal expansion and contraction caused by temperature changes on warpage. The semiconductor thermostat module can employ multiple TEC thermoelectric coolers, combined with a PID control algorithm, to stabilize the PCB surface temperature within a set range.

[0030] S2 generates a 3D model of warpage based on PCB 3D coordinate data.

[0031] In this step, a 3D model of warpage is established based on the PCB 3D coordinate data obtained in step S1. The PCB surface is divided into several quadrilateral grids. The PCB 3D coordinate data includes the planar coordinates of each grid and the height data of the sampling points within each grid; specifically, the sampling points within each grid are generally selected from the four corner points and the densified points of that grid cell.

[0032] For each grid cell, discrete height measurement points at the four corners and the densification point, along with their corresponding planar coordinates, are taken to construct a bicubic polynomial surface equation. The densification point directly uses all original point cloud data from the laser rangefinder array falling within the large grid. The coefficients of this polynomial are solved using the least squares method, and these coefficients serve as correction coefficients for S3, yielding the continuous height field expression within a single grid cell. For each grid cell, the coordinates and height values ​​of the four corners and the densification point are substituted into the bicubic polynomial surface equation, and the polynomial coefficients are solved using the least squares method (e.g., singular value decomposition) to obtain the continuous height field within that grid cell. The local surface height fields of all grid cells are then smoothly stitched together. During stitching, the height values ​​and first-order partial derivatives of adjacent grid cells on the common boundary remain consistent to ensure the continuity and smoothness of the surface. This application eliminates boundary faults through global optimization, generating a globally continuous surface height field. This refers to the three-dimensional model of warpage. The height field of this continuous surface is a continuous function, and the physical coordinates of the PCB board surface can be arbitrarily input. Real-time output of corresponding warp height This allows for a complete characterization of the global bending, local unevenness, edge warping, and regional stress deformation distribution of the PCB.

[0033] S3, based on a three-dimensional warp model, corrects the warp region images of PCB images from several viewpoints.

[0034] In this step, the three-dimensional warpage model established in step S2 is used as a basis. Warp geometry correction is performed on the PCB images from several perspectives obtained in step S1 to eliminate image stretching, compression and deformation caused by PCB warping.

[0035] Specifically, the intrinsic parameters of each CMOS camera, the distortion coefficients of the telecentric lens, and the spatial pose calibration matrix between the camera and the PCB reference plane are pre-stored. The coordinates of the original distorted image after PCB warping and twisting are defined as follows: The standard calibration coordinates of the warp-free flat reference plane are ( ).

[0036] For each viewpoint of the PCB image, retrieve the coordinates ( The corresponding height value ( A two-way distortion mapping equation system, including a warp height term, is constructed to establish the mapping relationship between the standard corrected coordinates and the original distorted image coordinates. This mapping equation system is in second-order polynomial form. Specifically, after obtaining the correction coefficients by solving the bicubic polynomial surface equation using the least squares method, a reverse mapping strategy is adopted: traversing all standard coordinates of the corrected flattened image (…). The sub-pixel coordinates of the original distorted image are solved in reverse by using the bidirectional distortion mapping equation system. Finally, bilinear interpolation pairs () are used. The grayscale values ​​of the surrounding original pixels are weighted and assigned to generate a globally warped and standardized image.

[0037] After geometric correction, all multi-view images are uniformly mapped to the same flat reference plane, eliminating the geometric distortion caused by pixel stretching in the PCB protrusion area and pixel compression in the concave area, and providing a unified spatial reference for subsequent multi-view image fusion.

[0038] S4 fuses the PCB images from several corrected perspectives to obtain a 3D visualization image of the PCB.

[0039] In this step, the PCB images from several perspectives after correction in step S3 are fused together to obtain a unified spatial coordinate system 3D visualization image of the PCB.

[0040] First, the corrected PCB images from several viewpoints are precisely aligned using an improved SIFT (Scale-Invariant Feature Transform) feature point matching algorithm. The improved SIFT algorithm, based on the traditional SIFT, extracts SIFT feature descriptors in parallel at both the original high-resolution scale and the downsampled low-resolution scale, and then fuses these features to enhance the uniqueness of key points. In the matching stage, Euclidean distance is used as the feature similarity measure. A threshold based on the ratio of nearest neighbor to second nearest neighbor distances is used to filter coarsely matched point pairs. Then, the RANSAC (Random Sample Consensus) algorithm is used for multiple rounds of iterative random sampling to solve the homography transformation matrix. Mismatched points caused by warping or repeated textures are eliminated, and the homography matrix with the optimal number of interior points is retained, achieving pixel-level precise alignment of the multi-view images.

[0041] Then, a weighted average fusion algorithm is used to perform pixel-by-pixel weighted fusion on the aligned multi-view corrected images. The gray value of a single pixel in the fused image is the weighted average of the gray values ​​of the corresponding view images at that pixel and the corresponding total weight. The total weight of a single view is dynamically calculated in real time by three factors: sharpness weight, defect feature saliency weight, and view coverage weight. The sharpness weight is calculated based on the Laplacian gradient energy of the pixel neighborhood, prioritizing images with high sharpness; the defect feature saliency weight is obtained based on the defect probability output pixel by pixel by the pre-trained defect saliency detection network, prioritizing views with obvious defect features; the view coverage weight is assigned a two-dimensional Gaussian distribution with the center of the flat reference image as the origin to reduce the influence of image edge distortion.

[0042] The fusion process simultaneously retrieves the height data of the 3D warpage model W(x,y), and assigns additional compensation weights to the viewpoints of high warpage regions to compensate for the loss of defect information caused by single-viewpoint occlusion. After fusion, a 3D visualization image of the PCB is obtained with a unified spatial coordinate system, eliminating single-viewpoint occlusion and associating PCB warpage height information.

[0043] S5 uses a target detection algorithm to perform an initial inspection on the PCB 3D visualization image. If the initial inspection fails, a list of initial defects is output; if the initial inspection passes, the PCB undergoes a collaborative inspection of internal defects and electrical performance, and a list of collaboratively detected defects is output.

[0044] In this step, a target detection algorithm is first used to perform preliminary surface defect detection on the PCB 3D visualization image obtained in step S4. The target detection algorithm preferably uses an improved YOLOv8 model. The backbone network of the improved YOLOv8 model adopts a concatenated structure of Conv2Former and C2f modules. Conv2Former integrates traditional convolutional and Transformer structures, extracting local features through convolutional kernels and capturing global dependencies through a self-attention mechanism. The C2f module adds cross-stage feature fusion based on CSPNet to enhance feature reuse and gradient flow. The improved YOLOv8 model also introduces a dual-channel SimAM attention mechanism (including parallel spatial attention layers and channel attention layers), evaluating the importance of each neuron by calculating its energy function. The dual-channel design acts on the spatial and channel dimensions respectively. The detection layer of the improved YOLOv8 model removes the large target detection layer of the original YOLOv8 and adds two small target detection layers, forming a three-layer detection structure, corresponding to the detection of extremely small defects, micro-defects, and small defects, respectively. The loss function adopts the improved Focal-CIoU loss function, which introduces the Focal mechanism on the basis of CIoU loss to increase the weight of hard-to-classify samples.

[0045] The 3D visualization image of the PCB is input into the target detection algorithm for inference, and a defect candidate list is output. Each defect includes the defect type, bounding box coordinates, confidence level, and layer information. If the defect candidate list is not empty and there are defects with a confidence level higher than a set threshold, the initial inspection is deemed unqualified, the initial inspection defect list is directly output, and the PCB enters the subsequent review stage.

[0046] If the initial inspection is successful (i.e., the defect candidate list is empty or the confidence level of all defects is below the set threshold), the collaborative inspection process for internal defects and electrical performance is initiated. The collaborative inspection includes two parallel stages: microfocus X-ray inspection and flying probe testing.

[0047] In the microfocus X-ray inspection process, the X-ray tube voltage and current are automatically adjusted according to the PCB thickness and material density to initiate the CT scan. The X-ray source and detector rotate synchronously, or the PCB rotates, to acquire projection data from multiple angles. A filtered back-projection algorithm is used to reconstruct the three-dimensional volume data inside the PCB. Internal defects are detected from the reconstructed three-dimensional volume data, including but not limited to copper-free holes, interlayer bubbles, cracks, residual stress, open circuits in inner layers, and short circuits in inner layers.

[0048] In the flying probe testing phase, the coordinates of all test points and network topology are extracted from the PCB's CAD or Gerber data. Multiple moving probes, arranged symmetrically in a ring, move independently, simultaneously contacting multiple pairs of test points. Connectivity tests are performed to measure the resistance between two points to determine open or short circuits; impedance tests are performed to measure the characteristic impedance and compare it with the design value; insulation tests are performed by applying voltage between adjacent networks to measure leakage current, and the flying probe test results are output.

[0049] The X-ray inspection results and the flying needle test results are aligned and merged in spatial coordinates to form a collaborative defect list.

[0050] S6 verifies each defect in the initial inspection defect list and the collaborative inspection defect list, and outputs the final inspection result.

[0051] In this step, each defect candidate region in the initial defect list or collaborative defect list output in step S5 is subjected to triple kernel processing, including multi-feature fusion, lightweight CNN (convolutional neural network) verification, and IPC standard criterion comparison.

[0052] In the multi-feature fusion stage, multi-dimensional feature vectors are extracted for each defect candidate region. The extracted feature vectors include, but are not limited to, geometric features, texture features, grayscale features, edge gradient features, and frequency domain features. Geometric features include area, perimeter, aspect ratio, circularity, rectangularity, convex hull area ratio, principal axis direction angle, etc.; texture features are extracted using the gray-level co-occurrence matrix to obtain parameters such as energy, entropy, contrast, and correlation in four directions; grayscale features include grayscale mean, grayscale variance, skewness, kurtosis, grayscale entropy, etc.; edge gradient features include gradient magnitude mean, gradient magnitude variance, gradient direction histogram, etc.; frequency domain features include Fourier descriptor coefficients, wavelet energy proportion, and Gabor filter response.

[0053] In the lightweight CNN verification stage, the defect region image is input into the lightweight CNN verification model for secondary recognition. The lightweight CNN verification model preferably adopts the MobileNetV3 architecture, taking the defect region image as input and outputting the defect type and verification confidence score. By employing a transfer learning strategy, the model is initialized with pre-trained weights and fine-tuned on a PCB defect dataset in this field to improve its generalization ability.

[0054] In the IPC standard criterion comparison process, the verification results are compared item by item with the IPC standard criteria. These IPC standard criteria include, but are not limited to, IPC-A-600H, IPC-6012D, and IPC-9252 standards. Defect types include open circuits, short circuits, pad detachment, copper-free vias, bubbles, cracks, residual stress, foreign matter residue, trace depressions, trace bumps, insufficient etching, and via misalignment. Defect levels are classified according to IPC standards into Level 1 defects (within IPC acceptable limits), Level 2 defects (outside IPC acceptable limits but repairable), and Level 3 defects (unrepairable).

[0055] The system combines the results of multi-feature fusion, CNN verification, and IPC comparison for triple verification, outputting the final judgment result for each defect, including defect type, defect level, and processing suggestions. After all defects have been verified, the final detection result is output, including the total number of defects, statistics on the number of defects of each type, and detailed information for each defect.

[0056] By implementing steps S1 to S6 above, this application can achieve full coverage detection of PCB surface defects, internal defects, and electrical performance defects; solve the detection error problem caused by PCB deformation through three-dimensional modeling and geometric correction of warpage; enhance the detection capability of small targets by improving the YOLOv8 algorithm; achieve dual verification of structure and electrical properties through X-ray and flying probe collaborative detection; and reduce the false negative rate and false positive rate to an extremely low level through a triple kernel mechanism.

[0057] In an exemplary embodiment, after acquiring PCB images from several viewpoints, the PCB images are preprocessed. Specifically, a weighted grayscale algorithm is first used to assign weights based on the differences in human eye sensitivity to the red, green, and blue channels. ), converting a color image to a grayscale image, where , and Indicates the three channels: red, green, and yellow. , , Sensitivity weights are assigned; then, bicubic interpolation is used to normalize all images to a uniform size to meet the input requirements of subsequent batch processing and deep learning models; next, a dual filtering strategy is executed—first, a two-dimensional Gaussian kernel function is used to convolve with the image to suppress Gaussian noise, and then the median of the pixels in the window is sorted and median filtered to effectively remove salt-and-pepper noise; finally, CLAHE (Contrast Limiting Adaptive Histogram Equalization) is applied to divide the image into several small blocks and perform histogram equalization independently, while setting a cropping limit value to limit excessive contrast enhancement, and then bilinear interpolation is used to smooth the transition between the small blocks, thereby enhancing local details while maintaining overall visual naturalness.

[0058] In an exemplary embodiment, a three-dimensional warpage model is generated based on PCB three-dimensional coordinate data. Specifically, the PCB is divided into several grids; the PCB three-dimensional coordinate data includes the planar coordinates and height data of each grid; based on the height data of each grid, the surface height field within the corresponding grid is fitted using a hyperbolic polynomial surface equation; and the surface height fields of all grids are stitched together to obtain the final three-dimensional warpage model. Specifically, to accurately characterize the complex non-rigid deformation of the PCB surface, this embodiment employs a mesh modeling strategy. First, using the vacuum adsorption stage plane as a unified XY reference plane, the PCB surface is divided into several quadrilateral grid units. The grid size can be adaptively adjusted according to the PCB size and warpage rate; for example, the grid can be finer for areas with severe warpage. A laser rangefinder array synchronously collects the discrete height values ​​of the four corners or internal key points of each grid unit, forming a model containing... A 3D point cloud dataset was used. Based on this, for each mesh cell, a local bicubic polynomial surface equation was constructed using its corresponding discrete height measurement points. The polynomial coefficients were solved using the least squares method to obtain a continuous and smooth surface height field within that mesh. Subsequently, the surface height fields of all local mesh cells were smoothly stitched together to eliminate numerical discontinuities at adjacent mesh boundaries, ultimately generating a globally continuous and smooth 2D height field model. This model can fully characterize the global curvature, local bumps and depressions, edge warping, and regional deformation distribution caused by residual stress of a PCB, and can be used to input any physical coordinates of the PCB board surface. The model can then output the corresponding warp height in real time. This refined modeling approach based on physical measurements provides a high-precision spatial deformation benchmark for subsequent image geometric correction, fundamentally overcoming the limitation of traditional methods that can only handle simple barrel or pincushion distortions.

[0059] In an exemplary embodiment, the warped region images of PCB images from several viewpoints are corrected by: solving the bicubic polynomial surface equation using the least squares method to obtain correction coefficients; wherein the input of the least squares method is N discrete detection points within the grid. Typically, the four corner points and additional points are taken from the grid. The additional points are obtained by directly using all the original point cloud data of the laser rangefinder array that fall within the large grid. To ensure a good fit, N points are required. This means that at least 10 points are needed for the least squares method. The output objective is to solve for the correction coefficient vector. Make the curved surface The one with the smallest fitting error is as follows: The first step is to construct the design matrix, which expresses the bicubic polynomial in matrix form. Design matrix A's first... Behavior: Observation vector ,in These represent the warp heights at N detection points; The first The X and Y coordinates of each detection point.

[0060] The second step is to establish the normal equation, and the least squares solution satisfies: The third step is to solve for the coefficients and perform singular value decomposition on A. ,but: Where U is a left singular matrix, It is a singular value matrix. It is a right singular value matrix. The calculation method is to take the reciprocal of the non-zero singular values.

[0061] In actual calculations, small singular values ​​smaller than a threshold are removed and then set to 0 to avoid perturbation of the ill-conditioned matrix. The critical threshold uses a relative tolerance, as shown in the formula: in, It is the maximum singular value. It is the machine precision of floating-point numbers (approximately 1000 ppm in double precision). ), It is the matrix dimension (N is the number of detection points, usually dozens, much greater than 10, so N is sufficient). The fourth step is to output the surface equations. Substituting the obtained coefficients c back into the polynomial will yield the continuous height field within the mesh. .

[0062] For each viewpoint of the PCB image, based on the correction coefficients and the reference plane pixel coordinates and corresponding height data of the PCB image, the sub-pixel coordinates of the original distorted image are calculated using a pre-constructed bidirectional distortion mapping equation set. Bilinear interpolation is then used to perform grayscale weighted assignment on the original pixels surrounding the sub-pixel coordinates of the original distorted image, generating corrected PCB images from several viewpoints. Specifically, the geometric correction process employs a reverse mapping mechanism to ensure the integrity and continuity of the corrected images. The system first traverses each standard pixel coordinate on the corrected flat reference image. Retrieve the height value at the corresponding position in the aforementioned three-dimensional warp model. Substituting the values ​​into the bidirectional distortion mapping equations, the subpixel coordinates of the point in the original distorted image are obtained by solving inversely. Due to the calculated Since the coordinates are typically not integers, the system further employs a bilinear interpolation algorithm. This algorithm assigns a weighted value based on the grayscale values ​​of the four nearest-neighbor original pixels around the sub-pixel coordinate and their distance weights, thereby generating the pixel value of the corrected image at the standard coordinates. This combination of reverse mapping and sub-pixel interpolation effectively avoids pixel holes or overlaps in the corrected image that may occur with forward mapping. It also eliminates geometric distortions caused by pixel stretching in PCB protrusions and pixel compression in recessed areas, enabling multi-view images to be uniformly mapped to the same flat reference plane. This lays a geometrically consistent foundation for subsequent feature matching and fusion.

[0063] For example, the expression for the bidirectional distortion mapping equation system is as follows: in, The x-coordinate of the reference plane pixel coordinates of the PCB image; The ordinate of the reference plane pixel coordinates of the PCB image; Representing coordinates Corresponding height data; The x-coordinate represents the subpixel coordinates of the original distorted image; The ordinate represents the subpixel coordinates of the original distorted image; , , , , , and as well as , , , , , and All are correction coefficients. Specifically, this system of equations constructs a second-order polynomial bidirectional distortion mapping relationship that includes a warp height term. Where, to as well as to These 14 correction coefficients are not fixed constants, but dynamic parameters obtained by jointly fitting the 3D warpage model and camera calibration data using the least squares method. They integrate camera intrinsic parameters, telecentric lens distortion characteristics, and the spatial pose relationship between the camera and the PCB reference plane. Specifically, and Both methods directly couple the Z-axis height variation into the XY-plane coordinate mapping. This differs from traditional two-dimensional correction, which only considers... And its higher-order terms; this embodiment introduces a height term. As an independent variable participating in the mapping calculation, this allows the correction model to perceive and compensate for nonlinear perspective distortion caused by PCB 3D deformation. When there are significant undulations on the PCB surface, this term can effectively correct local magnification differences caused by changes in object distance, thereby achieving true 3D geometric correction. It should be understood that although this embodiment uses a second-order polynomial form, in other embodiments, depending on the complexity of the PCB deformation, higher-order polynomials or other suitable surface fitting functions can be used to construct this mapping relationship, as long as the coordinate mapping correction function based on height information can be achieved.

[0064] In an exemplary embodiment, the PCB images from several corrected viewpoints are fused. Specifically, the PCB images from several corrected viewpoints are fused using an improved Scale-Invariant Feature Transform (SIFT) feature point matching algorithm to obtain a PCB feature map. The PCB feature map is then fused pixel-by-pixel using a weighted average fusion algorithm to obtain a 3D visualization image of the PCB.

[0065] Specifically, although the geometric correction in the above embodiments eliminates macroscopic deformation, the PCB surface contains a large number of repetitive line textures and highly reflective areas, making it prone to mismatches by traditional feature matching algorithms. Therefore, this embodiment employs an improved SIFT feature point matching algorithm. First, 128-dimensional SIFT feature descriptors are extracted at both the original high-resolution scale and the downsampled low-resolution scale. These two sets of descriptors are then concatenated end-to-end to generate a 256-dimensional fused feature vector, enhancing the uniqueness of key points in areas with weak texture. During matching, Euclidean distance is used as the metric, and a threshold for the ratio of the nearest neighbor to the second nearest neighbor distance is set, for example, 0.7, to filter initial matching point pairs. Subsequently, the RANSAC (Random Sample Consensus) algorithm is introduced for multiple rounds of iterative random sampling. Based on the criterion that the reprojection error is less than a preset pixel value for interior points, the optimal homography transformation matrix is ​​fitted to eliminate mismatches. Finally, using this homography matrix, a reverse mapping combined with bilinear interpolation algorithm is employed to resample the images from each viewpoint to a unified reference plane coordinate system, achieving pixel-level alignment. This improved strategy effectively overcomes the interference of PCB-specific texture structures on feature matching, ensuring the accuracy of the fusion benchmark.

[0066] Furthermore, in order to generate a 3D visualization image of the PCB that combines texture details and depth information, this embodiment uses a weighted average fusion algorithm to perform pixel-by-pixel fusion on the aligned multi-view corrected images. The grayscale value of a single pixel in the fused image is the weighted average of the grayscale value of the corresponding view image at that location and the corresponding total weight. The total weight of a single view is dynamically calculated in real time by three factors: sharpness weight, defect feature saliency weight, and view coverage weight. Specifically, the sharpness weight is calculated based on the Laplacian gradient energy of the pixel neighborhood. This metric is sensitive to focus and unaffected by brightness variations caused by local unevenness of the PCB, ensuring that data from sharper images is prioritized. The defect feature saliency weight is determined by the defect attribution probability output pixel-by-pixel by a pre-trained defect saliency detection network, giving perspectives containing potential defect features greater weight in the fusion process and preventing the dilution of defect information during multi-view averaging. The perspective coverage weight constructs a two-dimensional Gaussian distribution with the center of the flat reference image as the origin to avoid the influence of edge field distortion. Simultaneously, it retrieves the height data of the three-dimensional warp model W(x,y) and automatically assigns additional compensation weights to highly warped areas to compensate for information loss caused by occlusion in a single perspective. Through the above multi-dimensional dynamic weighting mechanism, the final generated PCB 3D visualization image not only eliminates blind spots and overexposure artifacts from single perspectives but also implicitly associates the 3D height information of the PCB surface, providing high-quality, unambiguous input data for subsequent target detection algorithms and significantly improving the detection rate and positioning accuracy of minor defects. It should be understood that although this embodiment uses a weighted average fusion algorithm, in other embodiments, multi-band fusion or end-to-end fusion strategy based on deep learning can be selected according to computing resources and accuracy requirements, as long as multi-view information complementarity and three-dimensional visualization representation can be achieved.

[0067] In some exemplary embodiments, the target detection algorithm employs an improved YOLOv8 model; the improved YOLOv8 model includes a backbone network, a feature enhancement module, and a detection layer; the backbone network includes a Conv2Former module and a C2f module; the Conv2Former module and the C2f module are stacked after being concatenated; the feature enhancement module is concatenated with the backbone network, and the feature enhancement module adopts a dual-channel SimAM; the detection layer is concatenated with the feature enhancement layer; the detection layer includes several layers of detection heads at different scales.

[0068] Specifically, such as Figure 3As shown, this embodiment addresses the challenges of feature extraction and strong background interference in PCB defect detection, especially for minute defects. It specifically reconstructs the traditional YOLOv8 network. In the backbone network, a Conv module is stacked with two Conv2Former modules in series, and a C2f module is also stacked in series. The Conv2Former module combines the local feature extraction capabilities of traditional Convolutional Neural Networks (CNNs) with the global context awareness capabilities of Transformers. It captures local texture details such as PCB traces and pads through convolutional kernels, while simultaneously establishing long-distance dependencies using a self-attention mechanism. This effectively solves the feature confusion problem caused by complex trace routing and high similarity between defects and normal patterns in PCB images. The C2f module adds a cross-stage feature fusion path to the Cross-Stage Partial Network (CSPNet), enhancing gradient flow and feature reuse efficiency. This allows the network to extract richer multi-scale semantic information while maintaining a lightweight design. This stacked design balances the extraction of fine local features and global structural information, laying a solid feature foundation for subsequent minute defect identification.

[0069] Furthermore, the feature enhancement module employs a dual-channel Simple Parameter-free Attention Module (SimAM) mechanism, which is connected in series with the backbone network output. SimAM is an attention mechanism that requires no additional parameters. Its core lies in evaluating the importance of each neuron by calculating its energy function; the lower the energy, the more critical the information contained in that neuron. In this embodiment, the dual-channel design operates on the spatial and channel dimensions respectively, including parallel spatial attention channels and channel attention channels: the spatial channel energy function is used to locate the precise position of the defect region on the feature map and suppress the interference of background noise such as PCB substrate and solder mask; the channel energy function is used to filter feature channels that are sensitive to defects and enhance the response intensity of defect-related features. Compared with traditional attention modules such as SE-Net or CBAM that require learning parameters, SimAM achieves adaptive enhancement of minute defect features without increasing the number of model parameters or inference time, making it particularly suitable for online scenarios with extremely high real-time requirements in PCB inspection.

[0070] In terms of detection layer design, this embodiment reconstructs the original YOLOv8 detection head, removing the detection layer designed for large targets and adding two new detection layers specifically for small targets, ultimately forming a structure containing three detection heads of different scales. Specifically, the feature map size of the first newly added detection layer is 320×320, corresponding to the original... Figure 4 The first detection layer has a receptive field of 4 pixels, specifically designed to detect micro-defects ranging from 10×10 to 20×20 pixels, such as minute scratches and pinholes. The second detection layer, with a feature map size of 160×160 pixels (corresponding to the original image's 8×8 pixel receptive field), is used to detect extremely small defects of 10×10 pixels or less, such as tiny foreign objects and etching residues. The third detection layer, with a feature map size of 80×80 pixels (corresponding to the original image's 16×16 pixel receptive field), is used to detect small defects ranging from 20×20 to 40×40 pixels, such as open circuits and short circuits. This multi-scale detection head reconstruction strategy fundamentally changes the shortcoming of general-purpose target detection models that "ignore" minute defects on PCBs. By adding detection branches to the high-resolution feature map, it significantly improves the model's recall rate for extremely small and micro-defects. It should be understood that although this embodiment provides a specific correspondence between the detection layer size and the defect scale, in other embodiments, the number, size and corresponding receptive field range of the detection layer can be flexibly adjusted according to the actual PCB product's line width and spacing specifications and defect distribution statistics, as long as it can achieve accurate layered detection of defects of different scales.

[0071] Furthermore, to further enhance the model's learning ability for difficult-to-classify samples, this embodiment also uses an improved Focal-CIoU loss function instead of the original CIoU loss function. The standard CIoU loss function formula is: in, The intersection-union ratio (IU) of the predicted bounding box and the ground truth bounding box. These represent the center coordinates of the predicted bounding box and the ground truth bounding box, respectively. Let be the Euclidean distance, and c be the diagonal length of the smallest closure rectangle that simultaneously contains both boxes. Used to measure aspect ratio consistency These represent the width of the predicted bounding box and the width of the ground truth bounding box, respectively. These represent the height of the predicted bounding box and the height of the ground truth bounding box, respectively. This is the balance coefficient.

[0072] Improved Focal-CIoU by introducing a modulation factor The losses are weighted as a whole, and the calculation formula is as follows: in, Focusing parameters (usually taken as...) In this formula, Smaller samples (i.e., samples with poor prediction quality) The larger the value, the higher the loss weight, forcing the model to pay more attention to these difficult samples.

[0073] This loss function, considering the overlap area between the predicted and ground truth bounding boxes, the distance between their center points, and the consistency of their aspect ratios, introduces a Focal mechanism (modulation factor) to dynamically adjust sample weights. This allows the training process to focus more on indistinguishable micro-defect samples and reduce the weight contribution of simple background samples. Combined with a channel pruning strategy based on batch normalization layer scaling factors, the model is lightweighted while maintaining detection accuracy, enabling it to meet the computational constraints of embedded deployments in industrial settings. Through the synergistic improvements to the backbone network, attention mechanism, detection head, and loss function, the improved YOLOv8 model constructed in this embodiment demonstrates excellent performance in PCB micro-defect detection tasks, effectively addressing the technical pain points of traditional algorithms, such as high false negative rates and insensitivity to small targets.

[0074] In some exemplary embodiments, the PCB is subjected to collaborative detection of internal defects and electrical performance. Specifically, the following steps are taken: the 3D visualization image of the PCB that has passed the initial inspection is used to reconstruct the 3D volume data of the PCB through a filtered back projection algorithm to identify internal defects; the electrical characteristics of the PCB are detected by flying probes, and the flying probe test results are output; the internal defects and the flying probe test results are aligned and fused in spatial coordinates to obtain a collaboratively detected defect list.

[0075] Specifically, in this embodiment, the system only initiates the relatively time-consuming collaborative inspection of internal structure and electrical performance after the PCB surface has passed the initial inspection. This on-demand triggering mechanism effectively avoids ineffective deep scanning of known surface defects, ensuring the overall inspection cycle of the production line. In the internal defect detection stage, the system uses a micro-focus X-ray inspection module to perform computed tomography (CT) scans on the PCB. The X-ray source and flat panel detector rotate synchronously around the PCB or rotate on the PCB itself, acquiring projection data penetrating the PCB from multiple angles. Subsequently, the acquired multi-angle projection data is preprocessed and filtered using a filtered back projection (FBP) algorithm to eliminate artifacts and enhance edge information. The filtered projection data is then back-projected into three-dimensional space to reconstruct high-resolution three-dimensional volume data of the PCB's internal structure. Based on this three-dimensional volume data, the system can accurately identify hidden defects that traditional optical inspection cannot detect, such as missing copper layers on the inner walls of vias (no copper in the via), interlayer dielectric delamination or bubbles, internal circuit cracks, and structural anomalies such as internal short circuits or open circuits. It should be understood that although this embodiment uses a filtered back projection algorithm, in other embodiments, an iterative reconstruction algorithm or an end-to-end reconstruction network based on deep learning can also be used depending on the computing resources and imaging accuracy requirements, as long as the three-dimensional volume data reflecting the internal structure of the PCB can be recovered from the projection data.

[0076] Furthermore, in the electrical performance testing phase, the system comprehensively verifies the electrical characteristics of the PCB using a flying probe testing module. This module contains multiple high-precision probes arranged symmetrically in a ring and capable of independent movement. These probes automatically locate and contact designated test points based on the PCB's design data (such as CAD or Gerber files). The testing encompasses three dimensions: first, connectivity testing, which applies a low-frequency test signal between two points and measures the resistance to determine if there are open or short circuits in the network; second, impedance testing, which applies a high-frequency signal to measure the characteristic impedance of the circuit to verify whether it meets the design specifications for high-speed signal transmission; and third, insulation testing, which applies a specified voltage between adjacent networks and monitors leakage current to assess the reliability of the insulation layer. This multi-dimensional electrical testing can uncover hidden defects that appear structurally intact but exhibit electrical performance failures, such as high-resistance contacts, impedance mismatches, or insulation degradation, thus compensating for the shortcomings of simple structural testing.

[0077] Furthermore, this embodiment precisely aligns and fuses the X-ray detection results and the flying needle test results in a unified spatial coordinate system. Since the optical imaging coordinate system, the X-ray voxel coordinate system, and the flying needle mechanical probe coordinate system have fundamental differences in physical definition and data representation, direct comparison is prone to misjudgment. Therefore, the system pre-establishes a global coordinate transformation model with the vacuum adsorption stage plane as the unified physical reference. During the detection process, the pose transformation matrix of each sensor relative to the global reference is first obtained through high-precision calibration; subsequently, the voxel coordinates of the internal defects reconstructed by X-ray and the mechanical coordinates of the flying needle test points are mapped to this global reference coordinate system through corresponding transformation matrices. Based on this, the system performs correlation analysis between the spatial location of the internal defects and the spatial location of electrical test anomalies: if an electrical test shows an open circuit at a certain location, and a crack or a hole without copper is found in the reconstructed data at the same spatial location, the system marks this composite defect as a "structural-electrical associated defect" and generates a collaboratively detected defect list containing defect type, three-dimensional coordinates, electrical parameters, and structural images. This spatial alignment and fusion mechanism ensures that the test results are no longer isolated, but can be mutually verified from both structural and functional dimensions, significantly improving the accuracy of defect diagnosis and root cause tracing capabilities, and providing valuable data support for subsequent process optimization.

[0078] In some exemplary embodiments, each defect in the initial defect list and the collaborative defect list is reviewed. Specifically, this involves: extracting multi-dimensional features for each defect in both lists to generate a multi-dimensional feature vector; the multi-dimensional feature vector includes geometric features, texture features, grayscale features, edge gradient features, and frequency features; using a Convolutional Neural Networks (CNN) model to identify defects from the multi-dimensional feature vector, outputting the defect type and review confidence level; and using the IPC standard to determine the defect type and review confidence level, outputting the final detection result.

[0079] Specifically, such as Figure 4 As shown, this embodiment constructs a three-layer kernel mechanism from machine vision features to industrial acceptance standards, aiming to solve the problems of single deep learning models being susceptible to noise interference and lacking standard interpretability in complex industrial scenarios. The first layer is multi-dimensional feature extraction. The system extracts features from the candidate region images of defects in the initial defect list and the collaborative defect list to obtain multi-dimensional features. Among them, geometric features are used to quantify the morphological attributes of defects, specifically including indicators such as area, perimeter, aspect ratio, roundness, rectangularity, convex hull area ratio, principal axis direction angle, Euler number, eccentricity, and compactness, which can effectively distinguish between point-like foreign objects, linear scratches, and surface copper foil residues; texture features are extracted using a gray-level co-occurrence matrix (GLCM), calculating parameters such as energy, entropy, contrast, correlation, inverse difference moment, variance, sum-mean, sum-variance, difference-mean, difference-variance, sum-entropy, and difference-entropy in four directions: 0°, 45°, 90°, and 135°, to capture the differences in microscopic texture structure between the PCB substrate and the defect area; gray-level features cover gray-level mean, variance, skewness, kurtosis, quantiles, gray-level range, gray-level entropy, and local binary mode. Patterns (LBP) histograms are used to characterize the brightness distribution and statistical characteristics of defective regions; edge gradient features include the mean gradient magnitude, variance of gradient magnitude, histogram of oriented gradient (HOG), edge density, edge connectivity, Canny edge response intensity, and Sobel gradient energy, which focus on enhancing the ability to describe edge-sensitive defects such as line breaks and burrs; frequency domain features extract periodic texture anomalies and high-frequency noise information through Fourier descriptor coefficients, wavelet energy proportions, and Gabor filter responses. These five types of features together constitute a high-dimensional feature vector (e.g., 156 dimensions), providing rich semantic information far exceeding that of a single image pixel value for subsequent recognition.

[0080] The second layer involves a lightweight CNN model for verification. Considering the stringent requirements of PCB production lines for inspection units per hour (UPH), this embodiment selects MobileNetV3 as the verification model architecture. Compared to heavy networks such as ResNet or VGG, MobileNetV3, through depthwise separable convolutions and Neural Architecture Search (NAS) optimization, maintains feature extraction capabilities while keeping the number of parameters below 5M. The inference time for a single defect image can be compressed to the 10ms level, fully meeting the real-time requirements of online full inspection. The model input is a standardized defect region image (e.g., 256×256 pixels), and the output is the defect type classification result and the corresponding verification confidence score. During the training phase, a transfer learning strategy is adopted, using pre-trained weights from a large-scale general image dataset for initialization, and then fine-tuning using a PCB-specific defect sample library, enabling the model to converge quickly and adapt to the unique visual patterns of PCBs. The CNN model complements the aforementioned multi-dimensional features: CNN excels at extracting abstract high-level semantic features, while hand-designed multi-dimensional features provide clear physical interpretability. The combination of the two significantly improves the accuracy of the review process in identifying difficult samples.

[0081] The third layer involves comparison with IPC standard criteria. The defect types and confidence levels output by the CNN are automatically compared against authoritative industry standards such as IPC-A-600H (Printed Circuit Board Acceptance Criteria), IPC-6012D (Rigid Printed Circuit Board Qualification and Performance Specification), and IPC-9252 (Electrical Testing Standard). Specifically, for 12 typical defects—open circuit, short circuit, pad detachment, copper-free vias, bubbles, cracks, residual stress, foreign matter residue, line dents, line bumps, insufficient etching, and via misalignment—the system has a built-in standardized judgment rule engine. For example, for the "line dent" defect, in addition to the type identified by the CNN, the system also considers the geometric dimensions from multi-dimensional features to determine whether the dent width exceeds 20% of the line width and whether the length exceeds a specified threshold, thus strictly distinguishing between "acceptable" and "rejectable" boundaries. Based on the comparison results, the system classifies defects into three levels: Level 1 defects are minor defects, within the acceptable range of the IPC standard, and do not require rework; Level 2 defects are moderate defects, exceeding the acceptable range but can be repaired through processes such as rework and replating; Level 3 defects are severe defects, unrepairable or with excessively high repair costs, and are directly judged as scrap. This classification mechanism avoids the crude judgment of traditional AI inspection, providing a refined basis for quality handling on the production floor, and significantly reducing the risk of excessive scrapping or missed inspections due to misjudgment. It should be understood that although this embodiment uses the IPC standard as an example, in other implementations, it can be replaced with JEDEC, UL, or enterprise-customized standards according to customer needs, as long as the rule-based defect level determination function can be achieved.

[0082] To further verify the effectiveness and advancement of the PCB defect detection method provided in this application in actual industrial production, this embodiment applies it to the online full inspection scenario of High Density Interconnector (HDI) printed circuit boards. Specifically, this application scenario targets 8- to 12-layer smartphone motherboards with a line width and spacing of 45μm and a single board size of 250mm × 300mm. Production cycle requirements are extremely stringent, and the inspection time for a single board must be controlled within 30 seconds. These HDI boards are characterized by a high number of layers, dense circuitry, and susceptibility to warping, making them the best test of the ability of this application's technical solution to address industry pain points.

[0083] In terms of inspection efficiency, the method of this application demonstrates excellent production adaptability. In actual operation, for boards requiring only surface inspection, the system inspection speed reaches 12 seconds / board; for boards triggering joint inspection of internal defects and electrical performance, the full-process inspection speed including X-ray scanning is 38 seconds / board. This efficiency fully meets or even exceeds the production cycle requirement of ≤30 seconds / board (Note: Joint inspection is usually used for sampling or for specific high-risk boards and does not affect the overall production line average UPH). This high efficiency is mainly due to the established diversion logic of "joint inspection is triggered only when the initial inspection is qualified" and the hardware acceleration architecture based on FPGA and GPU heterogeneous computing, which allows most surface-qualified boards to be quickly processed without waiting for time-consuming CT scans and flying probe tests, thereby maximizing production line throughput while ensuring full coverage inspection capability.

[0084] This application achieves significant technological breakthroughs in terms of detection accuracy and quality indicators. Compared with traditional AOI equipment before application, the false negative rate has been reduced from 1.8% to 0.04%, a decrease of 97.8%; the false positive rate has been reduced from 0.6% to 0.022%, a decrease of 96.3%. More importantly, the defect location error has been improved from the traditional ±0.5mm to ±5μm, a 100-fold increase in accuracy. These qualitative changes in quantitative indicators directly verify the core value of three-dimensional warp correction and the improved YOLOv8 algorithm. Specifically, by constructing a high-precision three-dimensional warp model and performing sub-pixel-level geometric correction on the image, the feature offset and blurring caused by board deformation are eliminated, enabling the algorithm to accurately identify minute line defects at the 45μm level on a unified flat benchmark; while the dual-channel SimAM attention mechanism and the reconstruction of the multi-scale detection head effectively solve the problem of traditional algorithms missing detection of extremely small targets in complex texture backgrounds, thus achieving dual suppression of false negatives and false positives.

[0085] In terms of defect coverage, this application successfully fills the technical blind spot of single optical inspection. In this HDI production line application, the internal defect detection rate increased from 0% (which traditional AOI could not detect) to 98.5%. This fully demonstrates the effectiveness of the multimodal collaborative inspection mechanism. By aligning and fusing the internal structural information reconstructed by microfocus X-ray CT with the electrical performance data from flying probe testing in a unified spatial coordinate system, the system can not only detect hidden structural defects such as copper-free holes and interlayer bubbles, but also identify functional defects such as impedance mismatch and insulation degradation. It truly achieves a leap from "visual inspection" to "functional inspection," providing comprehensive assurance for the reliability of high-end HDI products.

[0086] In terms of production closed-loop control and economic benefits, this application demonstrates a powerful intelligent empowerment effect. The batch defect response time has been reduced from 4 hours in the traditional manual feedback mode to 5 seconds in automatic feedback, a 2880-fold increase in response speed. When the system detects that the rate of the same type of defect in the same batch exceeds a preset threshold, it immediately sends process parameter adjustment suggestions to the production equipment via the industrial Ethernet protocol and triggers an early warning from the MES system, thus nipping quality accidents in the bud. Statistics show that the annual scrap loss of this production line has decreased from 3.2 million yuan to 950,000 yuan, a reduction of 70.3%.

[0087] In summary, this embodiment, through application verification in a real HDI production line, demonstrates with detailed comparative data the significant effectiveness of this application in addressing industry pain points such as missed detection of warped boards, difficulty in detecting minute defects, invisibility of internal defects, and delayed feedback. These data not only support the inventiveness and practicality of this application but also demonstrate that the technical solution possesses extremely high industrial promotion value and market competitiveness. It should be understood that although this embodiment uses an HDI motherboard as an example, in other embodiments, the method of this application is also applicable to the inspection scenarios of other high-value-added boards such as flexible printed circuit boards (FPC), rigid-flex boards, substrate-like boards (SLP), and aerospace PCBs. As long as the grid density, inspection head size, and IPC judgment criteria are adjusted accordingly based on the specific product characteristics, its core technical principles and beneficial effects are universally applicable.

[0088] Based on the same inventive concept, this application also provides a PCB defect detection system for implementing the PCB defect detection method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more PCB defect detection system embodiments provided below can be found in the limitations of the PCB defect detection method described above, and will not be repeated here.

[0089] In one exemplary embodiment, a PCB defect detection system is provided, comprising: The data acquisition module is used to acquire PCB images and PCB 3D coordinate data from several perspectives. The warpage model building module generates a 3D warpage model based on PCB 3D coordinate data. The warpage correction module is used to correct the warpage area images of PCB images from several viewpoints based on a three-dimensional warpage model. The image fusion module is used to fuse PCB images from several corrected perspectives to obtain a 3D visualization image of the PCB. The defect detection module is used to perform a preliminary inspection of the PCB 3D visualization image using a target detection algorithm. If the preliminary inspection fails, a preliminary defect list is output; if the preliminary inspection passes, the PCB undergoes a collaborative inspection of internal defects and electrical performance, and a collaborative defect list is output. The defect verification module is used to verify each defect in the initial defect list and the collaborative detection defect list, and output the final detection result.

[0090] As an optional implementation, this application provides an exemplary embodiment of a PCB defect detection system, the architecture of which is as follows: Figure 5 As shown, this system achieves fully automated execution of the PCB defect detection method described in the aforementioned embodiments through a modular hardware architecture. The PCB defect detection system includes: a data acquisition module, a warpage model construction module, a warpage correction module, an image fusion module, a defect detection module, and a defect verification module.

[0091] The data acquisition module is used to acquire PCB images and PCB 3D coordinate data from multiple perspectives. Specifically, the data acquisition module is the physical sensing front end of the system, and its hardware components include a vacuum adsorption stage, a three-in-one dust removal device, a semiconductor constant temperature module, a laser rangefinder array, and a multi-view image acquisition module. The vacuum adsorption stage surface is equipped with adjustable negative pressure adsorption holes to firmly fix the PCB to be inspected and provide a unified XY plane reference. The three-in-one dust removal device integrates high-pressure airflow nozzles, electrostatic dust removal rollers, and ion air bars, arranged sequentially along the conveying direction to remove surface impurities and eliminate static electricity. The semiconductor temperature control module consists of multiple thermoelectric coolers (TECs) attached to the back of the stage, which, together with a PID control algorithm, stabilize the board surface temperature within a set range, physically suppressing thermal warping. The laser rangefinder array uses a grid-arranged phase-type laser rangefinder to acquire high-density discrete height point clouds. The multi-view image acquisition module includes at least four high-resolution CMOS industrial cameras (top-view, left-view, right-view, and bottom-view) and a ring-shaped shadowless light source. All cameras and laser rangefinders achieve microsecond-level timing synchronization through hardware trigger signals, ensuring that each frame of RGB image is bound to precise depth data. This multi-sensor fusion hardware design provides a high-fidelity, spatiotemporally aligned raw data foundation for subsequent 3D reconstruction.

[0092] The 3D warpage model building module generates a 3D warpage model based on PCB 3D coordinate data. Specifically, this module is typically deployed in a Field Programmable Gate Array (FPGA) or Graphics Processing Unit (GPU), receiving discrete 3D point cloud data from a laser rangefinder array. Internally, the module runs a mesh generation and hyperbolic polynomial surface fitting algorithm to transform the discrete Z-axis height values ​​into a globally continuous height field W(x,y). Since the modeling process involves numerous matrix operations, using a dedicated hardware accelerator can significantly shorten the model generation time, enabling it to adapt to the production cycle of online full inspection.

[0093] The warpage correction module is used to correct warped regions in PCB images from multiple viewpoints based on a 3D warpage model. Specifically, this module is tightly coupled with the warpage model construction module and can also be implemented using FPGA hardware acceleration. The module reads height information from the height field model W(x,y), substitutes it into a pre-stored bidirectional distortion mapping equation set, and performs inverse mapping and bilinear interpolation resampling on the original images from multiple viewpoints. By performing this computationally intensive task at the hardware level, the system can eliminate image stretching, compression, and feature point offset caused by PCB warpage within milliseconds, outputting a standardized corrected image unified to a flat reference plane, providing geometrically consistent input for subsequent fusion and detection.

[0094] The image fusion module is used to fuse PCB images from several corrected viewpoints to obtain a 3D visualization image of the PCB. Specifically, this module performs an improved Scale-Invariant Feature Transform (SIFT) feature matching and weighted average fusion algorithm. The module first establishes pixel-level precise alignment between the corrected multi-view images, and then dynamically calculates the fusion weights based on sharpness, defect saliency, and viewpoint coverage, ultimately generating a 3D visualization image of the PCB that combines texture details and depth information.

[0095] The defect detection module performs an initial inspection of the PCB's 3D visualization image using a target detection algorithm. If the initial inspection fails, a list of initial defects is output; if the initial inspection passes, the PCB undergoes collaborative inspection for internal defects and electrical performance, outputting a list of collaboratively detected defects. Specifically, this module is the core decision-making unit of the system, comprising an initial inspection subunit and a collaborative inspection subunit. The initial inspection subunit runs an improved YOLOv8 model, utilizing a Conv2Former and C2f concatenated backbone network and a dual-channel SimAM attention mechanism to rapidly screen for surface defects in the 3D visualization image. The collaborative inspection subunit integrates a microfocus X-ray detection module and a flying probe testing module, activating only as needed when the initial inspection determines the surface is acceptable. The microfocus X-ray detection module includes a microfocus X-ray tube and a flat panel detector, supporting CT scanning and filtered backprojection reconstruction. The flying probe testing module contains multiple independently moving probes arranged symmetrically in a ring, capable of performing connectivity, impedance, and insulation tests. More importantly, the module incorporates a spatial coordinate alignment and fusion engine, which can map the optical coordinate system, X-ray voxel coordinate system, and mechanical probe coordinate system to a global physical reference, enabling three-dimensional correlation analysis of surface, internal, and electrical defects. This "surface-first, interior-later, on-demand triggering" hardware scheduling strategy maximizes equipment utilization while ensuring full coverage detection.

[0096] The defect verification module verifies each defect in the initial defect list and the collaborative detection defect list, outputting the final detection results. Specifically, this module runs a multi-dimensional feature extraction algorithm, a lightweight Convolutional Neural Networks (CNN) verification model, and an IPC standard comparison engine. The module extracts five types of feature vectors from the defect candidate region: geometric, texture, grayscale, edge gradient, and frequency domain. These are then used for secondary recognition via lightweight networks such as MobileNetV3. Finally, the recognition results are automatically compared with industry standards such as IPC-A-600H, outputting a final detection report containing the defect type, level, and processing suggestions. This module ensures the authority and interpretability of the detection conclusions, avoiding the risk of misjudgment associated with a single AI model.

[0097] The final inspection results can be output through the inspection interface. Optionally, the inspection result output interface includes: a basic information area displaying the PCB number, production batch number, inspection time, inspector, equipment number, inspection time, and QR code; an inspection result summary area displaying the total number of defects, surface defects, internal defects, electrical defects, defects at each level, and inspection conclusions; a defect details list area listing each defect's serial number, type, coordinates, layer, size, level, and handling suggestions in tabular form; a defect image area displaying a magnified image of each defect for easy manual review; and a feedback information area displaying the feedback status, feedback content, warning status, and data storage status.

[0098] In addition, to ensure the efficient coordination and stable operation of the aforementioned functional modules, the system in this embodiment also includes a central control unit and an environmental compensation module. The central control unit employs an industrial-grade embedded computer or heterogeneous computing platform, running a Real-Time Operating System (RTOS), responsible for coordinating the timing synchronization, data flow control, and anomaly handling of each module. For example, it achieves microsecond-level synchronization of the camera, laser ranging, X-ray exposure, and flying needle testing through hardware trigger signals; it employs a pipelined architecture to achieve parallel processing of each module to improve throughput; and it automatically performs diagnosis and recovery when a module fault is detected. The environmental compensation module includes temperature sensors, humidity sensors, and vibration sensors, used to monitor environmental parameters in real time and automatically activate the compensation mechanism to eliminate interference from environmental fluctuations on precision measurements. It should be understood that although... Figure 5This paper demonstrates a specific layout and connection relationship of each module. However, in other embodiments, the physical location, communication bus type, or hardware carrier form of each module can be adjusted according to the actual production line space and computing power requirements. For example, the warp model construction module and the correction module can be integrated into the same FPGA chip, or the functions of the central control unit can be distributed and deployed in each sub-module controller, as long as the functional logic and data interaction of the above modules can be realized.

[0099] Through the aforementioned hardware architecture, the PCB defect detection system provided in this embodiment solidifies the three-dimensional warp correction, multimodal collaborative detection, and triple kernel mechanism in the aforementioned method embodiments into a physical device. It not only realizes the fully automated closed loop from data acquisition to result output, but also ensures long-term stable operation in a high-speed, high-precision industrial production environment through dedicated hardware acceleration and environmental compensation design, providing reliable hardware support for real-time monitoring and process optimization of PCB manufacturing quality.

[0100] In one exemplary embodiment, a computer device is provided, which may be a server or a terminal, and its internal structure diagram may be as follows. Figure 6 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a PCB defect detection method.

[0101] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0102] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0103] In one exemplary embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0104] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0105] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0106] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).

[0107] The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchain. The processors involved in the embodiments provided in this application may be, but are not limited to, general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A PCB defect detection method, characterized in that, The PCB defect detection method includes: Acquire PCB images and PCB 3D coordinate data from several perspectives; Based on the PCB three-dimensional coordinate data, a three-dimensional model of warpage is generated; Based on the aforementioned three-dimensional warp model, the warp region images of the PCB images from several viewpoints are corrected. The PCB images from several corrected perspectives are fused to obtain a 3D visualization image of the PCB. The PCB 3D visualization image is used to perform a preliminary inspection of the PCB appearance. If the preliminary inspection fails, a preliminary defect list is output. If the preliminary inspection passes, the PCB internal defects and electrical performance are jointly inspected, and a joint inspection defect list is output. Each defect in the initial defect list and the collaborative defect list is reviewed, and the final detection result is output.

2. The PCB defect detection method according to claim 1, characterized in that, Based on the PCB three-dimensional coordinate data, a three-dimensional model of warpage is generated, specifically as follows: The PCB is divided into several grids; the PCB three-dimensional coordinate data includes the planar coordinates of each grid and the height data of the sampling points within each grid. Based on the planar coordinates of each grid on the PCB and the height data of the sampling points within each grid, a bicubic polynomial surface equation is constructed. The correction coefficients are obtained by solving the bicubic polynomial surface equation using the least squares method. Based on the correction coefficients, a continuous surface height field within the corresponding grid is generated by fitting a bicubic polynomial surface equation. By stitching together the continuous surface height fields of all meshes, the final three-dimensional model of warpage is obtained.

3. The PCB defect detection method according to claim 2, characterized in that, The warped region images of the PCB images from the aforementioned several viewpoints are corrected, specifically as follows: For each viewpoint of the PCB image, based on the correction coefficients, the sub-pixel coordinates of the original distorted image are calculated using a pre-constructed set of bidirectional distortion mapping equations, using the reference plane pixel coordinates and corresponding height data of the PCB image. Bilinear interpolation is used to assign grayscale weighted values ​​to the original pixels surrounding the subpixel coordinates of the original distorted image, generating PCB images from several corrected perspectives.

4. The PCB defect detection method according to claim 3, characterized in that, The expression for the bidirectional distortion mapping equation set is: in, The x-coordinate of the reference plane pixel coordinates of the PCB image; The ordinate of the reference plane pixel coordinates of the PCB image; Representing coordinates Corresponding height data; The x-coordinate represents the subpixel coordinates of the original distorted image; The ordinate represents the subpixel coordinates of the original distorted image; , , , , , and as well as , , , , , and All of these are correction coefficients.

5. The PCB defect detection method according to claim 1, characterized in that, The process of fusing the corrected PCB images from several viewpoints specifically involves: The PCB feature map is obtained by fusing features from several corrected PCB images from different viewpoints using an improved SIFT feature point matching algorithm. The PCB feature map is subjected to a weighted average fusion algorithm to perform pixel-by-pixel weighted fusion, resulting in a 3D visualization image of the PCB.

6. The PCB defect detection method according to claim 1, characterized in that, The target detection algorithm employs an improved YOLOv8 model; the improved YOLOv8 model includes a backbone network, a feature enhancement module, and a detection layer. The backbone network includes Conv2Former modules and C2f modules; the Conv2Former modules and C2f modules are connected in series and stacked. The feature enhancement module is connected in series with the backbone network, and the feature enhancement module adopts dual-channel SimAM; The detection layer is connected in series with the feature enhancement module; the detection layer includes several detection heads of different sizes.

7. The PCB defect detection method according to claim 1, characterized in that, The aforementioned joint inspection of internal defects and electrical performance of the PCB specifically includes: The internal three-dimensional volume data of the PCB is reconstructed from the 3D visualization image of the PCB that has passed the initial inspection by using a filtered back projection algorithm to identify internal defects. The electrical characteristics of the PCB are tested using flying probes, and the flying probe test results are output. By aligning and fusing the internal defects with the results of the flying probe test in spatial coordinates, a collaborative defect detection list is obtained.

8. The PCB defect detection method according to claim 1, characterized in that, Each defect in the initial defect list and the collaborative defect list is reviewed, specifically as follows: For each defect in the initial defect list and the collaborative defect list, multi-dimensional features are extracted to generate a multi-dimensional feature vector; the multi-dimensional feature vector includes geometric features, texture features, grayscale features, edge gradient features, and frequency domain features; The multi-dimensional feature vectors are used to perform defect identification using a CNN model, and the defect type and verification confidence level are output. The defect type and verification confidence level are determined using the IPC standard, and the final detection result is output.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the PCB defect detection method according to any one of claims 1-8.

10. A PCB defect detection system, characterized in that, The PCB defect detection system includes: The data acquisition module is used to acquire PCB images and PCB 3D coordinate data from several perspectives. The warpage model construction module generates a three-dimensional warpage model based on the PCB three-dimensional coordinate data. The warpage correction module is used to correct the warpage region images of the PCB images from several viewpoints based on the warpage three-dimensional model. The image fusion module is used to fuse PCB images from several corrected perspectives to obtain a 3D visualization image of the PCB. The defect detection module is used to perform a preliminary inspection of the PCB 3D visualization image using a target detection algorithm. If the preliminary inspection fails, a preliminary defect list is output; if the preliminary inspection passes, the PCB undergoes a collaborative inspection of internal defects and electrical performance, and a collaborative defect list is output. The defect verification module is used to verify each defect in the initial inspection defect list and the collaborative detection defect list, and output the final detection result.

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