Display device, pixel included in display device, and electronic device including display device

Abstract

The disclosure relates to a display device, a pixel included in the display device, and an electronic device including the display device. The display device includes a display panel including a pixel, a gate driver, an emission driver, and a data driver. The pixel includes a light emitting element including a first terminal and a second terminal receiving a low power voltage, a first transistor including a gate connected to a first node, a first terminal receiving a high power voltage, and a second terminal connected to a second node, a second transistor transmitting a data signal to a third node, a third transistor connecting the first node to the second node, a fourth transistor transmitting a reference voltage to the first node or the second node or connecting the second node to the third node, a fifth transistor connecting the second node to the first terminal of the light emitting element, and a first capacitor connected between the first node and the third node.

Description

Technical Field

[0001] Some aspects of implementations relate to display devices, pixels included in display devices, and electronic devices that include display devices. Background Technology

[0002] The display device may include a display panel, a gate driver, and a data driver. The display panel may include pixels, the gate driver may provide a gate signal to each of the pixels, and the data driver may provide a data voltage to each of the pixels.

[0003] A pixel may include a light-emitting element that emits light based on a drive current and multiple transistors including a drive transistor that generates the drive current. As the number of transistors included in a pixel increases, the pixel area may increase, and the implementation of high-resolution display devices may be limited.

[0004] Differences in pixel brightness can occur when there are differences in the threshold voltages of the driving transistors of a pixel. Therefore, the threshold voltages of the driving transistors can be compensated to reduce the differences in threshold voltages between the driving transistors.

[0005] The information disclosed in this background section is only intended to enhance the understanding of the background art, and therefore the information discussed in this background section does not necessarily constitute prior art. Summary of the Invention

[0006] Some aspects of this disclosure relate to display devices, pixels included in display devices, and electronic devices including display devices. For example, some aspects of the embodiments relate to display devices including pixels comprising a plurality of transistors, and electronic devices including display devices for displaying images.

[0007] Some aspects of the implementation include a display device with relatively high resolution, pixels wherein threshold voltages of driving transistors are compensated, and electronic devices including a display device with high resolution.

[0008] A display device according to some embodiments includes: a display panel including pixels; a gate driver providing a write gate signal, a compensation gate signal, and an initialization gate signal to each of the pixels; an emitter driver providing an emitter signal to each of the pixels; and a data driver providing a data signal to each of the pixels. According to some embodiments, each of the pixels includes: a light-emitting element including a first terminal and a second terminal receiving a low-power voltage; a first transistor including a gate connected to a first node, a first terminal receiving a high-power voltage having a voltage level higher than the low-power voltage, and a second terminal connected to a second node; a second transistor transmitting a data signal to a third node in response to the write gate signal; a third transistor connecting the first node to the second node in response to the compensation gate signal; a fourth transistor transmitting a reference voltage to the first node or the second node or connecting the second node to the third node in response to the initialization gate signal; a fifth transistor connecting the second node to the first terminal of the light-emitting element in response to the emitter signal; and a first capacitor connected between the first node and the third node.

[0009] According to some implementations, the fourth transistor can connect a data line carrying a data signal with a reference voltage to the first node in response to an initialization gate signal.

[0010] According to some implementations, during the initialization cycle, the data signal may have a reference voltage, and each of the compensation gate signal, the initialization gate signal, the write gate signal, and the transmit signal may have an activation voltage level.

[0011] According to some implementations, during the compensation cycle, the data signal may have a reference voltage, each of the compensation gate signal and the write gate signal may have an activation voltage level, and each of the initialization gate signal and the transmit signal may have a deactivation voltage level.

[0012] According to some implementations, during the write cycle, the data signal may have a data voltage, the write gate signal may have an activation voltage level, and each of the compensation gate signal, the initialization gate signal, and the transmit signal may have a deactivation voltage level.

[0013] According to some implementations, during the transmit cycle, the data signal may have a reference voltage, the transmit signal may have an activation voltage level, and each of the compensation gate signal, the initialization gate signal, and the write gate signal may have a deactivation voltage level.

[0014] According to some implementations, each of the pixels may further include: a second capacitor connected between the third node and the power line transmitting the high power voltage.

[0015] According to some implementations, each of the pixels may further include: a sixth transistor that transmits a low power voltage to a first terminal of the light-emitting element in response to a bypass gate signal.

[0016] According to some implementations, the bypass gate signal may have an activation voltage level during the initialization cycle, the compensation cycle, and the write cycle, and may have a deactivation voltage level during the transmit cycle.

[0017] According to some implementations, each of the pixels may further include: a sixth transistor that transmits an initialization voltage to a first terminal of the light-emitting element in response to a bypass gate signal.

[0018] According to some implementations, each of the pixels may further include: a second capacitor connected between the first node and the power line transmitting the high power voltage.

[0019] According to some implementations, the fourth transistor can connect a data line carrying a data signal with a reference voltage to the second node in response to an initialization gate signal.

[0020] According to some implementations, the fourth transistor can connect a reference line carrying a reference voltage to the second node in response to an initialization gate signal.

[0021] According to some implementations, the fourth transistor can connect the second node to the third node in response to an initialization gate signal.

[0022] A pixel according to some embodiments includes: a light-emitting element including a first terminal and a second terminal receiving a low power voltage; a first transistor including a gate connected to a first node, a first terminal receiving a high power voltage having a voltage level higher than the low power voltage, and a second terminal connected to a second node; a second transistor transmitting a data signal to a third node in response to a write gate signal; a third transistor connecting the first node to the second node in response to a compensation gate signal; a fourth transistor transmitting a reference voltage to the first node or the second node or connecting the second node to the third node in response to an initialization gate signal; a fifth transistor connecting the second node to the first terminal of the light-emitting element in response to a transmit signal; and a first capacitor connected between the first node and the third node.

[0023] According to some implementations, the fourth transistor can connect a data line carrying a data signal with a reference voltage to the first node in response to an initialization gate signal.

[0024] According to some implementations, the pixel may also include a second capacitor connected between the third node and the power line transmitting the high power voltage.

[0025] According to some implementations, the fourth transistor can connect a data line carrying a data signal with a reference voltage to the second node in response to an initialization gate signal.

[0026] According to some implementations, the fourth transistor can connect the second node to the third node in response to an initialization gate signal.

[0027] An electronic device according to some embodiments includes: a processor for generating input image data; a display device for displaying images based on the input image data; and a power module connected to the processor and the display device. According to some embodiments, the display device includes: a display panel including pixels; a gate driver for providing a write gate signal, a compensation gate signal, and an initialization gate signal to each of the pixels; an emitter driver for providing an emitter signal to each of the pixels; and a data driver for providing a data signal to each of the pixels. According to some embodiments, each of the pixels includes: a light-emitting element including a first terminal and a second terminal receiving a low power voltage; a first transistor including a gate connected to a first node, a first terminal receiving a high power voltage having a voltage level higher than the low power voltage, and a second terminal connected to a second node; a second transistor for transmitting a data signal to a third node in response to the write gate signal; a third transistor for connecting the first node to the second node in response to the compensation gate signal; a fourth transistor for transmitting a reference voltage to the first node or the second node or connecting the second node to the third node in response to the initialization gate signal; a fifth transistor for connecting the second node to the first terminal of the light-emitting element in response to the emitter signal; and a first capacitor connected between the first node and the third node.

[0028] In pixels, display devices, and electronic devices according to some embodiments, pixels include a relatively small number of transistors, thereby relatively reducing the pixel area and relatively increasing the resolution of the display device. Furthermore, pixels compensate for the threshold voltage of the driving transistors via diode connections, thereby relatively improving the image quality of the display device. Attached Figure Description

[0029] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 This is a block diagram illustrating aspects of a display device according to some embodiments.

[0031] Figure 2 It is shown Figure 1 The example of a pixel is shown in the circuit diagram.

[0032] Figure 3 It is shown Figure 2 Timing diagrams of aspects of the signal example.

[0033] Figure 4 It is used to describe Figure 3 A diagram of the initialization cycle.

[0034] Figure 5 It is used to describe Figure 3 The diagram shows the compensation cycle.

[0035] Figure 6 It is used to describe Figure 3 A graph showing the write cycle.

[0036] Figure 7 It is used to describe Figure 3 A diagram of the launch cycle.

[0037] Figure 8 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0038] Figure 9 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0039] Figure 10 It is shown Figure 9 A timing diagram of an example signal.

[0040] Figure 11 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0041] Figure 12 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0042] Figure 13 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0043] Figure 14 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0044] Figure 15 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0045] Figure 16 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0046] Figure 17 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0047] Figure 18 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0048] Figure 19 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0049] Figure 20 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0050] Figure 21 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0051] Figure 22 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0052] Figure 23 This is a circuit diagram illustrating aspects of a pixel according to some embodiments.

[0053] Figure 24 This is a block diagram illustrating aspects of an electronic device according to some embodiments.

[0054] Figure 25 This is a diagram illustrating aspects of an electronic device according to some embodiments. Detailed Implementation

[0055] In the following, display devices, pixels, and electronic devices according to some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. In the drawings, the same or similar reference numerals will be used for the same elements.

[0056] Figure 1 This is a block diagram illustrating a display device 100 according to some embodiments.

[0057] refer to Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a transmitter driver 130, a data driver 140, and a controller 150.

[0058] The display panel 110 may include pixels PX. Each of the pixels PX may emit light based on a gate signal GS, an emission signal EM, and a data signal DS.

[0059] Gate driver 120 can provide a gate signal GS to each of pixels PX. Gate driver 120 can generate gate signal GS on a pixel-by-pixel basis. Gate driver 120 can generate gate signal GS based on a first control signal CNT1. The first control signal CNT1 may include a gate start signal, a gate clock signal, etc.

[0060] The transmit driver 130 can provide a transmit signal EM to each of the pixels PX. The transmit driver 130 can generate the transmit signal EM on a row-by-row basis. The transmit driver 130 can generate the transmit signal EM based on a second control signal CNT2. The second control signal CNT2 may include a transmit start signal, a transmit clock signal, etc.

[0061] Data driver 140 can provide a data signal DS to each of the pixels PX. Data driver 140 can generate the data signal DS based on the output image data IMD2 and the third control signal CNT3. Data driver 140 can convert the digital output image data IMD2 into the analog data signal DS. The third control signal CNT3 may include a load signal, a data clock signal, an output data enable signal, etc.

[0062] The controller 150 can control the gate driver 120, the transmit driver 130, and the data driver 140. The controller 150 can provide a first control signal CNT1 to the gate driver 120, a second control signal CNT2 to the transmit driver 130, and output image data IMD2 and a third control signal CNT3 to the data driver 140. The controller 150 can generate output image data IMD2, the first control signal CNT1, the second control signal CNT2, and the third control signal CNT3 based on the input image data IMD1 and the input control signal CNT0. According to some embodiments, the input image data IMD1 may include red image data, green image data, and blue image data. The input control signal CNT0 may include a vertical synchronization signal, a horizontal synchronization signal, a master clock signal, an input data enable signal, etc.

[0063] Figure 2 It is shown Figure 1 A circuit diagram of an example aspect of pixel PX. Although Figure 2 Various components in a pixel PX according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0064] Figure 3 It is shown Figure 2 The timing diagrams are examples of signals DS, GC, GI, GW, and EM.

[0065] refer to Figure 2 and Figure 3 The pixel PX1 can receive the write gate signal GW, the compensation gate signal GC, the initialization gate signal GI, the transmit signal EM, the data signal DS, the high power voltage ELVDD, and the low power voltage ELVSS. Figure 1The gate signal GS may include a write gate signal GW, a compensation gate signal GC, and an initialization gate signal GI. The data signal DS may have a reference voltage VREF and a data voltage VDAT. The voltage level of the high power voltage ELVDD (e.g., 7 volts (V) or about 7V) may be higher than the voltage level of the low power voltage ELVSS (e.g., 0V or about 0V). Pixel PX1 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2.

[0066] The light-emitting element EL may include a first terminal (e.g., an anode) and a second terminal (e.g., a cathode) that receives a low power voltage ELVSS. According to some embodiments, the light-emitting element EL may be one of an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, and a micro light-emitting diode.

[0067] The first transistor T1 may include a gate connected to the first node N1, a first terminal receiving a high power voltage ELVDD, and a second terminal connected to the second node N2.

[0068] The second transistor T2 can transmit a data signal DS to the third node N3 in response to the write gate signal GW. The second transistor T2 may include a gate for receiving the write gate signal GW, a first terminal connected to the data line DL for transmitting the data signal DS, and a second terminal connected to the third node N3.

[0069] The third transistor T3 can connect the first node N1 to the second node N2 in response to the compensation gate signal GC. The third transistor T3 may include a gate for receiving the compensation gate signal GC, a first terminal connected to the first node N1, and a second terminal connected to the second node N2.

[0070] The fourth transistor T4 can transmit a reference voltage VREF to the first node N1 in response to the initialization gate signal GI. The fourth transistor T4 can also connect the data line DL, which transmits a data signal DS with the reference voltage VREF, to the first node N1 in response to the initialization gate signal GI. The fourth transistor T4 may include a gate for receiving the initialization gate signal GI, a first terminal connected to the data line DL, and a second terminal connected to the first node N1.

[0071] The fifth transistor T5 can connect the second node N2 to the first terminal of the light-emitting element EL in response to the emission signal EM. The fifth transistor T5 may include a gate for receiving the emission signal EM, a first terminal connected to the second node N2, and a second terminal connected to the first terminal of the light-emitting element EL.

[0072] According to some implementation methods, such as Figure 2 As shown, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be a p-type transistor (e.g., a PMOS transistor). According to some embodiments, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be an n-type transistor (e.g., an NMOS transistor).

[0073] A first capacitor C1 may be connected between a first node N1 and a third node N3. The first capacitor C1 may include a first terminal connected to the first node N1 and a second terminal connected to the third node N3.

[0074] The second capacitor C2 can be connected between the third node N3 and the power line PL that transmits the high power voltage ELVDD. The second capacitor C2 may include a first terminal connected to the third node N3 and a second terminal connected to the power line PL.

[0075] The frame period of pixel PX1 can include an initialization period P1, a compensation period P2, a write period P3, and an emission period P4. In the initialization period P1, the first node N1, the second node N2, the third node N3, and the first terminal of the light-emitting element EL are initialized. In the compensation period P2, the threshold voltage of the first transistor T1 is compensated. In the write period P3, the data voltage VDAT is written to the gate of the first transistor T1. In the emission period P4, the light-emitting element EL emits light.

[0076] The data signal DS can have a reference voltage VREF during the initialization period P1, the compensation period P2, and the transmit period P4, and can have a data voltage VDAT during the write period P3. For example, the voltage level of the reference voltage VREF can be 0V (or approximately 0V).

[0077] The compensation gate signal GC can have an activation voltage level (e.g., -10V or about -10V) in the initialization period P1 and the compensation period P2, and can have a deactivation voltage level (e.g., 10V or about 10V) in the write period P3 and the transmit period P4.

[0078] The initialization gate signal GI can have an activation voltage level (e.g., -10V or about -10V) in the initialization period P1, and can have a deactivation voltage level (e.g., 10V or about 10V) in the compensation period P2, write period P3 and emit period P4.

[0079] The write gate signal GW can have an activation voltage level (e.g., -10V or about -10V) during the initialization period P1, the compensation period P2, and the write period P3, and can have a deactivation voltage level (e.g., 10V or about 10V) during the transmit period P4.

[0080] The transmit signal EM can have an activation voltage level (e.g., -10V or about -10V) during the initialization period P1 and the transmit period P4, and can have a deactivation voltage level (e.g., 10V or about 10V) during the compensation period P2 and the write period P3.

[0081] Figure 4 It is used to describe Figure 3 The diagram of the initialization period P1.

[0082] refer to Figure 3 and Figure 4 In initialization cycle P1, the data signal DS may have a reference voltage VREF, and each of the compensation gate signal GC, the initialization gate signal GI, the write gate signal GW, and the transmit signal EM may have an activation voltage level. In initialization cycle P1, the reference voltage VREF may be applied to the third node N3 via a second transistor T2 that is turned on in response to the activation voltage level of the write gate signal GW. In initialization cycle P1, the reference voltage VREF may be applied to the first node N1 via a fourth transistor T4 that is turned on in response to the activation voltage level of the initialization gate signal GI, to the second node N2 via a third transistor T3 that is turned on in response to the activation voltage level of the compensation gate signal GC, and to the first terminal of the light-emitting element EL via a fifth transistor T5 that is turned on in response to the activation voltage level of the transmit signal EM. In initialization cycle P1, each of the voltages V_N1 of the first node N1, V_N2 of the second node N2, and V_N3 of the third node N3 may be VREF.

[0083] Figure 5 It is used to describe Figure 3 The diagram shows the compensation period P2.

[0084] refer to Figure 3 and Figure 5In compensation period P2, the data signal DS may have a reference voltage VREF, each of the compensation gate signal GC and the write gate signal GW may have an activation voltage level, and each of the initialization gate signal GI and the transmit signal EM may have a deactivation voltage level. In compensation period P2, the reference voltage VREF may be applied to the third node N3 via a second transistor T2 that is turned on in response to the activation voltage level of the write gate signal GW. In compensation period P2, a current path may be formed from the power line PL to the first node N1 via a first transistor T1 that is turned on and a third transistor T3 that is turned on in response to the activation voltage level of the compensation gate signal GC, and the voltage level of the first node N1 may increase until the first transistor T1 is turned off (until the voltage difference VGS between the gate and the first terminal of the first transistor T1 becomes equal to the threshold voltage VTH of the first transistor T1). Therefore, in compensation period P2, the voltage V_N1 of the first node N1 may be equal to the value ELVDD+VTH obtained by adding the threshold voltage VTH of the first transistor T1 to the high power voltage ELVDD. During the compensation period P2, each of the voltages V_N1 of the first node N1 and V_N2 of the second node N2 can be ELVDD+VTH, and the voltage V_N3 of the third node N3 can be VREF.

[0085] Figure 6 It is used to describe Figure 3 The graph shows the write cycle P3.

[0086] refer to Figure 3 and Figure 6 During the write cycle P3, the data signal DS can have a data voltage VDAT, the write gate signal GW can have an activation voltage level, and each of the compensation gate signal GC, the initialization gate signal GI, and the transmit signal EM can have a deactivation voltage level. During the write cycle P3, the data voltage VDAT can be applied to the third node N3 via the second transistor T2, which is turned on in response to the activation voltage level of the write gate signal GW. Therefore, the voltage V_N3 of the third node N3 can be changed from the reference voltage VREF to the data voltage VDAT. Due to the coupling effect of the first capacitor C1, the voltage V_N1 of the first node N1 during the write cycle P3 can be calculated using mathematical formula 1.

[0087] Mathematical Formula 1

[0088] During the write cycle P3, the voltage V_N1 of the first node N1 can be ELVDD+VTH+VDAT-VREF, the voltage V_N2 of the second node N2 can be ELVDD+VTH, and the voltage V_N3 of the third node N3 can be VDAT.

[0089] Figure 7 It is used to describe Figure 3 The diagram shows the launch period P4.

[0090] refer to Figure 3 and Figure 7 During the transmission cycle P4, the data signal DS can have a reference voltage VREF, the transmission signal EM can have an activation voltage level, and each of the compensation gate signal GC, the initialization gate signal GI, and the write gate signal GW can have a deactivation voltage level. During the transmission cycle P4, a current path can be formed by the first transistor T1 (conducted), the fifth transistor T5 (conducted in response to the activation voltage level of the transmission signal EM), and the light-emitting element EL, forming a line from the power line PL (transmitting the high power voltage ELVDD) to the power line PL (transmitting the low power voltage ELVSS), and a drive current ID can flow through the current path. During the transmission cycle P4, the light-emitting element EL can emit light with a brightness corresponding to the drive current ID. The drive current ID during the transmission cycle P4 can be calculated using mathematical formula 2.

[0091] Mathematical Formula 2

[0092] In mathematical formula 2, K is a proportionality constant. According to mathematical formula 2, the drive current ID can be determined by the data voltage VDAT, and is independent of the threshold voltage VTH of the first transistor T1, and the light-emitting element EL can emit light with a brightness corresponding to the data voltage VDAT during the emission period P4.

[0093] Reference Figures 1 to 7 In the described display device 100 and pixel PX1, pixel PX1 includes a relatively small number of transistors, which allows the area of ​​pixel PX1 to be reduced and the resolution of display device 100 to be increased. Furthermore, pixel PX1 compensates for the threshold voltage VTH of the driving transistor (first transistor T1) by means of a diode connection, thereby relatively improving the image quality of display device 100.

[0094] Figure 8 This is a circuit diagram showing pixel PX1-1 according to some embodiments. Figure 8 The pixel PX1-1 can be Figure 1 An example of a pixel PX.

[0095] refer to Figure 3 and Figure 8Pixel PX1-1 can receive a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a transmit signal EM, a data signal DS, a high power voltage ELVDD, and a low power voltage ELVSS. Pixel PX1-1 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1. Except for excluding the second capacitor C2, Figure 8 The pixel PX1-1 can be with Figure 2 The pixels PX1 are the same or substantially the same or similar.

[0096] Figure 9 This is a circuit diagram showing pixel PX1-2 according to some embodiments. Figure 9 The pixel PX1-2 can be Figure 1 An example of a pixel PX. Although Figure 9 Various components in pixels PX1-2 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, pixels may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0097] Figure 10 It is shown Figure 9 Timing diagrams for example signals DS, GC, GI, GW, EM, and GB.

[0098] refer to Figure 9 and Figure 10 Pixel PX1-2 can receive write gate signal GW, compensation gate signal GC, initialization gate signal GI, bypass gate signal GB, transmit signal EM, data signal DS, high power voltage ELVDD, and low power voltage ELVSS. Figure 1 The gate signal GS may include a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, and a bypass gate signal GB. Pixel PX1-2 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. In addition to including the sixth transistor T6, Figure 9 The pixel PX1-2 can be with Figure 2 The pixels PX1 are the same or substantially the same or similar.

[0099] The sixth transistor T6 can transmit a low-power voltage ELVSS to the first terminal of the light-emitting element EL in response to the bypass gate signal GB. The sixth transistor T6 may include a gate for receiving the bypass gate signal GB, a first terminal for receiving the low-power voltage ELVSS, and a second terminal connected to the first terminal of the light-emitting element EL.

[0100] According to some implementation methods, such as Figure 9 As shown, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be a p-type transistor (e.g., a PMOS transistor). According to some embodiments, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be an n-type transistor (e.g., an NMOS transistor).

[0101] The transmit signal EM may have a deactivation voltage level (e.g., 10V or about 10V) during the initialization period P1, the compensation period P2, and the write period P3, and may have an activation voltage level (e.g., -10V or about -10V) during the transmit period P4.

[0102] The bypass gate signal GB may have an activation voltage level (e.g., -10V or about -10V) during the initialization period P1, the compensation period P2, and the write period P3, and may have a deactivation voltage level (e.g., 10V or about 10V) during the transmit period P4.

[0103] During initialization period P1, the data signal DS may have a reference voltage VREF, and each of the compensation gate signal GC, the initialization gate signal GI, the write gate signal GW, and the bypass gate signal GB may have an activation voltage level, while the transmit signal EM may have a deactivation voltage level. During initialization period P1, the reference voltage VREF may be applied to the third node N3 via a second transistor T2 that is turned on in response to the activation voltage level of the write gate signal GW. During initialization period P1, the reference voltage VREF may be applied to the first node N1 via a fourth transistor T4 that is turned on in response to the activation voltage level of the initialization gate signal GI, and the reference voltage VREF may be applied to the second node N2 via a third transistor T3 that is turned on in response to the activation voltage level of the compensation gate signal GC. During initialization period P1, the low power voltage ELVSS may be applied to the first terminal of the light-emitting element EL via a sixth transistor T6 that is turned on in response to the activation voltage level of the bypass gate signal GB.

[0104] Figure 11 This is a circuit diagram showing pixels PX1-3 according to some embodiments. Figure 11The pixel PX1-3 can be Figure 1 An example of a pixel PX. Although Figure 11 Various components in pixels PX1-3 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, pixels may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0105] refer to Figure 10 and Figure 11 Pixel PX1-3 can receive the write gate signal GW, the compensation gate signal GC, the initialization gate signal GI, the bypass gate signal GB, the transmit signal EM, the data signal DS, the initialization voltage VINIT, the high power voltage ELVDD, and the low power voltage ELVSS. Pixel PX1-3 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. Except for the sixth transistor T6, which transmits the initialization voltage VINIT, Figure 11 The pixel PX1-3 can be with Figure 9 The pixels PX1-2 are the same or substantially the same or similar.

[0106] The sixth transistor T6 can transmit an initialization voltage VINIT to the first terminal of the light-emitting element EL in response to the bypass gate signal GB. The sixth transistor T6 may include a gate for receiving the bypass gate signal GB, a first terminal for receiving the initialization voltage VINIT, and a second terminal connected to the first terminal of the light-emitting element EL.

[0107] The voltage level of the initialization voltage VINIT can vary depending on the color of the light emitted by the light-emitting element EL. According to some embodiments, the voltage levels of the initialization voltage VINIT received by pixels PX1-3 including a light-emitting element EL emitting red light, the voltage levels of the initialization voltage VINIT received by pixels PX1-3 including a light-emitting element EL emitting green light, and the voltage levels of the initialization voltage VINIT received by pixels PX1-3 including a light-emitting element EL emitting blue light can be different from each other.

[0108] Figure 12 This is a circuit diagram showing pixels PX1-4 according to some embodiments. Figure 12 The pixels PX1-4 can be Figure 1 An example of a pixel PX. Although Figure 12Various components in pixels PX1-4 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, pixels may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0109] refer to Figure 3 and Figure 12 Pixel PX1-4 can receive a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a transmit signal EM, a data signal DS, a high power voltage ELVDD, and a low power voltage ELVSS. Pixel PX1-4 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Except for the location of the second capacitor C2, Figure 12 The pixel PX1-4 can be with Figure 2 The pixels PX1 are the same or substantially the same or similar.

[0110] The second capacitor C2 can be connected between the first node N1 and the power line PL. The second capacitor C2 may include a first terminal connected to the first node N1 and a second terminal connected to the power line PL.

[0111] During the write cycle P3, the data voltage VDAT can be applied to the third node N3 via the second transistor T2, which is turned on in response to the activation voltage level of the write gate signal GW. Therefore, the voltage of the third node N3 can be changed from the reference voltage VREF to the data voltage VDAT. Due to the coupling effect of the first capacitor C1, the voltage V_N1 of the first node N1 during the write cycle P3 can be calculated using mathematical formula 3.

[0112] Mathematical Formula 3

[0113] Figure 13 This is a circuit diagram showing a pixel PX2 according to some embodiments. Figure 13 The pixel PX2 can be Figure 1 An example of a pixel PX. Although Figure 13 Various components in a pixel PX2 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0114] refer to Figure 3 and Figure 13Pixel PX2 can receive a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a transmit signal EM, a data signal DS, a high power voltage ELVDD, and a low power voltage ELVSS. Pixel PX2 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Except for the location of the fourth transistor T4, Figure 13 The pixel PX2 can be with Figure 2 The pixels PX1 are the same or substantially the same or similar.

[0115] The fourth transistor T4 can transmit a reference voltage VREF to the second node N2 in response to the initialization gate signal GI. The fourth transistor T4 can also connect the data line DL, which transmits a data signal DS with the reference voltage VREF, to the second node N2 in response to the initialization gate signal GI. The fourth transistor T4 may include a gate for receiving the initialization gate signal GI, a first terminal connected to the data line DL, and a second terminal connected to the second node N2.

[0116] During initialization cycle P1, the reference voltage VREF can be applied to the third node N3 via the second transistor T2, which is turned on in response to the activation voltage level of the write gate signal GW. During initialization cycle P1, the reference voltage VREF can be applied to the second node N2 via the fourth transistor T4, which is turned on in response to the activation voltage level of the initialization gate signal GI; the reference voltage VREF can be applied to the first node N1 via the third transistor T3, which is turned on in response to the activation voltage level of the compensation gate signal GC; and the reference voltage VREF can be applied to the first terminal of the light-emitting element EL via the fifth transistor T5, which is turned on in response to the activation voltage level of the transmit signal EM.

[0117] Figure 14 This is a circuit diagram showing pixel PX2-1 according to some embodiments. Figure 14 The pixel PX2-1 can be Figure 1 An example of a pixel PX. Although Figure 14 Various components in a pixel PX2-1 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0118] refer to Figure 3 and Figure 14Pixel PX2-1 can receive a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a transmit signal EM, a data signal DS, a high power voltage ELVDD, and a low power voltage ELVSS. Pixel PX2-1 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1. Except for excluding the second capacitor C2, Figure 14 The pixel PX2-1 can be with Figure 13 The pixels PX2 are the same or substantially the same or similar.

[0119] Figure 15 This is a circuit diagram showing pixel PX2-2 according to some embodiments. Figure 15 The pixel PX2-2 can be Figure 1 An example of a pixel PX. Although Figure 15 Various components in a pixel PX2-2 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0120] refer to Figure 10 and Figure 15 Pixel PX2-2 can receive the write gate signal GW, the compensation gate signal GC, the initialization gate signal GI, the bypass gate signal GB, the transmit signal EM, the data signal DS, the high power voltage ELVDD, and the low power voltage ELVSS. Pixel PX2-2 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. In addition to including the sixth transistor T6, Figure 15 The pixel PX2-2 can be with Figure 13 The pixels PX2 are the same or substantially the same or similar.

[0121] The sixth transistor T6 can transmit a low-power voltage ELVSS to the first terminal of the light-emitting element EL in response to the bypass gate signal GB. The sixth transistor T6 may include a gate for receiving the bypass gate signal GB, a first terminal for receiving the low-power voltage ELVSS, and a second terminal connected to the first terminal of the light-emitting element EL.

[0122] Figure 16 This is a circuit diagram showing pixel PX2-3 according to some embodiments. Figure 16 The pixel PX2-3 can be Figure 1 An example of a pixel PX. Although Figure 16Various components in pixels PX2-3 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, pixels may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0123] refer to Figure 10 and Figure 16 Pixel PX2-3 can receive the write gate signal GW, the compensation gate signal GC, the initialization gate signal GI, the bypass gate signal GB, the transmit signal EM, the data signal DS, the initialization voltage VINIT, the high power voltage ELVDD, and the low power voltage ELVSS. Pixel PX2-3 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. Except for the sixth transistor T6, which transmits the initialization voltage VINIT, Figure 16 The pixel PX2-3 can be compared with Figure 15 The pixels PX2-2 are the same or substantially the same or similar.

[0124] The sixth transistor T6 can transmit an initialization voltage VINIT to the first terminal of the light-emitting element EL in response to the bypass gate signal GB. The sixth transistor T6 may include a gate for receiving the bypass gate signal GB, a first terminal for receiving the initialization voltage VINIT, and a second terminal connected to the first terminal of the light-emitting element EL.

[0125] Figure 17 This is a circuit diagram showing a pixel PX2-4 according to some embodiments. Figure 17 The pixel PX2-4 can be Figure 1 An example of a pixel PX. Although Figure 17 Various components in pixels PX2-4 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, pixels may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0126] refer to Figure 3 and Figure 17 Pixel PX2-4 can receive a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a transmit signal EM, a data signal DS, a high power voltage ELVDD, and a low power voltage ELVSS. Pixel PX2-4 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Except for the location of the second capacitor C2, Figure 17The pixel PX2-4 can be compared with Figure 13 The pixels PX2 are the same or substantially the same or similar.

[0127] The second capacitor C2 can be connected between the first node N1 and the power line PL. The second capacitor C2 may include a first terminal connected to the first node N1 and a second terminal connected to the power line PL.

[0128] Figure 18 This is a circuit diagram showing a pixel PX2-5 according to some embodiments. Figure 18 The pixel PX2-5 can be Figure 1 An example of a pixel PX. Although Figure 18 Various components in pixels PX2-5 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, pixels may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0129] refer to Figure 3 and Figure 18 Pixel PX2-5 can receive the write gate signal GW, the compensation gate signal GC, the initialization gate signal GI, the transmit signal EM, the data signal DS, the reference voltage VREF, the high power voltage ELVDD, and the low power voltage ELVSS. Pixel PX2-5 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Except for the connection of the fourth transistor T4, Figure 18 The pixel PX2-5 can be compared with Figure 13 The pixels PX2 are the same or substantially the same or similar.

[0130] The fourth transistor T4 can transmit a reference voltage VREF to the second node N2 in response to the initialization gate signal GI. The fourth transistor T4 can also connect the reference line RL for transmitting the reference voltage VREF to the second node N2 in response to the initialization gate signal GI. The fourth transistor T4 may include a gate for receiving the initialization gate signal GI, a first terminal connected to the reference line RL, and a second terminal connected to the second node N2.

[0131] Figure 19 This is a circuit diagram showing a pixel PX3 according to some embodiments. Figure 19 The pixel PX3 can be Figure 1 An example of a pixel PX. Although Figure 19Various components in a pixel PX3 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0132] refer to Figure 3 and Figure 19 Pixel PX3 can receive a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a transmit signal EM, a data signal DS, a high power voltage ELVDD, and a low power voltage ELVSS. Pixel PX3 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Except for the location of the fourth transistor T4, Figure 19 The pixel PX3 can be with Figure 2 The pixels PX1 are the same or substantially the same or similar.

[0133] The fourth transistor T4 can connect the second node N2 to the third node N3 in response to the initialization gate signal GI. The fourth transistor T4 may include a gate for receiving the initialization gate signal GI, a first terminal connected to the third node N3, and a second terminal connected to the second node N2.

[0134] During the initialization cycle P1, the reference voltage VREF can be applied to the third node N3 through the second transistor T2, which is turned on in response to the activation voltage level of the write gate signal GW; the reference voltage VREF can be applied to the second node N2 through the fourth transistor T4, which is turned on in response to the activation voltage level of the initialization gate signal GI; the reference voltage VREF can be applied to the first node N1 through the third transistor T3, which is turned on in response to the activation voltage level of the compensation gate signal GC; and the reference voltage VREF can be applied to the first terminal of the light-emitting element EL through the fifth transistor T5, which is turned on in response to the activation voltage level of the emission signal EM.

[0135] Figure 20 This is a circuit diagram showing pixel PX3-1 according to some embodiments. Figure 20 The pixel PX3-1 can be Figure 1 An example of a pixel PX. Although Figure 20 Various components in a pixel PX3-1 according to some embodiments are shown, but the embodiments of this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of the embodiments of this disclosure.

[0136] refer to Figure 3 and Figure 20 Pixel PX3-1 can receive a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a transmit signal EM, a data signal DS, a high power voltage ELVDD, and a low power voltage ELVSS. Pixel PX3-1 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a first capacitor C1. Except for excluding the second capacitor C2, Figure 20 The pixel PX3-1 can be with Figure 19 The pixels are the same as, substantially the same as, or similar to the PX3 pixels.

[0137] Figure 21 This is a circuit diagram showing a pixel PX3-2 according to some embodiments. Figure 21 The pixel PX3-2 can be Figure 1 An example of a pixel PX. Although Figure 21 Various components in a pixel PX3-2 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0138] refer to Figure 10 and Figure 21 Pixel PX3-2 can receive the write gate signal GW, the compensation gate signal GC, the initialization gate signal GI, the bypass gate signal GB, the transmit signal EM, the data signal DS, the high power voltage ELVDD, and the low power voltage ELVSS. Pixel PX3-2 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. In addition to including the sixth transistor T6, Figure 21 The pixel PX3-2 can be with Figure 19 The pixels are the same as, substantially the same as, or similar to the PX3 pixels.

[0139] The sixth transistor T6 can transmit a low-power voltage ELVSS to the first terminal of the light-emitting element EL in response to the bypass gate signal GB. The sixth transistor T6 may include a gate for receiving the bypass gate signal GB, a first terminal for receiving the low-power voltage ELVSS, and a second terminal connected to the first terminal of the light-emitting element EL.

[0140] Figure 22 This is a circuit diagram showing pixel PX3-3 according to some embodiments. Figure 22 The pixel PX3-3 can be Figure 1 An example of a pixel PX. Although Figure 22Various components in pixel PX3-3 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, a pixel may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0141] refer to Figure 10 and Figure 22 Pixel PX3-3 can receive the write gate signal GW, the compensation gate signal GC, the initialization gate signal GI, the bypass gate signal GB, the transmit signal EM, the data signal DS, the initialization voltage VINIT, the high power voltage ELVDD, and the low power voltage ELVSS. Pixel PX3-3 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2. Except for the sixth transistor T6, which transmits the initialization voltage VINIT, Figure 22 The pixel PX3-3 can be with Figure 21 The pixels of PX3-2 are the same or substantially the same or similar.

[0142] The sixth transistor T6 can transmit an initialization voltage VINIT to the first terminal of the light-emitting element EL in response to the bypass gate signal GB. The sixth transistor T6 may include a gate for receiving the bypass gate signal GB, a first terminal for receiving the initialization voltage VINIT, and a second terminal connected to the first terminal of the light-emitting element EL.

[0143] Figure 23 This is a circuit diagram showing pixel PX3-4 according to some embodiments. Figure 23 The pixel PX3-4 can be Figure 1 An example of a pixel PX. Although Figure 23 Various components in pixels PX3-4 according to some embodiments are shown, but the embodiments according to this disclosure are not limited thereto, and according to various embodiments, pixels may include additional or fewer components without departing from the spirit and scope of the embodiments according to this disclosure.

[0144] refer to Figure 3 and Figure 23 Pixel PX3-4 can receive a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI, a transmit signal EM, a data signal DS, a high power voltage ELVDD, and a low power voltage ELVSS. Pixel PX3-4 may include a light-emitting element EL, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, and a second capacitor C2. Except for the location of the second capacitor C2, Figure 23The pixel PX3-4 can be compared with Figure 19 The pixels are the same as, substantially the same as, or similar to the PX3 pixels.

[0145] The second capacitor C2 can be connected between the first node N1 and the power line PL. The second capacitor C2 may include a first terminal connected to the first node N1 and a second terminal connected to the power line PL.

[0146] Figure 24 This is a block diagram illustrating an electronic device according to some embodiments.

[0147] refer to Figure 24 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0148] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0149] Memory 13 can store data information required for the operation of processor 12 or display module 11. When processor 12 executes an application stored in memory 13, Figure 1 Input image data IMD1 and Figure 1 The input control signal CNT0 can be transmitted to the display module 11, and the display module 11 can output image information based on the input image data IMD1 and the input control signal CNT0.

[0150] The power module 14 may include a power supply module such as a power adapter, a battery device, etc., and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0151] According to some embodiments described above, at least one of the components of the electronic device 10 described above may be included in Figure 1 The display device 100 may include some of the individual modules that are functionally included in a single module, while other modules may be disposed separately from the display device 100. For example, the display device 100 may include a display module 11, and the processor 12, memory 13, and power module 14 may be disposed as other devices within the electronic device 10 besides the display device 100.

[0152] Figure 25 This is a diagram illustrating an electronic device according to some embodiments.

[0153] refer to Figure 25Electronic devices that utilize display devices according to some embodiments may include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices 10_3 including display modules such as car dashboards, center consoles, central information displays (CIDs) arranged on dashboards, and interior mirror displays.

[0154] The display device according to some embodiments can be applied to display devices including computers, laptops, mobile phones, smartphones, smartboards, smartwatches, PMPs, PDAs, MP3 players, etc.

[0155] Although aspects of display devices, pixels, and electronic devices according to some embodiments have been described with reference to the accompanying drawings, the embodiments shown are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the appended claims and their equivalents.

Claims

1. A display device, comprising: Display panel, including pixels; A gate driver configured to provide a write gate signal, a compensation gate signal, and an initialization gate signal to each of the pixels; A transmitter driver configured to provide a transmitter signal to each of the pixels; as well as A data driver, configured to provide a data signal to each of the pixels, Each of the pixels includes: A light-emitting element includes a first terminal and a second terminal configured to receive a low power voltage; The first transistor includes a gate connected to a first node, a first terminal configured to receive a high power voltage having a voltage level higher than the low power voltage, and a second terminal connected to a second node. The second transistor is configured to transmit the data signal to the third node in response to the write gate signal; A third transistor is configured to connect the first node to the second node in response to the compensation gate signal; A fourth transistor is configured to transmit a reference voltage to the first node or the second node or to connect the second node to the third node in response to the initialization gate signal; A fifth transistor, configured to connect the second node to the first terminal of the light-emitting element in response to the emission signal; and A first capacitor is connected between the first node and the third node.

2. The display device according to claim 1, wherein, The fourth transistor is configured to connect a data line configured to transmit the data signal having the reference voltage to the first node in response to the initialization gate signal.

3. The display device according to claim 1, wherein, During the initialization cycle, the data signal has the reference voltage, and each of the compensation gate signal, the initialization gate signal, the write gate signal, and the transmit signal has an activation voltage level.

4. The display device according to claim 1, wherein, During the compensation period, the data signal has the reference voltage, each of the compensation gate signal and the write gate signal has an activation voltage level, and each of the initialization gate signal and the transmit signal has a deactivation voltage level.

5. The display device according to claim 1, wherein, During the write cycle, the data signal has a data voltage, the write gate signal has an activation voltage level, and each of the compensation gate signal, the initialization gate signal, and the transmit signal has a deactivation voltage level.

6. The display device according to claim 1, wherein, During the transmit cycle, the data signal has the reference voltage, the transmit signal has an activation voltage level, and each of the compensation gate signal, the initialization gate signal, and the write gate signal has a deactivation voltage level.

7. The display device according to claim 1, wherein, Each of the pixels also includes: A second capacitor is connected between the third node and the power line configured to transmit the high power voltage.

8. The display device according to claim 1, wherein, Each of the pixels also includes: A sixth transistor is configured to transmit the low power voltage to the first terminal of the light-emitting element in response to a bypass gate signal.

9. The display device according to claim 8, wherein, The bypass gate signal has an activation voltage level during the initialization cycle, compensation cycle, and write cycle, and a deactivation voltage level during the transmit cycle.

10. The display device according to claim 1, wherein, Each of the pixels also includes: The sixth transistor is configured to transmit an initialization voltage to the first terminal of the light-emitting element in response to a bypass gate signal.

11. The display device according to claim 1, wherein, Each of the pixels also includes: A second capacitor is connected between the first node and the power line configured to transmit the high power voltage.

12. The display device according to claim 1, wherein, The fourth transistor is configured to connect a data line configured to transmit the data signal having the reference voltage to the second node in response to the initialization gate signal.

13. The display device according to claim 1, wherein, The fourth transistor is configured to connect a reference line configured to transmit the reference voltage to the second node in response to the initialization gate signal.

14. The display device according to claim 1, wherein, The fourth transistor is configured to connect the second node to the third node in response to the initialization gate signal.

15. Pixels, including: A light-emitting element includes a first terminal and a second terminal configured to receive a low power voltage; The first transistor includes a gate connected to a first node, a first terminal configured to receive a high power voltage having a voltage level higher than the low power voltage, and a second terminal connected to a second node. The second transistor is configured to transmit a data signal to the third node in response to a write gate signal; A third transistor is configured to connect the first node to the second node in response to a compensation gate signal; A fourth transistor is configured to transmit a reference voltage to the first node or the second node or to connect the second node to the third node in response to an initialization gate signal; A fifth transistor is configured to connect the second node to the first terminal of the light-emitting element in response to an emission signal; as well as A first capacitor is connected between the first node and the third node.

16. The pixel according to claim 15, wherein, The fourth transistor is configured to connect a data line configured to transmit the data signal having the reference voltage to the first node in response to the initialization gate signal.

17. The pixel of claim 15, further comprising: A second capacitor is connected between the third node and the power line configured to transmit the high power voltage.

18. The pixel according to claim 15, wherein, The fourth transistor is configured to connect a data line configured to transmit the data signal having the reference voltage to the second node in response to the initialization gate signal.

19. The pixel according to claim 15, wherein, The fourth transistor is configured to connect the second node to the third node in response to the initialization gate signal.

20. Electronic devices, including: The processor is configured to generate input image data; A display device is configured to display an image based on the input image; as well as The power module is connected to the processor and the display device. The display device includes: Display panel, including pixels; A gate driver configured to provide a write gate signal, a compensation gate signal, and an initialization gate signal to each of the pixels; A transmitter driver configured to provide a transmitter signal to each of the pixels; and A data driver, configured to provide a data signal to each of the pixels, and Each of the pixels includes: A light-emitting element includes a first terminal and a second terminal configured to receive a low power voltage; The first transistor includes a gate connected to a first node, a first terminal configured to receive a high power voltage having a voltage level higher than the low power voltage, and a second terminal connected to a second node. The second transistor is configured to transmit the data signal to the third node in response to the write gate signal; A third transistor is configured to connect the first node to the second node in response to the compensation gate signal; A fourth transistor is configured to transmit a reference voltage to the first node or the second node or to connect the second node to the third node in response to the initialization gate signal; A fifth transistor, configured to connect the second node to the first terminal of the light-emitting element in response to the emission signal; and A first capacitor is connected between the first node and the third node.

Images