Display device and display panel

Abstract

The disclosure provides a display device having a structure in which: a plurality of pixels are disposed in a display panel, each pixel including first, second, and third sub-pixels configured to emit light of different colors; at least two adjacent pixels among the plurality of pixels in a first direction are connected to the same data line; and at least two sub-pixels in one pixel are connected to different gate lines, thereby enabling the number of data channels to be effectively reduced.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0053489, filed on April 24, 2025, with the Korean Intellectual Property Office, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0002] This disclosure relates to electronic devices having a display, and more specifically, to display panels and display devices including display panels. Background Technology

[0003] Among various types of display devices, organic light-emitting diode (OLED) based organic light-emitting display devices have advantages obtained through self-emissive characteristics, such as short response time, high contrast, high luminous efficiency, brightness, and wide viewing angle, and such display devices are becoming increasingly attractive.

[0004] The demand for higher resolution and larger screen sizes in display devices is rapidly increasing, and to meet this demand, the number of data channels in data drive circuits is also constantly increasing.

[0005] However, increasing the number of data channels used to supply data voltage in a display device leads to increased manufacturing costs for the data drive circuitry and an increase in the size of the bezel area connected to the data channels. Therefore, it is necessary to reduce the number of data channels. Summary of the Invention

[0006] One or more aspects of this disclosure can provide a display panel and display device comprising a structure in which a pixel is configured with three sub-pixels and the arrangement and interconnection of multiple pixels and multiple data lines are optimized or improved, thereby enabling a more efficient reduction in the number of data channels.

[0007] One or more aspects of this disclosure may provide a display panel and display device, which include a structure in which the connection between white subpixels and white data lines and the connection between non-white subpixels and non-white data lines are configured differently, thereby enabling a more efficient reduction in the number of data channels.

[0008] One or more aspects of this disclosure may provide a display panel and display device comprising a structure in which white subpixels are arranged at equal intervals, thereby enabling or improving brightness uniformity and driving at low power.

[0009] One or more aspects of this disclosure can provide display panels and display devices that include a structure in which the number of data channels is minimized or reduced, thereby enabling lightweight and low manufacturing costs while ensuring space margins.

[0010] One or more aspects of this disclosure may provide a display panel and display device that includes a structure for sensing multiple colors in a single scan operation, thereby enabling a reduction in the time required to sense subpixels.

[0011] The aspects, examples, and embodiments provided in this disclosure are not limited to the foregoing description, and additional aspects, examples, and embodiments provided in this disclosure will become apparent to those skilled in the art from the following description.

[0012] According to one or more example embodiments of this disclosure, a display device may include a display panel comprising a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction intersecting the first direction, and a plurality of pixels, each pixel including a first sub-pixel, a second sub-pixel, and a third sub-pixel. In one or more aspects, one of the plurality of pixels may be connected to the same data line as at least one other pixel, said at least one other pixel being adjacent to said pixel in the first direction.

[0013] According to one or more example embodiments of the present disclosure, a display panel may include: a plurality of pixels, each pixel including a first sub-pixel, a second sub-pixel, and a third sub-pixel configured to emit light of different colors from each other, and the plurality of pixels being connected to a first gate line and a second gate line; a first color data line extending across the first, second, and third pixels of the plurality of pixels; a second color data line extending across the fourth, fifth, and sixth pixels of the plurality of pixels; a first white data line extending across the first and second pixels of the plurality of pixels; a second white data line extending across the third and fourth pixels of the plurality of pixels; and a third white data line extending across the fifth and sixth pixels of the plurality of pixels.

[0014] According to one or more example embodiments of this disclosure, a display panel may include: a plurality of gate lines extending in a first direction; a plurality of data lines extending in a second direction intersecting the first direction; and a plurality of pixels, each of the plurality of pixels including a plurality of sub-pixels, wherein a first pixel of the plurality of pixels is connected to the same data line as at least one other pixel adjacent to it in the first direction.

[0015] According to one or more aspects of this disclosure, a display panel and display device may be provided that can more effectively reduce the number of data channels based on a structure in which one pixel is configured with three sub-pixels and the arrangement and interconnection of multiple pixels and multiple data lines are optimized or improved.

[0016] According to one or more aspects of this disclosure, a display panel and display device may be provided that can more effectively reduce the number of data channels based on a structure in which the connections between white subpixels and white data lines and the connections between non-white subpixels and non-white data lines are configured differently.

[0017] According to one or more aspects of this disclosure, a display panel and display device may be provided that are capable of ensuring or improving brightness uniformity and being driven at low power based on a structure in which white subpixels are arranged at equal intervals.

[0018] According to one or more aspects of this disclosure, display panels and display devices can be provided that offer light weight and low manufacturing costs while ensuring space margins, based on a structure where the number of data channels is minimized or reduced.

[0019] According to one or more aspects of this disclosure, a display panel and display device may be provided that are capable of reducing the time required to sense subpixels based on a structure that senses multiple colors in a single scan operation.

[0020] The effects or advantages derived from the aspects, examples and embodiments described herein are not limited thereto, and additional effects or advantages will become apparent to those skilled in the art from the following description. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated into and constitute a part of this disclosure, illustrate various aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure. In the drawings:

[0022] Figure 1 The system configuration of the device is shown as an example of various aspects of this disclosure;

[0023] Figure 2 The illustration shows the configuration of example subpixels included in a display device according to various aspects of this disclosure;

[0024] Figure 3 The configuration of example pixels included in a display device according to various aspects of this disclosure is shown;

[0025] Figure 4 and Figure 5 An example arrangement of high-voltage lines included in a display device according to various aspects of this disclosure is shown;

[0026] Figure 6 An example arrangement of pixels included in a display device according to various aspects of this disclosure is shown; and

[0027] Figures 7 to 10An example driving sequence of subpixels included in pixels in a display device is shown according to various aspects of this disclosure. Detailed Implementation

[0028] Reference will now be made in detail to exemplary embodiments of this disclosure, examples or aspects of which may be illustrated in the accompanying drawings. In the following description, the structures, implementations, methods, and operations described herein are not limited to the specific examples, aspects, and embodiments set forth herein, and may be varied as is known in the art, unless otherwise stated. Unless otherwise stated, the same reference numerals always denote the same elements. The names of the corresponding elements used in the following explanation are chosen solely for ease of writing and may therefore differ from those used in actual products. The advantages and features of this disclosure and methods of implementation thereof will be elucidated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough and complete enough to assist those skilled in the art in a more complete understanding of the scope of this disclosure. Furthermore, the scope of protection of this disclosure may be defined by the claims and their equivalents. In the following description, detailed descriptions of relevant known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure aspects of this disclosure. The shapes, dimensions, ratios, angles, quantities, etc., shown in the drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. Terms such as “including,” “having,” “comprising,” “forming,” “composed of,” and “formed by” as used herein are generally intended to allow for the addition of additional components unless these terms are used in conjunction with more specific terms such as “only.” As used herein, the singular form is intended to include the plural form, and vice versa, unless the context clearly indicates otherwise.

[0029] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to refer to one element separately from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] When the specification describes a first element as "connected or coupled to" a second element, "contacting" a second element, or "overlapping" with a second element, it should be interpreted that not only is the first element "directly connected or coupled to" a second element, "directly contacting" a second element, or "directly overlapping" with a second element, but a third element may also be "inserted" between the first and second elements, or the first and second elements may be "connected or coupled," "contacting," or "overlapping" with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled," "contacting," or "overlapping" with each other.

[0031] When describing positional relationships, such as when using terms like "on top of," "above," "below," "over," "below," "next to," or "next to" to describe the positional relationship between two parts, one or more other parts may be located between the two parts, unless more restrictive terms such as "immediately," "directly," or "nearly" are used. For example, when an element or layer is positioned "on" another element or layer, a third element or layer may be inserted between them. Furthermore, the terms "left," "right," "top," "bottom," "down," "up," "upper," "lower," etc., refer to any frame of reference.

[0032] Furthermore, when referring to any size, relative size, etc., the numerical or corresponding information of an element or feature (e.g., level, range, etc.) should be considered to include tolerances or error ranges that can be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description of such tolerances or error ranges is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0033] In the following description, various exemplary aspects of this disclosure are described in detail with reference to the accompanying drawings. Reference numerals for elements in each drawing may indicate the same element in other drawings, and unless otherwise stated, the same reference numerals may refer to the same element. Identical or similar elements may be represented by the same reference numerals, even if they are depicted in different drawings. Furthermore, for ease of description, the scale, dimensions, size, and thickness of each element shown in the drawings may differ from the actual scale, dimensions, size, and thickness; therefore, aspects of this disclosure are not limited to the scale, dimensions, size, and thickness shown in the drawings.

[0034] Figure 1 The system configuration of the device is shown as an example of various aspects of this disclosure.

[0035] like Figure 1As shown, in one or more example embodiments, the display device 100 may include a display panel 110 and at least one driving circuit for driving the display panel 110.

[0036] At least one drive circuit may include a data drive circuit 120 and a gate drive circuit 130, and further include a controller 140 configured to control the data drive circuit 120 and the gate drive circuit 130. In one or more aspects, at least one drive circuit may also include a power management circuit configured to provide a drive voltage.

[0037] The display panel 110 may include multiple sub-pixels SP connected to multiple data lines DL and multiple gate lines GL.

[0038] In one or more aspects, multiple gate lines GL may extend in a first direction (e.g., row direction), and multiple data lines DL may extend in a second direction (e.g., column direction) intersecting the first direction.

[0039] For example, multiple sub-pixels SP may include multiple white sub-pixels configured to emit white light, and multiple non-white sub-pixels configured to emit light of a different color than white.

[0040] For example, multiple non-white sub-pixels may include one or more red sub-pixels configured to emit red light, one or more green sub-pixels configured to emit green light, and one or more blue sub-pixels configured to emit blue light.

[0041] However, the aspects of this disclosure are not limited thereto. For example, the plurality of subpixels may include one or more subpixels configured to emit light other than white, red, green and blue, such as magenta, yellow, cyan, etc.

[0042] In one or more aspects, a plurality of pixels may be disposed in the display panel 110, and each of the plurality of pixels may include a plurality of sub-pixels SP configured to emit a corresponding color. For example, the plurality of sub-pixels SP configured to emit different colors may be, for example, three sub-pixels adjacent to each other in a first direction.

[0043] In the following text, for ease of description, the three sub-pixels included in a pixel may be referred to as the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0044] In one or more aspects, any one of the multiple pixels can be connected to the same data line DL as one or more other pixels set in a first direction relative to a pixel.

[0045] Furthermore, at least two sub-pixels, including the first, second, and third sub-pixels of any one of the multiple pixels, can be connected to corresponding gate lines GL. For example, two gate lines GL can be provided in each of the multiple pixels.

[0046] The data driving circuit 120 can be a circuit for driving multiple data lines DL, and can provide data signals to the multiple data lines DL. The gate driving circuit 130 can be a circuit for driving multiple gate lines GL, and can provide gate signals to the multiple gate lines GL.

[0047] The controller 140 can provide a data control signal DCS to the data drive circuit 120 to control the operating time of the data drive circuit 120. The controller 140 can also provide a gate control signal GCS to the gate drive circuit 130 to control the operating time of the gate drive circuit 130.

[0048] The controller 140 can control the initiation of pixel scanning operations according to a corresponding time set in each frame. The controller 140 can convert image data received from external devices or systems (e.g., host system 150) into a data signal form that can be read by the data driving circuit 120, and supply the converted image data DATA to the data driving circuit 120. The controller 140 can control the data driving at a time set for scanning one or more corresponding pixels.

[0049] The controller 140 can receive display drive control signals and image data from external devices or systems (e.g., host system 150). For example, the display drive control signals may include a vertical sync signal (VSYNC), a horizontal sync signal (HSYNC), an input data enable signal (DE), a clock signal (CLK), etc. The controller 140 can generate several types of control signals based on the display drive control signals, such as a data drive control signal DCS and a gate drive control signal GCS, and output the generated control signals (DCS and GCS) to the data drive circuit 120 and the gate drive circuit 130.

[0050] In order to control the gate drive circuit 130, the controller 140 can output several types of gate control signals GCS, such as gate start pulse (GSP), gate shift clock (GSC), gate output enable signal (GOE), etc.

[0051] In order to control the data drive circuit 120, the controller 140 can output several types of data control signals DCS, such as source start pulse (SSP), source sampling clock (SSC), source output enable (SOE) signal, etc.

[0052] The controller 140 can be implemented in a component separate from the data drive circuit 120, or integrated with the data drive circuit 120, such that the controller 140 and the data drive circuit 120 can be implemented in a single integrated circuit.

[0053] The data drive circuit 120 can drive multiple data lines DL by receiving image data DATA from the controller 140 and providing data voltage to the multiple data lines DL. The data drive circuit 120 can also be referred to as a source drive circuit.

[0054] The data drive circuit 120 may include one or more source driver integrated circuits (SDICs).

[0055] In one or more aspects, each source driver integrated circuit (SDIC) may be connected to the display panel 110 in a strip auto-bonding (TAB) structure, or to a conductive pad of a bonding pad such as the display panel 110 in a chip-on-glass (COG) structure or a chip-on-panel (COP) structure, or to the display panel 110 in a chip-on-film (COF) structure.

[0056] The gate drive circuit 130 can output a gate signal with an on-state voltage level or a gate signal with an off-state voltage level under the control of the controller 140. The gate drive circuit 130 can sequentially drive multiple gate lines GL by sequentially providing gate signals with on-state voltage levels to multiple gate lines GL.

[0057] In one or more aspects, the gate drive circuit 130 may be connected to the display panel 110 in a strip auto-bonding (TAB) structure, or to conductive pads such as bonding pads of the display panel 110 in a chip-on-glass (COG) structure or a chip-on-panel (COP) structure, or to the display panel 110 in a chip-on-film (COF) structure. In one or more aspects, the gate drive circuit 130 may be disposed in the non-display area NDA of the display panel 110 in a gate-in-panel (GIP) structure. The gate drive circuit 130 may be disposed on or connected to the substrate SUB. Therefore, in the example where the gate drive circuit 130 is implemented in a GIP structure, the gate drive circuit 130 may be disposed in the non-display area NDA of the substrate SUB. In the example where the gate drive circuit 130 is implemented in a chip-on-glass (COG) structure, a chip-on-film (COF) structure, etc., the gate drive circuit 130 may be connected to the substrate SUB.

[0058] In one or more aspects, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be configured not to overlap with the plurality of sub-pixels SP, or configured to overlap with one or more or all of the plurality of sub-pixels SP.

[0059] When one or more specific gate lines are driven by the gate drive circuit 130, the data drive circuit 120 can convert the image data DATA received from the controller 140 into an analog data voltage and provide the resulting data voltage to multiple data lines DL.

[0060] In one or more aspects, the data driving circuit 120 may be disposed in only one side or one side (e.g., the upper or lower part) of the display panel 110, and / or electrically connected to only one side or one side of the display panel 110, but is not limited thereto. In one or more aspects, depending on the driving scheme, panel design scheme, etc., the data driving circuit 120 may be located in and / or electrically connected to at least two of the two sides or two sides (e.g., the upper and lower parts) of the display panel 110, or four sides or four sides (e.g., the upper, lower, left and right parts) of the display panel 110.

[0061] In one or more aspects, the gate drive circuit 130 may be located in one side or edge (e.g., left or right) of the display panel 110, and / or electrically connected to one side or edge of the display panel 110, but is not limited thereto. In one or more aspects, depending on the driving scheme, panel design, etc., the gate drive circuit 130 may be located in and / or electrically connected to at least two of the following: both sides (e.g., left and right) or all four sides (e.g., top, bottom, left and right) of the display panel 110.

[0062] Controller 140 may be a timing controller used in typical display technologies, or a control device / app capable of additionally performing control functions beyond the typical functions of a timing controller. In one or more embodiments, controller 140 may be one or more other control circuits different from a timing controller, or a circuit or component within a control device / app. Controller 140 may be implemented using various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0063] The controller 140 can be mounted on a printed circuit board, flexible printed circuit, etc., and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 through the printed circuit board, flexible printed circuit, etc.

[0064] In one or more aspects, the display device 100 may be a display including a backlight unit, such as a liquid crystal display, or a self-emitting display, such as an organic light-emitting diode (OLED) display, a quantum dot (QD) display, a micro light-emitting diode (micro LED) display, etc.

[0065] In examples where the display device 100 according to aspects of this disclosure is an OLED display or implemented using an OLED display, each sub-pixel SP may include an OLED as a light-emitting element, the OLED being a self-emissive element. In examples where the display device 100 according to aspects of this disclosure is a QD display or implemented using a QD display, each sub-pixel SP may include a light-emitting element configured with a QD, the QD being a self-emissive semiconductor crystal. In examples where the display device 100 according to aspects of this disclosure is a micro-LED display or implemented using a micro-LED display, each sub-pixel SP may include a micro-LED as a light-emitting element, the micro-LED being a self-emissive element and comprising inorganic materials.

[0066] In one or more aspects, the display panel 110 may have a top-emitting structure, a bottom-emitting structure, or a bidirectional-emitting structure.

[0067] Figure 2 An example subpixel configuration included in a display device 100 according to aspects of this disclosure is shown.

[0068] like Figure 2 As shown, in one or more example embodiments, each sub-pixel SP included in the display device 100 may include a light-emitting element ED and a sub-pixel circuit SPC for driving the light-emitting element ED.

[0069] The subpixel circuit SPC may include a driving transistor DRT for driving the light-emitting element ED, a scanning transistor SCT connected to a first node N1 of the driving transistor DRT, a sensing transistor SENT connected to a second node N2 of the driving transistor DRT, and a storage capacitor Cst for maintaining the voltage of a frame at a constant level.

[0070] The light-emitting element ED may include a pixel electrode PE and a common electrode CE, and may also include a light-emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0071] The pixel electrode PE of the light-emitting element ED can be an electrode set for each sub-pixel SP, and the common electrode CE can be an electrode set for all or one or more sub-pixels SP.

[0072] For example, the pixel electrode PE can be an anode electrode, and the common electrode CE can be a cathode electrode. In another example, the pixel electrode PE can be a cathode electrode, and the common electrode CE can be an anode electrode.

[0073] The common electrode CE of the light-emitting element ED can be connected to a low-voltage line VSSL for delivering low voltages such as low power supply voltages EVSS.

[0074] For example, the light-emitting element ED can be at least one of organic light-emitting diode (OLED), light-emitting diode (LED), or quantum dot (QD) light-emitting element.

[0075] The driving transistor DRT can be a transistor used to drive the light-emitting element ED, and includes a first node N1, a second node N2 and a third node N3.

[0076] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT, and can be electrically connected to the source or drain node of the scanning transistor SCT.

[0077] The second node N2 of the driving transistor DRT can be the source or drain node of the driving transistor DRT, and can be electrically connected to the pixel electrode PE of the light-emitting element ED.

[0078] The third node N3 of the driving transistor DRT can be the drain or source node of the driving transistor DRT, and can be electrically connected to the high voltage line VDDL to deliver high voltage EVDD, such as high power supply voltage.

[0079] The storage capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0080] The scanning transistor SCT can be controlled by a gate signal and connected between the first node N1 of the driving transistor DRT and the data line DL.

[0081] The scanning transistor SCT can be turned on by a gate signal having a turn-on voltage level delivered via the gate line GL, and the data voltage VDATA delivered via the data line DL is transmitted to the first node N1 of the driving transistor DRT.

[0082] The sensing transistor SENT can be controlled by a gate signal and is connected between the second node N2 of the driving transistor DRT and the sensing line SL.

[0083] For example, the sensing transistor SENT can be turned on by a gate signal having a turn-on voltage level delivered through the gate line GL, and control the connection between the sensing line SL and the second node N2 of the driving transistor DRT.

[0084] The sensing transistor SENT can be turned on by a gate signal of the turn-on voltage level and transmits the reference voltage Vref delivered through the sensing line SL to the second node N2 of the driving transistor DRT.

[0085] Furthermore, the sensing transistor SENT can be turned on by a gate signal of the turn-on voltage level, and transmit the voltage of the second node N2 of the driving transistor DRT to the sensing line SL.

[0086] The function of the sensing transistor SENT transmitting the voltage of the second node N2 to the sensing line SL can be used in the operation of driving the sub-pixel SP to sense the unique characteristics of the driving transistor DRT and / or the light-emitting element ED (e.g., the threshold voltage or mobility of the driving transistor DRT). In this example, the voltage transmitted to the sensing line SL can be a voltage used to calculate the unique characteristics of the sub-pixel SP or a voltage reflecting the unique characteristics of the sub-pixel SP.

[0087] like Figure 2 As shown, for example, the scan transistor SCT and the sensing transistor SENT can be connected to the same gate line GL.

[0088] In another example, the scan transistor SCT and the sensing transistor SENT can be connected to different gate lines GL. In this example, the scan transistor SCT can receive a scan gate signal with a turn-on voltage level from a scan gate line of the same type as gate line GL, and control the connection between the data line DL and the first node N1 of the driving transistor DRT. Furthermore, the sensing transistor SENT can receive a sensing gate signal with a turn-on voltage level from a sensing gate line of the same type as gate line GL, and control the connection between the sensing line SL and the second node N2 of the driving transistor DRT.

[0089] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. Here, for ease of description, the discussion is based on an example where each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT is an n-type transistor.

[0090] Figure 2 The structure of the sub-pixel SP shown is merely an example and can be modified in various ways, such as by including one or more additional transistors or one or more additional capacitors.

[0091] Figure 3 The configuration of example pixels included in a display device 100 according to various aspects of this disclosure is shown.

[0092] like Figure 3As shown, in some example embodiments, a plurality of subpixels SP disposed in the display device 100 may include a plurality of first subpixels SP1, a plurality of second subpixels SP2, and a plurality of third subpixels SP3. In one or more aspects, a pixel PXL may be configured with a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 positioned adjacent to each other in a first direction (e.g., the row direction).

[0093] The second sub-pixel SP2 in a pixel PXL can be located between the first sub-pixel SP1 and the third sub-pixel SP3.

[0094] The second sub-pixel SP2 can be a white sub-pixel configured to emit white light.

[0095] For example, the first sub-pixel SP1 could be a sub-pixel configured to emit light of one of a variety of non-white colors, different from white. The third sub-pixel SP3 could be a sub-pixel configured to emit light of another color among a variety of non-white colors.

[0096] For example, when the first sub-pixel SP1 is a red sub-pixel configured to emit red light, the third sub-pixel SP3 can be a green sub-pixel configured to emit green light or a blue sub-pixel configured to emit blue light.

[0097] In another example, when the first sub-pixel SP1 is a green sub-pixel, the third sub-pixel SP3 can be a red sub-pixel or a blue sub-pixel.

[0098] In another example, when the first sub-pixel SP1 is a blue sub-pixel, the third sub-pixel SP3 can be a red sub-pixel or a green sub-pixel.

[0099] At least one of the first sub-pixel SP1, the second sub-pixel SP2, or the third sub-pixel SP3 in a pixel PXL can be designed to have a flip structure, wherein the corresponding light-emitting area EA and the corresponding position of the sub-pixel circuit SPC are flipped.

[0100] like Figure 3 As shown, the second sub-pixel SP2 can be designed with a regular arrangement structure, wherein the corresponding sub-pixel circuit SPC is located below the corresponding light-emitting area EA, and the first sub-pixel SP1 and the third sub-pixel SP3 can be designed with a flip structure, wherein the corresponding sub-pixel circuit SPC is located above the corresponding light-emitting area EA.

[0101] However, the present disclosure is not limited thereto. For example, the second sub-pixel SP2 may be designed to have a flip structure, or at least one of the first sub-pixel SP1 or the third sub-pixel SP3 may be designed to have a regular arrangement structure.

[0102] The display device 100 according to one or more aspects of this disclosure can provide the advantage of preventing or suppressing short circuits between lines by optimizing or improving the arrangement of the data line DL, the high voltage line VDDL, and the sensing line SL.

[0103] Multiple data lines (CDL1 to CDL4) (hereinafter referred to as non-white data lines (CDL1 to CDL4)) for transmitting data voltage to non-white sub-pixels and a single data line WDL (hereinafter referred to as white data line WDL) for transmitting data voltage to white sub-pixels can be set in a pixel PXL.

[0104] For example, the plurality of non-white data lines (CDL1 to CDL4) may include at least one of a data line for delivering data voltage to a red sub-pixel (hereinafter referred to as a red data line), a data line for delivering data voltage to a green sub-pixel (hereinafter referred to as a green data line), or a data line for delivering data voltage to a blue sub-pixel (hereinafter referred to as a blue data line).

[0105] like Figure 3 As shown, the multiple non-white data lines (CDL1 to CDL4) may include a data line disposed in the area adjacent to one side of the first sub-pixel SP1 (hereinafter referred to as the first color data line CDL1) and a data line disposed in the area adjacent to the other side of the first sub-pixel SP1 and one side of the second sub-pixel SP2 (hereinafter referred to as the second color data line CDL2).

[0106] In addition, the multiple non-white data lines (CDL1 to CDL4) may include a data line (hereinafter referred to as the third color data line CDL3) located in the region adjacent to the other side of the second sub-pixel SP2 and the side of the third sub-pixel SP3, and a data line (hereinafter referred to as the fourth color data line CDL4) located in the region adjacent to the other side of the third sub-pixel SP3.

[0107] The white data line WDL can be a data line used to transmit data voltage to the white sub-pixel, and is located in an area adjacent to the other side of the first sub-pixel SP1 and the second sub-pixel SP2. In other words, the white data line WDL can be located in the area between the first sub-pixel SP1 and the second sub-pixel SP2.

[0108] For example, in the region adjacent to the first sub-pixel SP1 on the other side and the second sub-pixel SP2 on one side, the second color data line CDL2 can be set to be adjacent to the first sub-pixel SP1, and the white data line WDL can be set to be adjacent to the second sub-pixel SP2. In other words, the second color data line CDL2 can be set between the first sub-pixel SP1 and the white data line WDL, and the white data line WDL can be set between the second color data line CDL2 and the second sub-pixel SP2.

[0109] like Figure 3 As shown, for example, the first sub-pixel SP1 can be connected to the second color data line CDL2, the second sub-pixel SP2 can be connected to the white data line WDL, and the third sub-pixel SP3 can be connected to the fourth color data line CDL4.

[0110] However, the present disclosure is not limited thereto. For example, the first sub-pixel SP1 may be connected to the first color data line CDL1, or the third sub-pixel SP3 may be connected to the third color data line CDL3.

[0111] The first color data line CDL1 can be set between the high voltage line VDDL and the first sub-pixel SP1, and the fourth color data line CDL4 can be set between the third sub-pixel SP3 and another high voltage line VDDL.

[0112] The high-voltage line VDDL can be connected to each of the first to third sub-pixels (SP1 to SP3) via a first branch line having a zigzag shape. However, aspects of this disclosure are not limited thereto. For example, the first branch line can be formed in a straight line shape.

[0113] like Figure 3 As shown, the sensing line SL can be located in the area adjacent to the other side of the second sub-pixel SP2 and the side of the third sub-pixel SP3. In other words, the sensing line SL can be located in the area between the second sub-pixel SP2 and the third sub-pixel SP3.

[0114] For example, in the region adjacent to the other side of the second sub-pixel SP2 and the side of the third sub-pixel SP3, the sensing line SL can be set to be adjacent to the second sub-pixel SP2, and the third color data line CDL3 can be set to be adjacent to the third sub-pixel SP3.

[0115] like Figure 3 As shown, each of the sensing line SL and the first to third sub-pixels (SP1 to SP3) can be connected to each other by a second branch line extending across the corresponding light-emitting area EA of the first to third sub-pixels (SP1 to SP3).

[0116] For example, the second branch line can be a transparent line and set in a different layer than the multiple data lines (CDL1 to CDL4 and WDL).

[0117] like Figure 3 As shown, two different gate lines (GL1 and GL2) can be set in a pixel PXL, and each of the first to third sub-pixels (SP1 to SP3) can be connected to either of the two different gate lines (GL1 and GL2).

[0118] For example, the first sub-pixel SP1 and the third sub-pixel SP3 can be connected to the first gate line GL1, and the second sub-pixel SP2 can be connected to the second gate line GL2.

[0119] Figure 4 and Figure 5 An example arrangement of high-voltage lines included in a display device 100 according to various aspects of this disclosure is shown.

[0120] like Figure 4 and Figure 5 As shown, in some example embodiments, the plurality of pixels may include a first pixel to a sixth pixel disposed in a first direction, and each of the first pixel to the sixth pixel may include a corresponding first sub-pixel in the first sub-pixel (SP1-1 to SP1-6), a corresponding second sub-pixel in the second sub-pixel (SP2-1 to SP2-6), and a corresponding third sub-pixel in the third sub-pixel (SP3-1 to SP3-6).

[0121] like Figure 4 As shown, the high-voltage line VDDL can be set in the region adjacent to one side of each of the first to sixth pixels and in the region adjacent to the other side of each of the first to sixth pixels. In other words, each of the first to sixth pixels can be set in the region between two adjacent high-voltage lines in the plurality of high-voltage lines VDDL.

[0122] For example, the high voltage line VDDL can be respectively set in the region adjacent to one side of the first sub-pixel SP1-1 in the first pixel, the region adjacent to the other side of the third sub-pixel SP3-1 in the first pixel and one side of the first sub-pixel SP1-2 in the second pixel, the region adjacent to the other side of the third sub-pixel SP3-2 in the second pixel and one side of the first sub-pixel SP1-3 in the third pixel, and the region adjacent to the other side of the third sub-pixel SP3-3 in the third pixel and one side of the first sub-pixel SP1-4 in the fourth pixel.

[0123] In addition, the high voltage line VDDL can be respectively set in the region adjacent to the other side of the third sub-pixel SP3-4 in the fourth pixel and the side of the first sub-pixel SP1-5 in the fifth pixel, the region adjacent to the other side of the third sub-pixel SP3-5 in the fifth pixel and the side of the first sub-pixel SP1-6 in the sixth pixel, and the region adjacent to the other side of the third sub-pixel SP3-6 in the sixth pixel.

[0124] For example, according to Figure 4 In the example display device 100, seven high-voltage lines VDDL can be provided for delivering high-voltage VDDL to the first to sixth pixels.

[0125] For example, according to Figure 5 In the example display device 100, an adjacent pixel can be located in the region adjacent to the third sub-pixel of any one of the first to sixth pixels, and the high voltage line VDDL may not be located in the region between the third sub-pixel of a pixel and the first sub-pixel of an adjacent pixel. In other words, the high voltage line VDDL may also not be located in the region between two adjacent pixels.

[0126] For example, the high voltage line VDDL may not be set in the region adjacent to the other side of the third sub-pixel SP3-1 in the first pixel and the side of the first sub-pixel SP1-2 in the second pixel, the region adjacent to the other side of the third sub-pixel SP3-3 in the third pixel and the side of the first sub-pixel SP1-4 in the fourth pixel, and the region adjacent to the other side of the third sub-pixel SP3-5 in the fifth pixel and the side of the first sub-pixel SP1-6 in the sixth pixel.

[0127] For example, the high voltage line VDDL can be set in the region adjacent to one side of the first sub-pixel SP1-1 in the first pixel, the region adjacent to the other side of the third sub-pixel SP3-2 in the second pixel and one side of the first sub-pixel SP1-3 in the third pixel, the region adjacent to the other side of the third sub-pixel SP3-4 in the fourth pixel and one side of the first sub-pixel SP1-5 in the fifth pixel, and the region adjacent to the other side of the third sub-pixel SP3-6 in the sixth pixel.

[0128] Therefore, according to Figure 5 The example display device 100 can reduce the number of high-voltage lines (VDDL) used to supply high-voltage VDDL to the first through sixth pixels by allowing only four high-voltage lines (VDDL) to be configured. Therefore, the display device 100 can offer the advantage of reduced manufacturing costs.

[0129] Figure 6 An example arrangement of pixels included in a display device 100 according to various aspects of this disclosure is shown.

[0130] like Figure 6 As shown, in some example embodiments, the plurality of pixels included in the display device 100 may include the first to sixth pixels disposed in one or more odd-numbered rows ODD, and the seventh to twelfth pixels disposed in one or more even-numbered rows EVEN.

[0131] Although for the sake of explanation, Figure 6 Only the first to twelfth pixels, arranged in a 2×6 matrix, are shown. However, the arrangement of the first to twelfth pixels in a 2×6 matrix can be repeated in the display panel 110 according to design requirements or specifications.

[0132] like Figure 6 As shown, each of the first to twelfth pixels may include the corresponding first sub-pixel in the first sub-pixel (SP1-1 to SP1-12), the corresponding second sub-pixel in the second sub-pixel (SP2-1 to SP2-12), and the corresponding third sub-pixel in the third sub-pixel (SP3-1 to SP3-12).

[0133] The first to sixth pixels can be connected to the first gate line GL1 and the second gate line GL2, and the seventh to twelfth pixels can be connected to the third gate line GL3 and the fourth gate line GL4.

[0134] For example, among the sub-pixels included in each of the first to sixth pixels, one or more sub-pixels with a flip structure can be connected to the first gate line GL1, and one or more sub-pixels with a regular arrangement structure can be connected to the second gate line GL2.

[0135] Furthermore, among the sub-pixels included in each of the 7th to 12th pixels, one or more sub-pixels with a flip structure can be connected to the third gate line GL3, and one or more sub-pixels with a regular arrangement structure can be connected to the fourth gate line GL4.

[0136] like Figure 6 As shown, for example, the first sub-pixel SP1-1 and the third sub-pixel SP3-1 in the first pixel with the flip structure, the second sub-pixel SP2-2 in the second pixel, the third sub-pixel SP3-3 in the third pixel, the second sub-pixel SP2-4 and the third sub-pixel SP3-4 in the fourth pixel, the first sub-pixel SP1-5 and the third sub-pixel SP3-5 in the fifth pixel, and the second sub-pixel SP2-6 in the sixth pixel can each be connected to the first gate line GL1.

[0137] For example, the second sub-pixel SP2-1, the first sub-pixel SP1-2 and the third sub-pixel SP3-2 in the first pixel with a regular arrangement structure, the first sub-pixel SP1-3 and the second sub-pixel SP2-3 in the third pixel, the first sub-pixel SP1-4 in the fourth pixel, the second sub-pixel SP2-5 in the fifth pixel, and the first sub-pixel SP1-6 and the third sub-pixel SP3-6 in the sixth pixel can each be connected to the second gate line GL2.

[0138] For example, the first sub-pixel SP1-7 and the third sub-pixel SP3-7 in the seventh pixel with the flip structure, the second sub-pixel SP2-8 in the eighth pixel, the third sub-pixel SP3-9 in the ninth pixel, the second sub-pixel SP2-10 and the third sub-pixel SP3-10 in the tenth pixel, the first sub-pixel SP1-11 and the third sub-pixel SP3-11 in the eleventh pixel, and the second sub-pixel SP2-12 in the twelfth pixel can each be connected to the third gate line GL3.

[0139] For example, the second sub-pixel SP2-7 in the seventh pixel, the first sub-pixel SP1-8 and the third sub-pixel SP3-8 in the eighth pixel, the first sub-pixel SP1-9 and the second sub-pixel SP2-9 in the ninth pixel, the first sub-pixel SP1-10 in the tenth pixel, the second sub-pixel SP2-11 in the eleventh pixel, and the first sub-pixel SP1-12 and the third sub-pixel SP3-12 in the twelfth pixel, which have a regular arrangement structure, can each be connected to the fourth gate line GL4.

[0140] Each of the first to twelfth pixels can share the same data line DL with at least one other adjacent pixel in the first direction. Therefore, the display device 100 can provide the advantage of effectively reducing the number of data channels in the data driving circuit 120.

[0141] In one or more aspects, the same white data line may be set in one of the first to twelfth pixels and in another pixel adjacent to that one pixel in the first direction.

[0142] For example, two adjacent white sub-pixels in the first direction can share the same white data line.

[0143] like Figure 6 As shown, the first white data line W1 can be set in the first pixel, the second pixel, the seventh pixel and the eighth pixel, and the second sub-pixels (SP2-1, SP2-2, SP2-7, SP2-8) in the first pixel, the second pixel, the seventh pixel and the eighth pixel can be connected to the first white data line W1.

[0144] For example, the first white data line W1 can be connected to the first white channel pad in the data driving circuit 120 and branch into two sub-lines, and the two sub-lines can be respectively set in the first pixel and the seventh pixel and the second pixel and the eighth pixel.

[0145] The second white data line W2 can be set in the third, fourth, ninth and tenth pixels, and the second sub-pixels (SP2-3, SP2-4, SP2-9, SP2-10) in the third, fourth, ninth and tenth pixels can be connected to the second white data line W2.

[0146] For example, the second white data line W2 can be connected to the second white channel pad in the data driver circuit 120 and branch into two sub-lines, and the two sub-lines can be respectively set in the third and ninth pixels and the fourth and tenth pixels.

[0147] The third white data line W3 can be set in the fifth, sixth, eleventh and twelfth pixels, and the second sub-pixels (SP2-5, SP2-6, SP2-11, SP2-12) in the fifth, sixth, eleventh and twelfth pixels can be connected to the third white data line W3.

[0148] For example, the third white data line W3 can be connected to the third white channel pad in the data driver circuit 120 and branch into two sub-lines, and the two sub-lines can be respectively set in the fifth and eleventh pixels and the sixth and twelfth pixels.

[0149] For example, the second sub-pixel (SP2-1 to SP2-12) in the first to twelfth pixels can be a white sub-pixel.

[0150] As described above, the display device 100 may have the following structure, wherein the white subpixel that has the greatest influence on the brightness of the displayed image is disposed in the second subpixel located at the center of each pixel, such that the white subpixels are disposed at equal intervals in the display panel 110. Therefore, the display device 100 can provide the advantages of ensuring or improving the brightness uniformity of the display device 100 and improving image quality.

[0151] In one or more aspects, data lines of the same color may be provided in one of the first to twelfth pixels and in two other pixels adjacent to that pixel in a first direction. In other words, data lines of the same color may be connected to that pixel and the two other pixels adjacent to that pixel in a first direction.

[0152] For example, three sub-pixels that have the same color and are adjacent to each other in the first direction can share a data line of the same color.

[0153] like Figure 6 As shown, the first red data line R1, the first green data line G1, and the first blue data line B1 can be set in the first to third pixels and the seventh to ninth pixels, and the second red data line R2, the second green data line G2, and the second blue data line B2 can be set in the fourth to sixth pixels and the tenth to twelfth pixels.

[0154] For example, the first red data line R1, the first green data line G1, and the first blue data line B1 can be connected to the first red channel pad, the first green channel pad, and the first blue channel pad in the data driver circuit 120, respectively. Furthermore, each of the first red data line R1, the first green data line G1, and the first blue data line B1 can branch into three or four sub-lines, and these sub-lines can be respectively located in the first and seventh pixels, the second and eighth pixels, and the third and ninth pixels.

[0155] Furthermore, the second red data line R2, the second green data line G2, and the second blue data line B2 can be connected to the second red channel pad, the second green channel pad, and the second blue channel pad in the data driver circuit 120, respectively. Additionally, each of the second red data line R2, the second green data line G2, and the second blue data line B2 can branch into three or four sub-lines, and these sub-lines can be respectively located in the fourth and tenth pixels, the fifth and eleventh pixels, and the sixth and twelfth pixels.

[0156] For example, the first sub-pixel SP1-1 in the first pixel, the third sub-pixel SP3-2 in the second pixel, the first sub-pixel SP1-8 in the eighth pixel, and the third sub-pixel SP3-9 in the ninth pixel can be red sub-pixels and connected to the first red data line R1.

[0157] The third sub-pixel SP3-1 in the first pixel, the first sub-pixel SP1-3 in the third pixel, the first sub-pixel SP1-7 in the seventh pixel, and the third sub-pixel SP3-8 in the eighth pixel can be green sub-pixels and connected to the first green data line G1.

[0158] The first sub-pixel SP1-2 in the second pixel, the third sub-pixel SP3-3 in the third pixel, the third sub-pixel SP3-7 in the seventh pixel, and the first sub-pixel SP1-9 in the ninth pixel can be blue sub-pixels and connected to the first blue data line B1.

[0159] The first sub-pixel SP1-4 in the fourth pixel, the third sub-pixel SP3-5 in the fifth pixel, the first sub-pixel SP1-11 in the eleventh pixel, and the third sub-pixel SP3-12 in the twelfth pixel can be red sub-pixels and connected to the second red data line R2.

[0160] The third sub-pixel SP3-4 in the fourth pixel, the first sub-pixel SP1-6 in the sixth pixel, the first sub-pixel SP1-10 in the tenth pixel, and the third sub-pixel SP3-11 in the eleventh pixel can be green sub-pixels and connected to the second green data line G2.

[0161] The first sub-pixel SP1-5 in the fifth pixel, the third sub-pixel SP3-6 in the sixth pixel, the third sub-pixel SP3-10 in the tenth pixel, and the first sub-pixel SP1-12 in the twelfth pixel can be blue sub-pixels and connected to the second blue data line B2.

[0162] As described above, compared to the example structure that requires a total of 24 data channels (i.e., 6 white channels, 6 red channels, 6 green channels, and 6 blue channels) to drive the first to twelfth pixels, the display device 100 according to various aspects of this disclosure can provide the advantage of reducing the number of data channels used to drive the first to twelfth pixels by using a total of 9 channels (i.e., 3 white channels, 2 red channels, 2 green channels, and 2 blue channels) based on an optimized or improved arrangement and connection structure of the data lines.

[0163] In one or more aspects, at least one of three or four adjacent pixels adjacent to one of the first to twelfth pixels in a first direction and a second direction other than the first direction may include a sub-pixel configured to emit light that is not included in the color of said pixel.

[0164] For example, when the first sub-pixel SP1-2 in the second pixel is a blue sub-pixel and the third sub-pixel SP3-2 in the second pixel is a red sub-pixel, at least one of the first pixel, the third pixel, or the eighth pixel adjacent to the second pixel may include a green sub-pixel.

[0165] Furthermore, when the first sub-pixel SP1-10 in the tenth pixel is a green sub-pixel and the third sub-pixel SP3-10 in the tenth pixel is a blue sub-pixel, at least one of the fourth, ninth, or eleventh pixels adjacent to the tenth pixel may include a red sub-pixel.

[0166] like Figure 6 As shown, the third sub-pixel SP3-1 in the first pixel, the first sub-pixel SP1-3 in the third pixel, and the third sub-pixel SP3-8 in the eighth pixel can be green sub-pixels.

[0167] In addition, the first sub-pixel SP1-4 in the fourth pixel, the third sub-pixel SP3-9 in the ninth pixel, and the first sub-pixel SP1-11 in the eleventh pixel can be red sub-pixels.

[0168] As described above, since the display device 100 according to various aspects of this disclosure has the following structure: white subpixels are disposed in corresponding pixels and at least one red subpixel, at least one green subpixel and at least one blue subpixel are disposed in at least two adjacent pixels without omission, the display device 100 can provide the advantage of reducing the number of data pads without reducing display quality by optimizing or improving the color arrangement based on subpixels.

[0169] Figures 7 to 10 An example driving sequence of subpixels included in a pixel in a display device 100 according to various aspects of this disclosure is shown.

[0170] In some example embodiments, Figure 7 The diagram illustrates the driving sequence of the first to twelfth pixels in a scan operation by applying a gate signal with a conduction voltage level to the first gate line GL1, and... Figure 8 The drive sequence of the first to twelfth pixels is shown by applying a gate signal with a conduction voltage level to the second gate line GL2 during a scan operation.

[0171] also, Figure 9 The diagram illustrates the driving sequence of the first to twelfth pixels in a scan operation by applying a gate signal with a conduction voltage level to the third gate line GL3, and... Figure 10 The drive sequence of the first to twelfth pixels is shown by applying a gate signal with a conduction voltage level to the fourth gate line GL4 during a scan operation.

[0172] like Figures 7 to 10 As shown, when data voltage is transmitted through multiple data lines (W1, W2, R1, R2, G1, G2, B1, and B2), when a gate signal with a conduction voltage level is applied through the first gate line GL1, a sensing operation can be performed on the sub-pixels connected to the first gate line GL1 from the first pixel to the sixth pixel.

[0173] like Figure 7As shown, the sub-pixels connected to the first gate line GL1 can be the first sub-pixel SP1-1 and the third sub-pixel SP3-1 in the first pixel with a flip structure, the second sub-pixel SP2-2 in the second pixel, the third sub-pixel SP3-3 in the third pixel, the second sub-pixel SP2-4 and the third sub-pixel SP3-4 in the fourth pixel, the first sub-pixel SP1-5 and the third sub-pixel SP3-5 in the fifth pixel, and the second sub-pixel SP2-6 in the sixth pixel.

[0174] Subsequently, when data voltages are provided through multiple data lines (W1, W2, R1, R2, G1, G2, B1, and B2), a sensing operation can be performed on the sub-pixels connected to the second gate line GL2 when a gate signal with a conduction voltage level is applied through the second gate line GL2.

[0175] like Figure 8 As shown, the sub-pixels connected to the second gate line GL2 can be the second sub-pixel SP2-1 in the first pixel with a regular arrangement structure, the first sub-pixel SP1-2 and the third sub-pixel SP3-2 in the second pixel, the first sub-pixel SP1-3 and the second sub-pixel SP2-3 in the third pixel, the first sub-pixel SP1-4 in the fourth pixel, the second sub-pixel SP2-5 in the fifth pixel, and the first sub-pixel SP1-6 and the third sub-pixel SP3-6 in the sixth pixel.

[0176] Subsequently, when data voltage is supplied through multiple data lines (W1, W2, R1, R2, G1, G2, B1, and B2), a sensing operation can be performed on the sub-pixels connected to the third gate line GL3 when a gate signal with a conduction voltage level is applied through the third gate line GL3.

[0177] like Figure 8 As shown, the sub-pixels connected to the third gate line GL3 can be the first sub-pixels SP1-7 and the third sub-pixels SP3-7 in the seventh pixel with a flip structure, the second sub-pixels SP2-8 in the eighth pixel, the third sub-pixels SP3-9 in the ninth pixel, the second sub-pixels SP2-10 and the third sub-pixels SP3-10 in the tenth pixel, the first sub-pixels SP1-11 and the third sub-pixels SP3-11 in the eleventh pixel, and the second sub-pixels SP2-12 in the twelfth pixel.

[0178] Subsequently, when data voltage is supplied through multiple data lines (W1, W2, R1, R2, G1, G2, B1, and B2), a sensing operation can be performed on the sub-pixels connected to the fourth gate line GL4 when a gate signal with a conduction voltage level is applied through the fourth gate line GL4.

[0179] like Figure 10 As shown, the sub-pixels connected to the fourth gate line GL4 can be the second sub-pixel SP2-7 in the seventh pixel with a regular arrangement structure, the first sub-pixel SP1-8 and the third sub-pixel SP3-8 in the eighth pixel, the first sub-pixel SP1-9 and the second sub-pixel SP2-9 in the ninth pixel, the first sub-pixel SP1-10 in the tenth pixel, the second sub-pixel SP2-11 in the eleventh pixel, and the first sub-pixel SP1-12 and the third sub-pixel SP3-12 in the twelfth pixel.

[0180] Examples, aspects, and embodiments of the display device 100 and display panel 110 described herein can be described as follows.

[0181] According to one or more exemplary embodiments described herein, a display device may be provided, the display device comprising: a display panel including a plurality of gate lines extending in a first direction; a plurality of data lines extending in a second direction intersecting the first direction; a plurality of pixels, each pixel including a first sub-pixel, a second sub-pixel, and a third sub-pixel configured to emit light of different colors from each other; a gate driving circuit configured to drive the plurality of gate lines; and a data driving circuit configured to supply a data voltage to the plurality of data lines. In one or more aspects, one of the plurality of pixels may be connected to the same data line as at least one other pixel disposed in the first direction relative to the one pixel, and at least two sub-pixels of the first, second, or third sub-pixels of the one pixel may be connected to different gate lines from each other.

[0182] In one or more aspects, a first sub-pixel included in a pixel may be a sub-pixel configured to emit light of a first color among a plurality of colors other than white. In one or more aspects, a second sub-pixel included in a pixel may be a sub-pixel configured to emit white light. In one or more aspects, a third sub-pixel included in a pixel may be a sub-pixel configured to emit light of a second color among a plurality of colors.

[0183] In one or more aspects, the multiple colors may include at least one of red, green, or blue.

[0184] In one or more aspects, a first sub-pixel or a third sub-pixel included in at least one of three adjacent pixels of a pixel in a first direction and a second direction may be a sub-pixel configured to emit light of a third color among a plurality of colors, wherein the third color is different from the first color and the second color.

[0185] In one or more aspects, multiple non-white data lines and one white data line can be set in each of multiple pixels.

[0186] In one or more aspects, the same white data line may be set in one pixel and another pixel adjacent to said one pixel in a first direction.

[0187] In one or more aspects, data lines of the same color may be set in one pixel and two other pixels adjacent to said one pixel in a first direction.

[0188] In one or more aspects, at least one of the first sub-pixel, the second sub-pixel, or the third sub-pixel may have a flip structure in which the positions of the corresponding light-emitting area and the corresponding sub-pixel circuit are reversed.

[0189] In one or more aspects, the second sub-pixel may be located between the first sub-pixel and the third sub-pixel.

[0190] In one or more aspects, multiple data lines are respectively disposed in a region adjacent to one side of the first sub-pixel, a region adjacent to the other side of the first sub-pixel and one side of the second sub-pixel, a region adjacent to the other side of the second sub-pixel and one side of the third sub-pixel, and a region adjacent to the other side of the third sub-pixel.

[0191] In one or more aspects, the sensing line is positioned in the region adjacent to the other side of the second sub-pixel and one side of the third sub-pixel.

[0192] In one or more aspects, the sensing line can be connected to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel by branch lines extending across the respective light-emitting areas of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0193] In one or more aspects, a plurality of pixels may include adjacent pixels that are adjacent to a third sub-pixel included in a pixel.

[0194] In one or more aspects, the display device may have the following structure, wherein a high-voltage line is disposed in a region adjacent to one side of a first sub-pixel in a pixel and in a region adjacent to the other side of a third sub-pixel in an adjacent pixel, but the high-voltage line is not disposed in the region adjacent to the third sub-pixel in the pixel and the first sub-pixel in the adjacent pixel.

[0195] In one or more aspects, the plurality of pixels may include a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel sequentially disposed in at least one odd-numbered row of a plurality of rows, and a seventh pixel, an eighth pixel, a ninth pixel, a tenth pixel, an eleventh pixel, and a twelfth pixel sequentially disposed in at least one even-numbered row of the plurality of rows, corresponding respectively to the positions where the first pixel to the sixth pixel are disposed. In one or more aspects, the first pixel to the sixth pixel may be connected to a first gate line and a second gate line of a plurality of gate lines, and the seventh pixel to the twelfth pixel may be connected to a third gate line and a fourth gate line of a plurality of gate lines.

[0196] According to one or more example embodiments described herein, a display panel may be provided, the display panel comprising: a plurality of pixels, each of the plurality of pixels including a first sub-pixel, a second sub-pixel, and a third sub-pixel configured to emit light of different colors from each other, and the plurality of pixels being connected to a first gate line and a second gate line; a first color data line extending across the plurality of pixels from the first pixel to the third pixel; a second color data line extending across the plurality of pixels from the fourth pixel to the sixth pixel; a first white data line extending across the plurality of pixels from the first pixel to the second pixel; a second white data line extending across the plurality of pixels from the third pixel to the fourth pixel; and a third white data line extending across the plurality of pixels from the fifth pixel to the sixth pixel.

[0197] According to one or more example embodiments of this disclosure, a display panel may be provided, the display panel comprising: a plurality of gate lines extending in a first direction; a plurality of data lines extending in a second direction intersecting the first direction; and a plurality of pixels, each of the plurality of pixels comprising a plurality of sub-pixels, wherein a first pixel of the plurality of pixels is connected to the same data line as at least one other pixel adjacent to it in the first direction.

[0198] In one or more aspects, the data line is a white data line, and the at least one adjacent other pixel includes a second pixel, and the white data line is disposed in the first pixel and the second pixel among the plurality of pixels and connected to the first pixel and the second pixel.

[0199] The above description has been presented to enable any person skilled in the art to make and use the technical ideas of this disclosure, and has been provided in the context of specific example applications. Various modifications, additions, and substitutions to the described example embodiments will be apparent to those skilled in the art, and the various principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The above description and drawings are provided as examples of the technical ideas of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of this disclosure.

Claims

1. A display device, comprising: The display panel includes a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction intersecting the first direction, and a plurality of pixels, each of the plurality of pixels including a first sub-pixel, a second sub-pixel, and a third sub-pixel; In this configuration, one of the plurality of pixels is connected to the same data line as at least one other pixel, and the at least one other pixel is adjacent to the first pixel in the first direction.

2. The display device according to claim 1, wherein, The first sub-pixel, the second sub-pixel, and the third sub-pixel are configured to emit light of different colors from each other. The first sub-pixel included in the pixel is a sub-pixel configured to emit light of a first color among a plurality of colors that is different from white; The second sub-pixel included in the first pixel is a sub-pixel configured to emit white light; and The third sub-pixel included in the first pixel is a sub-pixel configured to emit light of the second color among the multiple colors.

3. The display device according to claim 2, wherein, The multiple colors include at least one of red, green, and blue.

4. The display device according to claim 2, wherein, The first sub-pixel or the third sub-pixel, which is one of at least three adjacent pixels of the three pixels adjacent to the first pixel in the first direction and the second direction, is a sub-pixel configured to emit light of a third color of the plurality of colors, wherein the third color is different from the first color and the second color.

5. The display device according to claim 1, wherein, Multiple non-white data lines and one white data line are provided in each of the plurality of pixels.

6. The display device according to claim 5, wherein, The same white data line is provided in the one pixel and another pixel adjacent to the one pixel in the first direction.

7. The display device according to claim 5, wherein, Data lines of the same color are arranged in the one pixel and two other pixels adjacent to the one pixel in the first direction.

8. The display device according to claim 1, wherein, The first sub-pixel, the second sub-pixel, and the third sub-pixel have a flip structure in which the positions of the corresponding light-emitting area and the corresponding sub-pixel circuit are reversed.

9. The display device according to claim 1, wherein, The second sub-pixel is located between the first sub-pixel and the third sub-pixel.

10. The display device according to claim 9, wherein, The multiple data lines are respectively located in the region adjacent to one side of the first sub-pixel, the region adjacent to the other side of the first sub-pixel and one side of the second sub-pixel, the region adjacent to the other side of the second sub-pixel and one side of the third sub-pixel, and the region adjacent to the other side of the third sub-pixel.

11. The display device according to claim 9, wherein, The sensing line is positioned in the region adjacent to the other side of the second sub-pixel and one side of the third sub-pixel.

12. The display device according to claim 11, wherein, The sensing line is connected to each of the first sub-pixel, the second sub-pixel, and the third sub-pixel via branch lines extending across the respective light-emitting areas of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

13. The display device according to claim 9, wherein, The plurality of pixels includes adjacent pixels adjacent to the third sub-pixel included in the one pixel, and the high voltage line is disposed in the region adjacent to one side of the first sub-pixel in the one pixel and the other side of the third sub-pixel in the adjacent pixels, and is not disposed in the region adjacent to the third sub-pixel in the one pixel and the first sub-pixel in the adjacent pixels.

14. The display device according to claim 1, wherein: The plurality of pixels includes a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel sequentially arranged in at least one odd-numbered row of the plurality of rows, and a seventh pixel, an eighth pixel, a ninth pixel, a tenth pixel, an eleventh pixel, and a twelfth pixel sequentially arranged in at least one even-numbered row of the plurality of rows to correspond respectively to the positions where the first pixel to the sixth pixel are arranged. The first pixel to the sixth pixel are connected to the first gate line and the second gate line among the plurality of gate lines, and the seventh pixel to the twelfth pixel are connected to the third gate line and the fourth gate line among the plurality of gate lines.

15. The display device according to claim 1, further comprising: A gate driving circuit configured to drive the plurality of gate lines; as well as A data driving circuit configured to provide data voltage to the plurality of data lines.

16. The display device according to claim 1, wherein, At least two of the first sub-pixel, the second sub-pixel, or the third sub-pixel in a pixel are each connected to different gate lines.

17. A display panel, comprising: A plurality of pixels, each of the plurality of pixels including a first sub-pixel, a second sub-pixel, and a third sub-pixel configured to emit light of different colors from each other, wherein the plurality of pixels are connected to a first gate line and a second gate line; A first color data line extends across a first pixel, a second pixel, and a third pixel of the plurality of pixels; A second color data line extends across the fourth, fifth and sixth pixels of the plurality of pixels; A first white data line extends across the first pixel and the second pixel of the plurality of pixels; A second white data line extends across the third and fourth pixels of the plurality of pixels; and A third white data line extends across the fifth and sixth pixels of the plurality of pixels.

18. A display panel, comprising: Multiple gate lines extend in the first direction; Multiple data lines extend in a second direction that intersects with the first direction; as well as Multiple pixels, each of which comprises multiple sub-pixels. The first pixel among the plurality of pixels is connected to the same data line as at least one other adjacent pixel in the first direction.

19. The display panel according to claim 18, wherein, The data line is white, and the at least one adjacent other pixel includes a second pixel. The white data line is disposed in the first pixel and the second pixel among the plurality of pixels, and is connected to the first pixel and the second pixel.

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