Display pixel and display device

Abstract

Display pixels and display apparatuses are provided. The display apparatus includes a first display pixel storing a first pixel driving data value; a brightness adjustment circuit configured to determine a plurality of adjustment parameters corresponding to the first pixel driving data value based on one or more reference tables; and a row driver configured to control operation of the first display pixel based on the plurality of adjustment parameters.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0054020, filed with the Korean Patent Office on April 24, 2025, and Korean Patent Application No. 10-2025-0126356, filed with the Korean Patent Office on September 5, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor displays. More specifically, this disclosure relates to display pixels and display devices including display pixels. Background Technology

[0003] Display pixels operating in pulse width modulation (PWM) mode may include light-emitting circuitry that generates light in response to a PWM signal. The duration for which the light-emitting circuitry is illuminated can be determined based on the duty cycle of the PWM signal.

[0004] The duty cycle of a PWM signal can be determined based on pixel drive data values ​​stored in the display pixels. For example, the duty cycle of a PWM signal can be determined linearly with respect to the pixel drive data values. However, even if the duty cycle of the PWM signal is determined linearly with respect to the pixel drive data values, the brightness of the display pixels can be determined non-linearly with respect to the duty cycle of the PWM signal due to various reasons. That is, the brightness of the display pixels can become too high or too low than expected due to various reasons. Summary of the Invention

[0005] This disclosure is intended to solve the aforementioned technical problems. More specifically, the purpose of this disclosure is to provide display pixels whose brightness is more precisely adjusted and display devices including display pixels.

[0006] A display device according to some embodiments may include: a first display pixel storing a first pixel driving data value; a brightness adjustment circuit configured to determine a plurality of adjustment parameters corresponding to the first pixel driving data value based on one or more reference tables; and a line driver configured to control the operation of the first display pixel based on the plurality of adjustment parameters.

[0007] A display pixel according to some embodiments may include: a pulse width modulation (PWM) generation circuit configured to generate a PWM signal corresponding to a plurality of pixel drive bits in response to a clock signal; a masking circuit configured to generate a masking PWM signal by masking the PWM signal based on a masking signal; and a light-emitting circuit configured to operate based on the masking PWM signal.

[0008] A display device according to some embodiments may include: a line driver configured to output a first clock signal and a second clock signal having a different waveform from the first clock signal during a frame period; a first display pixel configured to perform a first light emission operation based on a first pixel driving data value and the first clock signal; and a second display pixel configured to perform a second light emission operation based on a second pixel driving data value and the second clock signal. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a display device according to some embodiments of the present disclosure.

[0010] Figure 2 To show in more detail Figure 1 A block diagram showing the configuration of the display pixels.

[0011] Figure 3 This is a timing diagram showing the configuration of PWM signals according to some implementations.

[0012] Figure 4 It shows the basis Figure 3 A graph showing the relationship between the brightness of the display pixels and the pixel driving data values ​​in the implementation method.

[0013] Figure 5 This is a diagram illustrating a brightness adjustment scheme according to some embodiments of the present disclosure.

[0014] Figure 6 This is a diagram illustrating a brightness adjustment scheme according to some embodiments of the present disclosure.

[0015] Figure 7 This is a diagram illustrating a brightness adjustment scheme according to some embodiments of the present disclosure.

[0016] Figure 8 and Figure 9 This is a diagram showing the configuration of a reference table according to some implementation methods.

[0017] Figure 10 This is a diagram showing the configuration of a reference table according to some implementation methods.

[0018] Figure 11 This is a diagram showing in more detail the brightness correction method for multiple display pixels.

[0019] Figure 12 This is a flowchart illustrating an operation method of a display device according to some embodiments of the present disclosure.

[0020] Figure 13 This is a graph illustrating the relationship between the brightness of a display pixel and pixel driving data values ​​according to some embodiments of the present disclosure.

[0021] Figure 14 and Figure 15 This is a diagram showing the configuration of a reference table according to some implementation methods.

[0022] Figure 16 This is an exemplary diagram illustrating how a brightness adjustment circuit determines a combination of light emission shortening adjustment parameters.

[0023] Figure 17 This is a block diagram illustrating a display device according to some embodiments.

[0024] Figure 18 This is a diagram showing the configuration of a reference table according to some implementation methods. Detailed Implementation

[0025] In the following description, embodiments of the present disclosure will be clearly and in detail to the extent that those skilled in the art can readily practice the present disclosure.

[0026] The components described below can be implemented as various types of software (such as firmware, applications, etc.) or as various types of hardware (such as electrical circuits, electronic circuits, processors, etc.). However, the scope of this disclosure is not limited thereto, and the components described below can be implemented as a combination of software and hardware.

[0027] Figure 1 This is a block diagram illustrating a display device according to some embodiments of the present disclosure. The display device 100 may include a display pixel array 110, a column driver 120, a row driver 130, a timing controller 140, and a reference table memory circuit 150.

[0028] The display pixel array 110 may include a plurality of display pixels (or display pixel elements) PX. The plurality of display pixels PX may be arranged in a matrix along the row and column directions. However, the scope of this disclosure is not limited thereto, and the plurality of display pixels PX may be arranged in a zigzag pattern.

[0029] Each of the multiple display pixels PX can be connected to a data line DL and a clock line CL. For example, display pixels PX arranged in the same row of display pixels can share a clock line CL, and display pixels PX arranged in the same column of display pixels can share a data line DL.

[0030] In some implementations, a display pixel PX arranged in the i-th display pixel row and j-th display pixel column of the display pixel array 110 may be referred to as "PXij" (where i = 1, 2, 3... and j = 1, 2, 3...). For example, a display pixel PX connected to the i-th clock line CLI and the j-th data line DLj may be referred to as "PXij".

[0031] In some implementations, multiple display pixels PX can be connected to different clock lines CL. The following will refer to... Figure 17 Some implementations in which multiple display pixels PX are connected to different clock lines CL are described in more detail.

[0032] Multiple display pixels PX can be connected to different masking lines ML. For example, display pixel PXij can be connected to masking line MLij. For example, display pixel PX11 can be connected to masking line ML11, display pixel PX12 can be connected to masking line ML12, and display pixel PX13 can be connected to masking line ML13.

[0033] The column driver 120 can control multiple data lines DL. For example, the column driver 120 can provide different pixel drive data values ​​(hereinafter referred to as "PDD") to multiple display pixel columns via multiple data lines DL.

[0034] In some embodiments, column driver 120 may provide different pixel driving data values ​​PDD to display pixels PX arranged in a display pixel column in a time-division manner. For example, column driver 120 may provide pixel driving data values ​​PDD to display pixel PX11 via a first data line DL1, and then provide another pixel driving data value PDD to display pixel PX21. However, the scope of this disclosure is not limited thereto.

[0035] The line driver 130 can control multiple clock lines CL. For example, the line driver 130 can provide different clock signals (hereinafter referred to as "CLK") to multiple display pixel rows through multiple clock lines CL.

[0036] In some implementations, the row driver 130 can control multiple display pixels PX on a per-pixel-row basis. For example, the row driver 130 can jointly (e.g., simultaneously) control the operation of display pixels PX connected to the first clock line CL1 by controlling the logic level of a clock signal CLK provided via the first clock line CL1. As a more detailed example, in response to the logic level of the clock signal CLK provided via the first clock line CL1, a display pixel PX connected to the first clock line CL1 can store a pixel drive data value PDD provided via a data line DL, or perform a light-emitting operation based on the pixel drive data value PDD.

[0037] Row driver 130 can control multiple masking lines ML. For example, row driver 130 can provide multiple masking signals (hereinafter referred to as "MSK") to multiple display pixels PX via multiple masking lines ML. For simplicity, it is assumed below that row driver 130 controls multiple masking lines ML, but the scope of this disclosure is not limited thereto. For example, column driver 120 may be implemented instead of row driver 130 to control multiple masking lines ML, or a dedicated driver (not shown) other than column driver 120 and row driver 130 may be implemented to control multiple masking lines ML.

[0038] The timing controller 140 may receive frame data D_FRM from an external device (e.g., a central processing unit (CPU) or a graphics processing unit (GPU). The timing controller 140 may provide the frame data D_FRM to the column driver 120. The frame data D_FRM may include multiple pixel drive data values ​​PDD corresponding to different display pixels PX. The column driver 120 may divide the frame data D_FRM received from the timing controller 140 into units of pixel drive data values ​​PDD, and may provide the units of pixel drive data values ​​PDD to the display pixel array 110.

[0039] The timing controller 140 can control the overall operation of the display device 100. For example, the timing controller 140 can control the operating timing of the column driver 120 and the row driver 130.

[0040] The timing controller 140 may include a brightness adjustment circuit 141. The brightness adjustment circuit 141 may adjust the brightness of each of a plurality of display pixels PX. For example, the brightness adjustment circuit 141 may determine a plurality of adjustment parameters (e.g., a target brightness adjustment value for each display pixel PX) corresponding to each display pixel PX based on one or more reference tables TBL_REF stored in a reference table memory circuit 150.

[0041] The brightness adjustment circuit 141 can adjust the brightness of each display pixel PX to be higher or lower than the pixel drive data value PDD based on a brightness adjustment target value. More specifically, the brightness adjustment circuit 141 can adjust the brightness of each of the plurality of display pixels PX by adjusting the waveforms of a plurality of clock signals CLK and a plurality of masking signals MSK provided to the display pixel array 110. For example, the brightness adjustment circuit 141 can provide a plurality of adjustment parameters to the line driver 130. The line driver 130 can control the operation of each display pixel PX based on the plurality of adjustment parameters. For example, the line driver 130 can control the total light emission duration of each display pixel PX according to the pixel drive data value PDD based on the plurality of adjustment parameters. For example, the line driver 130 can control the total light emission duration of each display pixel PX by adjusting the waveforms of the plurality of clock signals CLK and the plurality of masking signals MSK based on the plurality of adjustment parameters.

[0042] In other words, the following will describe an example in which a brightness adjustment circuit 141, included in the timing controller 140, adjusts the brightness of a plurality of display pixels PX by controlling the line driver 130. However, the scope of this disclosure is not limited thereto. For example, the brightness adjustment circuit 141 may be implemented as a component included in the line driver 130, or the brightness adjustment circuit 141 may be implemented as a separate component outside the line driver 130 and the timing controller 140. That is, the scope of this disclosure is not limited to the specific implementation method of the brightness adjustment circuit 141.

[0043] In some embodiments, the reference table memory circuit 150 may be implemented as a volatile memory device (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.). However, the scope of this disclosure is not limited thereto, and the reference table memory circuit 150 may be implemented as a non-volatile memory device (such as flash memory).

[0044] Figure 2 To show in more detail Figure 1 A block diagram showing the configuration of the display pixels. (Refer to...) Figure 1 and Figure 2 The display pixel PX may include a pulse width modulation (PWM) generation circuit PGC, a masking circuit MC, and a light-emitting circuit LEC.

[0045] The PWM generation circuit PGC can receive the clock signal CLK via the clock line CL. In response to the clock signal CLK, the PWM generation circuit PGC can store the pixel drive data value PDD provided via the data line DL, and can generate a PWM signal SPWM based on the pixel drive data value PDD.

[0046] The PWM signal SPWM may include multiple bit emission periods (hereinafter referred to as "BEMs") having logic levels corresponding to the values ​​of the pixel drive data value PDD. The PWM generation circuit PGC may determine the logic levels of the multiple bit emission periods BEMs based on the bits included in the pixel drive data value PDD.

[0047] More specifically, the PWM generation circuit PGC may include a shift register SR. The shift register SR may include first unit C1 to k-th unit Ck (where k is an integer greater than 1). The shift register SR may store bits included in the pixel drive data value PDD and operates based on a clock signal CLK. For example, the shift register SR may sequentially store bits included in the pixel drive data value PDD in response to the clock signal CLK. For example, in response to the clock signal CLK, the shift register SR may sequentially store bits included in the pixel drive data value PDD in first unit C1 to k-th unit Ck. The shift register SR may generate a PWM signal SPWM in response to the clock signal CLK. For example, the shift register SR may determine the logic level of the PWM signal SPWM during each bit emission period BEM by performing shift or rotation operations on the first unit C1 to k-th unit Ck in response to the clock signal CLK.

[0048] In some implementations, each bit included in the pixel-driven data value PDD may be referred to as a "pixel-driven bit". However, the scope of this disclosure is not limited to these terms.

[0049] In some implementations, each of the first unit C1 to the kth unit Ck may be implemented as a flip-flop connected in series with each other and operating in response to a clock signal CLK. However, the scope of this disclosure is not limited thereto.

[0050] In some implementations, the PWM signal SPWM can be determined based on the output signal of the shift register SR. The logic level of the output signal of the shift register SR can be determined based on the bits stored in the last bit unit (e.g., the k-th bit unit Ck) of the shift register SR.

[0051] In some implementations, a shift operation can represent the operation of moving bits stored in the first unit C1 to the (k-1)th bit unit Ck-1 to the second unit C2 to the kth bit unit Ck and storing the pixel drive bit provided from the data line DL in the first unit C1. The shift register SR can store the pixel drive data value PDD in the first unit C1 to the kth bit unit Ck by performing the shift operation "k" times.

[0052] In some implementations, a rotation operation can represent moving bits stored in the first unit C1 to the (k-1)th bit unit Ck-1 to the second unit C2 to the kth bit unit Ck and storing the bit stored in the kth bit unit Ck back into the first unit C1. The shift register SR can perform the rotation operation to replace the bit stored in the kth bit unit Ck with additional bits included in the pixel drive data value PDD. The shift register SR can sequentially change the logic level of the PWM signal SPWM by performing the rotation operation multiple times.

[0053] The duty cycle (e.g., duty factor) of the PWM signal SPWM can be determined based on the pixel drive data value PDD. For example, when the pixel drive data value PDD is large, the PWM generation circuit PGC can generate a PWM signal SPWM that is kept high for a large proportion of the time; and when the pixel drive data value PDD is small, the PWM generation circuit PGC can generate a PWM signal SPWM that is kept high for a small proportion of the time.

[0054] The masking circuit MC can receive a masking signal MSK via a masking line ML. The masking circuit MC can generate a masked PWM signal SPWM_MSK by masking the PWM signal SPWM based on the masking signal MSK. For example, the masking circuit MC can determine the logic level of the masked PWM signal SPWM_MSK to be logic low during a specific time period (e.g., a period when the masking signal MSK is logic low), regardless of the pixel drive data value PDD; and can determine the logic level of the masked PWM signal SPWM_MSK to be the same as the logic level of the PWM signal SPWM during the remaining time period (e.g., a period when the masking signal MSK is logic high). That is, the masking circuit MC can perform a masking operation or a bypass operation on the PWM signal SPWM in response to the masking signal MSK. However, the scope of this disclosure is not limited to the specific operating method of the masking circuit MC.

[0055] In some implementations, the shielding circuit MC may be implemented as an AND gate. However, the scope of this disclosure is not limited thereto. For example, depending on how the shielding signal MSK is implemented, the shielding circuit MC may be implemented using various types of logic gates, such as NAND gates.

[0056] The light-emitting circuit (LEC) can operate in response to a PWM signal SPWM (e.g., perform a light-emitting operation). For example, the LEC may include a light-emitting diode that is turned on or off based on the logic level of the masking PWM signal SPWM_MSK.

[0057] In other words, the duration of light emission by the light-emitting circuit LEC can be determined based on the pixel drive data value PDD stored in the shift register SR. However, the brightness of the display pixel PX based on a specific pixel drive data value PDD may be higher or lower than expected for various reasons. In this case, the quality of the image represented by the display pixel PX may be degraded.

[0058] According to some embodiments of this disclosure, the brightness adjustment circuit 141 can control the waveforms of the masking signal MSK and the clock signal CLK by controlling the line driver 130. For example, the brightness adjustment circuit 141 can adjust the duty cycle of the masking PWM signal SPWM_MSK by adjusting the length of the masking period included in the masking signal MSK and the switching interval of the clock signal CLK. However, the scope of this disclosure is not limited thereto, and the brightness adjustment circuit 141 may also be implemented to control only the waveform of one of the masking signal MSK and the clock signal CLK.

[0059] Figure 3 This is a timing diagram illustrating the configuration of PWM signals according to some implementations. In the following text, reference is made to... Figures 1 to 3 The waveforms of the PWM signal SPWM and the masked PWM signal SPWM_MSK will be described when the brightness adjustment circuit 141 does not adjust the masking signal MSK and the clock signal CLK. In other words, below, it is assumed that the original clock signal CLK_raw (e.g., the clock signal CLK generated by the line driver 130 when the switching interval is not adjusted by the brightness adjustment circuit 141) is provided to the display pixel PX, and the masking circuit MC keeps the waveform of the masked PWM signal SPWM_MSK the same as the waveform of the PWM signal SPWM in response to the masking signal MSK (e.g., the masking signal MSK remains in a logic high state).

[0060] Furthermore, for a simpler explanation, it is assumed below that the pixel-driven data value PDD has a 4-bit code length and the shift register SR has a capacity of 4 bits (i.e., k is 4). However, the scope of this disclosure is not limited to this. For example, the capacity of the shift register SR and the code length of the pixel-driven data value PDD may be larger or smaller than 4 bits.

[0061] The display pixel PX can perform a light-emitting operation during the light-emitting period TEM based on the pixel driving data value PDD stored in the shift register SR. For example, during the time period between the first time point tA and the fifth time point tE corresponding to the light-emitting period TEM, the PWM generation circuit PGC can generate a PWM signal SPWM corresponding to the pixel driving data value PDD in response to the clock signal CLK; and the light-emitting circuit LEC can perform a light-emitting operation based on the PWM signal SPWM (more precisely, the same masking PWM signal SPWM_MSK as the PWM signal SPWM).

[0062] In some implementations, the emission period TEM can represent the time period during which a display pixel PX emits light within a frame period. For example, a display pixel PX may perform an emission operation corresponding to a pixel drive data value PDD during an emission period TEM.

[0063] The PWM generation circuit PGC can generate a PWM signal SPWM corresponding to the pixel drive data value PDD based on the clock signal CLK. For example, the shift register SR can generate the PWM signal SPWM in response to the clock signal CLK.

[0064] The clock signal CLK can be switched at each of the first time points tA to the fourth time point tD (e.g., from logic low to logic high, and then back to logic low). In this case, in response to the switching of the clock signal CLK, the bits stored in the last bit unit of the shift register SR (e.g., the k-th bit unit Ck) can be changed sequentially, and therefore the logic level of the PWM signal SPWM can be changed sequentially.

[0065] In response to the clock signal CLK switching at the first time point tA, the shift register SR stores the least significant bit (LSB) of the pixel drive data value PDD in the k-th bit unit Ck (i.e., the last bit unit). In response to the clock signal CLK switching at the second time point tB, the shift register SR performs a 1-bit rotation operation to store the second least significant bit of the pixel drive data value PDD in the k-th bit unit Ck. In response to the clock signal CLK switching at the third time point tC, the shift register SR performs a 1-bit rotation operation to store the second most significant bit of the pixel drive data value PDD in the k-th bit unit Ck. In response to the clock signal CLK switching at the fourth time point tD, the shift register SR performs a 1-bit rotation operation to store the most significant bit (MSB) of the pixel drive data value PDD in the k-th bit unit Ck.

[0066] Therefore, the logic level of the PWM signal SPWM during the time period between the first time point tA and the second time point tB can be determined based on the LSB of the pixel drive data value PDD; the logic level of the PWM signal SPWM during the time period between the second time point tB and the third time point tC can be determined based on the second least significant bit of the pixel drive data value PDD; the logic level of the PWM signal SPWM during the time period between the third time point tC and the fourth time point tD can be determined based on the second most significant bit of the pixel drive data value PDD; and the logic level of the PWM signal SPWM during the time period between the fourth time point tD and the fifth time point tE can be determined based on the MSB of the pixel drive data value PDD.

[0067] The emission duration TEM can include multiple bit emission durations (BEMs). These multiple bit emission durations (BEMs) can correspond to different bits included in the pixel drive data value (PDD). For example, the emission duration TEM can include the first emission duration (BEM1) through the fourth emission duration (BEM4).

[0068] The first transmission period BEM1 to the fourth transmission period BEM4 can represent the time periods determined by the logic level of the PWM signal SPWM based on the LSB, the second least significant bit, the second most significant bit, and the MSB of the pixel drive data value PDD, respectively. For example, the first transmission period BEM1 can correspond to the time period between the first time point tA and the second time point tB; the second transmission period BEM2 can correspond to the time period between the second time point tB and the third time point tC; the third transmission period BEM3 can correspond to the time period between the third time point tC and the fourth time point tD; and the fourth transmission period BEM4 can correspond to the time period between the fourth time point tD and the fifth time point tE.

[0069] For a more concise explanation, Figure 3 Representative examples are shown where the first transmission period BEM1 to the fourth transmission period BEM4 correspond to the LSB, the second least significant bit, the second most significant bit, and the MSB of the pixel driving data value PDD, but the scope of this disclosure is not limited thereto. For example, the order of the first transmission period BEM1 to the fourth transmission period BEM4 may be... Figure 3 The order shown is determined differently (e.g., in reverse order).

[0070] The duration of each of the first transmission period BEM1 to the fourth transmission period BEM4 can be determined based on the switching interval of the clock signal CLK. For example, the duration of the first transmission period BEM1 can be determined as the length of the time interval between a first time point tA and a second time point tB, during which the clock signal CLK switches between the first time point tA and the second time point tB.

[0071] The switching intervals of the original clock signal CLK_raw can form a geometric sequence with a common ratio of 2. For example, the interval between the first time point tA and the second time point tB can be "1UT", the interval between the second time point tB and the third time point tC can be "2UT", the interval between the third time point tC and the fourth time point tD can be "4UT", and the interval between the fourth time point tD and the fifth time point tE can be "8UT". Therefore, the lengths of the first transmit period BEM1 to the fourth transmit period BEM4 can be "1UT", "2UT", "4UT", and "8UT", respectively. That is, the lengths of the bit transmit periods BEM included in the PWM signal SPWM generated in response to the original clock signal CLK_raw can form a geometric sequence with a common ratio of "2".

[0072] "1UT" is merely a unit used to describe the relative length of the switching interval of the raw clock signal CLK_raw and the multiple bit transmit periods BEM, and the scope of this disclosure is not limited to the specific time length of "1UT".

[0073] In this way, the PWM generation circuit PGC can independently determine the logic level of the PWM signal SPWM for each bit transmission period BEM based on the pixel drive data value PDD. For example, as shown in Figure 1 GRP1, if the pixel drive data value PDD is "4" (e.g., binary 0100), the PWM generation circuit PGC can determine the logic level of the PWM signal SPWM as logic high during the third bit transmission period BEM3. As shown in Figure 2 GRP1, when the pixel drive data value PDD is "5" (e.g., binary 0101), the PWM generation circuit PGC can determine the logic level of the PWM signal SPWM as logic high during the first bit transmission period BEM1 and the third bit transmission period BEM3. As shown in Figure 3 GRP2, when the pixel drive data value PDD is "6" (e.g., binary 0110), the PWM generation circuit PGC can determine the logic level of the PWM signal SPWM as logic high during the second bit transmission period BEM2 and the third bit transmission period BEM3.

[0074] The LED circuit can emit light during the period when the PWM signal SPWM is logic high. That is, the LED circuit can emit light during the bit emission period when the PWM signal SPWM is logic high. For example, when the pixel drive data value PDD is 4, the LED circuit can emit light during "4UT" (e.g., the third bit emission period BEM3); when the pixel drive data value PDD is 5, the LED circuit can emit light during "5UT" (e.g., the first bit emission period BEM1 and the third bit emission period BEM3); and when the pixel drive data value PDD is 6, the LED circuit can emit light during "6UT" (e.g., the second bit emission period BEM2 and the third bit emission period BEM3).

[0075] Figure 4 It shows the basis Figure 3 A graph showing the relationship between the brightness of the display pixels and the pixel driving data values ​​in the implementation method. Figure 4 The horizontal axis can represent the pixel-driven data value (PDD), and Figure 4 The vertical axis represents the brightness of the displayed pixel PX.

[0076] Reference Figures 1 to 4 The brightness of pixel PX can be non-linear with respect to the pixel drive data value PDD. For example, as mentioned above... Figure 3 As described in Figures GRPa to GRPC, when the pixel driving data value PDD is 4, the light-emitting circuit LEC can emit light within 4UT; when the pixel driving data value PDD is 5, the light-emitting circuit LEC can emit light within 5UT; and when the pixel driving data value PDD is 6, the light-emitting circuit LEC can emit light within 6UT. However, when the pixel driving data value PDD is 4 to 6, the brightness of the display pixel PX may not be linear.

[0077] More specifically, the average brightness of a display pixel PX when the pixel driving data value PDD is 4 and when the pixel driving data value PDD is 6 can differ from the brightness of a display pixel PX when the pixel driving data value PDD is 5. For example, the brightness of a display pixel PX with a pixel driving data value PDD of 5 can be greater than the brightness of a display pixel PX with a pixel driving data value PDD of 4 and when the pixel driving data value PDD is 6. In other words, if the pixel driving data value PDD is 5, the brightness of the display pixel PX can be higher than expected based on the pixel driving data value PDD.

[0078] Such nonlinearity in the brightness of display pixel PX and the value of pixel drive data value PDD can occur for various reasons. However, for the sake of simplicity, it is assumed below that the nonlinearity in the brightness of display pixel PX and the value of pixel drive data value PDD occurs based on the difference in the number of logic level transitions of the value of pixel drive data value PDD. However, the scope of this disclosure is not limited to the specific causes of the nonlinearity in the brightness of display pixel PX and the value of pixel drive data value PDD.

[0079] The number of logic level transitions can represent the number of changes in the logic level of the PWM signal SPWM generated based on the pixel drive data value PDD during the emission period TEM. For example, when the pixel drive data value PDD is 4, the number of logic level transitions can be "2" (e.g., the third time point tC and the fourth time point tD); when the pixel drive data value PDD is 5, the number of logic level transitions can be "4" (e.g., the first time point tA, the second time point tB, the third time point tC, and the fourth time point tD); when the pixel drive data value PDD is 6, the number of logic level transitions can be "2" (e.g., the second time point tB and the fourth time point tD). In this way, when the pixel drive data value PDD is one of 2 to 4 and 6 to 8, the number of logic level transitions can be 2, and when the pixel drive data value PDD is 5, the number of logic level transitions can be 4.

[0080] For the sake of brevity, in the following description, it is assumed that the number of logic level transitions includes the logic level transitions of the PWM signal SPWM at the start and end times of the emission period TEM, but the scope of this disclosure is not limited thereto. For example, the number of logic level transitions may be implemented to include only the logic level transitions of the PWM signal SPWM between the start and end times of the emission period TEM.

[0081] When a display pixel PX operates based on a pixel drive data value PDD corresponding to the number of high logic level transitions, the brightness of the display pixel PX can be relatively increased. When a display pixel PX operates based on a pixel drive data value PDD corresponding to the number of low logic level transitions, the brightness of the display pixel PX can be relatively decreased. For example, compared to a pixel drive data value PDD with a logic level transition count of "2" (e.g., 2, 3, 4, 6, 7, 8), when the pixel drive data value PDD is "5", the number of logic level transitions is "4", therefore the brightness of the display pixel PX can be relatively higher.

[0082] Figure 5 This is a diagram illustrating a brightness adjustment scheme according to some embodiments of the present disclosure. (Refer to...) Figures 1 to 5The brightness adjustment circuit 141 can determine multiple light emission extension adjustment parameters tX. For example, the brightness adjustment circuit 141 can determine first light emission extension adjustment parameters tX1 to fourth light emission extension adjustment parameters tX4, which correspond to the first emission period BEM1 to the fourth emission period BEM4, respectively. The first light emission extension adjustment parameters tX1 to fourth light emission extension adjustment parameters tX4 can each represent the time length used to adjust the first emission period BEM1 to the fourth emission period BEM4.

[0083] The brightness adjustment circuit 141 can provide the first light emission extension adjustment parameter tX1 to the fourth light emission extension adjustment parameter tX4 to the line driver 130. The line driver 130 can generate an adjusted clock signal CLK_adj based on the first light emission extension adjustment parameter tX1 to the fourth light emission extension adjustment parameter tX4. For example, the line driver 130 can determine the switching interval of the adjusted clock signal CLK_adj based on the first light emission extension adjustment parameter tX1 to the fourth light emission extension adjustment parameter tX4. As a more detailed example, the line driver 130 can determine the switching interval of the adjusted clock signal CLK_adj to be longer than the switching interval of the original clock signal CLK_raw through the first light emission extension adjustment parameter tX1 to the fourth light emission extension adjustment parameter tX4. Therefore, the lengths of the first transmission period BEM1 to the fourth transmission period BEM4 can be "(1+tX1)×UT", "(2+tX2)×UT", "(4+tX3)×UT", or "(8+tX4)×UT".

[0084] In other words, according to Figure 5 In this implementation, the length of each bit emission period BEM can be extended based on the luminance extension adjustment parameter tX. In this case, the PWM signal SPWM can be increased based on the length of time a pixel drive bit remains logic high, so that the brightness of the display pixel PX can be adjusted to be relatively higher than the pixel drive data value PDD. However, the scope of this disclosure is not limited thereto. For example, one or more of the plurality of luminance extension adjustment parameters tX can be negative. In this case, the length of the bit emission period BEM corresponding to a negative luminance extension adjustment parameter tX can be decreased, so that the brightness of the display pixel PX can be adjusted to be relatively lower than the pixel drive data value PDD.

[0085] In some embodiments, the brightness adjustment circuit 141 may provide multiple light emission extension adjustment parameters tX to the line driver 130 in the form of light emission extension adjustment parameter combinations (hereinafter referred to as "CMB_tX"). For example, the brightness adjustment circuit 141 may provide the line driver 130 with a light emission extension adjustment parameter combination CMB_tX including a first light emission extension adjustment parameter tX1 to a fourth light emission extension adjustment parameter tX4. However, the scope of this disclosure is not limited thereto. For example, the line driver 130 may store multiple light emission extension adjustment parameter combinations CMB_tX corresponding to different identifiers, and the brightness adjustment circuit 141 may provide the line driver 130 with an identifier corresponding to a light emission extension adjustment parameter combination CMB_tX.

[0086] In some implementations, the row driver 130 may generate an adjusted clock signal CLK_adj instead of the one described above. Figure 3 The original clock signal CLK_raw is described. However, the scope of this disclosure is not limited to a specific method for generating the adjusted clock signal CLK_adj. For example, the row driver 130 may be based on the above reference. Figure 3 The original clock signal CLK_raw is used to generate the adjusted clock signal CLK_adj.

[0087] Figure 6 This is a diagram illustrating a brightness adjustment scheme according to some embodiments of the present disclosure. (Refer to...) Figures 1 to 4 and Figure 6 The brightness adjustment circuit 141 can determine multiple light emission shortening adjustment parameters tS. For example, the brightness adjustment circuit 141 can determine first light emission shortening adjustment parameters tS1 to fourth light emission shortening adjustment parameters tS4, which correspond to the first emission period BEM1 to the fourth emission period BEM4, respectively. The first light emission shortening adjustment parameters tS1 to fourth light emission shortening adjustment parameters tS4 can each represent the time length used to adjust the first emission period BEM1 to the fourth emission period BEM4.

[0088] The line driver 130 can generate a masking signal MSK. The masking signal MSK may include multiple masking periods MP, each corresponding to a multiple bit transmission periods BEM. For example, the masking signal MSK may include a first masking period MP1 to a fourth masking period MP4. The first masking period MP1 to the fourth masking period MP4 may be included in the first bit transmission period BEM1 to the fourth bit transmission period BEM4, respectively.

[0089] The brightness adjustment circuit 141 can provide the first light emission shortening adjustment parameters tS1 to the fourth light emission shortening adjustment parameters tS4 to the horizontal driver 130. The horizontal driver 130 can generate a masking signal MSK based on the first light emission shortening adjustment parameters tS1 to the fourth light emission shortening adjustment parameters tS4. The horizontal driver 130 can determine the duration of the first masking period MP1 to the fourth masking period MP4 included in the masking signal MSK based on the first light emission shortening adjustment parameters tS1 to the fourth light emission shortening adjustment parameters tS4. For example, the horizontal driver 130 can determine the duration of the first masking period MP1 to the fourth masking period MP4 to be the duration corresponding to the first light emission shortening adjustment parameters tS1 to the fourth light emission shortening adjustment parameters tS4, respectively.

[0090] During multiple masking periods (MPs), the masking signal MSK can be logic low. Periods that are not multiple masking periods (MPs) are referred to as bypass periods. During bypass periods, the masking signal MSK can be logic high.

[0091] The masking circuit MC can generate a masked PWM signal SPWM_MSK by masking the PWM signal SPWM based on the masking signal MSK. For example, when the masking signal MSK is logic high, the masking circuit MC can determine the logic level of the masked PWM signal SPWM_MSK to be the same as the logic level of the PWM signal SPWM. When the masking signal MSK is logic low, the masking circuit MC can determine the logic level of the masked PWM signal SPWM_MSK to be logic low. That is, as... Figure 6 As shown by the stripes, the masking circuit MC can determine the logic level of the masking PWM signal SPWM_MSK to be logic low during the first masking period MP1 to the fourth masking period MP4, regardless of the pixel drive data value PDD.

[0092] The masked PWM signal SPWM_MSK may include multiple shortened bit transmit periods (SBEMs). Each shortened bit transmit period (SBEM) may correspond to a different bit transmit period (BEM). For example, the masked PWM signal SPWM_MSK may include first shortened bit transmit periods (SBEM1) to fourth shortened bit transmit periods (SBEM4), each corresponding to a first transmit period (BEM1) to a fourth transmit period (BEM4).

[0093] The length of each of the shortened bit emission periods (SBEMs) can be a length corresponding to "the length of the corresponding bit emission period (BEM) minus the length of the corresponding occlusion period (MP)". For example, the length of the first shortened bit emission period (SBEM1) can correspond to the value obtained by subtracting the first emission shortening adjustment parameter tS1 from the length of the first emission period (BEM1). In this way, the lengths of the first shortened bit emission period (SBEM1) to the fourth shortened bit emission period (SBEM4) can be "(1-tS1)×UT", "(2-tS2)×UT", "(4-tS3)×UT", and "(8-tS4)×UT".

[0094] In other words, according to Figure 6 In this implementation, the duration for which the display pixel PX emits light based on a pixel drive bit can be shortened based on the light emission shortening adjustment parameter tS. In this case, the duration for which the light-emitting circuit LEC emits light based on a pixel drive bit can be shortened, so that the brightness of the display pixel PX can be adjusted to be relatively lower than the pixel drive data value PDD.

[0095] In some embodiments, the brightness adjustment circuit 141 may provide multiple light-emitting shortening adjustment parameters tS to the line driver 130 in the form of light-emitting shortening adjustment parameter combinations (hereinafter referred to as "CMB_tS"). For example, the brightness adjustment circuit 141 may provide the line driver 130 with a light-emitting shortening adjustment parameter combination CMB_tS including a first light-emitting shortening adjustment parameter tS1 to a fourth light-emitting shortening adjustment parameter tS4. However, the scope of this disclosure is not limited thereto. For example, the line driver 130 may store multiple light-emitting shortening adjustment parameter combinations CMB_tS corresponding to different identifiers, and the brightness adjustment circuit 141 may provide the line driver 130 with an identifier corresponding to a light-emitting shortening adjustment parameter combination CMB_tS.

[0096] Figure 7 This is a diagram illustrating a brightness adjustment scheme according to some embodiments of the present disclosure. (Refer to...) Figures 1 to 7 The brightness adjustment circuit 141 can be adjusted by applying the above reference. Figure 5 and Figure 6 The two methods described adjust the brightness of the display pixel PX. For example, the brightness adjustment circuit 141 can determine a plurality of light emission extension adjustment parameters tX and a plurality of light emission shortening adjustment parameters tS (hereinafter, these parameters may be referred to as adjustment parameters tX, tS). More specifically, the brightness adjustment circuit 141 can determine first light emission extension adjustment parameters tX1 to fourth light emission extension adjustment parameters tX4 and first light emission shortening adjustment parameters tS1 to fourth light emission shortening adjustment parameters tS4.

[0097] The brightness adjustment circuit 141 can provide the first light emission extension adjustment parameter tX1 to the fourth light emission extension adjustment parameter tX4 and the first light emission shortening adjustment parameter tS1 to the fourth light emission shortening adjustment parameter tS4 to the line driver 130.

[0098] The line driver 130 can generate an adjusted clock signal CLK_adj based on the first light-emitting extension adjustment parameters tX1 to the fourth light-emitting extension adjustment parameters tX4. The PWM generation circuit PGC can generate a PWM signal SPWM based on the first light-emitting extension adjustment parameters tX1 to the fourth light-emitting extension adjustment parameters tX4. In this case, the PWM signal SPWM can include the first transmission period BEM1 to the fourth transmission period BEM4. The lengths of the first transmission period BEM1 to the fourth transmission period BEM4 can be "(1+tX1)×UT", "(2+tX2)×UT", "(4+tX3)×UT", and "(8+tX4)×UT", respectively.

[0099] The line driver 130 can generate a masking signal MSK based on the first light-emitting shortening adjustment parameters tS1 to the fourth light-emitting shortening adjustment parameters tS4. The masking circuit MC can generate a masking PWM signal SPWM_MSK based on the PWM signal SPWM and the masking signal MSK. In this case, the masking PWM signal SPWM_MSK can include the first shortened bit transmission period SBEM1 to the fourth shortened bit transmission period SBEM4. The lengths of the first shortened bit transmission period SBEM1 to the fourth shortened bit transmission period SBEM4 can be "(1+tX1-tS1)×UT", "(2+tX2-tS2)×UT", "(4+tX3-tS3)×UT", and "(8+tX4-tS4)×UT", respectively.

[0100] In other words, according to Figure 7 In this implementation, the brightness adjustment circuit 141 can increase or decrease the brightness of the display pixel PX based on the pixel drive data value PDD by adjusting the waveform of the masking signal MSK and the waveform of the clock signal CLK.

[0101] The reference table may include, for example, a predetermined data structure stored in the reference table memory circuit 150, which associates pixel driving data values ​​(or characteristics derived from pixel driving data values) with brightness adjustment reference information (e.g., logic level transition counts, brightness adjustment target values, or emission extension / shortening adjustment parameters). The brightness adjustment reference information may be used by the brightness adjustment circuit 141 to determine specific adjustment parameters (which are subsequently used to modulate signal waveforms, such as the waveform of a clock signal and the waveform of a masking signal, to control the total emission time length of the pixels) to compensate for nonlinear brightness deviations.

[0102] Figure 8 and Figure 9 This is a diagram illustrating the configuration of a reference table according to some implementation methods. (Refer to...) Figures 1 to 9 The reference table memory circuit 150 may include a first reference table TBL_REFa and a second reference table TBL_REFb.

[0103] The first reference table TBL_REFa can indicate the number of logic level transitions (NLLTs) for each of the multiple pixel drive data values ​​(PDDs). For example, when the pixel drive data value (PDD) is 2 to 4, the first reference table TBL_REFa can indicate that the number of logic level transitions (NLLTs) is 2, and when the pixel drive data value (PDD) is 5, the first reference table TBL_REFa can indicate that the number of logic level transitions (NLLTs) is 4. In this way, the first reference table TBL_REFa can indicate the number of logic level transitions (NLLTs) corresponding to each of the cases where the pixel drive data value (PDD) is 0 to 15.

[0104] The second reference table TBL_REFb can indicate the target brightness adjustment value LATV corresponding to different numbers of logic level transitions NLLT. For example, the second reference table TBL_REFb can indicate that the target brightness adjustment value LATV when the number of logic level transitions NLLT is 0 is the first target brightness adjustment value LATVa; the target brightness adjustment value LATV when the number of logic level transitions NLLT is 2 is the second target brightness adjustment value LATVb; and the target brightness adjustment value LATV when the number of logic level transitions NLLT is 4 is the third target brightness adjustment value LATVc.

[0105] The brightness adjustment circuit 141 can identify the number of logic level transitions (NLLT) corresponding to the pixel drive data value PDD based on the first reference table TBL_REFa. For example, the brightness adjustment circuit 141 can identify that the number of logic level transitions (NLLT) corresponding to the pixel drive data value PDD "5" is "4" based on the first reference table TBL_REFa.

[0106] The brightness adjustment circuit 141 can identify the brightness adjustment target value LATV corresponding to the pixel driving data value PDD based on the second reference table TBL_REFb. For example, the brightness adjustment circuit 141 can identify the third brightness adjustment target value LATVc corresponding to the pixel driving data value PDD "5" based on the second reference table TBL_REFb.

[0107] Brightness adjustment circuit 141 can determine the light emission extension adjustment parameter combination CMB_tX and the light emission shortening adjustment parameter combination CMB_tS (hereinafter, these combinations may be referred to as adjustment parameter combinations CMB_tX and CMB_tS) based on the identified brightness adjustment target value LATV. For example, brightness adjustment circuit 141 can determine adjustment parameter combinations CMB_tX and CMB_tS such that display pixel PX operating based on pixel drive data value PDD "5" is above the reference value. Figure 3 The described method drives the operation by adjusting the target value of LATUC to a higher third brightness level.

[0108] In some implementations, one or more of the brightness adjustment target values ​​LATV included in the second reference table TBL_REFb may be negative. For example, the second brightness adjustment target value LATVb may be negative. However, the scope of this disclosure is not limited thereto.

[0109] In this way, the brightness adjustment circuit 141 can individually determine the adjustment parameter combination CMB_tX, CMB_tS for each display pixel PX based on the first reference table TBL_REFa and the second reference table TBL_REFb. In this case, the brightness of each display pixel PX can be individually adjusted according to the number of logic level transitions NLLT corresponding to the pixel drive data value PDD. Therefore, according to some embodiments of this disclosure, the color fidelity of the display device 100 can be improved.

[0110] Figure 10 This is a diagram illustrating the configuration of a reference table according to some implementation methods. (Refer to...) Figures 1 to 7 and Figure 10 The reference table memory circuit 150 may include a third reference table TBL_REFc.

[0111] The third reference table TBL_REFc can indicate the brightness adjustment target value LATV for each of the multiple pixel drive data values ​​PDD. For example, the third reference table TBL_REFc can store the zeroth brightness adjustment target value LATV0 to the fifteenth brightness adjustment target value LATV15 corresponding to the cases where the pixel drive data value PDD is 0 to 15, respectively.

[0112] The brightness adjustment circuit 141 can identify the brightness adjustment target value LATV corresponding to the pixel driving data value PDD based on the third reference table TBL_REFc. For example, the brightness adjustment circuit 141 can identify that the brightness adjustment target value LATV corresponding to the pixel driving data value PDD "5" is the fifth brightness adjustment target value LATV5.

[0113] The brightness adjustment circuit 141 can determine the adjustment parameter combination CMB_tX, CMB_tS based on the identified brightness adjustment target value LATV. For example, the brightness adjustment circuit 141 can determine the adjustment parameter combination CMB_tX, CMB_tS such that the display pixel PX operating based on the pixel driving data value PDD "5" is higher than the display pixel PX operating based on the pixel driving data value PDD '5'. Figure 3 The described method drives the operation by adjusting the target value of the LATTV5 brightness.

[0114] In some implementations, one or more of the brightness adjustment target values ​​LATV included in the third reference table TBL_REFc may be negative. For example, the fifth brightness adjustment target value LATV5 may be negative. However, the scope of this disclosure is not limited thereto.

[0115] In this way, the brightness adjustment circuit 141 can individually determine the adjustment parameter combination CMB_tX, CMB_tS for each display pixel PX based on the third reference table TBL_REFc and the second reference table TBL_REFb. In this case, the brightness of each display pixel PX can be adjusted individually based on the pixel drive data value PDD.

[0116] In addition, compared with the reference Figures 8 to 9 The described implementation methods differ, depending on... Figure 10 In this implementation, the brightness adjustment target value LATV is determined for each pixel drive data value PDD, thereby further improving the color fidelity of the display device 100.

[0117] Figure 11 This is a diagram illustrating in more detail the brightness correction method used for multiple display pixels. (See reference...) Figures 1 to 11 The display pixel array 110 may include a first display pixel row ROW1 and a second display pixel row ROW2. The first display pixel row ROW1 may include display pixels PX11, PX12, and PX13, and the second display pixel row ROW2 may include display pixels PX21, PX22, and PX23. (Previously referred to...) Figure 1 The physical configuration of the display pixel array 110 is described, therefore a detailed description is omitted.

[0118] The row driver 130 can generate a first clock signal CLK1 (e.g., as an adjusted clock signal CLK_adj) based on a first light emission extension adjustment parameter combination CMB_tXa. The row driver 130 can provide the first clock signal CLK1 to the first display pixel row ROW1.

[0119] Display pixels PX11, PX12, and PX13 can receive the first clock signal CLK1 via the first clock line CL1. Therefore, the brightness of each of display pixels PX11, PX12, and PX13 can be adjusted based on the first light emission extension adjustment parameter combination CMB_tXa.

[0120] The line driver 130 can generate a masking signal MSK11 based on a first light-emitting shortening adjustment parameter combination CMB_tSa, a masking signal MSK12 based on a second light-emitting shortening adjustment parameter combination CMB_tSb, and a masking signal MSK13 based on a third light-emitting shortening adjustment parameter combination CMB_tSc. The line driver 130 can provide the masking signals MSK11 to MSK13 to the masking lines ML11 to ML13 respectively.

[0121] Display pixels PX11, PX12, and PX13 can receive masking signals MSK11 to MSK13 via masking lines ML11 to ML13, respectively. Therefore, the brightness of display pixels PX11, PX12, and PX13 can be adjusted based on the first light emission shortening adjustment parameter combination CMB_tSa to the third light emission shortening adjustment parameter combination CMB_tSc, respectively.

[0122] In this way, the brightness of display pixels PX11, PX12, and PX13 can be adjusted jointly based on the first light emission extension adjustment parameter combination CMB_tXa, and can be adjusted independently based on the first light emission shortening adjustment parameter combination CMB_tSa to the third light emission shortening adjustment parameter combination CMB_tSc, respectively.

[0123] In other words, the brightness adjustment circuit 141 can individually determine the brightness adjustment target value LATV of each display pixel PX based on the corresponding pixel drive data value PDD (or the number of logic level transitions NLLT), and can adjust the brightness of each display pixel PX based on the determined brightness adjustment target value LATV.

[0124] More specifically, the brightness adjustment circuit 141 can individually determine the brightness adjustment target value LATV for each display pixel PX included in the first display pixel row ROW1. The brightness adjustment circuit 141 can determine the first light emission extension adjustment parameter combination CMB_tXa by considering the brightness adjustment target value LATV of the display pixel PX included in the first display pixel row ROW1. Thereafter, the brightness adjustment circuit 141 can individually determine the light emission shortening adjustment parameter combination CMB_tS corresponding to each display pixel PX included in the first display pixel row ROW1, such that the brightness adjustment target value LATV corresponding to each display pixel PX included in the first display pixel row ROW1 is satisfied.

[0125] Similarly, the brightness adjustment circuit 141 can individually adjust the brightness of the display pixels PX included in the second display pixel row ROW2. For example, the brightness adjustment circuit 141 can determine a second light emission extension adjustment parameter combination CMB_tXb for waveform adjustment of the second clock signal CLK2, and can determine a fourth light emission shortening adjustment parameter combination CMB_tSd to a sixth light emission shortening adjustment parameter combination CMB_tSf for waveform adjustment of the masking signals MSK21 to MSK23. The method for adjusting the brightness of the display pixels PX included in the second display pixel row ROW2 is similar to the method described above with reference to the first display pixel row ROW1, therefore a detailed description is omitted.

[0126] Figure 12 This is a flowchart illustrating an operation method of a display device according to some embodiments of the present disclosure. In the following, reference is made to... Figures 1 to 12 Describe a method to control a display pixel row (ROW).

[0127] In operation S110, the display device 100 can determine multiple brightness adjustment target values ​​LATV corresponding to multiple display pixels PX within a display pixel row ROW. For example, the brightness adjustment circuit 141 can be based on the above reference. Figures 8 to 10 The description of one or more reference tables TBL_REF determines the target value LATV for brightness adjustment of each of the display pixels PX11, PX12, and PX13.

[0128] In operation S120, the display device 100 may determine a combination of light emission extension adjustment parameters CMB_tX for a display pixel row ROW. For example, the brightness adjustment circuit 141 may determine a combination of light emission extension adjustment parameters CMB_tX based on a plurality of brightness adjustment target values ​​LATV previously determined in operation S110.

[0129] In some implementations, the display device 100 may determine the light emission extension adjustment parameter combination CMB_tX based on the highest value among a plurality of brightness adjustment target values ​​LATV determined in operation S110.

[0130] During operation S130, the display device 100 can determine multiple combinations of light emission shortening adjustment parameters CMB_tS corresponding to the multiple display pixels PX respectively. For example, the brightness adjustment circuit 141 can individually determine the combination of light emission shortening adjustment parameters CMB_tS corresponding to each display pixel PX, such that the brightness adjustment target value LATV corresponding to each display pixel PX is satisfied.

[0131] In operation S140, the display device 100 can drive the display pixel PX based on the light emission extension adjustment parameter combination CMB_tX and multiple light emission shortening adjustment parameter combinations CMB_tS determined in operations S120 and S130. For example, the brightness adjustment circuit 141 can provide the light emission extension adjustment parameter combination CMB_tX and multiple light emission shortening adjustment parameter combinations CMB_tS to the line driver 130. The line driver 130 can generate an adjusted clock signal CLK_adj based on the light emission extension adjustment parameter combination CMB_tX, and can generate multiple masking signals MSK based on the multiple light emission shortening adjustment parameter combinations CMB_tS.

[0132] Figure 13 This is a graph illustrating the relationship between the brightness of a display pixel and pixel driving data values ​​according to some embodiments of the present disclosure. Figure 13 The horizontal axis can represent the pixel-driven data value (PDD), and Figure 13 The vertical axis represents the brightness of the displayed pixel PX.

[0133] Reference Figures 1 to 13 The brightness adjustment circuit 141 can adjust the brightness of the display pixel PX based on the pixel driving data value PDD. For example, by determining the light emission extension adjustment parameter combination CMB_tX and the light emission shortening adjustment parameter combination CMB_tS, the brightness adjustment circuit 141 can increase the brightness of the display pixel PX when the pixel driving data value PDD has a value corresponding to the number of low logic level transitions NLLT (e.g., 2, 3, 4, 6, 7, 8), and can decrease the brightness of the display pixel PX when the pixel driving data value PDD has a value corresponding to the number of high logic level transitions NLLT (e.g., 5). Therefore, the brightness of the display pixel PX can be linear with respect to the pixel driving data value PDD, and the color fidelity of the display device 100 can be improved.

[0134] For a more concise explanation, Figure 13 The illustration shows a representative example in which the brightness adjustment circuit 141 decreases and increases the brightness of the display pixel PX according to the pixel driving data value PDD, but the scope of this disclosure is not limited thereto. For example, the brightness adjustment circuit 141 can linearize the brightness of the display pixel PX and the value of the pixel driving data value PDD by increasing the brightness of all display pixels PX; or it can linearize the brightness of the display pixel PX and the value of the pixel driving data value PDD by decreasing the brightness of all display pixels PX.

[0135] Figure 14 and Figure 15 This is a diagram illustrating the configuration of a reference table according to some implementation methods. (Refer to...) Figures 1 to 15The reference table memory circuit 150 may include a fourth reference table TBL_REFd and a fifth reference table TBL_REFe. In other words, the reference table memory circuit 150 may include the above-mentioned references. Figures 8 to 10 The description refers to one or more of the reference tables TBL_REF, the fourth reference table TBL_REFd, and the fifth reference table TBL_REFe.

[0136] The fourth reference table TBL_REFd can store multiple combinations of emission extension adjustment parameters CMB_tX. For example, the fourth reference table TBL_REFd may include a first emission extension adjustment parameter combination CMB_tX_A to a third emission extension adjustment parameter combination CMB_tX_C.

[0137] Multiple combinations of light emission extension adjustment parameters CMB_tX stored in the fourth reference table TBL_REFd can correspond to different combinations of the first to fourth light emission extension adjustment parameters tX1, tX2, tX3, and tX4, respectively. For example, the first light emission extension adjustment parameter combination CMB_tX_A may include light emission extension adjustment parameters tX1_A, tX2_A, tX3_A, and tX4_A; the second light emission extension adjustment parameter combination CMB_tX_B may include light emission extension adjustment parameters tX1_B, tX2_B, tX3_B, and tX4_B; and the third light emission extension adjustment parameter combination CMB_tX_C may include light emission extension adjustment parameters tX1_C, tX2_C, tX3_C, and tX4_C.

[0138] The brightness adjustment circuit 141 can determine a light emission extension adjustment parameter combination CMB_tX for a display pixel row ROW based on one of a plurality of light emission extension adjustment parameter combinations CMB_tX stored in the fourth reference table TBL_REFd. That is, the brightness adjustment circuit 141 can adjust the waveform of the clock signal CLK based on one of a plurality of predetermined light emission extension adjustment parameter combinations CMB_tX.

[0139] The fifth reference table TBL_REFe can store multiple combinations of emission shortening adjustment parameters CMB_tS. For example, the fifth reference table TBL_REFe may include a first emission shortening adjustment parameter combination CMB_tS_A to a third emission shortening adjustment parameter combination CMB_tS_C.

[0140] Multiple combinations of light emission shortening adjustment parameters CMB_tS stored in the fifth reference table TBL_REFe can correspond to different combinations of the first to fourth light emission shortening adjustment parameters tS1, tS2, tS3, and tS4, respectively. For example, the first light emission shortening adjustment parameter combination CMB_tS_A may include light emission shortening adjustment parameters tS1_A, tS2_A, tS3_A, and tS4_A; the second light emission shortening adjustment parameter combination CMB_tS_B may include light emission shortening adjustment parameters tS1_B, tS2_B, tS3_B, and tS4_B; and the third light emission shortening adjustment parameter combination CMB_tS_C may include light emission shortening adjustment parameters tS1_C, tS2_C, tS3_C, and tS4_C.

[0141] The brightness adjustment circuit 141 can determine the light emission shortening adjustment parameter combination CMB_tS for each display pixel PX based on one of a plurality of light emission shortening adjustment parameter combinations CMB_tS stored in the fifth reference table TBL_REFe. That is, the brightness adjustment circuit 141 can adjust the waveform of each masking signal MSK based on one of a plurality of predetermined light emission shortening adjustment parameter combinations CMB_tS.

[0142] In other words, the brightness adjustment circuit 141 can adjust the waveforms of the clock signal CLK and the masking signal MSK based on a predetermined combination of adjustment parameters CMB_tX and CMB_tS. However, the scope of this disclosure is not limited thereto, and the brightness adjustment circuit 141 can also adjust the waveforms of the clock signal CLK and the masking signal MSK based on any combination of multiple adjustment parameters tX and tS. That is, the scope of this disclosure is not limited to the specific method by which the brightness adjustment circuit 141 determines the combination of adjustment parameters CMB_tX and CMB_tS used to adjust the waveforms of the clock signal CLK and the masking signal MSK.

[0143] Figure 16 This is an exemplary diagram illustrating how a brightness adjustment circuit determines a combination of light emission shortening adjustment parameters. In the following text, refer to... Figures 1 to 16 An exemplary method is described for determining, via a brightness adjustment circuit 141, a combination of light-emitting shortening adjustment parameters CMB_tS to be applied to display pixel PX11.

[0144] The brightness adjustment circuit 141 can identify the brightness adjustment target value LATV corresponding to the pixel driving data value PDD stored in the display pixel PX11. For example, the brightness adjustment circuit 141 can determine the brightness adjustment target value LATV corresponding to the pixel driving data value PDD based on the first reference table TBL_REFa and the second reference table TBL_REFb, or it can determine the brightness adjustment target value LATV corresponding to the pixel driving data value PDD based on the third reference table TBL_REFc.

[0145] The brightness adjustment circuit 141 can determine the light emission extension adjustment parameter combination CMB_tX to be applied to the display pixel PX11. For example, the brightness adjustment circuit 141 can be configured with reference to the above. Figure 11 The operation S120 describes a similar method for determining the combination of light emission extension adjustment parameters CMB_tX.

[0146] More specifically, the brightness adjustment circuit 141 can determine the light emission extension adjustment parameter combination CMB_tX by considering the brightness adjustment target value LATV of each of the display pixels PX included in the first display pixel row ROW1. For example, the brightness adjustment circuit 141 can determine one of the multiple light emission extension adjustment parameter combinations CMB_tX stored in the fourth reference table TBL_REFd as the light emission extension adjustment parameter combination CMB_tX of the first display pixel row ROW1.

[0147] The brightness adjustment circuit 141 can calculate the expected increase in brightness (LEIV) based on the pixel driving data value PDD and the light emission extension adjustment parameter combination CMB_tX stored in the display pixel PX11. For example, the brightness adjustment circuit 141 can calculate the expected increase in brightness (LEIV) by adding the duration of the bit emission period BEM corresponding to the pixel driving bit whose value is "1" in the pixel driving data value PDD to the light emission extension adjustment parameter combination CMB_tX.

[0148] The brightness adjustment circuit 141 can calculate the brightness adjustment residual value RSDL based on the brightness adjustment target value LATV and the expected increase value LEIV corresponding to the pixel driving data value PDD stored in the display pixel PX11. For example, the brightness adjustment circuit 141 can determine the brightness adjustment residual value RSDL as the value obtained by subtracting the expected increase value LEIV from the brightness adjustment target value LATV.

[0149] The brightness adjustment circuit 141 can determine the light emission shortening adjustment parameter combination CMB_tS corresponding to the pixel drive data value PDD stored in the display pixel PX11 based on the brightness adjustment residual value RSDL. For example, the brightness adjustment circuit 141 can determine one of the multiple light emission shortening adjustment parameter combinations CMB_tS stored in the fifth reference table TBL_REFe as the light emission shortening adjustment parameter combination CMB_tS for the display pixel PX11. As a more detailed example, the brightness adjustment circuit 141 can determine the light emission shortening adjustment parameter combination CMB_tS such that the sum of the shortened time lengths of the bit emission period BEM corresponding to the pixel drive bit whose value is "1" in the pixel drive data value PDD becomes the brightness adjustment residual value RSDL (or a similar value).

[0150] In this way, the brightness adjustment circuit 141 can adjust the waveforms of the clock signal CLK and the masking signal MSK provided to each display pixel PX according to the pixel drive data value PDD.

[0151] In some implementations, the display pixel PX can perform light emission operations corresponding to different pixel driving data values ​​PDD during different frame periods. For example, the pixel driving data value PDD used by the display pixel PX for light emission operation during the light emission period TEM included in the first frame period may be different from the pixel driving data value PDD used by the display pixel PX for light emission operation during the light emission period TEM included in the second frame period. In this case, the waveforms of the clock signal CLK and the masking signal MSK provided by the brightness adjustment circuit 141 to the display pixel PX during the first frame period may be different from the waveforms of the clock signal CLK and the masking signal MSK provided to the display pixel PX during the second frame period. For example, the combination of the lengths of multiple masking periods during the first frame period may be different from the combination of the lengths of multiple masking periods during the second frame period after the first frame period. For example, the combination of the lengths of multiple bit emission periods during the first frame period may be different from the combination of the lengths of multiple bit emission periods during the second frame period.

[0152] Figure 17 This is a block diagram illustrating a display device according to some embodiments. (Refer to...) Figures 1 to 17 The display device 200 may include a display pixel array 210, a column driver 220, a row driver 230, a timing controller 240, and a reference table memory circuit 250. In the following description, the display device 200 and the above-mentioned reference table memory circuit will be primarily described. Figures 1 to 16 The differences between the described display devices 100.

[0153] Multiple display pixels PX can be connected to different clock lines CL and different masking lines ML. For example, display pixel PX11 can be connected to masking line ML11 and clock line CL11, and display pixel PX12 can be connected to masking line ML12 and clock line CL12.

[0154] The brightness adjustment circuit 241 can independently determine the light emission extension adjustment parameter combination CMB_tX for each display pixel PX. For example, the brightness adjustment circuit 241 can apply different light emission extension adjustment parameter combinations CMB_tX to display pixels PX included in a display pixel row ROW.

[0155] As a more detailed example, the brightness adjustment circuit 241 can apply different combinations of light emission extension adjustment parameters CMB_tX to display pixels PX11 and PX12. In this case, the line driver 230 can provide adjusted clock signals CLK_adj with different waveforms to clock lines CL11 and CL12.

[0156] For a more concise explanation, Figure 17 Some embodiments are shown that include all display pixels PX in display pixel array 210 connected to different clock lines CL, but the scope of this disclosure is not limited thereto. For example, some pixels included in display pixel array 210 may share clock line CL. As a more detailed example, adjacent display pixels PX forming a display pixel group (e.g., display pixel PX corresponding to red, display pixel PX corresponding to green, and display pixel PX corresponding to blue) may share a single clock line CL.

[0157] Figure 18 This is a diagram illustrating the configuration of a reference table according to some implementation methods. (Refer to...) Figures 1 to 18 The reference table memory circuit 250 may include a sixth reference table TBL_REFf.

[0158] The sixth reference table TBL_REFf can indicate multiple adjustment parameters tX, tS for each of the multiple pixel driving data values ​​PDD. For example, the sixth reference table TBL_REFf can represent different combinations of multiple adjustment parameters tX, tS for each of the cases where the pixel driving data value PDD is 0 to 15. For example, the sixth reference table TBL_REFf may include adjustment parameters tX1_0, tX2_0, tX3_0, tX4_0, tS1_0, tS2_0, tS3_0, tS4_0 for the case where the pixel driving data value PDD is 0; and may include adjustment parameters tX1_1, tX2_1, tX3_1, tX4_1, tS1_1, tS2_1, tS3_1, tS4_1 for the case where the pixel driving data value PDD is 1.

[0159] The brightness adjustment circuit 141 can individually determine the adjustment parameter combination CMB_tX, CMB_tS for each display pixel PX based on the sixth reference table TBL_REFf. In this case, the brightness of each display pixel PX can be adjusted individually based on the pixel drive data value PDD.

[0160] For a more concise explanation, Figure 18This is a representative example of how the brightness adjustment circuit 141 determines the combination of adjustment parameters CMB_tX and CMB_tS for each display pixel PX based on the sixth reference table TBL_REFf, but the scope of this disclosure is not limited thereto. For example, the brightness adjustment circuit 141 may be implemented with reference to the above reference table. Figures 8 to 10 The method described determines the brightness adjustment target value LATV for each display pixel PX, and the adjustment parameter combination CMB_tX and CMB_tS for each display pixel PX are determined based on the brightness adjustment target value LATV.

[0161] While this specification contains numerous specific details of implementation, these details should not be construed as limiting the scope of any invention or the scope of claims, but rather as descriptions of features specific to particular embodiments of the invention. Specific features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases one or more features from the combination may be removed, and the combination may be for sub-combinations or variations thereof.

[0162] The foregoing description describes specific embodiments for carrying out this disclosure. However, the scope of this disclosure is not limited thereto and should be determined based on the appended claims and their equivalents.

Claims

1. A display device, comprising: The first display pixel is configured to store the first pixel driving data value; The brightness adjustment circuit is configured to determine multiple adjustment parameters corresponding to the first pixel driving data value based on one or more reference tables; as well as The line driver is configured to control the operation of the first display pixel based on the plurality of adjustment parameters.

2. The display device as claimed in claim 1, wherein: The line driver is configured to provide a first clock signal to the first display pixel; The plurality of adjustment parameters includes a plurality of light emission extension adjustment parameters; and The line driver is also configured to determine multiple switching intervals of the first clock signal based on the multiple light emission extension adjustment parameters.

3. The display device as claimed in claim 2, wherein: The line driver is also configured to provide a first masking signal to the first display pixel; The plurality of adjustment parameters includes a plurality of light emission shortening adjustment parameters; and The line driver is also configured to determine the length of multiple occlusion periods included in the first occlusion signal based on the plurality of light-emitting shortening adjustment parameters.

4. The display device as claimed in claim 3, wherein, The brightness adjustment circuit is configured as follows: Based on the one or more reference tables, a first brightness adjustment target value corresponding to the first pixel driving data value is identified; and The plurality of light emission extension adjustment parameters and the plurality of light emission shortening adjustment parameters are determined based on the first brightness adjustment target value.

5. The display device as claimed in claim 4, wherein, The brightness adjustment circuit is configured as follows: The plurality of light emission extension adjustment parameters are determined based on the first brightness adjustment target value; The expected increase in brightness is calculated based on the multiple light emission extension adjustment parameters and the first pixel driving data value. Calculate the brightness adjustment residual value based on the first brightness adjustment target value and the expected increase in brightness; and The plurality of light emission shortening adjustment parameters are determined based on the brightness adjustment residual value.

6. The display device as claimed in claim 4, wherein, The one or more reference tables include: A first reference table indicates the number of logic level transitions for each pixel driving data value among a plurality of pixel driving data values, wherein the plurality of pixel driving data values ​​includes a first pixel driving data value; and The second reference table includes a plurality of brightness adjustment target values ​​corresponding to different numbers of logic level transitions.

7. The display device as claimed in claim 4, wherein, The one or more reference tables include: The third reference table stores a second plurality of brightness adjustment target values ​​corresponding to a plurality of pixel driving data values, wherein the plurality of pixel driving data values ​​include a first pixel driving data value.

8. The display device as claimed in claim 4, further comprising: The second display pixel is configured to store the second pixel driving data value. The row driver is also configured as follows: The first clock signal is provided to the second display pixel; and A second masking signal, different from the first masking signal, is provided to the second display pixel.

9. The display device as claimed in claim 8, wherein, The brightness adjustment circuit is also configured as follows: Based on the one or more reference tables, a second brightness adjustment target value corresponding to the second pixel driving data value is identified; and The plurality of light emission extension adjustment parameters are determined based on the fact that the first brightness adjustment target value is higher than the second brightness adjustment target value.

10. The display device as claimed in claim 3, wherein, The first display pixel includes: The pulse width modulation generation circuit is configured to generate a pulse width modulation signal corresponding to the first pixel driving data value based on a first clock signal. The masking circuit is configured to generate a masked pulse width modulation signal by masking the pulse width modulation signal based on a first masking signal; and The light-emitting circuit is configured to operate based on a masking pulse width modulation signal.

11. The display device as claimed in claim 2, further comprising: The third display pixel is configured to store the third pixel driving data value; as well as The column driver is configured to control the first data line to provide a first pixel driving data value to a first display pixel and a third pixel driving data value to a third display pixel. The row driver is also configured to provide a second clock signal with a different waveform than the first clock signal to the third display pixel.

12. The display device as claimed in claim 1, wherein, The row driver is configured as follows: Based on the aforementioned multiple adjustment parameters, the total light emission time of the first display pixel is controlled based on the first pixel driving data value.

13. A display pixel, comprising: The pulse width modulation generation circuit is configured to generate pulse width modulation signals corresponding to multiple pixel drive bits based on a clock signal; The masking circuit is configured to generate a masked pulse width modulation signal by masking the pulse width modulation signal based on the masking signal. as well as The light-emitting circuit is configured to operate based on a masking pulse width modulation signal.

14. The display pixel as claimed in claim 13, wherein: The pulse width modulation signal includes multiple bit transmission periods, each corresponding to one of the multiple pixel drive bits. The masking signal includes multiple masking periods, each corresponding to one of the multiple bit transmission periods, and The combination of lengths of multiple occlusion periods during the first frame period is different from the combination of lengths of multiple occlusion periods during the second frame period following the first frame period.

15. The display pixel as claimed in claim 14, wherein: The combination of lengths of multiple bit transmission periods during the first frame period is different from the combination of lengths of multiple bit transmission periods during the second frame period.

16. The display pixel as claimed in claim 15, wherein, The pulse width modulation generation circuit includes a shift register configured to store the plurality of pixel drive bits and operate based on a clock signal. The waveform of the clock signal during the first frame period is different from the waveform of the clock signal during the second frame period.

17. A display device, comprising: The line driver is configured to output a first clock signal and a second clock signal with a different waveform from the first clock signal during the first frame period. The first display pixel is configured to perform a first light-emitting operation based on a first pixel driving data value and a first clock signal; as well as The second display pixel is configured to perform a second light emission operation based on the second pixel drive data value and the second clock signal.

18. The display device of claim 17, further comprising: The column driver is configured to provide a first pixel driving data value to a first display pixel and a second pixel driving data value to a second display pixel via a first data line.

19. The display device as claimed in claim 17, in, The line driver is also configured to: generate a first masking signal based on a first pixel driving data value, and generate a second masking signal based on a second pixel driving data value. The first display pixel is configured to: generate a first pulse width modulation signal based on a first pixel driving data value and a first clock signal; generate a first masking pulse width modulation signal based on the first pulse width modulation signal and a first masking signal; and perform a first light emission operation based on the first masking pulse width modulation signal. The second display pixel is configured to: generate a second pulse width modulation signal based on the second pixel driving data value and the second clock signal; generate a second occlusion pulse width modulation signal based on the second pulse width modulation signal and the second occlusion signal; and perform a second light emission operation based on the second occlusion pulse width modulation signal.

20. The display device of claim 18, further comprising: The brightness adjustment circuit is configured as follows: The waveforms of the first clock signal and the first masking signal are determined based on the first pixel driving data value; and The waveforms of the second clock signal and the second masking signal are determined based on the second pixel driving data value.

Images