Display processing module, data processing method, data reading system

Abstract

The application discloses a display processing module, a data processing method and a data reading system, and belongs to the chip field.The display processing module comprises a mask register and a data reading unit;the mask register is used for storing a plurality of occlusion state bits, and each occlusion state bit is used for indicating whether an image block in a target layer is occluded by other layers;the target layer and the other layers are layers of a same picture;the data reading unit is used for reading a target occlusion state bit corresponding to a target image block from the mask register, reading pixel data of a target pixel segment from a memory in a case that the target occlusion state bit indicates that the target image block is not occluded by the other layers, the target pixel segment belongs to the target image block, and the target pixel segment is a pixel segment that is expected to acquire pixel data currently.The application can avoid invalid memory reading bandwidth by reading pixel data from the memory only for the pixel segment that is not occluded by the other layers according to the occlusion state bit configured in advance.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a display processing module, a data processing method, and a data reading system. Background Technology

[0002] The Display Processing Unit (DPU) is a dedicated hardware component in a System on Chip (SoC) responsible for blending layers and outputting the blended image to the screen.

[0003] In related technologies, the display processing unit reads all pixel data from memory for each layer, and then blends all pixel data of all layers according to a preset Z-axis order and transparency.

[0004] However, in related technologies, the pixel data of each layer that is occluded is also read, resulting in invalid memory read bandwidth. Summary of the Invention

[0005] This application provides a display processing module, a data processing method, and a data reading system. By using a pre-configured occlusion status bit, this application reads pixel data from memory only for pixel segments that are not occluded by other layers, thus avoiding invalid memory read bandwidth.

[0006] According to one aspect of this application, a display processing module is provided, the display processing module including a mask register and a data reading unit; The mask register is used to store multiple occlusion status bits, each occlusion status bit indicating whether an image block in the target layer is occluded by other layers; the target layer and the other layers are layers of the same image. The data reading unit is used to read the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0007] According to one aspect of this application, a data processing method is provided, executed by an operating system graphics stack, the method comprising: A coverage test is performed on the target layer to generate multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers. The target layer and the other layers are layers in the same image. Write the multiple occlusion status bits into the mask register of the display processing module.

[0008] According to one aspect of this application, a data reading system is provided, the system including an operating system graphics stack and a display processing module, the display processing module including a mask register and a data reading unit; The operating system graphics stack is used to perform a coverage test on the target layer to generate multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers. The target layer and the other layers are layers in the same frame. The operating system graphics stack is also used to write the plurality of occlusion status bits into the mask register; The data reading unit is used to read the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0009] According to one aspect of this application, a data reading method is provided, the method comprising: The operating system graphics stack performs a coverage test on the target layer to generate multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers. The target layer and the other layers are layers in the same frame. The operating system graphics stack writes the multiple occlusion status bits into the mask register of the display processing module; the display processing module also includes a data reading unit; The data reading unit reads the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0010] According to one aspect of this application, a chip is provided, the chip including a display processing module, the display processing module including a mask register and a data reading unit; The mask register is used to store multiple occlusion status bits, each occlusion status bit indicating whether an image block in the target layer is occluded by other layers; the target layer and the other layers are layers of the same image. The data reading unit is used to read the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0011] According to one aspect of this application, a computing device is provided, the computing device including a display processing module, the display processing module including a mask register and a data reading unit; The mask register is used to store multiple occlusion status bits, each occlusion status bit indicating whether an image block in the target layer is occluded by other layers; the target layer and the other layers are layers of the same image. The data reading unit is used to read the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0012] According to one aspect of this application, a computer device is provided, the computer device comprising: a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the data processing method as described above.

[0013] According to one aspect of this application, a computer-readable storage medium is provided that stores a computer program, which is loaded and executed by a processor to implement the data processing method described above.

[0014] According to one aspect of this application, a computer program product is provided, the computer program product storing a computer program that is loaded and executed by a processor to implement the data processing method described above.

[0015] The beneficial effects of the technical solutions provided in this application include at least the following:

[0016] Before reading the pixel data of the target pixel segment from memory, this application determines whether the target image block to which the target pixel segment belongs is occluded by other layers based on the target occlusion status bit. The pixel data of the target pixel segment is only read from memory if the target image block is not occluded. This can save the invalid memory read bandwidth of the occluded pixel segment and reduce the power consumption of the display processing module. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a display processing module provided in one embodiment of this application.

[0019] Figure 2 This is a schematic diagram of K mask registers provided in one embodiment of this application.

[0020] Figure 3 This is a schematic diagram of a target pixel segment provided in one embodiment of this application.

[0021] Figure 4 This is a flowchart of a data processing method provided in one embodiment of this application.

[0022] Figure 5 This is a schematic diagram of a data reading system provided in another embodiment of this application.

[0023] Figure 6 This is a flowchart of a data reading method provided in one embodiment of this application.

[0024] Figure 7 This is a schematic diagram of a chip provided in one embodiment of this application.

[0025] Figure 8 This is a schematic diagram of a computing device provided in one embodiment of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0027] First, some terms used in the embodiments of this application will be introduced: Display processing module: Optionally, this refers to the display processing unit. The display processing unit is a dedicated hardware module in the SoC responsible for processing graphics and video data and outputting the processing results to the display screen. The display processing unit typically independently performs operations such as multi-layer blending, color space conversion, scaling, and hardware cursor rendering, which can significantly reduce system power consumption and free up the computing power of the graphics processing unit (GPU).

[0028] Data reading unit: Optionally, it refers to the Direct Memory Access (DMA) engine; in a computer system, the DMA engine allows specific hardware peripherals (such as display processing units, network cards, and disk drives) to independently and directly read and write memory without the Central Processing Unit (CPU) being involved in and moving data throughout the process, thereby reducing transmission latency and increasing throughput.

[0029] Mask Register: An additional register added to the display processing module in this application. The mask register is used to store multiple masking status bits. Optionally, the mask register is a Static Random-Access Memory (SRAM). Static Random-Access Memory is a semiconductor memory that can retain data as long as it is powered on, unlike Dynamic Random-Access Memory (DRAM) which requires periodic refreshing. Due to its extremely high read / write speed and extremely low latency, Static Random-Access Memory is often integrated inside the chip as a cache or dedicated register.

[0030] Memory: In this application, pixel data of each layer is stored. Before performing multi-layer blending, the display processing module needs to read the pixel data of each layer from memory. Optionally, the memory is Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), often abbreviated as DDR.

[0031] Layer: In this application, it refers to a hardware layer. In the display processing module and graphics system driver (such as Linux DRM) architecture, it represents an independent hardware-level image overlay layer (such as the bottom full-screen video layer and the top user interface (UI) pop-up layer). Each layer has an independent physical memory base address, resolution, pixel format, and data reading unit. The display processing module is responsible for blending and overlaying multiple active layers in real time on the hardware side to form the final image and output it to the display screen.

[0032] Vertical Blanking Interval (VBLANK): This refers to the brief time interval between when the display screen has finished drawing the last line of a frame and the scan line moves back to the top left corner of the screen to prepare for drawing the next frame. This application will utilize this safe time window to update the mask register to prevent users from seeing torn images.

[0033] Burst Transmission: A highly efficient data read / write mechanism between modern system buses and memory. In a single bus transaction, only the starting physical address needs to be sent once to continuously read or write adjacent data blocks of a specified burst length, eliminating the overhead of address handshaking for each data word individually, thereby maximizing the effective throughput of memory bandwidth.

[0034] Hardware Layer Composition: This technique relies on the mixer within the display processing module to physically overlay multiple independent layers (such as a full-screen video layer and a semi-transparent UI layer) in real time during the direct scanning and output of data to the screen. Compared to software rendering and compositing using the graphics processor, this technique can significantly save bandwidth and overall power consumption.

[0035] In modern operating systems, the graphics stack commonly employs hardware layer compositing technology based on the display processing unit (GPU). This technology directly blends multiple layers at the hardware level through the GPU to output the final frame, effectively avoiding the high power consumption and high latency associated with rendering and compositing by calling the GPU.

[0036] However, in multi-window overlay scenarios (e.g., overlaying completely opaque application pop-ups or control panels in full-screen videos or games), existing display processing unit compositing mechanisms suffer from significant physical memory read waste. Specifically, areas in the lower layer obscured by upper opaque elements are actually invisible on the screen, but the direct memory access engine within the display processing unit still blindly reads this invalid pixel data completely from memory and transfers it to the internal mixer.

[0037] With the widespread adoption of high-resolution screens, the pressure on system bus bandwidth from such invalid reads is increasing exponentially. Taking 4K resolution (3840×2160) as an example, the data size of a single frame of uncompressed image is approximately 31.6MB. If the occlusion area of ​​the upper layer accounts for 50%, approximately 15.8MB of invalid data transmission will occur during the single-frame synthesis process. The larger the occlusion area, the higher the memory bandwidth occupied by invalid copies and the higher the read / write power consumption, which severely restricts the overall energy efficiency of the system under high-resolution screens and multi-tasking scenarios.

[0038] In multi-layer hardware compositing schemes of related technologies, the display of each frame of image highly depends on the serial collaboration of hardware and software. The operating system graphics stack first completes the calculation and configuration of the layer state; then, the display processing unit takes over control and allocates an independent direct memory access channel to each active hardware layer. During the line-by-line scan output process, each direct memory access channel independently initiates continuous read requests to physical memory in bursts through the system bus. Finally, the full pixel data of each layer is transported to the display processing unit, processed by the mixer, and output to the physical screen.

[0039] The complete process of the relevant technologies is as follows.

[0040] Software layer: Layer assignment and status delivery.

[0041] 1. Read the display pixel and metadata information submitted by other software programs (such as desktop, office software, video software) from memory, and then calculate the spatial position, Z-order and transparency (Alpha) of each window in the current frame.

[0042] 2. Call the driver interface (such as Linux DRM) to complete the allocation of hardware layers, and configure the physical memory base address, size and blending parameters of each layer into the hardware register of the display processing unit in the vertical blanking interval.

[0043] Hardware layer: Direct memory access channel addressing and burst reads.

[0044] 3. After frame scanning begins, the display processing unit wakes up the corresponding direct memory access channel for each active layer. As the scan line advances, the address generator of each direct memory access channel generates the target physical address and continuously initiates fixed-length (e.g., 128-byte) burst read transactions to memory via the system bus (e.g., Advanced eXtensible Interface Bus, AXI) to read pixel data.

[0045] Hardware layer: Layer blending and physical output.

[0046] 4. The mixer (Alpha Blender) inside the display processing unit extracts pixel data from the on-chip buffers of each layer. The mixer performs pixel-by-pixel physical overlay operations strictly according to the preset Z-axis order and transparency values. Pixels that are obscured at the bottom layer are logically covered (discarded) at this stage, and the final composited effective pixels are output to the physical screen through a display interface (such as a High Definition Multimedia Interface, HDMI).

[0047] It can be seen that the related technology lacks spatial occlusion awareness in its direct memory access channel when the display processing unit performs scan output. Regardless of the final visibility of the layer, the direct memory access channel performs 100% full data reading. Therefore, when a certain underlying hardware layer is largely obscured by an upper opaque layer, a large number of invalid pixels that are completely invisible on the physical screen will still be completely copied. This "blind extraction" mechanism results in significant unnecessary bandwidth consumption and additional system power consumption.

[0048] Figure 1 A schematic diagram of a display processing module 110 provided in an exemplary embodiment of this application is shown. The display processing module 110 includes a mask register 111 and a data reading unit 112. The display processing module 110 receives pixel data from each frame submitted by the software program, performs layer blending, and outputs the blended image. The software program is a graphical user interface program, such as a video player, news application, social interaction program, or game program. Optionally, the display processing module 110 is a dedicated hardware module for layer blending, implementing the layer blending function through integrated circuits deployed on it. Optionally, the display processing module 110 is a display processing unit (DPU). Optionally, the display processing module 110 is located on the SoC and is directly or indirectly connected to other hardware modules on the SoC. The display processing module 110 reads pixel data from the memory 120 submitted by the software program for each frame to perform layer blending.

[0049] Mask register 111 is a register added inside display processing module 110 in this application, used to store multiple occlusion status bits 101. Optionally, mask register 111 includes one or K mask registers, where K is a positive integer greater than one. Optionally, the number of mask registers depends on the number of multiple occlusion status bits 101. When the capacity of one mask register is sufficient to accommodate multiple occlusion status bits 101, one mask register is selected; when the capacity of one mask register is insufficient to accommodate multiple occlusion status bits 101, multiple mask registers are selected. Optionally, the mask register can be a 16-bit register, a 32-bit register, a 64-bit register, etc. The type of mask register can be determined according to the number of multiple occlusion status bits 101, or it can also depend on factors such as circuit layout, chip power consumption, timing optimization, and register cost.

[0050] The data reading unit 112 is a hardware unit within the display processing module 110 used to read pixel data, and its data reading function is implemented through integrated circuits deployed on it. Optionally, the data reading unit 112 is a direct memory access engine, which reads pixel data from memory 120 through a direct memory access channel. Optionally, the data reading unit 112 reads pixel data from memory 120 through the system bus.

[0051] The following example uses the target layer in a single frame of an image.

[0052] like Figure 1 As shown, the mask register 111 stores multiple occlusion status bits 101, which correspond to the target layer. Specifically, each occlusion status bit 101 indicates whether an image patch in the target layer is occluded by other layers. For example, if an image patch is occluded by other layers, the corresponding occlusion status bit is a first type of occlusion status bit; if an image patch is not occluded by other layers, the corresponding occlusion status bit is a second type of occlusion status bit.

[0053] Before reading the pixel data of the target pixel segment, the data reading unit 112 reads the target occlusion status bit 102 corresponding to the target image block from the mask register 111. The target pixel segment belongs to the target image block and is the pixel segment whose pixel data is currently expected to be acquired. When the target occlusion status bit 102 indicates that the target image block is occluded by other layers, the data reading unit 112 blocks the reading of pixel data of the target pixel segment from the memory 120. Optionally, the data reading unit 112 instead fills the target pixel segment with default pixel data in the internal data pipeline of the display processing module 110, such as filling it with all zeros. This allows the display processing module 110 to continue performing layer blending operations according to the original scheme. In this case, this application does not need to modify the layer blending operation logic originally performed by the display processing module 110.

[0054] When the target occlusion status bit 102 indicates that the target image block is not occluded by other layers, the data reading unit 112 reads the pixel data of the target pixel segment from the memory 120. Optionally, the data reading unit 112 sends the read pixel data to the internal data pipeline of the display processing module 110 so that the display processing module 110 can continue to perform layer blending operations.

[0055] It is understood that before reading the pixel data of the target pixel segment from the memory 120, this application will determine whether the target image block to which the target pixel segment belongs is occluded by other layers according to the target occlusion status bit 102. The pixel data of the target pixel segment will only be read from the memory 120 if the target image block is not occluded. This can save the invalid memory read bandwidth of the occluded pixel segment and reduce the power consumption of the display processing module 110.

[0056] In this application, the target layer and other layers are layers on the same screen; optionally, the target layer can be the bottom base screen layer, the middle control layer, or the top pop-up layer, etc.

[0057] Optionally, the image blocks corresponding to different occlusion state bits 101 may all have the same size, or at least two of the occlusion state bits 101 may correspond to image blocks with different sizes. The size of the image block can be 256. 16, 64 16, 64 32, etc., the unit is pixels.

[0058] Optionally, the target pixel segment is determined based on the number of pixels transmitted in a single data transfer. For example, if the data reading unit 112 reads data from memory using a burst transfer method, the length of the target pixel segment depends on the burst length. Exemplarily, the data reading unit 112 reads the pixel data of the next pixel segment after reading the pixel data of the previous pixel segment; that is, the data reading unit 112 reads pixel data serially. Therefore, the data reading unit 112 can obtain the coordinates of the end pixel of the next pixel segment by adding the burst length to the coordinates of the end pixel of the previous pixel segment, thus determining the pixel segment for each expected data reading.

[0059] It should be noted that the above only describes the pixel data reading scheme for a single layer (target layer). For multiple layers in the same image, the display processing module 110 can perform pixel data reading layer by layer or perform pixel data reading in parallel across multiple layers. This application does not impose any restrictions on this. Furthermore, for each layer, the display processing module 110 can read data in accordance with the method described above, which determines whether to read from memory 120 or block reading based on the occlusion status bit. Accordingly, at this time, the target layer is any one of the multiple layers in the same image.

[0060] In one embodiment, an occlusion status bit includes one bit. For example, a bit value of 0 indicates that the corresponding image block is not occluded by other layers, and a bit value of 1 indicates that the corresponding image block is occluded by other layers. In another embodiment, an occlusion status bit may include multiple bits, such as two bits. For example, a bit value of 00 indicates that the corresponding image block is not occluded by other layers, and a bit value of 01 indicates that the corresponding image block is occluded by other layers. Optionally, in addition to indicating whether an image block is occluded by other layers, the occlusion status bit can also be used to indicate the default pixel data to be filled when occluded by other layers. For example, a bit value of 10 indicates filling with a solid background color, and a bit value of 11 indicates filling with a preset pattern. If a target pixel segment is occluded, the data reading unit 112 will fill the target pixel segment with the corresponding default pixel data according to the indication of the target occlusion status bit.

[0061] In one embodiment, the mask register 111 can also be reused by other hardware modules. For example, the mask register 111 can be reused by a video decoder and / or a graphics processor. The video decoder and / or graphics processor can query multiple occlusion status bits before writing pixel data into memory. If it finds that the image block to which the pixel segment to be written belongs is occluded by other layers, it can directly skip the write operation of that pixel segment, thereby reducing memory write bandwidth. In this case, the present application achieves bidirectional bandwidth benefits for "read / write operations".

[0062] Double-ended occlusion detection logic In some cases, target pixel fragments may be distributed across different image blocks. In this embodiment, double-ended occlusion judgment will be performed based on the starting pixel and ending pixel of the target pixel fragment. Only when the occlusion status bit of the image block to which the starting pixel belongs and the occlusion status bit of the image block to which the ending pixel belongs both indicate that they are occluded by other layers will the reading of pixel data from memory 120 be blocked. At this time, a conservative reading strategy will be adopted to ensure that the image can be generated with high fidelity when the layers are mixed.

[0063] For example, the data reading unit 112 is used to read the first occlusion state bit corresponding to the first image block from the mask register 111, the first image block being the image block where the starting pixel of the target pixel segment is located; and to read the second occlusion state bit corresponding to the second image block from the mask register 112, the second image block being the image block where the ending pixel of the target pixel segment is located. The data reading unit 112 is used to read pixel data of the target pixel segment from the memory 120 when the first occlusion status bit indicates that the first image block is not occluded by other layers, and / or the second occlusion status bit indicates that the second image block is not occluded by other layers.

[0064] In other words, when the data reading unit 112 satisfies at least one of the following conditions: the first occlusion status bit indicates that the first image block is not occluded by other layers, and the second occlusion status bit indicates that the second image block is not occluded by other layers, the data reading unit 112 will read the pixel data of the target pixel segment from memory.

[0065] I. Method for reading the first occlusion status bit In one embodiment, the mask register 111 includes K mask registers, each of the K mask registers being used to store Q occlusion state bits, where K and Q are positive integers greater than one; The data reading unit 112 is used to determine the number of the first image block based on the pixel coordinates of the starting pixel; The data reading unit 112 is used to determine the first mask register from K mask registers according to the number of the first image block and Q, and to determine the offset of the first occlusion state bit in the first mask register. The data reading unit 112 is used to read the first occlusion status bit from the first mask register according to the status bit offset.

[0066] like Figure 2 As shown, Figure 2 Two mask registers are shown: mask register 0 and mask register 1. To read a certain occlusion status bit, you need to first determine the mask register in which the occlusion status bit is located, as well as the status bit offset of the occlusion status bit within that mask register.

[0067] For example, the length and height of each image block in the target layer contain a fixed number of pixels. The data reading unit 112 can easily determine the first image block where the starting pixel is located, i.e., the number of the first image block, based on the pixel coordinates of the starting pixel. Then, based on the number of the first image block and the number of occlusion status bits stored in each mask register, it can easily determine the first mask register where the occlusion status bit (first occlusion status bit) corresponding to the first image block is located, i.e., the number of the first mask register, and the status bit offset of the first occlusion status bit in the first mask register. Thus, after determining the number of the first mask register and the status bit offset of the first occlusion status bit in the first mask register, the first occlusion status bit can be read from the first mask register according to the status bit offset.

[0068] (a) Calculation method for the numbering of the first image block In one embodiment, each image block in the target layer has a length of w pixels and a height of h pixels, where w and h are positive integers greater than one. The data reading unit 112 is used to calculate the quotient of the horizontal coordinate of the starting pixel and w to obtain the horizontal index of the first image block; and to calculate the quotient of the vertical coordinate of the starting pixel and h to obtain the vertical index of the first image block. The data reading unit 112 is used to calculate the product of the vertical index and the number of image blocks in each row of the target layer, and obtain the number of the first image block based on the sum of the product and the horizontal index.

[0069] For example, suppose the target layer is divided into 128 image blocks, the length of the target layer is W, the height is H, and it is divided into N_col columns horizontally and N_row rows vertically (i.e., N_col... N_row = 128). Therefore, the length of a single image block is w = W / N_col, and the height is h = H / N_row.

[0070] Calculate the quotient of the x-coordinate x of the starting pixel and w to obtain the horizontal index Grid_X of the first image block; Calculate the quotient of the ordinate y of the starting pixel and h to obtain the vertical index Grid_Y of the first image block; At this point, (Grid_X, Grid_Y) represents the two-dimensional coordinates of the image patch; however, to map it to a one-dimensional sequential arrangement of occlusion states, the one-dimensional index of the image patch needs to be derived. Specifically, the product of the vertical index Grid_Y of the first image patch and the number of image patches N_col in each row of the target layer is calculated, and then the sum of this product and the horizontal index Grid_X of the first image patch is calculated to obtain the index of the first image patch. For example, this can be expressed by the formula Index = Grid_Y. N_col + Grid_X.

[0071] In one embodiment, w and h are both powers of two, and the data reading unit 112 can perform multiplication and division operations through shift operations to achieve higher hardware execution efficiency.

[0072] For the horizontal index of the first image block, for example, the data reading unit 112 is used to shift the value in the first binary sequence to the right by a bits to obtain the horizontal index of the first image block; the first binary sequence is used to represent the horizontal coordinate of the starting pixel, and a is the logarithm of w with base 2. For example, the first binary sequence is 01000110, which means the starting pixel horizontal coordinate is 70, w is 64, and the corresponding value of a is 6. After the shift operation, the resulting binary sequence is 00000001, which means the horizontal index of the first image block is 1.

[0073] For the vertical index of the first image block, for example, the data reading unit 112 is used to shift the value in the second binary sequence to the right by b bits to obtain the vertical index of the first image block; the second binary sequence is used to represent the vertical coordinate of the starting pixel, and b is the logarithm of h with base 2. For example, the second binary sequence is 10000110, which means the starting pixel's vertical coordinate is 134, w is 16, and the corresponding value of b is 4. After the shift operation, the resulting binary sequence is 00001000, which means the vertical index of the first image block is 8.

[0074] The product of the vertical index and the number of image blocks in each row of the target layer is a power of two. For example, the data reading unit 112 is used to shift the value in the third binary sequence to the left by c bits to obtain the product. The third binary sequence is used to represent the vertical index, and c is the logarithm of the number of image blocks in each row of the target layer with base two. For example, the third binary sequence is 00001000, which means the vertical index of the first image block is 8, the number of image blocks in each row N_col is 4, and the corresponding value of c is 2. After the shift operation, the resulting binary sequence is 00100000, which means the product is 32.

[0075] (ii) Calculation method of the numbering of the first mask register and the offset of the status bit In one embodiment, the data reading unit 112 is used to calculate the quotient of the number of the first image block and Q to obtain the number of the first mask register; For example, the first mask register number Reg_Index = Index / Q, where Index is the number of the first image patch. Optionally, the quotient calculation can be implemented through a shift operation.

[0076] For example, the data reading unit 112 is used to shift the value in the fourth binary sequence to the right by d bits to obtain the number of the first mask register; the fourth binary sequence is used to represent the number of the first image block, and d is the logarithm of Q to the base 2. For example, if the fourth binary sequence is 01100000, that is, the number of the first image block is 96, the value of Q is 64, and the corresponding value of d is 6, then after the shift operation, the resulting binary sequence is 00000001, that is, the number of the first mask register is 1.

[0077] The data reading unit 112 is used to calculate the remainder between the number of the first image block and Q to obtain the offset of the first occlusion state bit in the first mask register.

[0078] For example, the first occlusion state bit offset in the first mask register is Bit_Offset = Index % Q, where Index is the number of the first image patch. Optionally, the modulo operation is performed using a bitwise AND operation.

[0079] For example, the data reading unit 112 is used to perform a bitwise AND operation on the fourth binary sequence and the fifth binary sequence to obtain the offset of the first occlusion state bit in the first mask register; the fourth binary sequence is used to represent the number of the first image block, and the fifth binary sequence is used to represent the value obtained by subtracting one from Q. For example, if the fourth binary sequence is 01100000, that is, the number of the first image block is 96, the value of Q is 64, and the corresponding fifth binary sequence is 00111111, then after the bitwise AND operation, the resulting binary sequence is 00100000, that is, the offset of the state bit is 32.

[0080] Therefore, it can be determined that when the number of the first image block is 96 and each mask register stores 64 occlusion status bits, the 32nd occlusion status bit will be read from mask register 1 to obtain the first occlusion status bit.

[0081] In this embodiment, the data reading unit 112 can perform quotient operations through shift operations and remainder operations through bitwise AND operations, thereby achieving high hardware execution efficiency.

[0082] II. Method for reading the second occlusion status bit In this embodiment, the first occlusion status bit can be read for the starting pixel in the more complex manner described above. For the ending pixel, since the length of a single image block is aligned with the maximum burst length of a burst transmission when the size of the image block is designed in this application (which will be described in detail below), the pixel fragments transmitted in each burst transmission will only fall into one or at most two image blocks. Therefore, the second occlusion status bit corresponding to the ending pixel can only be the same as the first occlusion status bit, or the next occlusion status bit of the first occlusion status bit.

[0083] Therefore, after determining the first occlusion status bit, the second occlusion status bit can be quickly read from the mask register by judging whether the starting pixel and the ending pixel belong to the same image block.

[0084] Indicatively, Figure 3 Five cases of the target pixel segment are shown: A: The starting pixel P1 and ending pixel P2 of the target pixel segment fall into the same image block, and the occlusion status bit corresponding to the image block is not occluded by other layers; B: The starting pixel P1 and ending pixel P2 of the target pixel segment fall into the same image block, and the occlusion status bit of the corresponding image block is occluded by other layers; C: The starting pixel P1 and the ending pixel P2 of the target pixel segment fall into different image blocks, and the occlusion status bit of the image block to which the starting pixel P1 belongs is not occluded by other layers, while the occlusion status bit of the image block to which the ending pixel P2 belongs is occluded by other layers. D: The starting pixel P1 and the ending pixel P2 of the target pixel segment fall into different image blocks, and the occlusion status bit of the image block to which the starting pixel P1 belongs is occluded by other layers, while the occlusion status bit of the image block to which the ending pixel P2 belongs is not occluded by other layers. E: The starting pixel P1 and ending pixel P2 of the target pixel fragment fall into different image blocks, and the occlusion status bits of the image blocks to which the starting pixel P1 and ending pixel P2 belong both indicate that they are occluded by other layers.

[0085] In one embodiment, the data reading unit 112 is used to determine whether the starting pixel and the ending pixel are in the same image block; The data reading unit 112 is used to determine the first occlusion state bit as the second occlusion state bit when the starting pixel and the ending pixel are in the same image block; The data reading unit 112 is used to read the next occlusion state bit from the mask register 111 as the second occlusion state bit when the starting pixel and the ending pixel are not in the same image block.

[0086] Optionally, the data reading unit 112 determines the first image block number where the starting pixel is located and the second image block number where the ending pixel is located. If the two are equal, it is determined that the starting pixel and the ending pixel are in the same image block. If the two are not equal, it is determined that the starting pixel and the ending pixel are not in the same image block.

[0087] The method for determining the number of the first image block has been described above.

[0088] Optionally, the numbering of the second image block can also be determined in a similar manner to that of the first image block. For example, the data reading unit 112 calculates the quotient of the horizontal coordinate of the endpoint pixel and w to obtain the horizontal index of the second image block; and calculates the quotient of the vertical coordinate of the endpoint pixel and h to obtain the vertical index of the second image block; the product of the vertical index and the number of image blocks in each row of the target layer is calculated, and the number of the second image block is obtained based on the sum of the product and the horizontal index. Similarly, the data reading unit 112 can use shift operations to perform multiplication and division operations to obtain the number of the second image block. Further details are omitted here.

[0089] The content of the display processing module 110 has been introduced above, that is, the "hardware part" has been introduced. The following will introduce the execution content of the operating system graphics stack, that is, the "software part". The operating system graphics stack is used to generate multiple occlusion status bits 101 and write the multiple occlusion status bits 101 into the mask register 111.

[0090] Figure 4 A flowchart of a data processing method provided in an exemplary embodiment of this application is shown. The method is executed by the operating system graphics stack and includes: Step 420: Perform an overlay test on the target layer to generate multiple occlusion status bits; each occlusion status bit is used to indicate whether an image patch in the target layer is occluded by other layers, and the target layer and other layers are layers in the same image. The operating system graphics stack is a set of programs within the operating system related to graphics processing. Specifically, it is a layered software component system that, from top to bottom, is responsible for transforming the drawing instructions of software programs into a final display image. Optionally, the operating system graphics stack is run by the central processing unit (CPU).

[0091] In one embodiment, the operating system graphics stack divides the target layer into image blocks according to a grid template; wherein the grid template contains grids corresponding one-to-one with each image block, and any two grids in the grid template have the same size. For example, the size of a grid is 256. 16, all units are pixels, meaning one grid cell is 256 pixels long and 16 pixels high. After dividing according to the grid template, the target layer is divided into several 256-pixel grids. 16 image blocks.

[0092] Optionally, the grid template can be reused by other layers. In this case, the operating system graphics stack only needs to generate the grid template once to divide the image into blocks for all layers of an image, thus improving the division efficiency.

[0093] Optionally, the display processing module includes a data reading unit, which reads pixel data from memory using burst transmission; the length of each grid in the grid template is aligned with the maximum burst length of the burst transmission. Alignment means equal or integer multiples of each other.

[0094] Optionally, the length of each grid cell is equal to the maximum burst length, such as a grid cell length of 256 pixels and a maximum burst length of 256.

[0095] It should be noted that in actual operation, the actual transmission length of a single burst transmission is dynamically variable, but due to hardware architecture limitations, there is a fixed maximum length limit for the actual transmission length. In this embodiment, by aligning the length of the constraint grid with the maximum burst length of the data reading unit, it can be ensured that subsequent possible read blocking operations will not disrupt the continuity of the burst transmission and memory consistency.

[0096] This embodiment uses a read blocking unit with a complete burst length as the minimum, which effectively avoids the memory addressing fragmentation problem caused by non-aligned interception. While reaping the benefits of memory read bandwidth, it absolutely guarantees the throughput stability of the data pipeline inside the display processing module.

[0097] In one embodiment, a conservative occlusion detection strategy is used to determine whether an image patch is occluded by other layers. For example, for any image patch in the target layer, if the image patch is completely occluded by other layers, a first type of occlusion status bit is generated for the image patch. The first type of occlusion status bit is used to indicate that the current image patch is occluded by other layers. If an image block is not obscured by other layers or is partially visible, a second type of occlusion status bit is generated for the image block. The second type of occlusion status bit is used to indicate that the current image block is not obscured by other layers.

[0098] Optionally, the first type of occlusion state bit and the second type of occlusion state bit may have different values. For example, the first type of occlusion state bit may have a value of one, while the second type of occlusion state bit may have a value of zero.

[0099] It is understood that this embodiment generates a first type of occlusion status bit only when the image block is completely occluded, and generates a second type of occlusion status bit when the image block is not completely occluded or is partially occluded. This conservative occlusion judgment strategy is conducive to reading pixel data from memory as much as possible, with the final output image quality as the priority, and avoids blindly blocking data reading in order to reduce memory read bandwidth.

[0100] Step 440: Write multiple occlusion status bits into the mask register of the display processing module.

[0101] In one embodiment, the operating system graphics stack writes multiple occlusion status bits into a mask register during the vertical blanking interval of the display screen. The vertical blanking interval refers to the brief time interval between when the scan lines move back to the top left corner of the screen to prepare for drawing the next frame after the last line of a frame has been drawn. This application utilizes this safe time window to write multiple occlusion status bits to the target layer, thus preventing users from seeing torn images.

[0102] It should be noted that the operating system's graphics stack configures multiple occlusion state bits of each layer in the same frame of image into the mask register associated with each layer. For ease of explanation, this application mainly discusses the configuration scheme for multiple occlusion state bits of a target layer, where the target layer is any one of multiple layers in the same frame of image.

[0103] In summary, in this embodiment, multiple occlusion status bits of the target layer are generated by the operating system graphics stack, and these multiple occlusion status bits are written into the mask register inside the display processing module. This embodiment achieves the generation of complex multiple occlusion status bits through a "software solution", which can reduce hardware overhead. On the hardware side, only the mask register and the reading blocking judgment logic need to be introduced inside the display processing module.

[0104] Figure 5 This illustration shows a schematic diagram of a data reading system provided in an exemplary embodiment of this application. The system includes an operating system graphics stack 130 and a display processing module 110. The display processing module 110 includes a mask register 111 and a data reading unit 112. For ease of description, Figure 5 It also shows a memory of 120.

[0105] The operating system graphics stack 130 is used to perform coverage testing on the target layer and generate multiple occlusion status bits 101. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers; the target layer and other layers are layers in the same frame. The operating system graphics stack 130 is also used to write multiple occlusion status bits 101 into the mask register 111; The data reading unit 112 is used to read the target occlusion status bit corresponding to the target image block from the mask register 111. When the target occlusion status bit indicates that the target image block is not occluded by other layers, the pixel data of the target pixel fragment is read from the memory 120. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0106] In one embodiment, the operating system graphics stack 130 is used to generate a grid template, wherein the length of each grid in the grid template is aligned with the maximum burst length of the burst transmission; then, the target layer is divided into individual image blocks according to the grid template.

[0107] In one embodiment, for any image block in the target layer, if the image block is completely occluded by other layers, the operating system graphics stack 130 is used to generate a first type of occlusion status bit for the image block. The first type of occlusion status bit is used to indicate that the current image block is occluded by other layers. If an image block is not obscured by other layers or is partially visible, a second type of occlusion status bit is generated for the image block. The second type of occlusion status bit is used to indicate that the current image block is not obscured by other layers.

[0108] In one embodiment, the operating system graphics stack 130 is used to write multiple occlusion status bits 101 into the mask register 111 in the vertical blanking interval of the display screen.

[0109] In one embodiment, the data reading unit 112 is used to read the first occlusion status bit corresponding to the first image block from the mask register, the first image block being the image block where the starting pixel of the target pixel segment is located, and to read the second occlusion status bit corresponding to the second image block from the mask register, the second image block being the image block where the ending pixel of the target pixel segment is located. The data reading unit 112 is used to read pixel data of the target pixel segment from the memory 120 when the first occlusion status bit indicates that the first image block is not occluded by other layers, and / or the second occlusion status bit indicates that the second image block is not occluded by other layers.

[0110] In one embodiment, the mask register includes K mask registers, each of which stores Q occlusion status bits, where K and Q are positive integers greater than one. The data reading unit 112 is used to determine the number of the first image block based on the pixel coordinates of the starting pixel; The data reading unit 112 is used to determine the first mask register from K mask registers according to the number of the first image block and Q, and to determine the offset of the first occlusion state bit in the first mask register. The data reading unit 112 is used to read the first occlusion status bit from the first mask register according to the status bit offset.

[0111] In one embodiment, each image block in the target layer has a length of w pixels and a height of h pixels, where w and h are positive integers greater than one. The data reading unit 112 is used to calculate the quotient of the horizontal coordinate of the starting pixel and w to obtain the horizontal index of the first image block; and to calculate the quotient of the vertical coordinate of the starting pixel and h to obtain the vertical index of the first image block. The data reading unit 112 is used to calculate the product of the vertical index and the number of image blocks in each row of the target layer, and obtain the number of the first image block based on the sum of the product and the horizontal index.

[0112] In one embodiment, w and h are both powers of two; the data reading unit 112 is used to shift the value in the first binary sequence to the right by a bits to obtain the horizontal index of the first image block; the first binary sequence is used to represent the horizontal coordinate of the starting pixel, and a is the logarithm of w to the base two. The data reading unit 112 is used to shift the value in the second binary sequence to the right by b bits to obtain the vertical index of the first image block; the second binary sequence is used to represent the vertical coordinate of the starting pixel, and b is the logarithm of h to the base 2.

[0113] In one embodiment, the number of image blocks in each row of the target layer is a power of two; the data reading unit 112 is used to shift the value in the third binary sequence to the left by c bits to obtain the product; the third binary sequence is used to represent the vertical index, and c is the logarithm of the number of image blocks in each row of the target layer with base two.

[0114] In one embodiment, the data reading unit 112 is used to calculate the quotient of the number of the first image block and Q to obtain the number of the first mask register; The data reading unit 112 is used to calculate the remainder between the number of the first image block and Q to obtain the offset of the first occlusion state bit in the first mask register.

[0115] In one embodiment, the data reading unit 112 is used to shift the value in the fourth binary sequence to the right by d bits to obtain the number of the first mask register; the fourth binary sequence is used to represent the number of the first image block, and d is the logarithm of Q to the base 2.

[0116] In one embodiment, the data reading unit 112 is used to perform a bitwise AND operation on the fourth binary sequence and the fifth binary sequence to obtain the offset of the first occlusion state bit in the first mask register; the fourth binary sequence is used to represent the number of the first image block, and the fifth binary sequence is used to represent the value obtained by subtracting one from Q.

[0117] In one embodiment, the data reading unit 112 is used to determine whether the starting pixel and the ending pixel are in the same image block; The data reading unit 112 is used to determine the first occlusion state bit as the second occlusion state bit when the starting pixel and the ending pixel are in the same image block; The data reading unit 112 is used to read the next occlusion state bit of the first occlusion state bit from the mask register as the second occlusion state bit when the starting pixel and the ending pixel are not in the same image block.

[0118] In one embodiment, the data reading unit 112 is used to fill the target pixel fragment with default pixel data in the internal data pipeline of the display processing module when the target occlusion status bit indicates that the target image block is occluded by other layers.

[0119] The data reading system provided in this application adopts the concept of hardware-software decoupling, floating the complex calculation of occlusion state bits to the operating system graphics stack. The hardware only needs to introduce a mask register with a very small capacity and pure combinational logic composed of shifters. The hardware complexity is constant at O(1), which does not diverge with the increase of the number of screen windows, nor does it require the introduction of expensive multipliers and dividers or high-latency addressing modules, thus achieving extremely low hardware area and timing overhead. Pixel data reading can be completed in one clock cycle.

[0120] Furthermore, the data reading system provided in this application perfectly matches the physical characteristics of burst reads in memory, avoiding bus read fragmentation. Unlike traditional pixel-level culling schemes, this scheme forcibly introduces a constraint that aligns with the maximum burst length of the display processing module when the operating system graphics stack generates the mesh template. This strategy ensures that hardware-level data read blocking is always executed in units of complete burst transmission, and will never fragment continuous long burst read transactions, thereby completely avoiding memory data loss and memory throughput degradation caused by unaligned memory access or short bursts.

[0121] It should be noted that other aspects of the data reading system provided in this application can be found in the above descriptions of the "display processing module" and "data processing method," and will not be repeated here.

[0122] This application proposes a hardware-software co-operated memory read culling mechanism. At the hardware level, a mask register array and shift judgment logic circuit aligned with the maximum burst length of the system bus are introduced inside the display processing module. At the software level, the operating system synchronously sends out the occlusion configuration (BitMap) when submitting each frame display task. Through hardware-software collaboration, memory access requests for occluded areas are precisely blocked before a read request is initiated through the direct memory access channel, thereby completely eliminating the read overhead of invalid pixels.

[0123] I. Overview This solution is mainly achieved through the following technical means.

[0124] At the software level: a dynamic occlusion bitmap generation and frame-by-frame delivery mechanism based on the meshing and layer overlap relationship of the physical screen layer is introduced; At the hardware level: A configuration mask register array and shift blocking logic circuit aligned with the maximum burst length of the system bus are added inside the display processing module.

[0125] II. Overall Process Software layer: Layer allocation and status updates 1. The operating system's graphics stack receives display pixel and metadata information submitted by other software programs, and calculates the spatial position, Z-axis level, and transparency of each window in the current frame.

[0126] 2. Meshing and Bitmap Generation: Logically divide the physical screen into a grid whose size is strictly aligned with the maximum burst read boundary of the display processing module. The operating system graphics stack only needs to divide the grid once, and multiple layers can be reused subsequently. Traverse the layer overlap relationship; if a grid is completely covered by an opaque window above, set the corresponding bit to 1; otherwise, set it to 0, thereby generating an occlusion state mask table (one for each layer).

[0127] 3. Call the driver interface to complete the allocation of hardware layers. Within the vertical blanking interval, in addition to configuring the physical memory base address, size, and blending parameters of each layer into the regular hardware registers of the display processing module, the generated bitmap data is simultaneously written into the newly added mask register array associated with that layer inside the display processing module.

[0128] Hardware layer: Direct memory access engine addressing and burst read 4. After frame scanning begins, the display processing module wakes up the corresponding direct memory access channel for each active layer. As the scan line advances, the address generator of each direct memory access channel generates the target physical address.

[0129] 5. Perform bus-level physical blocking: Before initiating a burst read operation, the Direct Memory Access Engine uses the current starting coordinates to locate the corresponding bit in the mask register array through a single-cycle shift operation. The bus behavior is then determined by performing a logical AND operation with this bit. If the bit value is 0 (visible area): a burst read transaction is normally initiated to memory via the system bus.

[0130] If the bit value is 1 (occlusion area): the bus read transaction is physically blocked on the side of the direct memory access channel (no read request is sent), and the default value (dummy placeholder zero pixel) is directly filled into the data pipeline inside the display processing module.

[0131] Hardware layer: Layer blending and physical output 6. The mixer inside the display processing module synchronously extracts data from the caches of each layer (this includes the actual pixel data read and possible default values ​​filled after blocking). The mixer performs pixel-by-pixel physical overlay operations strictly according to the preset Z-axis order and alpha value. The final synthesized effective pixels are output to the physical screen through the display interface.

[0132] III. Grid-based The operating system's graphics software stack (display server and drivers) is responsible for the grid-based abstraction and configuration distribution of the screen space state. The specific process is as follows: 1. Physical Screen Grid Constraints: Before submitting a frame, the operating system's graphics software stack logically divides the physical screen into a fixed-size macroblock grid. The size constraint of this grid is aligned with the maximum burst size of the memory controller of the current display processing module (e.g., configured as 256 bytes wide × 16 rows high) to ensure that subsequent hardware interruptions do not disrupt the continuity of burst transmissions on the bus and memory consistency.

[0133] 2. Conservative Occlusion Detection and State Aggregation: The desktop compositor software traverses all opaque windows above the current underlying hardware layer from top to bottom, performing a conservative culling algorithm: If a grid is completely covered by one (or two) opaque windows above it, the bit position corresponding to that grid in that layer is set to 1 (representing that the area is physically invisible); if it is not completely covered or is visible, it is set to 0. Only when a grid is completely covered will the bit position corresponding to that grid be set to 1; otherwise, it remains 0.

[0134] 3. Register data writing: During the vertical blanking interval of screen scanning, the driver writes the bitmap data sent by the graphics software stack into the newly added mask register array inside the display processing module in one go, completing the software and hardware state synchronization.

[0135] IV. Screen Grid and Bitmap Mapping Relationship Assuming the screen is divided into 128 grids, numbered 0 to 127 from left to right and top to bottom, it can be represented by two 64-bit registers. That is, a u64 bitmap[2]. Since the screen resolution is fixed, the relationship between these indices and pixels can be easily determined. Specifically, there is a strict linear mapping relationship between the grid division and the screen pixel coordinates, and this mapping can be fully implemented in the underlying hardware logic by constant shift and bitwise AND operation with extremely low latency, without consuming expensive multiplier and divider resources.

[0136] Assume the screen (or display buffer) has a width of W and a height of H. The entire screen is divided horizontally into N_col columns and vertically into N_row rows (N_col in this example). (N_row = 128 grids). Therefore, the pixel width of a single grid is w = W / N_col, and the pixel height is h = H / N_row.

[0137] To maximize hardware processing efficiency, w and h are usually forced to be powers of 2 during configuration (e.g., 64, 128, or 256, which is consistent with the maximum burst length). Given any pixel screen coordinates (x, y) to be extracted by the display processing module, the process of mapping it to specific bits in u64bitmap[2] consists of four steps: 1. Calculate the coordinates of the 2D grid (Grid_X, Grid_Y): Horizontal index: Grid_X = x / W_grid. In hardware RTL, this is equivalent to x >> log2(w).

[0138] Vertical index: Grid_Y = y / H_grid. In hardware RTL, this is equivalent to y >> log2(h).

[0139] 2. Calculate the absolute index of a one-dimensional grid: Numbering formula: Index = Grid_Y N_col + Grid_X. This results in an absolute integer between 0 and 127. Since N_col is also a power of 2, this multiplication can also be optimized into a bit shift operation.

[0140] 3. Locate the target register (Reg_Index) and bit offset (Bit_Offset): The destination register index (0 or 1) is Reg_Index = Index / 64. In hardware RTL, this is equivalent to Index >> 6. The destination bit offset (0 to 63) is Bit_Offset = Index % 64. In hardware RTL, this is equivalent to Index & 63.

[0141] 4. Extract the final occlusion mask value (MaskState): By using (bitmap[Reg_Index]>>Bit_Offset)&1, you can output whether the grid where the pixel is located is completely occluded within one clock cycle (1 for occlusion, 0 for visibility).

[0142] V. Burst Read Alignment The display processing module's direct memory access channel initiates system bus read transactions at the burst level. In actual operation, the actual transmission length of a single burst is dynamically variable, but it has a fixed maximum length limit due to hardware architecture limitations. This solution, during the screen meshing stage, enforces that the horizontal dimension of the mesh is not less than the system's maximum burst length (therefore, a single burst transmission will only fall into at least one, and at most two, meshes); simultaneously, on the hardware execution side, it introduces dual-end concurrent lookup logic for the coordinates of the start and end pixels of the burst. Only when both ends of the burst's coordinates hit a mesh in a fully occluded state (Bit=1) is the segment considered to have completely fallen into an invisible area, thus implementing a complete physical blockage. If either end hits the visible area (i.e., Bit=0), the process is conservatively allowed to proceed. This design, which uses complete burst transmission as the smallest blocking unit, effectively avoids the memory addressing fragmentation problem caused by unaligned interception. While reaping bandwidth benefits, it absolutely guarantees the throughput stability of the data pipeline inside the display processing module.

[0143] VI. Hardware read blocking The display processing module is responsible for performing O(1) complexity table lookup and read interception at the front end of the data path.

[0144] New hardware architecture features: Between the direct memory access engine of the display processing module and the AXI bus interface, an on-chip configurable mask register array (or a small SRAM area) is added to store the screen grid occlusion state mask issued by the operating system graphics stack.

[0145] Hardware execution process: 1. Coordinate Extraction and Grid Positioning: Before a specific layer in the display processing module initiates a burst read operation, the address generator extracts the screen starting coordinates (X, Y) and burst length for this read. The hardware, using the simple circuit logic described in the previous section, performs a simple shift operation based on the starting coordinates to locate the corresponding bit in the mask register array that maps to the grid region (a single burst transfer mostly falls within one grid, and at most two grids) within one clock cycle.

[0146] 2. Status lookup table and execution determination: The hardware directly determines the bus behavior of this burst transmission by performing a bitwise AND operation with the extracted bits. a) If bit == 1 (complete occlusion): Physical blocking is implemented directly on the bus transaction initiation side, and no read request operation is initiated to memory. At the same time, the internal hardware state machine directly provides a default value of equal length (dummy occupies zero pixels) to the line buffer (first-in, first-out buffer) of the display processing module to maintain the normal progress of the pipeline clock tick and coordinate pointer.

[0147] b) If bit == 0 (validally visible): the burst read request is initiated normally to memory.

[0148] Figure 6 A flowchart of a data reading method provided by an exemplary embodiment of this application is shown, the method including the following steps 620 to 660.

[0149] Step 620: The operating system graphics stack performs a coverage test on the target layer to generate multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image patch in the target layer is occluded by other layers. The target layer and other layers are layers in the same frame. In one embodiment, the operating system graphics stack generates a grid template, the length of each grid in the grid template being aligned with the maximum burst length of the burst transmission; then, the target layer is divided into individual image blocks according to the grid template.

[0150] In one embodiment, for any image block in the target layer, if the image block is completely occluded by other layers, the operating system graphics stack generates a first type of occlusion status bit for the image block. The first type of occlusion status bit indicates that the current image block is occluded by other layers. If an image patch is not obscured by other layers or is partially visible, a second type of occlusion status bit is generated for the image patch. The second type of occlusion status bit indicates that the current image patch is not obscured by other layers.

[0151] Step 640: The operating system graphics stack writes multiple occlusion status bits into the mask register of the display processing module; the display processing module also includes a data reading unit. In one embodiment, the operating system graphics stack writes multiple occlusion status bits into a mask register during the vertical blanking interval of the display screen.

[0152] Step 660: The data reading unit reads the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by other layers, the pixel data of the target pixel fragment is read from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0153] In one embodiment, the data reading unit reads the first occlusion status bit corresponding to the first image block from the mask register, the first image block being the image block where the starting pixel of the target pixel segment is located, and reads the second occlusion status bit corresponding to the second image block from the mask register, the second image block being the image block where the ending pixel of the target pixel segment is located. The data reading unit reads pixel data of the target pixel fragment from memory when the first occlusion status bit indicates that the first image block is not occluded by other layers, and / or the second occlusion status bit indicates that the second image block is not occluded by other layers.

[0154] In one embodiment, the mask register includes K mask registers, each of the K mask registers stores Q occlusion state bits, where K and Q are positive integers greater than one; The data reading unit determines the number of the first image block based on the pixel coordinates of the starting pixel; The data reading unit determines the first mask register from K mask registers based on the number of the first image block and Q, and determines the offset of the first occlusion state bit in the first mask register. The data reading unit reads the first occlusion status bit from the first mask register according to the status bit offset.

[0155] In one embodiment, each image block in the target layer has a length of w pixels and a height of h pixels, where w and h are positive integers greater than one. The data reading unit calculates the quotient of the horizontal coordinate of the starting pixel and w to obtain the horizontal index of the first image block; and calculates the quotient of the vertical coordinate of the starting pixel and h to obtain the vertical index of the first image block. The data reading unit calculates the product of the vertical index and the number of image blocks in each row of the target layer, and obtains the number of the first image block based on the sum of the product and the horizontal index.

[0156] In one embodiment, w and h are both powers of two; the data reading unit shifts the value in the first binary sequence a bits to the right to obtain the horizontal index of the first image block; the first binary sequence represents the horizontal coordinate of the starting pixel, and a is the logarithm of w to the base two; The data reading unit shifts the value in the second binary sequence to the right by b bits to obtain the vertical index of the first image block; the second binary sequence represents the vertical coordinate of the starting pixel, and b is the logarithm of h to the base 2.

[0157] In one embodiment, the number of image blocks in each row of the target layer is a power of two; the data reading unit shifts the value in the third binary sequence to the left by c bits to obtain the product; the third binary sequence represents the vertical index, and c is the logarithm of the number of image blocks in each row of the target layer with base two.

[0158] In one embodiment, the data reading unit calculates the quotient of the number of the first image block and Q to obtain the number of the first mask register; The data reading unit calculates the remainder between the number of the first image block and Q to obtain the offset of the first occlusion state bit in the first mask register.

[0159] In one embodiment, the data reading unit shifts the value in the fourth binary sequence to the right by d bits to obtain the number of the first mask register; the fourth binary sequence represents the number of the first image block, and d is the logarithm of Q to the base 2.

[0160] In one embodiment, the data reading unit performs a bitwise AND operation on the fourth binary sequence and the fifth binary sequence to obtain the offset of the first occlusion state bit in the first mask register; the fourth binary sequence represents the number of the first image block, and the fifth binary sequence represents the value obtained by subtracting one from Q.

[0161] In one embodiment, the data reading unit determines whether the starting pixel and the ending pixel are in the same image block; The data reading unit determines the first occlusion state bit as the second occlusion state bit when the starting pixel and the ending pixel are in the same image block. The data reading unit reads the next occlusion state bit from the mask register when the starting pixel and the ending pixel are not in the same image block, and uses it as the second occlusion state bit.

[0162] In one embodiment, the data reading unit fills the target pixel fragment with default pixel data in the internal data pipeline of the display processing module when the target occlusion status bit indicates that the target image block is occluded by other layers.

[0163] It should be noted that other details regarding the data reading method provided in this application can be found in the above descriptions of the "display processing module" and "data processing method," and will not be repeated here.

[0164] Figure 7 The diagram shows a structural block diagram of a chip provided in an exemplary embodiment of this application. The chip 700 includes a display processing module 110, which includes a mask register 111 and a data reading unit 112. Mask register 111 is used to store multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers. The target layer and other layers are layers in the same frame. The data reading unit 112 is used to read the target occlusion status bit 102 corresponding to the target image block from the mask register 111. When the target occlusion status bit 102 indicates that the target image block is not occluded by other layers, the pixel data of the target pixel fragment is read from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0165] It should be noted that other details regarding the chip provided in this application can be found in the above description of the "display processing module," and will not be repeated here. Those skilled in the art will understand that... Figure 7 The structure shown does not constitute a limitation on chip 700. Chip 700 may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0166] Figure 8 The diagram shows a structural block diagram of a computing device provided in an exemplary embodiment of this application. The computing device 800 includes a display processing module 110, which includes a mask register 111 and a data reading unit 112. Mask register 111 is used to store multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers. The target layer and other layers are layers in the same frame. The data reading unit 112 is used to read the target occlusion status bit 102 corresponding to the target image block from the mask register 111. When the target occlusion status bit 102 indicates that the target image block is not occluded by other layers, the pixel data of the target pixel fragment is read from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

[0167] It should be noted that other aspects of the computing device provided in this application can be found in the above description of the "display processing module," and will not be repeated here. Those skilled in the art will understand that... Figure 8 The structure shown does not constitute a limitation on the computing device 800. The computing device 800 may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0168] Optionally, the computing device can be a portable mobile terminal, such as a smartphone, tablet, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop, or desktop computer. The computing device may also be referred to as a user device, portable terminal, laptop terminal, desktop terminal, or other names. Optionally, the computing device can also be a server.

[0169] In one embodiment, this application provides a computer device, which includes a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the data processing method described above.

[0170] Alternatively, the computer device can be a portable mobile terminal, such as a smartphone, tablet, MP3 player, MP4 player, laptop, or desktop computer. The computing device may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other names. Optionally, the computer device can also be a server.

[0171] Optionally, the computer device used to perform the data processing method and the computing device including the display processing module are the same computer device.

[0172] In one embodiment, this application provides a computer-readable storage medium storing at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the data processing method provided in the above method embodiment.

[0173] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the data processing method provided in the above-described method embodiments.

[0174] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0175] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0176] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent switching, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display processing module, characterized in that, The display processing module includes a mask register and a data reading unit; The mask register is used to store multiple occlusion status bits, each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers; The target layer and the other layers are layers in the same frame; The data reading unit is used to read the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

2. The display processing module according to claim 1, characterized in that, The data reading unit is used to read the first occlusion status bit corresponding to the first image block from the mask register, and to read the second occlusion status bit corresponding to the second image block from the mask register; The data reading unit is configured to read pixel data of the target pixel segment from the memory when the first occlusion status bit indicates that the first image block is not occluded by the other layers, and / or when the second occlusion status bit indicates that the second image block is not occluded by the other layers; Wherein, the first image block is the image block where the starting pixel of the target pixel segment is located, and the second image block is the image block where the ending pixel of the target pixel segment is located.

3. The display processing module according to claim 2, characterized in that, The mask register includes K mask registers, each of which stores Q occlusion status bits, where K and Q are positive integers greater than one. The data reading unit is used to determine the number of the first image block based on the pixel coordinates of the starting pixel. The data reading unit is used to determine the first mask register from the K mask registers according to the number of the first image block and Q, and to determine the offset of the first occlusion state bit in the first mask register. The data reading unit is used to read the first occlusion status bit from the first mask register according to the status bit offset.

4. The display processing module according to claim 3, characterized in that, The length of each image block in the target layer is w pixels and the height is h pixels, where w and h are positive integers greater than one. The data reading unit is used to calculate the quotient of the horizontal coordinate of the starting pixel and w to obtain the horizontal index of the first image block; And, calculate the quotient of the ordinate of the starting pixel and h to obtain the vertical index of the first image block; The data reading unit is used to calculate the product of the vertical index and the number of image blocks in each row of the target layer, and obtain the number of the first image block based on the sum of the product and the horizontal index.

5. The display processing module according to claim 4, characterized in that, Both w and h are powers of two; The data reading unit is used to shift the value in the first binary sequence to the right by a bits to obtain the horizontal index of the first image block; the first binary sequence is used to represent the horizontal coordinate of the starting pixel, and a is a logarithm with base 2 w. The data reading unit is used to shift the value in the second binary sequence to the right by b bits to obtain the vertical index of the first image block; the second binary sequence is used to represent the vertical coordinate of the starting pixel, and b is a logarithm with base 2 h.

6. The display processing module according to claim 4, characterized in that, The number of image blocks in each row of the target layer is a power of two; The data reading unit is used to shift the value in the third binary sequence to the left by c bits to obtain the product; the third binary sequence is used to represent the vertical index, and c is the logarithm of the number of image blocks in each row of the target layer with base 2.

7. The display processing module according to claim 3, characterized in that, The data reading unit is used to calculate the quotient of the number of the first image block and Q to obtain the number of the first mask register; The data reading unit is used to calculate the remainder between the number of the first image block and Q to obtain the offset of the first occlusion state bit in the first mask register.

8. The display processing module according to claim 7, characterized in that, The data reading unit is used to shift the value in the fourth binary sequence to the right by d bits to obtain the number of the first mask register; the fourth binary sequence is used to represent the number of the first image block, and d is a logarithm with base 2 Q.

9. The display processing module according to claim 7, characterized in that, The data reading unit is used to perform a bitwise AND operation on the fourth binary sequence and the fifth binary sequence to obtain the offset of the first occlusion state bit in the first mask register. The fourth binary sequence is used to represent the number of the first image block, and the fifth binary sequence is used to represent the value obtained by subtracting one from Q.

10. The display processing module according to claim 2, characterized in that, The data reading unit is used to determine whether the starting pixel and the ending pixel are in the same image block; The data reading unit is used to determine the first occlusion state bit as the second occlusion state bit when the starting pixel and the ending pixel are in the same image block; The data reading unit is used to read the next occlusion state bit of the first occlusion state bit from the mask register as the second occlusion state bit when the starting pixel and the ending pixel are not in the same image block.

11. The display processing module according to any one of claims 1 to 10, characterized in that, The data reading unit is used to fill the target pixel fragment with default pixel data in the internal data pipeline of the display processing module when the target occlusion status bit indicates that the target image block is occluded by the other layers.

12. A data processing method, characterized in that, Executed by the operating system graphics stack, the method includes: A coverage test is performed on the target layer to generate multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers. The target layer and the other layers are layers in the same image. Write the multiple occlusion status bits into the mask register of the display processing module.

13. The method according to claim 12, characterized in that, The process of performing a coverage test on the target layer generates multiple occlusion status bits, including: For any image block in the target layer, if the image block is completely occluded by the other layers, a first type of occlusion status bit is generated for the image block. The first type of occlusion status bit is used to indicate that the current image block is occluded by the other layers. If the image block is not obscured by the other layers or is partially visible, a second type of occlusion status bit is generated for the image block. The second type of occlusion status bit is used to indicate that the current image block is not obscured by the other layers.

14. The method according to claim 12, characterized in that, The method further includes: The target layer is divided into image blocks according to the grid template; The grid template contains grids that correspond one-to-one with each of the image blocks, and any two grids in the grid template have the same size.

15. The method according to claim 14, characterized in that, The display processing module includes a data reading unit, which is used to read pixel data from memory using a burst transmission method; The length of each grid in the grid template is aligned with the maximum burst length of the burst transmission.

16. The method according to claim 12, characterized in that, The step of writing the plurality of occlusion status bits into the mask register of the display processing module includes: The plurality of occlusion status bits are written into the mask register in the vertical blanking range of the display screen.

17. A data reading system, characterized in that, The system includes an operating system graphics stack and a display processing module, and the display processing module includes a mask register and a data reading unit. The operating system graphics stack is used to perform a coverage test on the target layer to generate multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers. The target layer and the other layers are layers in the same frame; The operating system graphics stack is also used to write the plurality of occlusion status bits into the mask register; The data reading unit is used to read the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

18. A data reading method, characterized in that, The method includes: The operating system graphics stack performs a coverage test on the target layer to generate multiple occlusion status bits. Each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers. The target layer and the other layers are layers in the same frame. The operating system graphics stack writes the multiple occlusion status bits into the mask register of the display processing module; the display processing module also includes a data reading unit; The data reading unit reads the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

19. A chip, characterized in that, The chip includes a display processing module, which includes a mask register and a data reading unit. The mask register is used to store multiple occlusion status bits, each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers; The target layer and the other layers are layers in the same frame; The data reading unit is used to read the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

20. A computing device, characterized in that, The computing device includes a display processing module, which includes a mask register and a data reading unit. The mask register is used to store multiple occlusion status bits, each occlusion status bit is used to indicate whether an image block in the target layer is occluded by other layers; The target layer and the other layers are layers in the same frame; The data reading unit is used to read the target occlusion status bit corresponding to the target image block from the mask register. When the target occlusion status bit indicates that the target image block is not occluded by the other layers, the unit reads the pixel data of the target pixel fragment from memory. The target pixel fragment belongs to the target image block and is the pixel fragment for which pixel data is currently expected to be acquired.

21. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the data processing method as described in any one of claims 12 to 16.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that is loaded and executed by a processor to implement the data processing method as described in any one of claims 12 to 16.

23. A computer program product, characterized in that, The computer program product stores a computer program that is loaded and executed by a processor to implement the data processing method as described in any one of claims 12 to 16.

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