Gate driving circuit and display panel

Abstract

The present disclosure provides a gate drive circuit and a display panel. The gate drive circuit comprises at least one cascade group, each cascade group comprising a plurality of cascaded GOA units, each GOA unit comprising a first control node, a pull-down holding circuit, the pull-down holding circuit comprising an input end, an output end, a control end, a high-level end, a low-level end and a second control node. The pull-down holding circuit is configured to, in a display stage, when the first control node is at a low level, in response to the control end being at a high level, control the second control node to be at a high level by using a high-level signal of the high-level end, so that the second control node maintains the first control node at a low level by using a low-level signal of the low-level end; in a shutdown discharge stage, in response to a discharge rate of the control end being less than a discharge rate of the high-level end, the second control node is turned on with the high-level end until the second control node is discharged to a low level, so as to prolong the service life of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and more specifically, relates to a gate driving circuit and a display panel. Background Technology

[0002] Gate Driver On Array (GOA) technology is a technique used in display panels to fabricate the gate scanning drive circuit of a thin film transistor (TFT) on an array substrate, replacing the external silicon chip driver chip. It provides gate drive signals for row-by-row scanning and has the advantages of reducing manufacturing costs and narrowing bezel width.

[0003] Existing GOA (Grid-Based Aperture) cells typically include a pull-down sustaining circuit. This circuit maintains the GOA cell at a low potential after the current scan cycle, preventing accidental activation. However, in current pull-down sustaining circuits, the pull-down sustaining TFTs are subjected to voltage bias for an extended period after the display panel is powered off and discharged, significantly impacting the lifespan of the display panel. Summary of the Invention

[0004] The purpose of this application is to provide a gate drive circuit and a display panel to solve the technical problem that the current GOA circuit is biased due to the long-term voltage resistance of the TFT after power-off discharge due to pull-down maintenance, so as to improve the charge discharge capability of the display panel during power-off discharge and thus improve its lifespan.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, embodiments of this application provide a gate driving circuit, also known as a GOA circuit. The gate driving circuit includes at least one cascaded group, each cascaded group including multiple cascaded GOA units, and each GOA unit including a first control node and a pull-down sustaining circuit. The pull-down sustaining circuit includes an input terminal, an output terminal, a control terminal, a high-level terminal, a low-level terminal, and a second control node. The input and output terminals of the pull-down sustaining circuit are both electrically connected to the first control node. The pull-down sustaining circuit is configured as follows: During the display phase, when the first control node is at a low level, in response to the control terminal being at a high level, the high-level signal of the high-level terminal is used to control the second control node to be at a high level, so that the second control node uses the low-level signal of the low-level terminal to maintain the first control node at a low level. During the power-off discharge phase, in response to the discharge rate at the control terminal being less than the discharge rate at the high-level terminal, the second control node is connected to the high-level terminal until the second control node discharges to the low level.

[0006] In the gate driving circuit provided in this embodiment, during the display stage, the pull-down sustaining circuit normally controls the potential change of the second control node according to the potential of the first control node and the potential of the control terminal. When the first control node is at a low level, the second control node is set to a high level, causing the first sustaining circuit to maintain the first control node at a low level. In this embodiment, without changing the normal operation of the pull-down sustaining circuit, during the power-off discharge stage, when all signal lines are pulled high to the initial potential and then drop, the discharge rate between the control terminal and the high-potential terminal of the pull-down sustaining circuit is optimized to create a rate difference, thereby generating a potential difference. This voltage difference controls the discharge path from the second control node to the high-level terminal, providing an effective charge discharge path for the second control node. Because the second control node is in a conducting state before discharging to a low level, it can discharge to a low level without residual charge. Therefore, the pull-down sustaining TFT in the pull-down sustaining circuit controlled by the second control node is no longer biased by the threshold voltage for a long time after power-off, thus extending the lifespan of the display panel.

[0007] In some non-limiting embodiments, the pull-down sustaining circuit includes: An inverter circuit is electrically connected to the input terminal, control terminal, high-level terminal, low-level terminal, and second control node, respectively. The inverter circuit is configured to: during the display phase, selectively use the high-level signal or the low-level signal opposite to the first control node, based on the potentials of the control terminal and the input terminal, to control the level of the second control node to be opposite to the level of the first control node; during the power-off discharge phase, in response to the discharge rate of the control terminal being less than the discharge rate of the high-level terminal, conduct the second control node and the high-level terminal until the second control node discharges to a low level. The first sustaining circuit is electrically connected to the second control node, the output terminal, and the low-level terminal, respectively, and is configured to: during the display phase, in response to the second control node being at a high level, conduct the first control node and the low-level terminal, thereby maintaining the first control node at a low level.

[0008] In this GOA circuit, when the pull-down sustaining circuit is constructed as described above, during the display phase, when the first control node is at a low level, the inverter circuit selectively transmits the high-level signal from the high-level terminal to the second control node based on the potentials of the control terminal and the input terminal, causing the second control node to be at a high level. This drives the first sustaining circuit to conduct between the first control node and the low-level terminal, reliably maintaining the first control node at a low level, thus fully realizing the function of the pull-down sustaining circuit during the normal display phase.

[0009] During the power-off discharge phase, as all signal potentials decrease, the inverter circuit generates a potential difference because the discharge rate at the control terminal is less than the discharge rate at the high-level terminal. This potential difference automatically opens the discharge path from the second control node to the high-level terminal, allowing the residual charge on the second control node to be completely discharged to the low level. This achieves the discharge function of the pull-down sustaining circuit during the power-off discharge phase.

[0010] In some non-limiting embodiments, the pull-down sustaining circuit further includes a third control node. The inverter circuit includes: The first thin-film transistor has its gate electrically connected to the control terminal, its first electrode electrically connected to the high-level terminal, and its second electrode electrically connected to the third control node. The second thin-film transistor has its gate electrically connected to the third control node, its first electrode electrically connected to the first electrode of the first thin-film transistor, and its second electrode electrically connected to the second control node. The third thin-film transistor has its gate electrically connected to the input terminal, its first electrode electrically connected to the third control node, and its second electrode electrically connected to the low-level terminal. The fourth thin-film transistor has its gate electrically connected to the input terminal, its first electrode electrically connected to the second control node, and its second electrode electrically connected to the low-level terminal.

[0011] In this embodiment, during the display stage, the inverter circuit achieves precise control of the second control node's potential through the coordinated operation of the first to fourth thin-film transistors. When the first control node is at a low level, the third and fourth thin-film transistors are off. If the control terminal is at a high level, the first thin-film transistor is turned on, charging the third control node and causing the second thin-film transistor to turn on, transmitting the high level from the high-level terminal to the second control node, thus placing the second control node in a high-level state. When the first control node is at a high level, the third and fourth thin-film transistors are turned on, rapidly pulling the potentials of both the third and second control nodes down to the low level of the low-level terminal, placing the second control node in a low-level state. This achieves precise control where the second control node's potential is opposite to that of the first control node, ensuring that the pull-down sustaining circuit operates normally when the first control node's potential is low and stops operating when the first control node's potential is high, without interference.

[0012] During the power-off discharge phase, the potential of the first control signal is higher than that of the first input signal, creating a positive voltage difference between the gate and source of the first thin-film transistor (TFT). This voltage difference keeps the first TFT in a conducting state, providing a charge discharge path for the third control node through the first and third TFTs to the high-level terminal. Simultaneously, the second TFT remains conducting because its gate is connected to the third control node, discharging any residual charge from the second control node through the second and first TFTs to the high-level terminal, thus completely discharging the second control node to a low level. This avoids the problem of continuous stress on the pull-down TFT caused by residual charge at the second control node.

[0013] In some non-limiting embodiments, the GOA unit further includes a first control circuit and a second control circuit. Both the first and second control circuits include a control terminal, an input terminal, and an output terminal, with their output terminals electrically connected to the first control node. The first and second control circuits are configured to conduct their input and output terminals in response to their control terminals being at a high level. The control terminal of the first control circuit is configured to receive the front-stage gate drive signal or its stage transmission signal of the GOA unit, and the control terminal of the second control circuit is configured to receive the rear-stage gate drive signal or its stage transmission signal of the GOA unit.

[0014] The input terminals of the two control circuits can be implemented as follows: In the first implementation: the input terminal of the first control circuit is electrically connected to its control terminal, and the input terminal of the second control circuit is configured to receive a low-level signal.

[0015] In this embodiment, when the control terminal of the first control circuit receives the gate drive signal or its stage transmission signal from the preceding stage, the control circuit directly provides the level of that signal to the first control node, charging the first control node to a high level and enabling this stage. Although the control terminal of the second control circuit receives the gate drive signal or its stage transmission signal from the following stage, it is still at a low level, so it has no effect on the first control node. This embodiment uses the gate drive signal from the preceding stage as the charging power supply, simplifying the power supply routing design and eliminating the need for additional high-level power lines, thus reducing wiring complexity. By fixing the input terminal of the second control circuit to a low level, this control circuit is only used for reset, ensuring stable forward scanning of the circuit.

[0016] The second implementation: the input terminal of the first control circuit is configured to receive a first DC voltage signal and the input terminal of the second control circuit is configured to receive a second DC voltage signal, wherein the first DC voltage signal and the second DC voltage signal are a pair of voltage signals with opposite levels.

[0017] In this embodiment, the pull-up charging power supply comes from an independent high level, rather than the gate drive signal or its transmission signal from the front or rear stage. This avoids voltage loss that may occur due to heavy load on the front or rear stage signals, ensuring that the first control node can be charged to a stable high level. This improves the output capability of the gate drive signal, making the pixels charge more fully and the display brightness more uniform.

[0018] Optionally, the level of the second DC voltage signal can be switched with the level of the first DC voltage signal.

[0019] This embodiment implements bidirectional scanning functionality for the GOA circuit. In forward scanning mode, the first control circuit is responsible for the pull-up charging of the first control node; in reverse scanning mode, the second control circuit takes over the pull-up function. This symmetrical design allows the same GOA unit to flexibly adapt to different scanning directions without modifying the hardware structure, simply by switching external levels. It is suitable for display panels requiring bidirectional drive (such as some touchscreens or special display modes), while simplifying circuit design and reducing manufacturing costs.

[0020] In some non-limiting embodiments, the first control circuit includes a fifth thin-film transistor, the gate of which serves as the control terminal of the first control circuit, its first terminal as the input terminal of the first control circuit, and its second terminal as the output terminal of the first control circuit; the second control circuit includes a sixth thin-film transistor, the gate of which serves as the control terminal of the second control circuit, its first terminal as the output terminal of the second control circuit, and its second terminal as the input terminal of the second control circuit.

[0021] This embodiment uses a single-transistor structure to implement the control circuit, forming the control path of the first control node with the simplest components. Compared to complex logic gate circuits, each control path only requires one thin-film transistor to complete the signal transmission function, significantly reducing the number of transistors, reducing the layout area of ​​the GOA unit, and facilitating the narrow bezel design of the display panel.

[0022] In some non-limiting embodiments, each GOA unit includes two pull-down sustaining circuits: a first pull-down sustaining circuit and a second pull-down sustaining circuit. The control terminal of the first pull-down sustaining circuit is configured to receive a first control signal, and the control terminal of the second pull-down sustaining circuit is configured to receive a second control signal. The first and second control signals are a pair of AC signals with opposite phases, alternating between high and low levels, so that the first and second pull-down sustaining circuits alternately maintain the first control node at a low level.

[0023] This embodiment uses two pull-down sustaining circuits that operate alternately. The pull-down sustaining task, originally handled continuously by one set of pull-down transistors, is now shared by two sets of pull-down transistors. Each set of pull-down transistors operates only during its corresponding half-cycle and remains off during the other half-cycle. This alternating operation mechanism effectively prevents the thin-film transistors from being biased due to prolonged DC gate voltage stress, significantly slowing down device aging and greatly extending the lifespan of the display panel.

[0024] In some non-limiting embodiments, at least one cascade group includes multiple pairs of GOA units, each pair of GOA units including two adjacent GOA units, namely a first GOA unit and a second GOA unit; The pull-down sustaining circuits of the first GOA unit and the second GOA unit also include a second sustaining circuit; the second sustaining circuit of the first GOA unit is electrically connected to the first control node of the first GOA unit, the second control node of the second GOA unit, and the low-level terminal, and the second sustaining circuit of the second GOA unit is electrically connected to the first control node of the second GOA unit, the second control node of the first GOA unit, and the low-level terminal. The second sustaining circuit in the first GOA unit is configured to: during the display phase, when the second control node of the second GOA unit is at a high level, conduct the second control terminal and the low-level terminal of the first GOA unit; The second sustaining circuit in the second GOA unit is configured to: during the display phase, when the second control node of the first GOA unit is at a high level, conduct the second control node and the low-level terminal of the second GOA unit; The control terminal of the pull-down sustaining circuit of the first GOA unit is configured to receive a first control signal, and the control terminal of the pull-down sustaining circuit of the second GOA unit is configured to receive a second control signal. The first control signal and the second control signal are a pair of AC signals with opposite phases and alternating high levels.

[0025] This embodiment adds a second sustaining circuit, allowing adjacent GOA units in each pair to share an inverter circuit. Previously, each GOA unit stage required two independent, complete inverter circuits for alternating control; now, each pair of GOA units only needs two inverter circuits to achieve alternating control. This shared design significantly reduces the number of transistors in the inverter circuit, effectively shrinking the overall layout area of ​​the GOA circuit and facilitating a narrower display panel bezel.

[0026] In some non-limiting embodiments, based on the previous embodiment, the first GOA unit is the pre-stage of the second GOA unit, and the pull-down sustaining circuit further includes a seventh thin-film transistor, whose first electrode is electrically connected to the second control node and whose second electrode is electrically connected to the low-level terminal; the gates of the seventh thin-film transistors of the first GOA unit and the second GOA unit are both configured to be connected to the same pre-stage gate drive signal or its stage transmission signal of the first GOA unit.

[0027] In this embodiment, since the seventh thin-film transistors of two adjacent GOA cells in the same pair of GOA cells are controlled by the same signal simultaneously, their conduction and cutoff actions are synchronized. This makes the reset actions of the two second control nodes in each pair of GOA cells consistent in time, maintaining the consistency of voltage stress on the TFT during the pull-down of the two adjacent GOA cells in each pair of GOA cells, and improving display stability.

[0028] In some non-limiting embodiments, the control terminals of the second control circuits of the first GOA unit and the second GOA unit are configured to be connected to the same subsequent gate drive signal or its transmission signal of the second GOA unit.

[0029] In this embodiment, since two adjacent GOA units in the same pair are controlled by the same signal simultaneously, their turn-on and turn-off actions are synchronized. This makes the reset actions of the two first control nodes in each pair of GOA units consistent in time, which further promotes the consistency of voltage stress on the TFT during the pull-down of the two adjacent GOA units, thereby further improving the display stability.

[0030] In some non-limiting embodiments, the inverter circuit also includes a capacitor electrically connected between the third control node and the second control node.

[0031] In this embodiment, a capacitor is connected between the third control node and the second control node to form a coupling path, which couples the potential changes of the third and second control nodes. When the potential of one node fluctuates due to circuit operation or external interference, the potential of the other node will fluctuate synchronously through the coupling effect of the capacitor. This coupling effect makes the potential change trends of the third and second control nodes more consistent, reducing the potential difference fluctuation between them and thus improving the stability of the circuit operation.

[0032] Secondly, embodiments of this application also provide a display panel. The display panel includes the gate driving circuit provided in any embodiment of the first aspect.

[0033] The beneficial effects achievable by the display panel provided in the second aspect are adaptable to the beneficial effects described in the relevant embodiments of the first aspect, and will not be repeated here. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a plan view of a display panel provided in an embodiment of this application; Figure 2 This is a schematic diagram of a GOA circuit in related technologies; Figure 3 for Figure 2 A waveform diagram of multiple nodes and signals during the power-off discharge phase of the display panel; Figure 4 A schematic diagram of a GOA circuit provided in an embodiment of this application; Figure 5 A waveform diagram of the first control signal LC1 and the second control signal LC2 provided for embodiments of this application; Figure 6 for Figure 4 A schematic diagram of the waveforms of multiple nodes and signals during the power-off discharge phase; Figure 7 A schematic diagram of another GOA circuit provided in an embodiment of this application; Figure 8 A schematic diagram of another GOA circuit provided in an embodiment of this application; Figure 9 A schematic diagram of another GOA circuit provided in an embodiment of this application; Figure 10 A schematic diagram of another GOA circuit provided in an embodiment of this application; Figure 11 This is a schematic diagram of another GOA circuit provided in an embodiment of this application. Detailed Implementation

[0036] To make the technical problems, technical solutions and beneficial effects to be solved by this application clearer, the following describes this application in further detail with reference to the accompanying drawings and embodiments.

[0037] For example, please refer to Figure 1 , Figure 1 This is a plan view of a display panel 000 provided in an embodiment of this application. The display panel 000 includes an array substrate 001 and a display medium layer 002 stacked along the thickness direction.

[0038] The array substrate 001 includes a substrate 100, multiple gate lines 200, multiple data lines 300, a gate driving circuit 400, a data driving circuit 500, etc.

[0039] Multiple gate lines 200 extend along the row direction (as shown in the Y-axis direction) and are arranged sequentially along the column direction (as shown in the X-axis direction). Multiple data lines 300 extend along the column direction and are arranged sequentially along the row direction. The two are insulated from each other and cross each other, thereby dividing the structure into multiple pixel structures arranged in a multi-row and multi-column matrix.

[0040] Each pixel structure contains a thin-film transistor (not shown in the figure) and a pixel electrode (not shown in the figure). The gate of the thin-film transistor is electrically connected to the gate line 200 of the corresponding row, the source is electrically connected to the data line 300 of the corresponding column, and the drain is electrically connected to the pixel electrode. The pixel electrode cooperates with the optical medium in the corresponding area of ​​the display medium layer 002 above to form a sub-pixel for display. It should be noted that sub-pixels in the same row constitute a pixel row, and the same pixel row corresponds to at least one gate line 200.

[0041] The gate drive circuit 400 (also known as the GOA circuit) is located in the non-display area on the side of the array substrate in the Y-axis direction of the display area. It is electrically connected to each gate line and is used to generate gate scan signals (also known as gate drive signals) row by row. The gate scan signals are applied sequentially to the thin film transistor gates of each row pixel drive unit through the gate lines 200 of each pixel row to control each pixel row to turn on sequentially.

[0042] The data driving circuit 500 (also known as the source driving circuit) is located in the non-display area on the side of the array substrate in the X-axis direction of the display area. It is electrically connected to each data line 300 and is responsible for writing the data voltage into the pixel electrode of the corresponding pixel driving unit through the data line during the period when each pixel row is turned on, so as to realize the line-by-line scanning display.

[0043] The gate drive circuit 400 includes at least one cascaded group, each cascaded group containing a multi-stage GOA unit arranged in a cascaded manner.

[0044] Each GOA unit has a corresponding gate line. Each GOA unit is used to output a gate drive signal to the corresponding gate line, so that the thin film transistor connected to the gate line is turned on, so that the corresponding pixel electrode receives the data signal provided by the data line 300, thereby controlling the optical state of the corresponding display medium area and realizing the display.

[0045] Each pixel row can be controlled by at least one GOA unit via an electrical connection to the gate line 200 corresponding to that pixel row. In other words, a pixel row can be controlled by one or more gate lines and driven by one or more GOA units.

[0046] As an optional implementation, in a conventional 1G1D architecture, each pixel row corresponds to one gate line 200, and each gate line 200 corresponds to one GOA unit. In this case, there is a one-to-one correspondence between the GOA unit, the gate line, and the pixel row. For example, the display panel 000 may include the first to Nth pixel rows arranged from top to bottom along the X-axis. N gate lines 200 may be disposed on the substrate 100, and the gate driving circuit 400 may have N GOA units. The first GOA unit corresponds to the first pixel row and is electrically connected to the first gate line 200; ..., the Nth GOA unit corresponds to the Nth pixel row and is electrically connected to the Nth gate line 200.

[0047] In other architectures (such as dual-gate architecture, bilateral drive architecture, or internally compensated pixel circuit), the same pixel row may also correspond to multiple gate lines 200 and / or multiple GOA units, and this application embodiment does not limit this.

[0048] It should be noted that when the gate driving circuit 400 includes multiple cascaded groups, the pixel rows driven by the GOA units in different cascaded groups are physically staggered along the column direction. In other words, the pixel rows corresponding to each level of GOA units in the same cascaded group are not arranged continuously in the display area, but are interspersed with the pixel rows corresponding to other cascaded groups. For example, the (n-4)th level GOA unit, the nth level GOA unit, and the (n+4)th level GOA unit form the first cascade group; the (n-3)th level GOA unit, the (n+1)th level GOA unit, and the (n+5)th level GOA unit form the second cascade group; and the (n-2)th level GOA unit, the (n+2)th level GOA unit, and the (n+6)th level GOA unit form the third cascade group. In the second cascade group, the (n-3)th pixel row corresponding to the (n-3)th level GOA unit is interspersed between the (n-4)th pixel row corresponding to the (n-4)th level GOA unit in the first cascade group and the (n-2)th pixel row corresponding to the (n-2)th level GOA unit in the third cascade group. This results in the preceding or following level GOA unit in the cascade not being the preceding or following level GOA unit in the traditional sense (ordinal number). For example, the preceding level GOA unit in the cascade of the nth level GOA unit is the (n-4)th level GOA unit, not the (n-1)th level GOA unit.

[0049] Because the pixel rows corresponding to the GOA units in different cascade groups are staggered along the X-axis, if all cascade groups are driven by clock signals of the same phase, multiple cascade groups will output gate drive signals simultaneously at the same time, causing multiple non-adjacent pixel rows to be turned on at the same time, making normal line-by-line scanning impossible. Therefore, it is necessary to provide clock signals of different phases for different cascade groups so that the gate drive signals output by each group are staggered in time. For example, when the first cascade group outputs to drive the (n-4)th row, the second cascade group has not yet output; after the first cascade group finishes outputting, the second cascade group outputs to drive the (n-3)th row; then the third cascade group outputs to drive the (n-2)th row, and so on. In this way, combined with the spatially staggered arrangement of pixel rows, each pixel row can be scanned line by line along the X-axis in a top-to-bottom or bottom-to-top order.

[0050] GOA (Gateway Availability) cells typically include a pull-down sustaining circuit. This circuit maintains the GOA cell at a low potential after the current scan cycle, preventing accidental activation. However, in current pull-down sustaining circuits, the pull-down sustaining TFT is biased for an extended period after power-off discharge, significantly impacting the lifespan of the display panel. Analysis reveals the following reason: during power-off discharge, the control node of the pull-down sustaining TFT in the circuit cannot be completely discharged, leaving residual charge. This causes the pull-down sustaining TFT to be biased for an extended period, leading to a shift in the threshold voltage Vth. The following section discusses... Figure 2 and Figure 3 An example is provided.

[0051] Please refer to the reference. Figure 2 , Figure 3 , Figure 2 This is a schematic diagram of a GOA circuit in related technologies. Figure 3 for Figure 2 The waveform diagram of multiple nodes and signals during the power-off discharge phase of the display panel.

[0052] Figure 2 Only one GOA unit of the GOA circuit is shown in the image. The display panel is in the power-off discharge phase. Figure 3 The potential of each node shown will first be pulled up to VGH and then dropped to GND to complete the discharge, thus avoiding residual charge at each node that could cause the TFT in the circuit to be biased by a bias voltage, resulting in Vth being forward biased.

[0053] However, in the pull-down sustaining circuit of this circuit (the part highlighted by the dashed line), taking the pull-down sustaining circuit where T51 is located as an example, T42 and T32 are both pull-down sustaining TFTs, and their control node is Kn. Since T51 is a diode connection (as shown in the figure, the gate and source of T51 are electrically connected), during the LC1 pull-up discharge process, Vgs of T51 will be 0V, which makes T51 in the off state and unable to discharge; at the same time, Vgs of T54 is 0V, also in the off state, and the control node Kn cannot be completely discharged through T51 and T54. Figure 3 This illustrates the case where Kn is not discharged to GND, resulting in residual charge at the control node Kn. This residual charge at the control node Kn causes T42 and T32 to be forward-biased by the bias voltage, thus affecting their lifespan. Similarly, in the pull-down sustaining circuit containing T61, residual charge also exists at the control node Pn, causing the pull-down sustaining thin-film transistors T43 and T33 to be forward-biased by the bias voltage.

[0054] To address the aforementioned technical problems, embodiments of this application provide... Figures 4 to 11 The GOA circuit shown.

[0055] Please see Figure 4 , Figure 4 This is a schematic diagram of a GOA circuit 400 provided in an embodiment of this application.

[0056] The GOA circuit 400 includes at least one cascaded group, and each cascaded group includes multiple cascaded GOA units. Figure 4 The image shows one of the first-level GOA units. Below is an example... Figure 4 Taking the nth level GOA unit as an example, we will illustrate the GOA unit exemplarily, where n is a positive integer.

[0057] The nth-level GOA unit includes two control circuits (defined as the first control circuit 410 and the second control circuit 420, respectively), a pull-up circuit 430, a reset circuit 440, two pull-down sustaining circuits (defined as the first pull-down sustaining circuit 450 and the second pull-down sustaining circuit 460, respectively), a first control node Qn, and a gate drive node Xn. These functional modules are described below.

[0058] Optionally, the potential of the first control node Qn is used to control the nth-level GOA unit to turn on or off, thereby selecting whether the nth-level GOA unit outputs or does not output the nth-level gate drive signal Gn to the corresponding pixel row for scanning. When the first control node Qn is high, it indicates that output is selected; when the first control node Qn is low, it indicates that no output is selected.

[0059] The potential of the first control node Qn is controlled independently by two control circuits, which are referred to as the first control circuit and the second control circuit for easy distinction. The first control circuit is used to pull the first control node Qn high, and the second control circuit is used to pull the first control node Qn low. Figure 4 The circuit has two scanning modes: forward scanning mode and reverse scanning mode. In forward scanning mode, the first control circuit is used to pull the first control node Qn high, and the second control circuit is used to pull the first control node Qn low. In reverse scanning mode, the first control circuit is used to pull the first control node Qn low, and the second control circuit is used to pull the first control node Qn high. The details are explained below.

[0060] Specifically, the first control circuit 410 includes a control terminal P21, an input terminal I21, and an output terminal O21 electrically connected to the first control node Qn. The second control circuit 420 includes a control terminal P22, an input terminal I22, and an output terminal O22 electrically connected to the first control node Qn.

[0061] The control terminal P21 of the first control circuit 410 is configured to connect to the front gate drive signal or its transmission signal of the nth stage GOA unit. Figure 4 The gate drive signal of the nth stage GOA unit shown is the gate drive signal of the first four stages of the nth stage GOA unit, i.e., the gate drive signal Gn-4 of the (n-4)th stage; the control terminal P22 of the second control circuit 420 is configured to receive the gate drive signal of the nth stage GOA unit or its stage transmission signal. Figure 4 The gate drive signal of the nth stage GOA cell shown is the gate drive signal of the last four stages of the nth stage GOA cell, i.e., the gate drive signal of the (n+4th)th stage. It should be noted that... Figure 4 The example shown illustrates the use of the gate drive signal. In other embodiments, a cascade signal of the gate drive signal can also be used. The cascade signal is essentially a clone of the gate drive signal. This will be explained in detail in subsequent embodiments and will not be elaborated here.

[0062] It should be noted that the gate drive signal of the nth level GOA unit refers to the gate drive signal Gn of this level that is output before the gate drive signal Gn of the nth level GOA unit. It is output by the previous level GOA unit in the same cascaded group of multi-level GOA units with a cascade relationship, and not by the previous level GOA unit of the ordinal number. For example, the gate drive signal Gn-4 of the n-4th level here is output by the previous level GOA unit (i.e., the four levels of GOA units before the nth level GOA unit) - the n-4th level GOA unit, and not by the (n-1)th level GOA unit.

[0063] The gate drive signal of the nth stage GOA unit refers to the gate drive signal output later than the gate drive signal Gn of the current stage of the nth stage GOA unit, and is not necessarily output by the next stage GOA unit cascaded from the nth stage GOA unit.

[0064] The next stage GOA unit cascaded from the nth stage GOA unit is determined by the gate drive signal Gn of the nth stage GOA unit or its cascade transmission signal passed to the next stage GOA unit. When the (n-4)th stage GOA unit completes its scan, it outputs the (n-4)th stage gate drive signal Gn-4 to drive the first control node Qn of the nth stage GOA unit to a high level, thereby starting the scan of the nth stage GOA unit; when the nth stage GOA unit completes its scan, it outputs the nth stage gate drive signal Gn to drive the next stage GOA unit cascaded from the nth stage GOA unit (here, the (n+4)th stage GOA unit) to start its scan, and so on.

[0065] The output terminal O21 of the first control circuit 410 and the output terminal O22 of the second control circuit 420 are both electrically connected to the first control node Qn.

[0066] The input terminal I21 of the first control circuit 410 and the input terminal I22 of the second control circuit 420 are configured to receive signals with opposite levels. This does not limit the levels of the two to always being opposite; they can be opposite for a period of time.

[0067] The first control circuit 410 is configured to: in response to the control terminal P21 being at a high level, conduct input terminal I21 and output terminal O21, so as to perform one of a pull-high and pull-low operation on the first control node Qn electrically connected to output terminal O21 using the level of input terminal I21. The second control circuit 420 is configured to: in response to the control terminal P22 being at a high level, conduct its input terminal I22 and output terminal O22, so as to perform the other of a pull-high and pull-low operation on the first control node Qn electrically connected to output terminal O21 using the level of input terminal I22 opposite to that of input terminal I21.

[0068] Optionally, in order to support two scanning modes, the input terminal I21 of the first control circuit 410 is configured to be connected to the first DC voltage signal VDS, and the input terminal I22 of the second control circuit 420 is configured to be connected to the second DC voltage signal VSD. The first DC voltage signal VDS and the second DC voltage signal VSD are a pair of voltage signals with opposite levels, and the level of the second DC voltage signal VSD can be switched with the level of the first DC voltage signal VDS.

[0069] The two scanning modes are as follows: Forward Scan Mode: The GOA circuit 400 scans from top to bottom along the X-axis. In this mode, VDS connected to the input terminal I21 of the first control circuit 410 is at a high level, and VSD connected to the input terminal I22 of the second control circuit 420 is at a low level. The first control circuit 410 is a pull-up control circuit. In response to the (n-4)th stage gate drive signal Gn-4 connected to its control terminal P21 being at a high level, it turns on the input terminal I21 and the output terminal O21, using the high level of the input terminal I21 to pull up the potential of the first control node Qn, thus turning on the nth stage GOA unit. At this time, although the control terminal P22 of the second control circuit 420 is connected to the (n+4)th stage gate drive signal Gn+4, it is still at a low level and cannot turn on the input terminal I22 and the output terminal O22, so it has no effect on the first control node Qn. As the scan proceeds from top to bottom, the second control circuit 420 is a pull-down control circuit. In response to the high level of the gate drive signal Gn+4 of the (n+4)th stage connected to its control terminal P22, the input terminal I22 and the output terminal O22 are turned on. The low level of the input terminal I22 is used to pull down the potential of the first control node Qn, so that the nth stage GOA unit is turned off.

[0070] Reverse Scan Mode: The GOA circuit 400 scans from bottom to top along the X-axis. In this mode, VDS connected to the input terminal I21 of the first control circuit 410 is at a low level, and VSD connected to the input terminal I22 of the second control circuit 420 is at a high level. The second control circuit 420 is a pull-up control circuit. In response to the (n+4)th stage gate drive signal Gn+4 connected to its control terminal P22 being at a high level, it turns on the input terminal I22 and the output terminal O22. It uses the high level of the input terminal I22 to pull up the potential of the first control node Qn, so that the nth stage GOA unit is turned on. At this time, although the control terminal P21 of the first control circuit 410 is connected to the (n-4)th stage gate drive signal Gn-4, it is still at a low level and cannot turn on the input terminal I21 and the output terminal O21, so it has no effect on the first control node Qn. As the scan proceeds from bottom to top, the first control circuit 410 is a pull-down control circuit. In response to the high level of the gate drive signal Gn-4 of the n-4th stage connected to its control terminal P21, the input terminal I21 and the output terminal O21 are turned on. The low level of the input terminal I21 is used to pull down the potential of the first control node Qn, so that the nth stage GOA unit is turned off.

[0071] This symmetrical design allows the same GOA unit to flexibly adapt to different scanning directions without modifying the hardware structure, simply by switching external levels. It is suitable for display panels requiring bidirectional drive (such as some touchscreens or special display modes), while also simplifying circuit design and reducing manufacturing costs. In this embodiment, because switching VDS and VSD allows switching the control circuits used as pull-up control circuits in the first control circuit 410 and the second control circuit 420, the first control circuit 410 and the second control circuit 420 are symmetrical, and the GOA units connected to their control terminals have the same level interval as the nth level GOA unit, both being 4 levels apart.

[0072] Specifically, please continue to refer to Figure 4 The first control circuit 410 includes a fifth thin-film transistor T11, and the second control circuit 420 includes a sixth thin-film transistor T41.

[0073] The gate of the fifth thin-film transistor T11 serves as the control terminal P21 of the first control circuit 410, its first terminal serves as the input terminal I21 of the first control circuit 410, and its second terminal serves as the output terminal O21 of the first control circuit 410.

[0074] The gate of the sixth thin-film transistor T41 serves as the control terminal P22 of the second control circuit 420, its first terminal serves as the output terminal O22 of the second control circuit 420, and its second terminal serves as the input terminal I22 of the second control circuit 420.

[0075] Taking VDS as high and VSD as low as an example, when the current stage gate drive signal Gn-4 is high, thin-film transistor T11 is in the on state, with its source and drain connected, thus transferring VDS connected to the source of thin-film transistor T11 to the drain, thereby pulling up the potential of the first control node Qn. When the subsequent stage gate drive signal Gn+4 is high, thin-film transistor T41 is in the on state, with its source and drain connected, thus transferring VSD connected to the source of thin-film transistor T11 to the drain, thereby pulling down the potential of the first control node Qn.

[0076] This embodiment uses a single-transistor structure to implement the control circuit, forming the control path of the first control node Qn with the simplest components. Compared to complex logic gate circuits, each control path only requires one thin-film transistor to complete the signal transmission function, significantly reducing the number of transistors, reducing the layout area of ​​the GOA unit, and facilitating the narrow bezel design of the display panel 000.

[0077] The pull-up circuit 430 is electrically connected between the gate driving node Xn and the first control node Qn, and is configured to selectively output to the gate driving node Xn according to the potential of the first control node Qn, so that the gate driving node Xn outputs it to the gate line 200 of the corresponding pixel row of the display panel 000.

[0078] The aforementioned selective output of the nth-level gate drive signal through the gate drive node Xn refers to selecting whether or not to output the nth-level gate drive signal through the gate drive node Xn. The pull-up circuit 430 functions similarly to a switch for the entire GOA unit. The potential of the first control node Qn controls the switching of this switch, thereby controlling the GOA unit to turn on or off, thus selecting whether or not to output the nth-level gate drive signal to scan the gate line 200 of the corresponding pixel row.

[0079] Specifically, the pull-up circuit 430 includes a thin-film transistor T21, whose first terminal receives the clock signal CLKn from the nth-level GOA unit, whose gate is electrically connected to the first control node Qn, and whose second terminal is electrically connected to the gate drive node Xn. When the first control node Qn is high, T21 is in the on state. The clock signal CLKn received by the first terminal of T21 is transmitted to the second terminal, causing the gate drive node Xn to output the nth-level gate drive signal Gn, representing the selection to output the nth-level gate drive signal. When the first control node Qn is low, T21 is in the off state. The clock signal CLKn from the first terminal of T21 cannot be transmitted to the second terminal of T21, and the gate drive node Xn of the GOA unit cannot output the nth-level gate drive signal, representing the selection not to output the nth-level gate drive signal.

[0080] It should be noted that in the embodiments of this application, the first electrode of the thin-film transistor is one of the source and the drain, and the second electrode of the thin-film transistor is the other of the source and the drain. For example, the first electrode of the thin-film transistor is the source, and the second electrode of the thin-film transistor is the drain.

[0081] Optionally, the pull-up circuit 430 also includes a bootstrap capacitor Cbt, the first end of which is electrically connected to the gate of T21 (i.e., the first control node Qn), and the second end of which is electrically connected to the second pole of T21 (i.e., the gate drive node Xn), for bootstrapping the gate drive node Xn to a higher potential when the first control node Qn is high, so as to ensure the stable output of the nth stage gate drive signal Gn.

[0082] The reset circuit 440 is electrically connected to the gate drive node Xn and the first control node Qn, and is configured to: in response to the incoming reset signal RESET being at a high level, forcibly pull the potential of the gate drive node Xn and the first control node Qn low to achieve a reset. The reset signal RESET usually appears at the end of a frame scan.

[0083] Specifically, the reset circuit 440 includes a thin-film transistor TRQ and a thin-film transistor TRG.

[0084] The gates of TRQ and TRG are electrically connected to form the control terminal of the reset circuit 440, used to receive the reset signal RESET. The first terminal of TRQ is electrically connected to the first control node Qn, and its second terminal is connected to a low-level signal VSS. The first terminal of TRG is electrically connected to the gate drive node Xn, and its second terminal is connected to a low-level signal VSS. When a high-level reset signal RESET is received, both TRQ and TRG are in the ON state, pulling the first control node Qn and the gate drive node Xn low to VSS, thereby achieving a reset.

[0085] Taking the first pull-down sustaining circuit 450 as an example, for Figure 4 The pull-down sustaining circuit in the circuit will be introduced.

[0086] The first pull-down sustaining circuit 450 includes an input terminal I1, an output terminal O11, an output terminal O12, a control terminal P11, a high-level terminal V1, a low-level terminal V2, and a second control node Kn. Input terminal I1 and output terminal O11 are both electrically connected to the first control node Qn, and output terminal O12 is electrically connected to the gate drive node Xn. The high-level terminal V1 is configured to receive a high-level signal VGH, the low-level terminal V2 is configured to receive a low-level signal VSS, and the control terminal P11 is configured to receive a first control signal LC1. The first pull-down sustaining circuit 450 is configured as follows: During the display phase, based on the potential of control terminal P11 (i.e., the potential of the first control signal LC1) and input terminal I1 (i.e., the potential of the first control node Qn), the potential of the second control node Kn is normally controlled using the high-level signal VGH of high-level terminal V1 and the low-level signal VSS of low-level terminal V2. Specifically, when the first control node Qn is at a low level, in response to its control terminal P11 being at a high level (i.e., the first control signal LC1 being at a high level), the high-level signal VGH controls the second control node Kn to be at a high level, so that the second control node Kn uses the low-level signal VSS to maintain the first control node Qn and the gate drive node Xn at a low level.

[0087] During the power-off discharge phase, in response to the discharge rate difference between the control terminal P11 and the high-level terminal V1, the second control node Kn is turned on to the high-level terminal V1 until the second control node Kn discharges to the low level. That is, the discharge path from the second control node Kn to the high-level terminal V1 is controlled and is in the on state before the second control node Kn discharges to the low level.

[0088] It should be noted that, Figure 2In the diode configuration of T51, both its gate and source receive the same signal (as shown in LC1). Therefore, during the power-off discharge phase, the discharge rates of the gate and source of T51 are consistent, and their potentials remain the same. T51 cannot conduct, and Kn is turned off through the discharge path of T51.

[0089] In this embodiment, without altering the normal operation of the first pull-down sustaining circuit 450, during the power-off discharge phase, as all signal lines are pulled high to their initial potential and then decrease, the discharge rate between the control terminal P11 and the high-level terminal V1 of the first pull-down sustaining circuit 450 is optimized to create a discharge rate difference, thus establishing a positive potential difference. This positive voltage difference controls the discharge path from the second control node Kn to the high-level terminal V1, providing an effective charge discharge path for the second control node Kn. Because this discharge path is in a conducting state before the second control node Kn discharges to a low level, the second control node Kn can discharge to a low level without residual charge. Consequently, the pull-down sustaining TFT in the pull-down sustaining circuit controlled by the second control node Kn no longer experiences prolonged bias due to bias voltage after power-off, thereby extending the lifespan of the display panel 000.

[0090] Alternatively, please continue to refer to Figure 4 The first pull-down sustaining circuit 450 includes an inverter circuit 451 and a first sustaining circuit 452.

[0091] The inverter circuit 451 is electrically connected to the input terminal I1, the control terminal P11, the high-level terminal V1, the low-level terminal V2, and the second control node Kn, and is configured as follows: During the display phase, based on the potentials of the control terminal P11 and the input terminal I1, one of the high-level signal VGH and the low-level signal VSS is selectively used to control the level of the second control node Kn, so that the level of the second control node Kn is opposite to that of the first control node Qn. Specifically, when the control terminal P11 is at a high level, the high-level terminal V1 is connected to the second control node Kn, and the second control node Kn is pulled high using VGH of the high-level terminal V1. When the control terminal P11 is at a low level, the high-level terminal V1 is disconnected from the second control node Kn (i.e., the discharge path between the high-level terminal V1 and the second control node Kn is disconnected). When the input terminal I1 is at a high level (i.e., the first control node Qn is at a high level), the low-level terminal V2 is connected to the second control node Kn (i.e., the discharge path between the low-level terminal V2 and the second control node Kn is connected), and the second control node Kn is pulled low using VSS of the low-level terminal V2. When the input terminal I1 is at a low level (i.e., the first control node Qn is at a low level), the low-level terminal V2 is disconnected from the second control node Kn (i.e., the discharge path between the low-level terminal V2 and the second control node Kn is disconnected).

[0092] During the power-off discharge phase, in response to the discharge rate of the control terminal P11 being less than the discharge rate of the high-level terminal V1, the second control node Kn is turned on and connected to the high-level terminal V1 until the second control node Kn discharges to a low level. The first sustaining circuit 452 is electrically connected to the second control node Kn, output terminal O11, and output terminal O12, and is configured to: during the display phase, in response to the second control node Kn being at a high level, conduct the discharge path between the first control node Qn and the low-level terminal V2 (referred to as conducting the first control node Qn and the low-level terminal V2), and also conduct the discharge path between the gate driving node Xn and the low-level terminal V2 (referred to as conducting the gate driving node Xn and the low-level terminal V2), thereby maintaining the first control node Qn and the gate driving node Xn at a low level.

[0093] When the first pull-down sustaining circuit 450 is constructed as described above, during the display phase, when the first control node Qn is at a low level, the inverter circuit 451 selectively transmits the high-level signal VGH of the high-level terminal V1 to the second control node Kn according to the potential of the control terminal P11 and the input terminal I1, making the second control node Kn at a high level. This drives the first sustaining circuit 452 to conduct the first control node Qn and the low-level terminal V2, reliably maintaining the first control node Qn at a low level, thus fully realizing the function of the first pull-down sustaining circuit 450 during the normal display phase. During the power-off discharge phase, as all signal potentials decrease, the inverter circuit 451 generates a positive potential difference because the discharge rate of the control terminal P11 is less than the discharge rate of the high-level terminal V1. This positive potential difference automatically opens the discharge path from the second control node Kn to the high-level terminal V1, allowing the residual charge on the second control node Kn to be completely discharged to a low level, thereby realizing the discharge function of the first pull-down sustaining circuit 450 during the power-off discharge phase.

[0094] Specifically, please continue to refer to Figure 4 The inverter circuit 451 includes a first thin-film transistor T51, a second thin-film transistor T53, a third thin-film transistor T52, and a fourth thin-film transistor T54.

[0095] The gate of the first thin-film transistor T51 is electrically connected to the control terminal P11, its first electrode is electrically connected to the high-level terminal V1, and its second electrode is electrically connected to the third control node Sn. The gate of the second thin-film transistor T53 is electrically connected to the third control node Sn, its first electrode is electrically connected to the first electrode of the first thin-film transistor T31, and its second electrode is electrically connected to the second control node Kn. The gate of the third thin-film transistor T52 is electrically connected to the input terminal I1, its first terminal is electrically connected to the third control node Sn, and its second terminal is electrically connected to the low-level terminal V2. The gate of the fourth thin-film transistor T54 is electrically connected to the input terminal I1, its first terminal is electrically connected to the second control node Kn, and its second terminal is electrically connected to the low-level terminal V2.

[0096] Optionally, the first sustaining circuit 452 includes a thin-film transistor T42 and a thin-film transistor T32. The gates of both thin-film transistor T42 and T32 are electrically connected to the second control node Kn; the first electrode of thin-film transistor T42 is electrically connected to the output terminal O11, and the first electrode of thin-film transistor T32 is electrically connected to the aforementioned output terminal O12; the second electrodes of both thin-film transistor T42 and T32 are electrically connected to the low-level terminal V2.

[0097] In this embodiment, during the display stage, the inverter circuit 451 achieves precise control of the potential of the second control node Kn through the coordinated operation of the first thin-film transistor T51 to the fourth thin-film transistor T54.

[0098] When the first control node Qn is low, the third thin-film transistor T52 and the fourth thin-film transistor T54 are turned off. If the first control signal LC1 received by the control terminal P11 is high, the first thin-film transistor T51 is turned on, charging the third control node Sn, which turns on the second thin-film transistor T53. The high-level signal VGH is used to pull the second control node Kn to a high level, turning on T42 and T32. The first control node Qn and the gate drive node Xn are maintained at a low level through VSS.

[0099] When the first control node Qn is high, the third thin-film transistor T52 and the fourth thin-film transistor T54 are turned on. The low-level signal VSS quickly pulls the potential of the third control node Sn and the second control node Kn to a low level, so that the second control node Kn is at a low level. T42 and T32 are turned off, and the potential of the first control node Qn and the gate drive node Xn is not affected.

[0100] During the power-off discharge phase, the discharge rate of LC1 is less than that of VGH, causing the potential of the gate of T51 (i.e., control terminal P11) to be higher than the potential of the first terminal of T51 (i.e., high potential terminal V1). This creates a positive voltage difference between the gate and the first terminal of the first thin-film transistor T51, keeping it in a conducting state and providing a charge discharge path for the third control node Sn through the first terminal of the first thin-film transistor T51. Simultaneously, the second thin-film transistor T53 remains conducting because its gate is connected to the third control node Sn, discharging the residual charge of the second control node Kn through the source of the second thin-film transistor T53 and the first terminal of the first thin-film transistor T51, thus completely discharging the second control node Kn to a low level.

[0101] The function, specific structure, and principle of the second pull-down sustaining circuit 460 in discharging the residual charge of the second control node Pn during the power-off discharge phase can be found in the relevant content of the first pull-down sustaining circuit 450, and will not be repeated here. The following focuses on the differences between the two.

[0102] Unlike the first pull-down sustaining circuit 450, the control terminal P12 of the second pull-down sustaining circuit 460 ( Figure 4 The signal (provided by the gate of the first thin-film transistor T61) is configured to receive the second control signal LC2.

[0103] The first control signal LC1 and the second control signal LC2 are configured as a pair of AC signals with opposite phases, alternating between high and low levels (e.g., with a period of 1-2 seconds). Figure 5 As shown, Figure 5 The waveform diagrams of the first control signal LC1 and the second control signal LC2 provided in the embodiments of this application are shown.

[0104] During the display phase, when the first control node Qn is low, in response to the first control signal LC1 being low and the second control signal LC2 being high, the operating state switches to the operation of the second pull-down sustaining circuit 460: the inverter circuit 461 of the second pull-down sustaining circuit 460 uses the high-level signal VGH of the high-level terminal V1 to set the second control node Pn to a high level, so that its first sustaining circuit 462 maintains the first control node Qn and the gate drive node Xn at a low level; at this time, the first control signal LC1 is low, and the first pull-down sustaining circuit 450 stops working.

[0105] When the first control signal LC1 is high and the second control signal LC2 is low, the operating state switches to the first pull-down sustaining circuit 450. This cycle repeats, with the inverter circuit 451 of the first pull-down sustaining circuit 450 and the inverter circuit 461 of the second pull-down sustaining circuit 460 alternately controlling their respective second control nodes Kn and Pn to be high based on this pair of signals. This causes the first sustaining circuit 452 of the first pull-down sustaining circuit 450 and the first sustaining circuit 462 of the second pull-down sustaining circuit 460 to alternately maintain the first control node Qn and the gate drive node Xn at a low level, thus achieving continuous pull-down sustaining of the first control node Qn and the gate drive node Xn.

[0106] This embodiment uses two pull-down sustaining circuits that operate alternately. The pull-down sustaining task, originally handled continuously by one set of pull-down transistors, is now shared by two sets of pull-down transistors in rotation. Each set of pull-down transistors operates only during its corresponding half-cycle and remains off during the other half-cycle. This alternating operation mechanism effectively prevents the threshold voltage (Vth) of thin-film transistors T42, T32, T43, and T33 from shifting positively due to prolonged DC gate voltage stress, significantly slowing down device aging and greatly extending the lifespan of the display panel.

[0107] It should be noted that in some other embodiments, each GOA unit may also be equipped with only one pull-down sustaining circuit to achieve continuous pull-down sustaining of the first control node Qn and the gate drive node Xn.

[0108] Please refer to the reference. Figure 6 , Figure 6 for Figure 4 The diagram illustrates the waveforms of multiple nodes and signals during the power-off discharge phase. Specifically, the second control nodes Kn and Pn are pulled high and then lowered to GND. This avoids the problem of residual charge at the second control node Kn causing stress on T32 and T42, and residual charge at the second control node Pn causing stress on T33 and T43, which are the four pull-down mechanisms for maintaining continuous stress on the TFT.

[0109] Please see Figure 7 , Figure 7 This is a schematic diagram of another GOA circuit 400 provided in an embodiment of this application.

[0110] Different from Figure 4 The GOA circuit 400 shown is... Figure 7 In the GOA circuit 400 shown, taking the nth stage GOA unit as an example, the input terminal I21 of the first control circuit 410 (provided by the first pole of T11 in the figure) is electrically connected to its control terminal P21 (provided by the gate of T11 in the figure). Therefore, the input terminal I21 of the first control circuit 410 is also connected to the previous stage gate drive signal (here, the gate drive signal Gn-4 of the n-4th stage) as a charging power supply; the input terminal I22 of the second control circuit 420 (provided by the second pole of T41 in the figure) is electrically connected to the low-level terminal V2 to access the low-level signal VSS.

[0111] Figure 7The GOA circuit 400 shown operates in unidirectional scanning mode. When the pre-stage gate drive signal Gn-4 connected to the control terminal P21 of the first control circuit 410 is at a high level, the first control circuit 410 turns on the input terminal I21 and the output terminal O21. The input terminal I21 is also connected to the signal and is at a high level. Therefore, the first control circuit 410 directly provides its high level to the first control node Qn electrically connected to the output terminal O21, so that the first control node Qn is charged to a high level and the stage is turned on. At this time, although the control terminal P22 of the second control circuit 420 is connected to the subsequent stage gate drive signal Gn+4, it is still at a low level and cannot turn on the input terminal I22 and the output terminal O22, so it has no effect on the first control node Qn. As the scan proceeds from top to bottom, when the gate drive signal Gn+4 of the (n+4)th stage is at a high level, the second control circuit 420 turns on the input terminal I22 and the output terminal O22. It uses the low-level signal VSS connected to the input terminal I22 to pull the first control node Qn electrically connected to the output terminal O22 down to a low level, thereby turning off the nth stage GOA unit and realizing the forward scanning process from top to bottom.

[0112] Figure 7 The GOA circuit 400 shown uses the front-stage gate drive signal as the pull-up charging power supply for the first control node Qn, simplifying the power supply routing design and eliminating the need for an additional high-level power line, thus reducing wiring complexity. By fixing the input of the second control circuit 420 to receive the low-level signal VSS, the second control circuit 420 is used as a pull-down module, ensuring stable unidirectional scanning of the circuit.

[0113] Please see Figure 8 , Figure 8 This is a schematic diagram of another GOA circuit 400 provided in an embodiment of this application.

[0114] Different from Figure 7 The GOA circuit 400 shown is... Figure 8 In the GOA circuit 400 shown, the input terminal I21 of the first control circuit 410 (provided by the first pole of T11 shown) is configured to receive a high-level signal VGH (when the first DC voltage signal is a high-level signal), and the input terminal I22 of the second control circuit 420 (provided by the second pole of T41 shown) is configured to receive a low-level signal VSS (when the second DC voltage signal is a low-level signal).

[0115] In this case Figure 8The GOA circuit 400 shown operates in unidirectional scanning mode: when the gate drive signal Gn-4 of the (n-4)th stage connected to the control terminal P21 of the first control circuit 410 is at a high level, the input terminal I21 and the output terminal O21 are turned on. The first control circuit 410 uses the high-level signal VGH connected to the output terminal O21 to charge the first control node Qn electrically connected to the output terminal O21 to a high level, so that the nth stage GOA unit is turned on. Although the control terminal P22 of the second control circuit 420 is connected to the gate drive signal Gn+4 of the subsequent stage, it is still at a low level and cannot turn on the input terminal I22 and the output terminal O22, so it has no effect on the first control node Qn. As the scan proceeds from top to bottom, when the gate drive signal Gn+4 of the (n+4)th stage is at a high level, the second control circuit 420 turns on the input terminal I22 and the output terminal O22. It uses the low-level signal VSS connected to the input terminal I22 to pull the first control node Qn electrically connected to the output terminal O22 down to a low level, thereby turning off the nth stage GOA unit and realizing the forward scanning process from top to bottom.

[0116] In this embodiment, the pull-up charging power supply comes from an independent high level, rather than the previous stage gate drive signal or its stage transmission signal. Using an independent high level as the pull-up charging power supply for the first control node Qn avoids voltage loss that might occur due to heavy load on the previous stage signal, ensuring that the first control node Qn can be charged to a stable high level. This improves the output capability of the gate drive signal, resulting in more complete pixel charging and more uniform display brightness. The second control circuit 420 is used as a pull-down module to ensure stable unidirectional scanning of the circuit.

[0117] Alternatively, please continue to refer to Figure 8 The inverter circuit 451 of the first pull-down sustaining circuit 450 also includes a capacitor C2, electrically connected between the third control node Sn and the second control node Kn, forming a coupling path. This couples the potential changes of the third control node Sn and the second control node Kn of the first pull-down sustaining circuit 450. When the potential of either the third control node Sn or the second control node Kn of the first pull-down sustaining circuit 450 fluctuates due to circuit operation or external interference, the potential of the other node will fluctuate synchronously through the coupling effect of the capacitor. This coupling effect makes the potential change trends of the third control node Sn and the second control node Kn of the first pull-down sustaining circuit 450 tend to be consistent, reducing the potential difference fluctuation between them, thereby improving the stability of circuit operation.

[0118] The inverter circuit 461 of the second pull-down sustaining circuit 460 also includes a capacitor C3, which is electrically connected between the third control node Tn and the second control node Pn of the second pull-down sustaining circuit 460. Its effect is similar to that of the capacitor C2.

[0119] Please see Figure 9 , Figure 9 This is a schematic diagram of another GOA circuit 400 provided in an embodiment of this application.

[0120] At least one cascaded group of the GOA circuit 400 includes multiple pairs of GOA units, each pair of GOA units including two adjacent GOA units, which are defined as the first GOA unit and the second GOA unit, respectively. The first GOA unit and the second GOA unit are adjacent to each other, meaning that the pixel rows corresponding to the first GOA unit and the second GOA unit are physically adjacent. Figure 9 The GOA circuit 400 shown illustrates a pair of GOA units, namely the nth level GOA unit and the (n+1)th level GOA unit, with the nth level GOA unit being the first GOA unit and the (n+1)th level GOA unit being the second GOA unit.

[0121] Compared to the aforementioned embodiments, Figure 9 The GOA units shown have at least the following differences: Figure 9 The GOA unit shown also includes a cascade circuit 480.

[0122] Taking the stage transmission circuit 480 of the nth stage GOA unit as an example, it is electrically connected between the first control node Qn and the stage transmission node Yn. It is configured to selectively output the nth stage transmission signal STn (the stage transmission signal of the nth stage gate drive signal Gn) through the stage transmission node Yn according to the potential of the first control node Qn. The nth stage transmission signal STn is also generated by the clock signal CLKn of the nth stage GOA unit.

[0123] The operation principle of the stage transmission circuit 480 is similar to that of the pull-up circuit 430, both generating their respective output signals based on the clock signal CLKn. The difference is that the nth-stage gate drive signal Gn generated by the pull-up circuit 430 is used to output to the gate line 200 of the nth pixel row for scanning and is not used for stage transmission, while the nth-stage stage transmission signal STn generated by the stage transmission circuit 480 is dedicated to stage transmission (for example, STn-4 in the figure is the stage transmission signal of the front-stage gate drive signal of the nth stage, and STn+6 is the stage transmission signal of the rear-stage gate drive signal of the (n+1)th stage), and is not used for scanning, thus improving display stability.

[0124] Specifically, the stage transmission circuit 480 of the nth stage GOA unit includes a thin film transistor T22. The gate of the thin film transistor T22 is electrically connected to the first control node Qn. Its first terminal is configured to receive the clock signal CLKn of the nth stage GOA unit, and its second terminal is used as a stage transmission node Yn and is configured to output the nth stage transmission signal STn.

[0125] To reduce the circuit layout area, unlike Figure 4 , Figure 7 , Figure 8The two pull-down sustaining circuits of the GOA circuit 400 shown are... Figure 9 In the GOA circuit 400 shown, each GOA unit includes only one pull-down sustaining circuit 470. However, in addition to the inverter circuit 471 and the first sustaining circuit 472, the pull-down sustaining circuit 470 also includes a second sustaining circuit 473. The second sustaining circuit 473 works in conjunction with the inverter circuit 471 in the adjacent GOA unit of the same pair of GOA units, replacing the aforementioned circuit. Figure 4 , Figure 7 , Figure 8 The second pull-down sustaining circuit in the GOA circuit 400 shown is used to achieve pull-down sustaining of the control node at this level, which will be explained in detail below.

[0126] The nth-level GOA unit involves three control nodes that need to be pulled down for sustaining: the first control node Qn, the gate drive node Xn, and the cascade node Yn. The pull-down sustaining circuit 470 of the nth-level GOA unit is used to sustain the pull-down of these three control nodes. In this case, the pull-down sustaining circuit 470 of the nth-level GOA unit includes three output terminals, referred to as output terminal O11, output terminal O12, and output terminal O13, which are electrically connected to the three control nodes respectively.

[0127] The (n+1)th stage GOA unit involves three control nodes that require pull-down sustaining: the first control node Qn+1, the gate drive node Xn+1, and the cascade node Yn+1. The pull-down sustaining circuit 470 of the (n+1)th stage GOA unit is used to sustain the pull-down of these three control nodes. In this case, the pull-down sustaining circuit 470 of each (n+1)th stage GOA unit includes three output terminals, referred to as output terminal O11, output terminal O12, and output terminal O13, which are electrically connected to the three control nodes respectively.

[0128] Figure 9 In this configuration, the low-level terminals include a first low-level terminal V21 and a second low-level terminal V22. The first low-level terminal V21 is configured to receive a low-level signal VSSQ; the second low-level terminal V22 is configured to receive a low-level signal VSSG.

[0129] The first sustaining circuit 472 and the second sustaining circuit 473 of the nth level GOA unit are both electrically connected to the output terminals O11, O12, and O13 of the pull-down sustaining circuit 470 of the nth level GOA unit, and are also electrically connected to the first low-level terminal V21 and the second low-level terminal V22. The first sustaining circuit 472 of the nth level GOA unit is also electrically connected to the second control node Kn of the nth level GOA unit, and the second sustaining circuit 473 of the nth level GOA unit is also electrically connected to the second control node Pn+1 of the (n+1)th level GOA unit. The second sustaining circuit 473 of the nth level GOA unit is configured to, during the display phase, when the second control node Pn+1 of the (n+1)th level GOA unit is at a high level, connect the output terminal O11 (i.e., the first control node Qn of the pull-down sustaining circuit 470 of the nth level GOA unit) to the first low-level terminal V21, the output terminal O12 to the second low-level terminal V22, and the output terminal O13 to the second low-level terminal V22, thereby maintaining the three control nodes—the first control node Qn, the gate drive node Xn, and the stage transmission node Yn—at a low level.

[0130] The first sustaining circuit 472 and the second sustaining circuit 473 of the (n+1)th level GOA unit are both electrically connected to the output terminals O11, O12, and O13 of the pull-down sustaining circuit 470 of the (n+1)th level GOA unit, and are also electrically connected to the first low-level terminal V21 and the second low-level terminal V22. The first sustaining circuit 472 of the (n+1)th level GOA unit is also electrically connected to the second control node Pn+1 of the (n+1)th level GOA unit, and the second sustaining circuit 473 of the (n+1)th level GOA unit is also electrically connected to the first control node Kn of the nth level GOA unit. The second sustaining circuit 473 of the (n+1)th level GOA unit is configured to, during the display phase, when the second control node Kn of the nth level GOA unit is at a high level, connect the output terminal O11 (i.e., the first control node Qn+1 of the pull-down sustaining circuit 470 of the (n+1)th level GOA unit) to the first low-level terminal V21, the output terminal O12 to the second low-level terminal V22, and the output terminal O13 to the second low-level terminal V22, thereby maintaining the three control nodes—the first control node Qn+1, the gate drive node Xn+1, and the stage transmission node Yn+1—at a low level.

[0131] Specifically, the first sustaining circuit 472 of the nth-level GOA unit and the (n+1)th-level GOA unit both include thin-film transistor T32, thin-film transistor T72, and thin-film transistor T42. The second sustaining circuit 473 of the nth-level GOA unit and the (n+1)th-level GOA unit both include thin-film transistor T33, thin-film transistor T73, and thin-film transistor T43.

[0132] In the nth-level GOA unit, the gates of thin-film transistors T32, T72, and T42 are all electrically connected to the second control node Kn of this level. The gates of thin-film transistors T33, T73, and T43 are all electrically connected to the second control node Pn+1 of the (n+1)th-level GOA unit. The second terminals of thin-film transistors T42, T43, T72, and T73 are each electrically connected to the first low-level terminal V21 to receive the low-level signal VSSQ. The second terminals of thin-film transistors T32 and T33 are electrically connected to the second low-level terminal V22 to receive the low-level signal VSSG. The first terminals of thin-film transistors T42, T72, and T32 are respectively electrically connected to the three output terminals O11, O12, and O13 of the pull-down sustaining circuit 470 of the nth level GOA unit. The first terminals of thin-film transistors T43, T73, and T33 are also respectively electrically connected to the three output terminals O11, O12, and O13 of the pull-down sustaining circuit 470 of the nth level GOA unit.

[0133] In the (n+1)th level GOA unit, the gates of thin-film transistors T32, T72, and T42 are all electrically connected to the second control node Pn+1 of this level. The gates of thin-film transistors T33, T73, and T43 are all electrically connected to the second control node Kn of the nth level GOA unit. The second terminals of thin-film transistors T42, T43, T72, and T73 are all electrically connected to the first low-level terminal V21 to receive the low-level signal VSSQ. The second terminals of transistors T32 and T33 are each electrically connected to the second low-level terminal V22 to receive the low-level signal VSSG. The first terminals of thin-film transistors T42, T72, and T32 are respectively electrically connected to the three output terminals O11, O12, and O13 of the pull-down sustaining circuit 470 of the (n+1)th level GOA unit. The first terminals of thin-film transistors T43, T73, and T33 are respectively electrically connected to the three output terminals O11, O12, and O13 of the pull-down sustaining circuit 470 of the (n+1)th level GOA unit.

[0134] The control terminal P11 of the pull-down sustaining circuit 470 of the nth-level GOA unit (provided by the gate of T51 of the nth-level GOA unit) is configured to connect to the first control signal LC1, and the control terminal P11 of the pull-down sustaining circuit 470 of the (n+1)th-level GOA unit (provided by the gate of T51 of the (n+1)th-level GOA unit) is configured to connect to the second control signal LC2. The first control signal LC1 and the second control signal LC2 are a pair of AC signals with opposite phases and alternating high levels, so that the first sustaining circuit 472 and the second sustaining circuit 473 of the pull-down sustaining circuit 470 of the same GOA unit alternately control the second control nodes Kn and Pn+1 to be at a high level, so as to maintain the low level of the three control nodes of the nth-level GOA unit and the (n+1)th-level GOA unit respectively.

[0135] In this embodiment, adjacent GOA units in each pair share each other's inverter circuit 471 and second sustaining circuit 473. Previously, each GOA unit required two independent complete pull-down sustaining circuits (each pull-down sustaining circuit including an inverter circuit and a sustaining circuit) to achieve alternating control. Now, each pair of GOA units only needs two inverter circuits 471 to achieve alternating control of each GOA unit. This shared design significantly reduces the number of transistors in the inverter circuit 471, effectively reducing the overall layout area of ​​the GOA circuit 400, which is beneficial for achieving a narrower display panel bezel.

[0136] In some non-limiting embodiments, please continue to refer to Figure 9 Unlike the inverter circuit 471 in the aforementioned GOA circuit 400, Figure 9 In the process, the inverter circuits 471 of the nth-level GOA unit and the (n+1)th-level GOA unit respectively also include waveform adjustment modules, such as thin-film transistors T55, configured to adjust the waveforms of the third control node Sn in the nth-level GOA unit and the third control node Sn+1 in the (n+1)th-level GOA unit, so that they tend to be consistent, so that... Figure 9 The two adjacent GOA units can obtain the same inverter circuit 471 so that they can work together to achieve the pull-down maintenance of the first control nodes Qn and Qn+1.

[0137] Optionally, the waveform adjustment module is a thin-film transistor T55. The gate of T55 in the nth-level GOA unit is electrically connected to the first control node Qn+1, its first electrode is electrically connected to the third control node Sn, and its second electrode is connected to VSSQ; the gate of T55 in the (n+1)th-level GOA unit is electrically connected to the first control node Qn, its first electrode is electrically connected to the third control node Sn+1, and its second electrode is connected to VSSQ.

[0138] In some non-limiting embodiments, please continue to refer to Figure 9The pull-down sustaining circuit 470 of the nth level GOA unit and the pull-down sustaining circuit 470 of the (n+1)th level GOA unit also include a seventh thin film transistor T56, whose second terminal is electrically connected to its respective first low-level terminal V21 to receive a low-level signal VSSQ, and whose first terminal is electrically connected to the second control node Kn of the nth level GOA unit and the second control node Pn+1 of the (n+1)th level GOA unit.

[0139] The gates of the seventh thin-film transistors T56 of the two GOA units are both configured to receive the same pre-stage gate drive signal (such as the (n-4)th stage gate drive signal Gn-4) or its stage transmission signal (such as the (n-4)th stage transmission signal STn-4) of the nth stage GOA unit. Figure 9 This demonstrates the case where the gate of the seventh thin-film transistor T56 is configured to receive the (n-4)th stage transmission signal STn-4.

[0140] In this embodiment, since the seventh thin-film transistors T56 of two adjacent GOA units in the same pair of GOA units are controlled by the same signal simultaneously, their conduction and cutoff actions are synchronized. This makes the reset actions of the two second control nodes Kn and Pn+1 in each pair of GOA units consistent in time, maintaining the consistency of voltage stress on the TFT during the pull-down of two adjacent GOA units in each pair of GOA units, and improving display stability.

[0141] In some non-limiting embodiments, please continue to refer to Figure 9 Unlike the aforementioned second control circuit 420, in this embodiment, the control terminal P22 of the second control circuit 420 for the same pair of GOA units (provided by the gate of the thin film transistor T41) is configured to receive the same subsequent gate drive signal or its transmission signal of the (n+1)th stage GOA unit, such as the (n+6)th stage transmission signal STn+6 (that is, the transmission signal of the (n+6)th stage gate drive signal) shown in the figure.

[0142] In this embodiment, since the thin-film transistors T41 of two adjacent GOA units in the same pair of GOA units are controlled by the same signal simultaneously, their turn-on and turn-off actions are synchronized. This makes the reset actions of the two first control nodes Qn and Qn+1 in each pair of GOA units consistent in time, which further promotes the consistency of voltage stress on the TFT maintained by the pull-down of the two adjacent GOA units, thereby further improving the display stability.

[0143] Optionally, Figure 9In the GOA circuit 400 shown, taking the nth level GOA unit as an example, the input terminal I21 of the first control circuit 410 (provided by the first pole of T11) is electrically connected to its control terminal (specifically the gate of T11), and is configured to connect to the n-4th level transmission signal STn-4 (the transmission signal of the n-4th level gate drive signal, that is, the transmission signal of the previous level gate drive signal). With this setting, it is equivalent to using the previous level gate drive signal as the pull-up charging power supply of the first control node Qn, which simplifies the power supply routing design, eliminates the need for additional high-level power lines, helps reduce wiring complexity, and improves stability.

[0144] visible, Figure 9 The thin-film transistor T11 uses a diode connection (gate and first electrode shorted), resulting in a Vgs of 0V for this transistor. Since the threshold voltage (Vth) drift of a thin-film transistor mainly depends on the continuous gate bias stress (the larger Vgs, the more severe the drift), a constant Vgs of 0 means that the transistor is not subjected to any DC voltage stress. Therefore, its threshold voltage is unlikely to shift, resulting in higher long-term reliability and stability. However, at the same time, because it uses the cascaded signal of the previous stage gate drive signal as the pull-up charging power supply, the accumulated load caused by the cascaded connection leads to voltage loss, resulting in poor voltage transmission capability of the GOA circuit. With this voltage loss, the first control node Qn cannot charge to a stable ideal high level, thus limiting the driving force of this stage's GOA unit and reducing its load-carrying capacity.

[0145] In some other embodiments, the control terminal P21 of the first control circuit 410 can also be referred to. Figure 7 The embodiment shown is configured to receive the (n-4)th stage gate drive signal Gn-4.

[0146] Please see Figure 10 , Figure 10 This is a schematic diagram of another GOA circuit 400 provided in an embodiment of this application. Compared to Figure 9 At least the following differences exist: Taking the nth level GOA unit as an example, the input terminal I21 of the first control circuit 410 (provided by the first pole of T11) is configured to connect to the high-level signal VGH.

[0147] Compared to Figure 9 In other words, Figure 10Because the thin-film transistor T11 does not use a diode connection, its long-term reliability and stability are relatively poor. However, at the same time, because it uses an independent high-level power supply VGH directly as the pull-up charging power supply, it avoids the load accumulation effect on the cascaded signal path and eliminates the voltage loss caused by the previous stage transmission. Therefore, the voltage transmission capability of this GOA circuit is extremely strong. With a stable voltage supply, the first control node Qn can be charged to a stable ideal high level, thus giving this stage of GOA unit sufficient driving force and significantly improving its load-carrying capacity. This setting is equivalent to using an independent high-level power supply as the pull-up charging power supply for the first control node Qn, rather than the previous stage gate drive signal or its cascade transmission signal, avoiding the voltage loss that may be caused by the previous stage signal under heavy load, and ensuring that the first control node Qn can be charged to a stable high level.

[0148] In some other embodiments, the control terminal P21 of the first control circuit 410 can also be referred to. Figure 8 The embodiment shown is configured to receive the (n-4)th stage gate drive signal Gn-4.

[0149] Please see Figure 11 , Figure 11 This is a schematic diagram of another GOA circuit 400 provided in an embodiment of this application. Compared to Figure 10 At least the following differences exist: Taking the nth-stage GOA unit as an example, the input terminal I21 of the first control circuit 410 (provided by the first pole of T11) is configured to receive the (n-4)th-stage gate drive signal Gn-4 (i.e., the gate drive signal preceding the nth-stage gate drive signal); the control terminal P21 of the first control circuit 410 (provided by the gate of T11) is configured to receive the (n-4)th-stage transmission signal STn-4 (the transmission signal of the (n-4)th-stage gate drive signal, i.e., the transmission signal preceding the gate drive signal). It can be seen that... Figure 11 The thin-film transistor T11 also uses and Figure 9 Similar diode connections offer higher reliability and stability over long-term operation, but because they use the gate drive signal or cascaded signal as the pull-up charging power supply, the accumulated load from the cascaded connection causes voltage loss, resulting in poor voltage transmission capability. In comparison, Figure 9 Using the stage transmission signal STn-4 as the input signal of T11, compared to Figure 11 It exhibits improved voltage transmission capability: the stage transmission signal STn-4 has a shorter trace and less voltage loss compared to the gate drive signal Gn-4. Consequently, the charging upper limit of the first control node Qn is higher, resulting in better load-carrying capacity for this stage's GOA unit.

[0150] In addition, it is different from Figure 9 , Figure 10The thin-film transistor T55 in the inverter circuit 471, Figure 11 In the inverter circuits 471 of the nth and (n+1)th GOA units, the gates of the thin-film transistors T55 are configured to receive the same gate drive signal as the stage transmission signal, specifically the (n-4)th stage transmission signal STn-4, which is the stage transmission signal of the (n-4)th stage gate drive signal Gn-4, and not... Figure 9 , Figure 10 The first control nodes are connected to each other. This configuration causes a phase difference between the third control nodes Sn and Sn+1, which in turn causes a phase difference in the waveforms of the first control nodes Qn and Qn+1, consistent with the first control nodes Qn and Qn+1 in the aforementioned embodiment of the non-shared inverter circuit.

[0151] It should be noted that, taking the nth level GOA unit as an example, the above embodiment uses the control node Qn, which controls the opening or closing of the GOA unit, as the first control node for illustration, and... Figures 4 to 8 The pull-down sustaining circuit maintains the low level of the first control node Qn and the gate drive node Xn. Figures 9 to 11 The pull-down sustaining circuit maintains the first control node Qn, the gate drive node Xn, and the cascade node Yn at a low level. In some other embodiments, the first control node is not limited to the aforementioned control node Qn; the aforementioned gate drive node Xn and cascade node Yn can also serve as the first control node. Furthermore, the nodes maintained by the pull-down sustaining circuit are not limited to the above embodiments and can be more or fewer. Theoretically, any node maintained low by the pull-down sustaining circuit can serve as the first control node.

[0152] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application. When one element is connected to another element, the connection can be direct or indirect.

[0153] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0154] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, It includes at least one cascade group, each cascade group comprising cascaded multi-level GOA units, each level of the GOA unit comprising: First control node; A pull-down sustaining circuit includes an input terminal, an output terminal, a control terminal, a high-level terminal, a low-level terminal, and a second control node. The input terminal and the output terminal are both electrically connected to the first control node. The pull-down sustaining circuit is configured as follows: During the display phase, when the first control node is at a low level, in response to the control terminal being at a high level, the high-level signal of the high-level terminal is used to control the second control node to be at a high level, so that the second control node uses the low-level signal of the low-level terminal to maintain the first control node at a low level; During the power-off discharge phase, in response to the discharge rate of the control terminal being less than the discharge rate of the high-level terminal, the second control node is connected to the high-level terminal until the second control node discharges to a low level.

2. The gate driving circuit according to claim 1, characterized in that, The pull-down sustaining circuit includes: The inverter circuit, electrically connected to the input terminal, the control terminal, the high-level terminal, the low-level terminal, and the second control node respectively, is configured as follows: During the display phase, based on the potentials of the control terminal and the input terminal, one of the high-level signal and the low-level signal is selectively used to control the level of the second control node, so that the level of the second control node is opposite to the level of the first control node; during the power-off discharge phase, in response to the discharge rate of the control terminal being less than the discharge rate of the high-level terminal, the second control node is connected to the high-level terminal until the second control node discharges to a low level; A first sustaining circuit, electrically connected to the second control node, the output terminal, and the low-level terminal respectively, is configured to: during the display phase, in response to the second control node being at a high level, conduct the first control node and the low-level terminal, thereby maintaining the first control node at a low level.

3. The gate driving circuit as described in claim 2, characterized in that, The pull-down sustaining circuit also includes a third control node; The inverter circuit includes: A first thin-film transistor, whose gate is electrically connected to the control terminal, whose first electrode is electrically connected to the high-level terminal, and whose second electrode is electrically connected to the third control node; The second thin-film transistor has its gate electrically connected to the third control node, its first electrode electrically connected to the first electrode of the first thin-film transistor, and its second electrode electrically connected to the second control node. The third thin-film transistor has its gate electrically connected to the input terminal, its first electrode electrically connected to the third control node, and its second electrode electrically connected to the low-level terminal. The fourth thin-film transistor has its gate electrically connected to the input terminal, its first electrode electrically connected to the second control node, and its second electrode electrically connected to the low-level terminal.

4. The gate driving circuit as described in claim 2, characterized in that, The GOA unit also includes: The first control circuit and the second control circuit each include a control terminal, an input terminal and an output terminal. Their output terminals are electrically connected to the first control node. The first control circuit and the second control circuit are configured to turn on their input terminals and output terminals in response to their control terminals being at a high level. The control terminal of the first control circuit is configured to receive the front gate drive signal or its stage transmission signal of the GOA unit, and the control terminal of the second control circuit is configured to receive the rear gate drive signal or its stage transmission signal of the GOA unit. The input terminal of the first control circuit is electrically connected to its control terminal, and the input terminal of the second control circuit is configured to receive a low-level signal; or, The input terminal of the first control circuit is configured to receive a first DC voltage signal and the input terminal of the second control circuit is configured to receive a second DC voltage signal, wherein the first DC voltage signal and the second DC voltage signal are a pair of voltage signals with opposite levels.

5. The gate driving circuit as described in claim 4, characterized in that, The level of the second DC voltage signal can be switched with the level of the first DC voltage signal.

6. The gate driving circuit as described in claim 4, characterized in that, The first control circuit includes a fifth thin-film transistor, the gate of which is used as the control terminal of the first control circuit, the first terminal of which is used as the input terminal of the first control circuit, and the second terminal of which is used as the output terminal of the first control circuit. The second control circuit includes a sixth thin-film transistor, the gate of which serves as the control terminal of the second control circuit, the first terminal of which serves as the output terminal of the second control circuit, and the second terminal of which serves as the input terminal of the second control circuit.

7. The gate driving circuit according to any one of claims 1 to 6, characterized in that, Each GOA unit includes two pull-down sustaining circuits, namely a first pull-down sustaining circuit and a second pull-down sustaining circuit; The control terminal of the first pull-down sustaining circuit is configured to receive a first control signal, and the control terminal of the second pull-down sustaining circuit is configured to receive a second control signal; the first control signal and the second control signal are a pair of AC signals with opposite phases and alternating high levels.

8. The gate driving circuit according to any one of claims 4 to 6, characterized in that, The at least one cascaded group includes multiple pairs of GOA units, and each pair of GOA units includes two adjacent GOA units, namely a first GOA unit and a second GOA unit; The pull-down sustaining circuits of the first GOA unit and the second GOA unit each include a second sustaining circuit; the second sustaining circuit of the first GOA unit is electrically connected to the first control node of the first GOA unit, the second control node of the second GOA unit, and the low-level terminal, and the second sustaining circuit of the second GOA unit is electrically connected to the first control node of the second GOA unit, the second control node of the first GOA unit, and the low-level terminal. The second sustaining circuit in the first GOA unit is configured to: during the display phase, when the second control node of the second GOA unit is at a high level, conduct the first control node of the first GOA unit and the low-level terminal; The second sustaining circuit in the second GOA unit is configured to: during the display phase, when the second control node of the first GOA unit is at a high level, conduct the first control node of the second GOA unit and the low-level terminal; The control terminal of the pull-down sustaining circuit of the first GOA unit is configured to receive a first control signal, and the control terminal of the pull-down sustaining circuit of the second GOA unit is configured to receive a second control signal; the first control signal and the second control signal are a pair of AC signals with opposite phases and alternating high levels.

9. The gate driving circuit as described in claim 8, characterized in that, The first GOA unit is the pre-stage of the second GOA unit. The pull-down sustaining circuit also includes a seventh thin-film transistor, whose first electrode is electrically connected to the second control node and whose second electrode is electrically connected to the low-level terminal. The gates of the seventh thin-film transistors of the first GOA unit and the second GOA unit are both configured to be connected to the same front-stage gate drive signal or its stage transmission signal of the first GOA unit.

10. The gate driving circuit as described in claim 9, characterized in that, The control terminals of the second control circuits of the first GOA unit and the second GOA unit are both configured to be connected to the same subsequent gate drive signal or its transmission signal of the second GOA unit.

11. The gate driving circuit as described in claim 3, characterized in that, The inverter circuit also includes a capacitor electrically connected between the third control node and the second control node.

12. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 11.

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