Display pixels and display devices comprising display pixels

Abstract

A display pixel and a display device are provided. The display pixel includes a shift register including a plurality of serial bit cells; an independent bit cell; a source selection multiplexer configured to generate a pulse width modulation (PWM) signal based on a first output signal from the shift register and a second output signal from the independent bit cell; and a light emitting circuit configured to operate based on the PWM signal. During a first period in which the source selection multiplexer activates the second output signal as the PWM signal, the shift register can be configured to perform a bit cyclic shift operation for the plurality of serial bit cells.

Description

Cross-reference to related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0054019 filed with the Korean Intellectual Property Office on April 24, 2025 and Korean Patent Application No. 10-2025-0121198 filed with the Korean Intellectual Property Office on August 28, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display pixel, and to a semiconductor display including the display pixel. More specifically, this disclosure relates to a display pixel operating based on pulse width modulation. Background Technology

[0003] Display pixels may include light-emitting diodes (LEDs) that generate light in response to a pulse-width modulation (PWM) signal. The PWM signal determines the duration for which the LED emits light.

[0004] The logic level of the PWM signal can be determined based on multiple pixel drive bits corresponding to different durations. For example, the PWM signal can be divided into multiple bit emit cycles, and the logic level of the PWM signal during each bit emit cycle can be determined based on different pixel drive bits.

[0005] The order of the multiple bit emission cycles included in the PWM signal can be the same across multiple frames. Therefore, depending on the arrangement of the logic high (or low) periods in the PWM signal of the previous and next frames, a pseudo-contour effect may occur, making the displayed pixels appear to be temporarily brighter or darker compared to changes in multiple pixel drive bits. Summary of the Invention

[0006] A display pixel according to an embodiment of the present disclosure may include: a shift register including a plurality of serial bit units; independent bit units; a source select multiplexer configured to generate a pulse width modulation (PWM) signal based on a first output signal from the shift register and a second output signal from the independent bit units; and a light-emitting circuit configured to operate based on the PWM signal, wherein, during a first time period during which the source select multiplexer activates the second output signal as the PWM signal, the shift register is configured to perform a bit rotation operation on the plurality of serial bit units.

[0007] A display device according to embodiments of the present disclosure may include: a column driver configured to output a plurality of bits; a display pixel configured to store a plurality of bits; and a row driver configured to: control the display pixel to perform a first emission operation for a first subset of the plurality of bits during a first segmented driving cycle; and control the display pixel to perform a second emission operation for a second subset of the plurality of bits during a second segmented driving cycle, the second segmented driving cycle being included in the same frame cycle as the first segmented driving cycle, wherein the first subset and the second subset include two or more common bits.

[0008] A display pixel according to an embodiment of the present disclosure may include: a shift register configured to store a first bit and a second bit; an independent bit unit configured to store a third bit; a source select multiplexer including a first input terminal connected to the shift register, a second input terminal connected to the independent bit unit, and an output terminal for outputting a pulse width modulation (PWM) signal; and a light-emitting circuit configured to emit light based on the PWM signal, wherein: the source select multiplexer is configured to determine the logic level of the PWM signal based on the first bit using a first number; the source select multiplexer is configured to determine the logic level of the PWM signal based on the second bit using a second number; and the first number is different from the second number. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0010] Figure 2 To show in more detail Figure 1 A block diagram showing the configuration of the display pixels.

[0011] Figure 3 This is a timing diagram showing the configuration of the PWM signal according to the comparative example.

[0012] Figure 4 It shows the basis Figure 3 A diagram illustrating the pseudo-contour effect of an embodiment.

[0013] Figure 5 This is a circuit diagram illustrating the configuration of display pixels according to an embodiment of the present disclosure.

[0014] Figure 6 To show in more detail Figure 5 A diagram showing the operation of displaying pixels.

[0015] Figure 7 This is an exemplary timing diagram showing how a row driver drives display pixels during a light emission cycle according to an embodiment of the present disclosure.

[0016] Figure 8 and Figure 9 It shows the basis in more detail. Figure 7 A timing diagram of the operation of the display device in an embodiment.

[0017] Figure 10 To present the reference in a more concise form Figures 7 to 9 A table describing the driving methods.

[0018] Figure 11 It shows the basis Figures 7 to 10 A graph showing the magnitude of the pseudo-contour effect in the embodiment.

[0019] Figures 12 to 14 This is a table illustrating a method for driving display pixels according to an embodiment.

[0020] Figure 15 This is a timing diagram illustrating a frame period implemented according to an embodiment.

[0021] Figure 16 This is a block diagram illustrating a display system according to an embodiment of the present disclosure.

[0022] Figure 17 This is an exemplary illustration according to an embodiment. Figure 16 A diagram showing the configuration of the pixel-driven logic table.

[0023] Figure 18 This is an exemplary illustration according to an embodiment. Figure 16 A diagram showing the configuration of the pixel-driven logic table. Detailed Implementation

[0024] The embodiments of this disclosure will be described clearly and in detail below, to the extent that those skilled in the art can readily implement this disclosure.

[0025] The components described below can be implemented as various types of software (such as firmware, applications, etc.) or as various types of hardware (such as circuits, electronic circuits, processors, etc.). However, the scope of this disclosure is not limited thereto, and the components described below can be implemented as a combination of software and hardware.

[0026] This disclosure relates to a display pixel with minimized pseudo-contour effect and a display device including the display pixel.

[0027] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure. The display device 100 may include a display pixel array 110, a column driver 120, a row driver 130, and a timing control circuit 140.

[0028] The display pixel array 110 may include a plurality of display pixels PX. The plurality of display pixels PX may be arranged in a matrix along the row and column directions. However, the scope of this disclosure is not limited thereto, and the plurality of display pixels PX may be arranged in a zigzag pattern.

[0029] Each of the multiple display pixels PX can be connected to one or more data lines DL and one or more control lines CL. For example, display pixels PX arranged in the same row of display pixels can share one or more control lines CL, and display pixels PX arranged in the same column of display pixels can share one or more data lines DL.

[0030] The column driver 120 can control multiple data lines DL. For example, the column driver 120 can provide different pixel drive data (hereinafter referred to as "PDD") to multiple display pixel columns via multiple data lines DL.

[0031] The line driver 130 can control multiple control lines CL. For example, the line driver 130 can provide different pixel control signals (hereinafter referred to as "CTRL") to multiple display pixels via multiple control lines CL.

[0032] The line driver 130 can control multiple display pixels PXs on a per-display-pixel-row basis. For example, the line driver 130 can control the logic level of a pixel control signal CTRL provided to a display-pixel-row, thereby controlling the operation of the display pixels PXs included in the corresponding display-pixel-row. In a more detailed example, by controlling the pixel control signal CTRL provided to a display-pixel-row, the line driver 130 can control the display pixels PXs included in the display-pixel-row to receive pixel drive data PDD from one or more data lines DL, and can control the display pixels PXs included in the display-pixel-row to generate light based on the pixel drive data PDD.

[0033] Timing control circuitry 140 can receive frame data D_FRM from an external device (e.g., CPU or GPU). Timing control circuitry 140 can provide frame data D_FRM to column driver 120. Column driver 120 can divide the frame data D_FRM received from timing control circuitry 140 into pixel drive data PDD units and provide them to display pixel array 110.

[0034] The timing control circuit 140 can control the overall operation of the display device 100. For example, the timing control circuit 140 can control the operating timing of the column driver 120 and the row driver 130.

[0035] Figure 2 To show in more detail Figure 1 A block diagram showing the configuration of the display pixels. (Refer to...) Figure 1 and Figure 2 The display pixel PX may include a PWM control circuit PCC and a light-emitting circuit LEC.

[0036] The PWM control circuit PCC can receive pixel drive data PDD through one or more data lines DL and multiple pixel control signals CTRL through one or more control lines CL. The PWM control circuit PCC can generate a PWM signal SPWM corresponding to the pixel drive data PDD in response to the multiple pixel control signals CTRL.

[0037] The PWM signal SPWM may include multiple bit emit cycles (hereinafter referred to as "BEMs") having logic levels corresponding to the values ​​of the pixel drive data PDD. The PWM control circuit PCC may determine the logic levels of the multiple bit emit cycles BEMs based on the bits included in the pixel drive data PDD.

[0038] In an embodiment, each bit included in the pixel-driven data PDD may be referred to as a 'pixel-driven bit'. However, the scope of this disclosure is not limited to these terms.

[0039] The duty cycle (e.g., duty rate) of the PWM signal SPWM can be determined based on the amplitude of the pixel drive data PDD. For example, the larger the amplitude of the pixel drive data PDD, the more of a percentage of the PWM control circuit PCC can generate the PWM signal SPWM with a logic high duration; conversely, the smaller the amplitude of the pixel drive data PDD, the less of a percentage of the PWM control circuit PCC can generate the PWM signal SPWM with a logic high duration. However, the scope of this disclosure is not limited thereto.

[0040] The light-emitting circuit (LEC) can operate in response to a PWM signal (SPWM). For example, the LEC may include a light-emitting diode configured to be turned on or off based on a logic level of the PWM signal (SPWM).

[0041] Figure 3 This shows the timing diagram configuration for the PWM signal based on the comparison example. (Refer to...) Figures 1 to 3 The presence or absence of light emission from the LED circuit during the emission period TEM can be determined based on the PWM signal SPWM. The emission period TEM may include multiple bit emission periods (BEMs). Each of the multiple bit emission periods (BEMs) may correspond to a different bit included in the pixel drive data PDD and may have a different duration. For simplicity, an example in which the emission period TEM includes eight bit emission period (BEMs) is described below as a representative example. However, the scope of this disclosure is not limited thereto, and the emission period TEM may include a number of bit emission period (BEMs) corresponding to the code length of the pixel drive data PDD. For example, if the code length of the pixel drive data PDD is 4 bits, the emission period TEM may include four bit emission period (BEMs); if the code length of the pixel drive data PDD is 10 bits, the emission period TEM may include ten bit emission period (BEMs).

[0042] The emission period TEM may include the first emission period BEM1 to the eighth emission period BEM8. The first emission period BEM1 to the eighth emission period BEM8 may be consecutive to each other. For example, the start time points of the first emission period BEM1 to the eighth emission period BEM8 may correspond to time points tA to tH, respectively, and the end time points of the first emission period BEM1 to the eighth emission period BEM8 may correspond to time points tB to tI, respectively. However, the scope of this disclosure is not limited thereto. For example, the order of the first emission period BEM1 to the eighth emission period BEM8 may be... Figure 3 The different determinations shown (e.g., in reverse order) are as follows.

[0043] The durations of each of the first transmission cycle (BEM1) to the eighth transmission cycle (BEM8) can form a geometric sequence with a common ratio of 2. For example, the duration of the first transmission cycle (BEM1) can be '1UT', and the duration of the second transmission cycle (BEM2) can be '2UT'. Thus, the duration of the eighth transmission cycle (BEM8) can be '128UT'. '1UT' is merely a unit used to describe the relative lengths of multiple transmission cycles (BEMs), and the scope of this disclosure is not limited to a specific duration of '1UT'.

[0044] Each of the first transmit cycle BEM1 to the eighth transmit cycle BEM8 may correspond to a different bit included in the pixel drive data PDD. For example, the first transmit cycle BEM1 may correspond to the least significant bit (LSB) of the pixel drive data PDD, and the eighth transmit cycle BEM8 may correspond to the most significant bit (MSB) of the pixel drive data PDD.

[0045] The PWM control circuit PCC can determine the logic level of the PWM signal SPWM during each period from the first transmit cycle BEM1 to the eighth transmit cycle BEM8 based on the corresponding bits of the pixel drive data PDD. For example, the PWM control circuit PCC can determine the logic level of the PWM signal SPWM during the first transmit cycle BEM1 based on the LSB of the pixel drive data PDD, and can determine the logic level of the PWM signal SPWM during the eighth transmit cycle BEM8 based on the MSB of the pixel drive data PDD.

[0046] Thus, the PWM control circuit PCC can determine the logic level of the PWM signal SPWM in units of bit emission periods (BEM) based on the value of the pixel drive data PDD. For example, if the value of the pixel drive data PDD is 126 (e.g., binary 01111110), the PWM control circuit PCC can determine that the logic level of the PWM signal SPWM is logic high during the time period between time point tB and time point tH, as shown by the first curve GRPb. When the value of the pixel drive data PDD is 127 (e.g., binary 01111111), the PWM control circuit PCC can determine that the logic level of the PWM signal SPWM is logic high during the time period between time point tA and time point tH, as shown by the second curve GRPb. When the value of the pixel drive data PDD is 128 (e.g., binary 10000000), the PWM control circuit PCC can determine that the logic level of the PWM signal SPWM is logic high during the time period between time point tH and time point tI, as shown by the third curve GRPc.

[0047] Figure 4 It shows the basis Figure 3 A diagram illustrating the pseudo-contour effect in an embodiment. (Refer to...) Figures 1 to 4 The column driver 120 and the row driver 130 can drive a display pixel PX within multiple frame periods (FRM). For example, the column driver 120 and the row driver 130 can drive a display pixel PX within the first frame period (FRMa) to the third frame period (FRMc). The first frame period (FRMa) to the third frame period (FRMc) can correspond to different and consecutive frames.

[0048] The first frame period FRMa to the third frame period FRMc may each include a first emission period TEMA to a third emission period TEMc. The column driver 120 and the row driver 130 may drive the display pixel PX based on different pixel driving data PDDs during the first emission period TEMA to the third emission period TEMc. For example, the column driver 120 may provide pixel driving data PDD with a value of '126' to the display pixel PX in the first frame period FRMa; may provide pixel driving data PDD with a value of '127' to the display pixel PX in the second frame period FRMb; and may provide pixel driving data PDD with a value of '128' to the display pixel PX in the third frame period FRMc.

[0049] In response to the control of the line driver 130, the PWM control circuit PCC included in the display pixel PX can be configured as described above. Figure 3The PWM signal SPWM is generated in the manner described. For example, the PWM signal SPWM generated by the PWM control circuit PCC may have a waveform similar to the first curve GRPb during the first light-emitting period TEMA, a waveform similar to the second curve GRPb during the second light-emitting period TEMb, and a waveform similar to the third curve GRPc during the third light-emitting period TEMc. In this case, the relative ratio of the duty cycles of the PWM signal SPWM during the first light-emitting period TEMA to the third light-emitting period TEMc may be '126:127:128'. Therefore, the ratio of the on-time of the light-emitting diodes included in the light-emitting circuit LEC during the first light-emitting period TEMA to the third light-emitting period TEMc may also be '126:127:128'. In this case, the brightness of the light-emitting circuit LEC perceived by the human eye can be expected to be '126:127:128'.

[0050] However, the brightness of the light-emitting circuit LEC as perceived by the human eye can be determined to be approximately the result of comprehensively considering the brightness of the light-emitting circuit LEC within a specific time period. Therefore, when transitioning from the second frame period FRMb to the third frame period FRMc, the brightness of the light-emitting circuit LEC as perceived by the human eye may be incorrect. For example, as the light-emitting circuit LEC emits intense light during the early stages of the first light-emitting period TEA and the second light-emitting period TEMb, and also emits intense light during the later stages of the third light-emitting period TEMc, the brightness of the light-emitting circuit LEC as perceived by the human eye may temporarily and significantly decrease during the early stages of the third light-emitting period TEMc. In this case, a pseudo-contour effect may occur, in which the position corresponding to the display pixel PX on the display pixel array 110 appears to be the boundary of an object, which may lead to a deterioration in the quality of the image output by the display device 100. In addition, according to the similarity principle, based on the value of the pixel driving data PDD corresponding to each of the first light-emitting period TEA to the third light-emitting period TEMc, a phenomenon may occur in which the brightness of the light-emitting circuit LEC as perceived by the human eye temporarily and significantly increases.

[0051] The difference between the perceived brightness of the light-emitting circuit (LEC) and the desired brightness of the LEC can be determined by the similarity between the arrangement of the bit emission period (BEM) and the logic high values ​​of the PWM signal SPWM in the previous and next frames. For example, if the logic low period of the PWM signal SPWM is in the later stage of the emission period TEM, like the second frame period FRMb, and then the logic low period of the PWM signal SPWM is concentrated in the early stage of the emission period TEM, like the third frame period FRMc, then the difference between the perceived brightness of the LEC and the desired brightness of the LEC can be greater as the PWM signal SPWM remains at a logic low for a longer period.

[0052] In other words, depending on the length and arrangement of the bit emission period (BEM), the brightness of the light-emitting circuit (LEC) perceived by the human eye may be suboptimal. Specifically, this problem may be more pronounced due to the varying duration of each bit's holding time in the logic level of the PWM signal SPWM.

[0053] According to embodiments of this disclosure, each bit emission cycle (BEM) can be divided into two or more. In this case, the logic level of the PWM signal SPWM can be reduced by the length of the time each bit is held. Therefore, according to embodiments of this disclosure, errors in the brightness of the light-emitting circuit (LEC) perceived by the human eye can be minimized.

[0054] Figure 5 This is a circuit diagram illustrating the configuration of display pixels according to an embodiment of the present disclosure. (Refer to...) Figures 1 to 5 The display pixel PX may include a PWM control circuit PCC and a light-emitting circuit LEC. Below, as a representative example, the configuration of the PWM control circuit PCC that receives 8 bits of pixel drive data PDD in each frame period will be described. However, the scope of this disclosure is not limited thereto.

[0055] The PWM control circuit PCC may include a feedback multiplexer MUX_FB, a shift register SR, an independent bit cell CIDP, and a source selection multiplexer MUX_SRC.

[0056] The pixel-driven data PDD may include shift register data D_SR and independent bit cell data D_CIDP. The shift register data D_SR may include the LSB to the second most significant bit (e.g., the bit with the second largest bit value) of the pixel-driven data PDD. The independent bit cell data D_CIDP may include the MSB of the pixel-driven data PDD. However, the scope of this disclosure is not limited thereto. For example, the independent bit cell data D_CIDP may include the second most significant bit of the pixel-driven data PDD, while the shift register data D_SR may include the remaining bits of the pixel-driven data PDD. However, for the sake of brevity in the following explanation, it is assumed that the independent bit cell data D_CIDP includes the MSB of the pixel-driven data PDD.

[0057] In this embodiment, the PWM control circuit PCC can receive the shift register data D_SR sequentially, one bit at a time.

[0058] In this embodiment, the PWM control circuit PCC can receive shift register data D_SR and independent bit cell data D_CIDP via different data lines DL. For example, the PWM control circuit PCC can receive shift register data D_SR and independent bit cell data D_CIDP from the column driver 120 via two data lines DL. However, the scope of this disclosure is not limited thereto. For example, the PWM control circuit PCC can receive shift register data D_SR and independent bit cell data D_CIDP from the column driver 120 in a time-division manner via a single data line DL.

[0059] The pixel control signal CTRL may include one or more shift register control signals CS_SR, feedback enable signal FB_EN, independent bit cell control signal CS_CIDP, source select signal SEL_SRC, and PWN enable signal PWN_EN.

[0060] The first input terminal of the feedback multiplexer MUX_FB can receive shift register data D_SR. The output terminal of the feedback multiplexer MUX_FB can be connected to the first node NA. The first node NA can be connected to the input terminal of the shift register SR. The second input terminal of the feedback multiplexer MUX_FB can be connected to the second node NB. The second node NB can be connected to the output terminal of the shift register SR.

[0061] The feedback multiplexer MUX_FB operates in response to the feedback enable signal FB_EN. For example, when the logic level of the feedback enable signal FB_EN is low, the feedback multiplexer MUX_FB can determine that the logic level of the first node NA is the same as the logic level of the first input terminal. The feedback multiplexer MUX_FB can determine that the logic level of the first node NA is the same as the logic level of the second input terminal (or the second node NB) when the logic level of the feedback enable signal FB_EN is high.

[0062] The shift register SR can be connected between the first node NA and the second node NB. The shift register SR may include multiple bit units C connected in series between the first node NA and the second node NB. For example, the shift register SR may include first bit units C1 to seventh bit units C7 and a feedback bit unit CFB. The feedback bit unit CFB may be connected to the first node NA, and the first bit unit C1 may be connected to the second node NB.

[0063] For a more concise explanation, the following description uses an embodiment where the feedback bit unit CFB is placed between the feedback multiplexer MUX_FB and the seventh bit unit C7 as a representative example. However, the scope of this disclosure is not limited thereto. For example, the feedback bit unit CFB may be placed between the first bit unit C1 and the source selection multiplexer MUX_SRC.

[0064] An independent bit cell CIDP may include an eighth bit cell C8. That is, an independent bit cell CIDP may be implemented to store 1 bit. However, the scope of this disclosure is not limited thereto. For example, an independent bit cell CIDP may include more than one bit cell.

[0065] Each of the first unit C1 through the eighth unit C8 and the feedback bit unit CFB can be implemented as a latch. For example, the first unit C1 through the seventh unit C7 and the feedback bit unit CFB can be implemented as latches configured to change the stored data value in response to the first shift register control signal CS_SR1 through the eighth shift register control signal CS_SR8. The eighth unit C8 can be implemented as a latch configured to change the stored data value in response to the independent bit unit control signal CS_CIDP. However, the scope of this disclosure is not limited thereto, and each of the first unit C1 through the eighth unit C8 and the feedback bit unit CFB can be implemented as any type of data storage element, such as a flip-flop. For example, if each of the first unit C1 through the seventh unit C7 and the feedback bit unit CFB is implemented as a flip-flop, then the first unit C1 through the seventh unit C7 and the feedback bit unit CFB can be implemented to share a single shift register control signal CS_SR.

[0066] In embodiments, each of the first unit C1 through the seventh unit C7 may be referred to as a serial bit unit or a serial latch. The eighth unit C8 may be referred to as an independent bit unit or an independent latch. However, the scope of this disclosure is not limited to these terms.

[0067] In an embodiment, the feedback bit unit CFB may operate in response to the eighth shift register control signal CS_SR8. From this perspective, the eighth shift register control signal CS_SR8 may also be referred to as the shift register feedback control signal CS_FB. However, the scope of this disclosure is not limited to these terms.

[0068] The shift register SR can sequentially receive each bit of the shift register data D_SR via the feedback multiplexer MUX_FB. For example, the shift register SR can sequentially receive the shift register data D_SR one bit at a time in response to the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8, and store it in the first bit unit C1 to the seventh bit unit C7 and the feedback bit unit CFB.

[0069] Independent bit cells (CIDPs) can directly receive independent bit cell data (D_CIDP) via the data line DL. For example, the eighth bit cell (C8) can receive and store independent bit cell data (D_CIDP) in response to the independent bit cell control signal CS_CIDP.

[0070] The logic level of the output signal of the shift register SR corresponds to a single bit stored in the first bit unit C1. The logic level of the output signal of the independent bit unit CIDP corresponds to a single bit stored in the eighth bit unit C8.

[0071] In this embodiment, the shift register SR can perform a cyclic bit shift operation on bits 1 through 7 in response to the control of the row driver 130. For example, in response to the first shift register control signal CS_SR1 through the eighth shift register control signal CS_SR8, the shift register SR can move bits stored in bits 2 through 7 to bits 1 through 6 respectively to bits 1 through 6, and can move bits stored in the feedback bit unit CFB to bits 7, and can copy bits stored in bits 1 to the feedback bit unit CFB. Therefore, bits stored in bits 1 through 7 can be cyclically shifted, and the feedback bit unit CFB can store the same bits as bits 1.

[0072] In an embodiment, the shift register SR can perform a full rotation operation on bits 1 through 7 in response to control of the row driver 130. For example, the shift register SR can repeatedly perform a bit rotation operation in response to first shift register control signals CS_SR1 through eighth shift register control signals CS_SR8, the number of repetitions being the same as the number of serial bit units (e.g., bits 1 through 7) included in the shift register SR. For a more detailed example, the shift register SR can perform seven bit rotation operations. That is, a full rotation operation can refer to a 7-bit bit rotation operation.

[0073] The first input terminal of the source selection multiplexer MUX_SRC can be connected to the second node NB (e.g., the first unit C1). That is, the first input terminal of the source selection multiplexer MUX_SRC can receive the output signal from the shift register SR.

[0074] The second input terminal of the source selection multiplexer MUX_SRC can be connected to the eighth bit unit C8. That is, the second input terminal of the source selection multiplexer MUX_SRC can receive the output signal from the independent bit unit CIDP.

[0075] The output terminal of the source selection multiplexer MUX_SRC can output a PWM signal SPWM. The source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the logic level of the first input terminal and the logic level of the second input terminal.

[0076] More specifically, the source selection multiplexer MUX_SRC can operate in response to the source selection signal SEL_SRC. For example, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the bit stored in the first bit unit C1 when the logic level of the source selection signal SEL_SRC is logic low. The source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the bit stored in the eighth bit unit C8 when the logic level of the source selection signal SEL_SRC is logic high.

[0077] In this embodiment, while performing a complete cyclic shift operation on bit units C1 through C7, the bits stored in bit unit C1 can be changed sequentially. In this case, the bits used to determine the logic level of the PWM signal SPWM can be changed sequentially.

[0078] In this way, the row driver 130 can control multiple pixel control signals CTRL so that the source selection multiplexer MUX_SRC generates a PWM signal SPWM.

[0079] According to embodiments of this disclosure, the Independent Bit Cell (CIDP) can be physically separated from the shift register (SR). In this case, the row driver 130 can (e.g., regardless of the order of other bit emit cycles (BEMs)) freely determine the time period for determining the logic level of the bit-based PWM signal SPWM stored in the Independent Bit Cell (CIDP). For example, the row driver 130 can divide the bit emit cycle (BEM) corresponding to the bits stored in the Independent Bit Cell (CIDP) into multiple sub-bit emit cycles (hereinafter referred to as "SUB_BEM"). That is, the row driver 130 can divide the eighth bit emit cycle (BEM8) into two or more sub-bit emit cycles. For a more detailed example, the row driver 130 can divide the eighth bit emit cycle (BEM8) in various ways (such as two '64UT', four '32UT', eight '16UT', etc.). Therefore, during one emission cycle (TEM), the source selection multiplexer (MUX_SRC) determines the logic level of the bit-based PWM signal SPWM stored in the Independent Bit Cell (CIDP) two or more times. However, the scope of this disclosure is not limited thereto, and the row driver 130 may not divide the bit emission period (BEM) corresponding to the bits stored in the independent bit cell (CIDP).

[0080] According to embodiments of this disclosure, the row driver 130 can divide a bit-emit cycle BEM for one or more bits stored in the shift register SR into multiple sub-bit-emit cycles SUB_BEM. For example, the row driver 130 can divide the seventh bit-emit cycle BEM7 into two or more sub-bit-emit cycles SUB_BEM. More specifically, the row driver 130 can divide the seventh bit-emit cycle BEM7 in various ways (such as two '32UT', four '16UT', eight '8UT', etc.). Therefore, during one emission cycle TEM, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the specific position stored in the shift register SR two or more times. (Refer to below) Figure 6 A more detailed description of the specific way to divide a bit emit cycle (BEM) for one or more bits stored in the shift register SR into multiple sub-bit emit cycles.

[0081] Therefore, according to embodiments of this disclosure, any bit emission period (BEM) included in a single emission period (TEM) can be divided into two or more sub-bit emission periods (SUB_BEM). In this case, the pseudo-contour effect caused by the length of the bit emission period (BEM) can be minimized, and the image quality produced by the display device 100 can be improved.

[0082] The light-emitting circuit LEC may include a PWM gate GT_PWM, a first driving transistor DT1, a second driving transistor DT2, and a light-emitting diode ED.

[0083] The PWM gate GT_PWM can gate the PWM signal SPWM in response to the PWM enable signal PWM_EN. For example, in response to the PWM enable signal PWM_EN, the PWM gate GT_PWM can generate a gated PWM signal SPWMgtd by gated the PWM signal SPWM.

[0084] The first driving transistor DT1 and the second driving transistor DT2 can be connected in series between the power supply voltage VDD and the light-emitting diode ED. The light-emitting diode ED can be connected to the ground voltage VSS. The gate terminal of the first driving transistor DT1 can receive the gated PWM signal SPWMgtd. The gate terminal of the second driving transistor DT2 can receive the bias voltage VBIAS.

[0085] The first driving transistor DT1 can supply the power supply voltage VDD to the second driving transistor DT2 during the period when the gated PWM signal SPWMgtd is logic low. In this case, current can be supplied to the light-emitting diode ED via the second driving transistor DT2, and the light-emitting diode ED can be turned on (e.g., generating light).

[0086] The first driving transistor DT1 can electrically isolate the power supply voltage VDD from the second driving transistor DT2 during the period when the gated PWM signal SPWMgtd is logic high. In this case, the second driving transistor DT2 can be turned off, thereby turning off the light-emitting diode ED (e.g., not producing light).

[0087] In an embodiment, the first driving transistor DT1 and the second driving transistor DT2 may be implemented as p-channel metal-oxide-semiconductor transistors (PMOS). In this case, the PWM gate GT_PWM may perform a NAND operation. For example, the PWM gate GT_PWM may determine that the gated PWM signal SPWMgtd is logic high when the PWM enable signal PWM_EN is logic low, and may determine that the gated PWM signal SPWMgtd has the opposite logic level of the PWM signal SPWM when the PWM enable signal PWM_EN is logic high. However, the scope of this disclosure is not limited thereto. For example, the first driving transistor DT1 and the second driving transistor DT2 may be implemented as n-channel metal-oxide-semiconductor transistors (NMOS). In this case, the PWM gate GT_PWM may perform an AND operation.

[0088] In this embodiment, the light-emitting circuit LEC may not include the second driving transistor DT2. For example, the light-emitting diode ED may be directly connected to the first driving transistor DT1. That is, the scope of this disclosure is not limited to a specific implementation of the light-emitting circuit LEC.

[0089] Figure 6 To show in more detail Figure 5 A diagram illustrating the operation of displaying pixels. (See reference...) Figures 1 to 6 When the source selection signal SEL_SRC is at a logic high, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the bits stored in the independent bit unit CIDP.

[0090] When determining the logic level of the PWM signal SPWM based on the bits stored in the independent bit cell CIDP, the output of the shift register SR may not affect the logic level of the PWM signal SPWM. For example, when determining the logic level of the PWM signal SPWM based on the bits stored in the independent bit cell CIDP, even if the data output from the shift register SR changes, the logic level of the PWM signal SPWM can still be determined based on the bits stored in the eighth bit cell C8 (e.g., the MSB bit of the pixel drive data PDD).

[0091] The row driver 130 can control the shift register SR to perform bit cyclic shift operations. For example, in response to the first shift register control signals CS_SR1 to the eighth shift register control signals CS_SR8, the shift register SR can shift bits stored in the first unit C1 to the seventh unit C7. More specifically, in response to the first shift register control signals CS_SR1 to the eighth shift register control signals CS_SR8, the shift register SR can move bits stored in the second unit C2 to the seventh unit C7 to the first unit C1 to the sixth unit C6, move bits stored in the feedback bit unit CFB to the seventh unit C7, and copy bits stored in the first unit C1 to the feedback bit unit CFB.

[0092] Thus, when determining the logic level of the PWM signal SPWM based on the bits stored in the independent bit cell CIDP, the row driver 130 can control the shift register SR to perform a bit cyclic shift operation once or multiple times. In this case, when the logic level of the source select signal SEL_SRC transitions to logic low after the period in which the logic level of the PWM signal SPWM is determined by the bits stored in the independent bit cell CIDP has ended, any bit stored in the shift register SR can be determined as the logic level of the PWM signal SPWM based on the number of bit cyclic shift operations performed by the shift register SR. In other words, immediately after the logic level of the source select signal SEL_SRC transitions to logic low, any bit included in the shift register data D_SR can be used to determine the logic level of the PWM signal SPWM based on the number of bit cyclic shift operations performed by the shift register SR.

[0093] Figure 7 This is an exemplary timing diagram illustrating how a line driver, according to an embodiment of the present disclosure, drives display pixels during one emission cycle. (See also...) Figures 1 to 7 The line driver 130 can drive a light emission period TEM by dividing it into two or more segmented driving periods PDP. That is, a light emission period TEM may include two or more segmented driving periods PDP.

[0094] For a more concise explanation, the following description of an embodiment of a light-emitting period TEM comprising a first segmented driving period PDP1 and a second segmented driving period PDP2 is provided as a representative example. However, the scope of this disclosure is not limited thereto, and a light-emitting period TEM may include any number of segmented driving periods PDP, such as four, eight, etc.

[0095] The first segmented driving cycle PDP1 can be the time period between the tenth time point t10 and the twentieth time point t20. The second segmented driving cycle PDP2 can be the time period between the twentieth time point t20 and the thirtieth time point t30.

[0096] In an embodiment, the length of the first segmented driving cycle PDP1 and the length of the second segmented driving cycle PDP2 may be different from each other.

[0097] The line driver 130 can drive the display pixel PX by dividing the bit emission period BEM corresponding to the bit stored in the independent bit unit CIDP into multiple sub-bit emission periods SUB_BEM. For example, the line driver 130 can drive the display pixel PX by dividing the eighth bit emission period BEM8 into the first sub-bit emission periods SUB_BEM8a to the fourth sub-bit emission periods SUB_BEM8d. The first sub-bit emission periods SUB_BEM8a to the fourth sub-bit emission periods SUB_BEM8d may not be sequentially consecutive.

[0098] The line driver 130 can drive the display pixel PX by dividing a bit emit period BEM corresponding to one or more bits stored in the shift register SR into multiple sub-bit emit periods SUB_BEM. For example, the line driver 130 can drive the display pixel PX by dividing the seventh bit emit period BEM7 into a first sub-bit emit period SUB_BEM7a and a second sub-bit emit period SUB_BEM7b. The first sub-bit emit period SUB_BEM7a and the second sub-bit emit period SUB_BEM7b may not be sequentially consecutive.

[0099] The sub-bit transmit cycle SUB_BEM corresponding to the bit stored in the shift register SR can be included in different segmented drive cycles PDP. For example, the first sub-bit transmit cycle SUB_BEM7a can be included in the first segmented drive cycle PDP1, and the second sub-bit transmit cycle SUB_BEM7b can be included in the second segmented drive cycle PDP2.

[0100] The sub-bit transmit periods SUB_BEM corresponding to the bits stored in the Independent Bit Module (CIDP) can be arranged discontinuously. For example, the row driver 130 is free to determine the order of the sub-bit transmit periods SUB_BEM corresponding to the bits stored in the CIDP, as long as the sub-bit transmit periods SUB_BEM are discontinuous with each other. For a more detailed example, the first segmented drive period PDP1 may include a first sub-bit transmit period SUB_BEM8a and a second sub-bit transmit period SUB_BEM8b. The second segmented drive period PDP2 may include a third sub-bit transmit period SUB_BEM8c and a fourth sub-bit transmit period SUB_BEM8d.

[0101] The number of times the logic level of the PWM signal SPWM is determined based on each bit stored in the shift register SR during each segmented drive cycle PDP can be 1 or 0. For example, each of the bit emit cycle BEM and sub-bit emit cycle SUB_BEM included in each segmented drive cycle PDP can correspond to the independent bit cell data D_CIDP, or can correspond to different bits included in the shift register data D_SR.

[0102] The order of the bit transmit cycle BEM and sub-bit transmit cycle SUB_BEM for the bits included in the shift register data D_SR within each segmented drive cycle PDP can be determined based on the order in which each bit included in the shift register data D_SR has been stored in the shift register SR.

[0103] In this way, the row driver 130 can freely determine the bits that will be used to determine the logic level of the PWM signal SPWM in each segmented drive cycle PDP. For example, the row driver 130 may determine the logic level of the PWM signal SPWM during the first segmented drive cycle PDP1 based on a first subset of the bits included in the pixel drive data PDD, and may determine the logic level of the PWM signal SPWM during the second segmented drive cycle PDP2 based on a second subset of the bits included in the pixel drive data PDD. For a more detailed example, the first segmented drive cycle PDP1 may include the first transmit cycle BEM1 to the fifth transmit cycle BEM5, the first sub-transmit cycle SUB_BEM8a, the first sub-transmit cycle SUB_BEM7a, and the second sub-transmit cycle SUB_BEM8b. The second segmented drive cycle PDP2 may include the sixth transmit cycle BEM6, the third sub-transmit cycle SUB_BEM8c, the second sub-transmit cycle SUB_BEM7b, and the fourth sub-transmit cycle SUB_BEM8d.

[0104] In this embodiment, the lengths of the first segmented drive cycle PDP1 and the second segmented drive cycle PDP2 may be different from each other. For example, the first transmit cycle BEM1 may be included in only one segmented drive cycle PDP. That is, the first transmit cycle BEM1 may not be segmented.

[0105] In an embodiment, the length of the first segmented driving cycle PDP1 and the length of the second segmented driving cycle PDP2 can be approximately the same. For example, the length of the first segmented driving cycle PDP1 and the length of the second segmented driving cycle PDP2 can differ by '1UT'. However, the scope of this disclosure is not limited thereto, and the length of the first segmented driving cycle PDP1 and the length of the second segmented driving cycle PDP2 can differ by a significant number of '1UT' or more.

[0106] In this embodiment, the boundary between the first segmented driving cycle PDP1 and the second segmented driving cycle PDP2 can be referred to as the segmented standard time point PC. For example, the twentieth time point t20 can be referred to as the segmented standard time point PC.

[0107] For a more concise explanation, Figure 7 An example is shown in which the row driver 130 arranges a plurality of bit transmit cycles (BEMs) and a plurality of sub-bit transmit cycles (SUB_BEMs), but the scope of this disclosure is not limited thereto. For example, the row driver 130 is free to determine the arrangement of the plurality of bit transmit cycles (BEMs) and is free to determine the length, number, and arrangement of the plurality of sub-bit transmit cycles (SUB_BEMs).

[0108] In addition, Figure 7 The present invention describes a representative embodiment in which a bit emit period BEM corresponding to only one bit (e.g., the second most significant bit) of a plurality of bits included in shift register data D_SR is divided into two sub-bit emit periods SUB_BEM, but the scope of the present disclosure is not limited thereto. For example, row driver 130 may divide each of a bit emit period BEM corresponding to two or more bits included in shift register data D_SR into two or more sub-bit emit periods SUB_BEM. Reference is made below. Figures 12 to 14 An embodiment in which the row driver 130 divides each of the two or more bit emit cycles BEMs included in the shift register data D_SR into two or more sub-bit emit cycles SUB_BEMs is described in more detail.

[0109] According to embodiments of this disclosure, problems caused by the length of the bit emission period (BEM) corresponding to a specific bit can be minimized. For example, according to embodiments of this disclosure, not only can the bit emission period (BEM) corresponding to the MSB of the pixel driving data (PDD) be divided into multiple sub-bit emission periods (SUB_BEM), but the bit emission period corresponding to the second most significant bit can also be divided into multiple sub-bit emission periods (SUB_BEM), thereby minimizing the pseudo-contour effect. Therefore, the display device 100 according to embodiments of this disclosure will be able to produce higher quality images.

[0110] Figure 8 and Figure 9 It shows the basis in more detail. Figure 7 A timing diagram illustrating the operation of the display device in an embodiment. That is, below, referring to... Figures 1 to 9 This will describe in detail how to... Figure 7 Implementation examples drive Figure 6 The method for displaying pixels PX.

[0111] A frame periodic FRM may include a data write period (DW) and a light emission period (TEM). For simplicity, as a representative example, an embodiment in which one frame periodic FRM includes a light emission period (TEM) is described below, but the scope of this disclosure is not limited thereto. For example, a frame periodic FRM may include multiple subframes, and each of the subframes may include a light emission period (TEM).

[0112] The data write cycle (DW) can be before the emission cycle (TEM). For example, the data write cycle (DW) can be the time period between the first time point t1 and the tenth time point t10.

[0113] During the data write cycle (DW), the column driver 120 can provide bits included in the pixel drive data (PDD) to the display pixel (PX) via one or more data lines (DL). The display pixel (PX) can store the pixel drive data (PDD) in the shift register (SR) and the independent bit cell (CIDP). For example, the shift register (SR) can store shift register data (D_SR), and the independent bit cell (CIDP) can store independent bit cell data (D_CIDP).

[0114] More specifically, row driver 130 can set the feedback enable signal FB_EN low during the data write cycle DW. Column driver 120 can sequentially provide the first bit D1 through the seventh bit D7 included in the pixel drive data PDD to the feedback multiplexer MUX_FB. In this case, the feedback multiplexer MUX_FB can sequentially provide the first bit D1 through the seventh bit D7 to the first node NA, and the shift register SR can sequentially store the first bit D1 through the seventh bit D7 in response to the control of row driver 130.

[0115] For example, between a first time point t1 and a second time point t2, column driver 120 may provide the first bit D1 to the feedback multiplexer MUX_FB via data line DL. Row driver 130 may sequentially switch (e.g., from logic low to logic high and then back to logic low) the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. In this case, the first bit D1 may be stored in the feedback bit cell CFB.

[0116] Then, between the second time point t2 and the third time point t3, column driver 120 can provide the second bit D2 to the feedback multiplexer MUX_FB via data line DL. Row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. In this case, the first bit D1 stored in the feedback bit unit CFB can be shifted to the seventh bit unit C7, and the second bit D2 can be newly stored in the feedback bit unit CFB.

[0117] Thus, column driver 120 can sequentially provide bits 3 through 7 to the feedback multiplexer MUX_FB between the third time point t3 and the eighth time point t8. Row driver 130 can sequentially store bits 3 through 7 in shift register SR by controlling the first shift register control signal CS_SR1 through the eighth shift register control signal CS_SR8. Therefore, at the eighth time point t8, bits 1 through 6 can be stored in the second bit unit C2 through the seventh bit unit C7 respectively, and bit 7 can be stored in the feedback bit unit CFB.

[0118] For a more concise explanation, Figure 8 The embodiment is typically described in which the row driver 130 sequentially switches all of the first shift register control signals CS_SR1 to the eighth shift register control signal CS_SR8 each time a new bit is stored in the shift register SR; however, the scope of this disclosure is not limited thereto. For example, between a first time point t1 and a second time point t2, the row driver 130 can store the first bit D1 in the feedback bit cell CFB by switching only the eighth shift register control signal CS_SR8. Similarly, between a second time point t2 and an eighth time point t8, the row driver 130 can store the first bit D1 to the seventh bit D7 in the shift register SR without switching some of the shift register control signals CS_SR. In this case, the power consumption of the row driver 130 can be minimized.

[0119] Between time point t8 and time point t10, column driver 120 can provide the eighth bit D8 to data line DL. Row driver 130 can toggle the independent bit cell control signal CS_CIDP. In this case, the eighth bit D8 can be stored in the eighth bit cell C8.

[0120] For a more concise explanation, Figure 8 The embodiment is representatively described in which the eighth bit D8 is stored in the eighth bit cell C8 between the eighth time point t8 and the tenth time point t10, but the scope of this disclosure is not limited thereto. For example, if the independent bit cell CIDP and the column driver 120 are connected via a first data line, and the feedback multiplexer MUX_FB and the column driver 120 are connected via a second data line, then the eighth bit D8 may be stored in the eighth bit cell C8 before the eighth time point t8. For example, the row driver 130 may switch the independent bit cell control signal CS_CIDP at a time point before the eighth time point t8.

[0121] In one embodiment, the row driver 130 may set the PWM enable signal PWN_EN low during the data write cycle DW. In this case, the gated PWM signal SPWMgtd may remain high during the data write cycle DW, so that the light-emitting circuit LEC may not generate light.

[0122] At time point t10, the row driver 130 can convert the feedback enable signal FB_EN and the PWM enable signal PWM_EN to logic high. In this case, the feedback multiplexer MUX_FB can maintain the logic level of the first node NA at the same logic level as the second node NB. That is, the feedback bit unit CFB can be connected to the first bit unit C1. The PWM gate GT_PWM can generate the gated PWM signal SPWMgtd based on the PWM signal SPWM.

[0123] At the tenth time point t10, the row driver 130 can switch the first shift register control signal CS_SR1. In this case, the first bit D1 stored in the second bit cell C2 can be stored in the first bit cell C1, and the logic level of the second node NB can be determined based on the first bit D1. Then, the row driver 130 can sequentially switch the second shift register control signal CS_SR2 to the seventh shift register control signal CS_SR7 to store the second bit D2 to the seventh bit D7 in the second bit cells C2 to the seventh bit cell C7. Then, the row driver 130 can switch the eighth shift register control signal CS_SR8 to copy the first bit D1 stored in the first bit cell C1 to the feedback bit cell CFB. Therefore, at the eleventh time point t11, the first bit cells C1 to the seventh bit cells C7 can store the first bit D1 to the seventh bit D7 respectively, and the feedback bit cell CFB can store the same bit as the first bit cell C1 (e.g., the first bit D1).

[0124] Since the source selection signal SEL_SRC is logic low and the logic level of the second node NB is determined based on the first bit D1, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM to the value corresponding to the first bit D1 between the tenth time point t10 and the eleventh time point t11 ​​(e.g., the first transmit period BEM1).

[0125] For a more concise explanation, Figure 8 An embodiment is shown in which the row driver 130 sequentially switches the second shift register control signal CS_SR2 to the eighth shift register control signal CS_SR8 after the tenth time point t10, but the scope of this disclosure is not limited thereto. For example, the row driver 130 may be implemented to sequentially switch the second shift register control signal CS_SR2 to the eighth shift register control signal CS_SR8 between the eighth time point t8 and the tenth time point t10.

[0126] At the eleventh time point t11, the row driver 130 can control the shift register SR to perform a bit cyclic shift operation. For example, the row driver 130 can switch the first shift register control signal CS_SR1 at the eleventh time point t11. In this case, the second bit D2 stored in the second bit unit C2 can be stored in the first bit unit C1, and the logic level of the second node NB can be determined based on the second bit D2. Then, the row driver 130 can sequentially switch the second shift register control signal CS_SR2 to the seventh shift register control signal CS_SR7 to sequentially move the bits stored in the third bit units C3 to the seventh bit units C7 to the second bit units C2 to the sixth bit units C6, move the first bit D1 stored in the feedback bit unit CFB to the seventh bit unit C7, and copy the bits stored in the first bit unit C1 to the feedback bit unit CFB. In this case, at the twelfth time point t12, the first unit C1 to the sixth unit C6 can store the second bit D2 to the seventh bit D7 respectively, the seventh unit C7 can store the first bit D1, and the feedback bit unit CFB can store the same bit as the first unit C1 (e.g., the second bit D2).

[0127] Since the logic level of the second node NB is determined based on the second bit D2, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM to the value corresponding to the second bit D2 between the eleventh time point t11 ​​and the twelfth time point t12 (e.g., the second bit transmit period BEM2).

[0128] The line driver 130 can control the display pixel PX in a similar manner during the third bit transmission cycle BEM3 to the fifth bit transmission cycle BEM5 (i.e., between the twelfth time point t12 and the fifteenth time point t15). Therefore, at the fifteenth time point t15, the fifth bit D5 to the seventh bit D7 can be stored in the first unit C1 to the third unit C3 respectively, the first bit D1 to the fourth bit D4 can be stored in the fourth unit C4 to the seventh unit C7 respectively, and the fifth bit D5 can be stored in the feedback bit unit CFB.

[0129] The time period between the fifteenth time point t15 and the sixteenth time point t16 can correspond to the first sub-bit transmit cycle SUB_BEM8a. The line driver 130 can hold the source select signal SEL_SRC high between the fifteenth time point t15 and the sixteenth time point t16. In this case, the source select multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the bits stored in the eighth bit unit C8.

[0130] The time period between the sixteenth time point t16 and the seventeenth time point t17 can correspond to the first sub-bit transmit cycle SUB_BEM7a. The line driver 130 can keep the source select signal SEL_SRC low between the sixteenth time point t16 and the seventeenth time point t17. In this case, the source select multiplexer MUX_SRC may need to determine the logic level of the PWM signal SPWM based on the seventh bit D7 stored in the first unit C1.

[0131] In other words, immediately after the sixteenth time point t16, the seventh bit D7 may need to be stored in the first unit C1. Conversely, the sixth bit D6 should be stored in the first unit C1 immediately before the sixteenth time point t16. However, since the fifth bit D5 is stored in the first unit C1 immediately before the fifteenth time point t15, the shift register SR may need to perform multiple (e.g., two) bit cyclic shift operations immediately after the sixteenth time point t16 when the bit cyclic shift operation is performed. Therefore, within a specific time period after the sixteenth time point t16 when the bit cyclic shift operation is performed, the logic level of the PWM signal SPWM can be determined based on the sixth bit D6 instead of the seventh bit D7. In this case, noise or errors may appear in the image generated by the display device 100.

[0132] According to embodiments of this disclosure, the shift register SR can perform a bit cyclic shift operation during the first sub-bit transmit cycle SUB_BEM8a in response to the control of the row driver 130. For example, the row driver 130 can control the shift register SR to perform a bit cyclic shift operation by sequentially switching the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8 during the first sub-bit transmit cycle SUB_BEM8a. In this case, as referenced above... Figure 6 Similarly, while the source selection signal SEL_SRC remains high, the shift register SR can perform a bit cyclic shift operation. Therefore, immediately before the sixteenth time point t16, the first unit C1 can be in the state of storing the sixth bit D6. In this case, since the value of the bit stored in the first unit C1 during the bit cyclic shift operation does not affect the logic level of the PWM signal SPWM, no noise will appear in the image generated by the display device 100 even if the bit cyclic shift operation is performed.

[0133] The line driver 130 can control the display pixel PX during the first sub-bit transmission period SUB_BEM7a in a manner similar to that previously described with reference to the first transmission period BEM1 and the second transmission period BEM2.

[0134] Then, during the period between the seventeenth time point t17 and the twentieth time point t20 corresponding to the second sub-bit transmit cycle SUB_BEM8b, the line driver 130 can hold the source selection signal SEL_SRC high. That is, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the value of the bit stored in the eighth bit unit C8.

[0135] During the period between the twentieth time point t20 and the twenty-first time point t21 corresponding to the sixth transmit cycle BEM6, the row driver 130 can keep the source selection signal SEL_SRC low. That is, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the value of the bit stored in the first unit C1.

[0136] Immediately before the seventeenth time point t17, the seventh bit D7 can be stored in the first unit C1. However, immediately before the twentieth time point t20, the first unit C1 can be in the state of storing the fifth bit D5 (for example, the bit stored in the first unit C1 can immediately change to the state of the sixth bit D6).

[0137] Therefore, the shift register SR can perform a bit-circular shift operation (e.g., a multi-bit circular shift operation) on multiple bits during the second sub-bit transmit cycle SUB_BEM8b in response to the control of the row driver 130. For example, the row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8 once between the seventeenth time point t17 and the eighteenth time point t18. In this case, the shift register SR can perform a one-bit circular shift operation, so the first bit D1 can be stored in the first unit C1. Then, the row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8 once between the eighteenth time point t18 and the nineteenth time point t19. In this case, the shift register SR can perform a one-bit circular shift operation to allow the second bit D2 to be stored in the first unit C1. In this way, the row driver 130 can cause the shift register SR to repeatedly perform the bit-circular shift operation so that the fifth bit D5 is stored in the first unit C1. In this case, immediately after the twentieth time point t20, the value of the bit stored in the first unit C1 can be immediately changed to the sixth bit D6.

[0138] In this way, the row driver 130 can control the shift register SR to perform a full cyclic shift operation. While the shift register SR is performing a full cyclic shift operation (e.g., between the tenth time point t10 and the seventeenth time point t17, or between the eleventh time point t11 ​​and the eighteenth time point t18, etc.), the source selection multiplexer MUX_SRC can change the logic level of the PWM signal SPWM based on the bit sequence included in the shift register data D_SR and the independent bit cell data D_CIDP.

[0139] In other words, the line driver 130 can control the operation of the display pixel PX during multiple bit transmission cycles BEM and multiple sub-bit transmission cycles SUB_BEM by controlling multiple pixel control signals CTRL. The way the line driver 130 controls the operation of the display pixel PX during the second sub-bit transmission cycle SUB_BEM7b, the third sub-bit transmission cycle SUB_BEM8c, and the fourth sub-bit transmission cycle SUB_BEM8d is similar to the method described above, therefore a detailed description thereof is omitted.

[0140] In an embodiment, the line driver 130 can determine each of the time intervals between the tenth time point t10 and the thirtieth time point t30 as a predetermined length. For example, by controlling the timing of changes in the logic levels of multiple pixel control signals CTRL, the line driver 130 can use the above-mentioned reference... Figure 7 The lengths of the described bit emission period BEM and sub-bit emission period SUB_BEM are set for each of the time intervals between the tenth time point t10 and the thirtieth time point t30.

[0141] For a more concise explanation, Figure 8 and Figure 9 The diagram shows the row driver 130 switching the first shift register control signal CS_SR1 immediately after the start of the bit transmit cycle BEM or the sub-bit transmit cycle SUB_BEM, but the scope of this disclosure is not limited thereto. For example, the row driver 130 may be implemented to switch the first shift register control signal CS_SR1 immediately before the start of the bit transmit cycle BEM or the sub-bit transmit cycle SUB_BEM corresponding to each of the plurality of bits included in the shift register data D_SR (e.g., such that the time at which the first shift register control signal CS_SR1 transitions to logic low coincides with the time at which the bit transmit cycle BEM or the sub-bit transmit cycle SUB_BEM begins).

[0142] Figure 10 The reference is shown in a more concise form. Figures 7 to 9 A table describing the driving methods. (See reference...) Figures 1 to 10 The line driver 130 can divide the light emission period TEM into a first segmented driving period PDP1 and a second segmented driving period PDP2.

[0143] The line driver 130 can control the logic level of the PWM signal SPWM during a first segmented driving cycle PDP1 and during a second segmented driving cycle PDP2 based on different combinations of multiple bits. For example, the line driver 130 can determine the logic level of the PWM signal SPWM during the first segmented driving cycle PDP1 based on bits 1 through 5 (D5) and bits 7 through 8 (D8), which is a first subset of the bits included in the pixel driving data PDD; and can determine the logic level of the PWM signal SPWM during the second segmented driving cycle PDP2 based on bits 6 through 8 (D8), which is a second subset of the bits included in the pixel driving data PDD. In other words, in response to the control of the line driver 130, the display pixel PX can perform a light-emitting operation based on the bits included in the first subset during the first segmented driving cycle PDP1, and can perform a light-emitting operation based on the bits included in the second subset during the second segmented driving cycle PDP2.

[0144] The line driver 130 can drive the display pixel PX in a predetermined order during the first segmented driving cycle PDP1 and the second segmented driving cycle PDP2. More specifically, the line driver 130 can drive the display pixel PX to sequentially perform light emission operations for 'first bit D1-second bit D2-third bit D3-fourth bit D4-fifth bit D5-eighth bit D8_P1-seventh bit D7-eighth bit D8_P2' during the first segmented driving cycle PDP1, and can drive the display pixel PX to sequentially perform light emission operations for 'sixth bit D6-eighth bit D8_P1-seventh bit D7-eighth bit D8_P2' during the second segmented driving cycle PDP2.

[0145] In an embodiment, the bits used for logic level control of the PWM signal SPWM during the first segmented drive cycle PDP1 and the bits used for logic level control of the PWM signal SPWM during the second segmented drive cycle PDP2 may include two or more interleaved portions (e.g., common bits). For example, the MSB bit of the pixel drive data PDD (e.g., a bit stored in the independent bit unit CIDP) and the second most significant bit of the pixel drive data PDD (e.g., the most significant bit in the bits stored in the shift register SR) may be used during both the first segmented drive cycle PDP1 and the second segmented drive cycle PDP2. In this case, due to the above reference... Figure 3The relatively long bit emission period BEM described can be divided into multiple sub-bit emission periods SUB_BEM, thus minimizing pseudo-contour effects. However, the scope of this disclosure is not limited thereto. For example, one of the MSB bits and the second most significant bit of the pixel drive data PDD may not be used during one or more of the first segmented drive period PDP1 and the second segmented drive period PDP2.

[0146] In an embodiment, when the Independent Bit Unit (CIDP) is implemented as the MSB storing pixel driving data (PDD), the image quality generated by the display device 100 can be further improved because the bit emission period (BEM) corresponding to the bit that has the greatest impact on the pseudo-contour effect can be divided into a larger number of sub-bit emission periods (SUB_BEM). However, the scope of this disclosure is not limited thereto.

[0147] In an embodiment, each of the eighth bits D8_P1 and D8_P2 may be identical to the eighth bit D8. The eighth bits D8_P1 and D8_P2 may correspond to different time periods (e.g., phases) in each segmented drive cycle PDP where the logic level of the PWM signal SPWM is determined based on the eighth bit D8. That is, the eighth bits D8_P1 and D8_P2 may correspond to different sub-bit transmit cycles SUB_BEM included in each segmented drive cycle PDP for the eighth bit D8. For example, the eighth bit D8_P1 may correspond to the first sub-bit transmit cycle SUB_BEM8a and the third sub-bit transmit cycle SUB_BEM8c, and the eighth bit D8_P2 may correspond to the second sub-bit transmit cycle SUB_BEM8b and the fourth sub-bit transmit cycle SUB_BEM8d.

[0148] The sum of the lengths of the time intervals used by bits 1 to 8 (d1 to 8) during the TEM period to determine the logic level of the PWM signal SPWM can be equal to the above reference. Figure 3 The lengths of the first transmit cycle BEM1 to the eighth transmit cycle BEM8 are described. For example, the sum of the lengths of the time periods during the first segmented drive cycle PDP1 and the second segmented drive cycle PDP2 when the first bit D1 is used to determine the logic level of the PWM signal SPWM can be '1UT'; and the sum of the lengths of the time periods during the first segmented drive cycle PDP1 and the second segmented drive cycle PDP2 when the seventh bit D7 is used to determine the logic level of the PWM signal SPWM can be '64UT'; the sum of the lengths of the time periods during the first segmented drive cycle PDP1 and the second segmented drive cycle PDP2 when the eighth bit D8 is used to determine the logic level of the PWM signal SPWM can be '128UT' (for example, the sum of the lengths of the time periods corresponding to the eighth bit D8_P1 '64UT' and the sum of the lengths of the time periods corresponding to the eighth bit D8_P2 '64UT').

[0149] In other words, according to embodiments of this disclosure, the row driver 130 can divide the bit emit period BEM corresponding to one or more bits (e.g., the seventh bit D7 or more bits) included in the shift register data D_SR into two or more sub-bit emit periods SUB_BEM. That is, the logic level of the PWM signal SPWM can be determined based on the seventh bit D7 two or more times during the emission period TEM. Therefore, according to embodiments of this disclosure, the pseudo-profile effect caused by the bit emit period BEM corresponding to the bits included in the shift register data D_SR can be minimized.

[0150] In an embodiment, a first plurality of bits (e.g., bits D1 to D5, D7, and D8) can be used to determine the logic level of the PWM signal SPWM during the first segmented drive cycle PDP1; and a second plurality of bits (e.g., bits D6 to D8) can be used to determine the logic level of the PWM signal SPWM during the second segmented drive cycle PDP2. The arrangement order of the bit emit period BEM and sub-bit emit period SUB_BEM corresponding to the first plurality of bits in the first segmented drive cycle PDP1 and the arrangement order of the bit emit period BEM and sub-bit emit period SUB_BEM corresponding to the second plurality of bits in the second segmented drive cycle PDP2 can be determined based on a single reference order. The reference order can be 'bit D1 - bit D2 - bit D3 - bit D4 - bit D5 - bit D6 - bit D8_P1 - bit D7 - bit D8_P2'. In this way, the row driver 130 can determine the order of the bit emission period BEM and the sub-bit emission period SUB_BEM within each segmented driving cycle PDP based on a predetermined reference order. In this case, the number of bit cyclic shift operations required during the emission period TEM can be minimized. However, the scope of this disclosure is not limited thereto, and the row driver 130 can drive the display pixels PX based on different reference orders during the first segmented driving cycle PDP1 and the second segmented driving cycle PDP2.

[0151] Figure 11 It shows the basis Figures 7 to 10 A diagram showing the magnitude of the pseudo-contour effect in the embodiment. (Refer to...) Figures 1 to 11 The column driver 120 and the row driver 130 can drive a display pixel PX within the first frame period FRMa to the third frame period FRMc. For example, the column driver 120 can provide pixel drive data PDD with a value of '126' to the display pixel PX in the first frame period FRMa; it can provide pixel drive data PDD with a value of '127' to the display pixel PX in the second frame period FRMb; and it can provide pixel drive data PDD with a value of '128' to the display pixel PX in the third frame period FRMc.

[0152] The first frame period FRMa to the third frame period FRMC can each include a first emission period TEMa to a third emission period TEMc. Each of the first emission period TEMa to the third emission period TEMc can include a first segmented drive period PDP1 and a second segmented drive period PDP2. That is, the line driver 130 can be configured as described above. Figures 7 to 10 The described method drives the display pixel PX. In this case, the periods during which the display pixel PX emits light (e.g., the periods when the PWM signal SPWM is logic high) can be distributed across each emission cycle TEM, thereby minimizing the pseudo-contour effect.

[0153] Figures 12 to 14 This is a table illustrating a method for driving display pixels according to an embodiment. (Refer to...) Figures 1 to 14 The row driver 130 can divide the light emission period TEM into two or more segmented driving periods PDP. For example, the row driver 130 can divide the light emission period TEM into the first segmented driving period PDP1 to the eighth segmented driving period PDP8.

[0154] In an embodiment, each of the first segmented driving cycles PDP1 to the eighth segmented driving cycles PDP8 may include two or more sub-bit transmit cycles SUB_BEM for a bit stored in the Independent Bit Unit (CIDP). For example, each of the first segmented driving cycles PDP1 to the eighth segmented driving cycles PDP8 may include three sub-bit transmit cycles SUB_BEM for the eighth bit D8.

[0155] In embodiments, the lengths of the sub-bit transmit cycles SUB_BEM corresponding to the independent bit cell data D_CIDP included in a segmented drive cycle PDP may be the same or different from each other. For example, the lengths of the sub-bit transmit cycles SUB_BEM for the eighth bit D8 included in the first segmented drive cycle PDP1 of the row driver 130 may be 4UT, 4UT, and 8UT, respectively. However, the scope of this disclosure is not limited thereto.

[0156] In embodiments, the length and number of sub-bit transmit cycles SUB_BEM corresponding to the independent bit cell data D_CIDP included in each segmented drive cycle PDP may be the same or different from each other. For example, in Figure 12In this embodiment, each of the first segmented driving cycles PDP1 to the eighth segmented driving cycles PDP8 includes three sub-bit transmit cycles SUB_BEM corresponding to the independent bit cell data D_CIDP, and the lengths of the three sub-bit transmit cycles SUB_BEM included in each of the first segmented driving cycles PDP1 to the eighth segmented driving cycles PDP8 are 4UT, 4UT, and 8UT, respectively, but the scope of this disclosure is not limited thereto. For example, a particular segmented driving cycle PDP may include any number of sub-bit transmit cycles SUB_BEM corresponding to independent bit cell data D_CIDP other than three; and the length of the sub-bit transmit cycles SUB_BEM corresponding to independent bit cell data D_CIDP included in a particular segmented driving cycle PDP may not be 4UT or 8UT.

[0157] In this embodiment, each of the first segmented driving cycles PDP1 to the eighth segmented driving cycles PDP8 may include a sub-bit transmit cycle SUB_BEM for two or more bits stored in the shift register SR. For example, each of the first segmented driving cycles PDP1 to the eighth segmented driving cycles PDP8 may include a sub-bit transmit cycle SUB_BEM for the fourth bit D4 to the sixth bit D6 and the seventh bit D7. The first segmented driving cycles PDP1 to the fourth segmented driving cycles PDP4 may include a sub-bit transmit cycle SUB_BEM for the third bit D3. That is, the row driver 130 can not only divide the seventh bit transmit cycle BEM7, but also divide the other bit transmit cycles BEM in a similar manner to the seventh bit transmit cycle BEM7.

[0158] In other words, according to embodiments of this disclosure, the row driver 130 can freely determine which bit in the shift register SR is used to divide the corresponding bit transmit period BEM, and how many sub-bit transmit periods SUB_BEM are divided into for the corresponding bit. Specifically, compared with reference to... Figures 7 to 11 Compared to the described embodiments, since each bit transmission period (BEM) can be divided into shorter sub-bit transmission periods (SUB_BEM), therefore... Figures 12 to 14 The illustrated embodiments can further reduce the pseudo-contour effect.

[0159] according to Figures 12 to 14 The driving method for the display pixel PX shown can vary the magnitude of the pseudo-contour effect. For example, when... Figure 13 The bit emission period BEM and sub-bit emission period SUB_BEM of the lower bits (e.g., the first bit D1 to the third bit D3) of the pixel-driven data PDD are concentrated in the middle of the emission period TEM (e.g., the third segment driving period PDP3 to the sixth segment driving period PDP6), as shown. Figure 12The illustrated embodiments reduce the pseudo-contour effect compared to (e.g., where the lower bit emission period BEM and sub-bit emission period SUB_BEM for pixel-driven data PDD are concentrated in the early or late stages of the emission period TEM). However, the scope of this disclosure is not limited thereto.

[0160] For another example, according to Figure 14 In the illustrated embodiment, the sub-bit emission periods SUB_BEM corresponding to each bit can be evenly distributed across the first segmented driving periods PDP1 to the eighth segmented driving periods PDP8. For example, each of the sub-bit emission periods SUB_BEM corresponding to the third bit D3 can be included in an even-numbered segmented driving period PDP. In this case, since the sub-bit emission periods SUB_BEM corresponding to each bit can be more uniformly arranged throughout the entire emission period TEM, it is more effective than... Figure 12 and Figure 13 The illustrated embodiments can further reduce the pseudo-contour effect. However, the scope of this disclosure is not limited thereto.

[0161] Figure 15 This is a timing diagram illustrating one frame period according to an embodiment. (Refer to...) Figures 1 to 15 A frame period FRM may include a data write period (DW) and one or more subframe periods (SFRMs). For example, a frame period FRM may include a data write period (DW) and first subframe periods (SFRM1) to third subframe periods (SFRM3). However, the scope of this disclosure is not limited thereto, and a frame period FRM may include only one subframe period (SFRM).

[0162] In an embodiment, a frame period (FRM) may include a data write period (DW). For example, at different frame period FRMs, the display pixel (PX) may receive different pixel drive data (PDD). In this case, the waveform of the PWM signal (SPWM) at different frame period FRMs may be different. However, the scope of this disclosure is not limited thereto.

[0163] A single pixel drive data PDD can be shared across the first subframe period SFRM1 through the third subframe period SFRM3. For example, during the first subframe period SFRM1 through the third subframe period SFRM3, the display pixel PX can reuse the pixel drive data PDD received in the data write period DW. That is, the waveforms of the PWM signal SPWM for each of the first subframe periods SFRM1 through the third subframe period SFRM3 can be identical to each other. However, the scope of this disclosure is not limited thereto. For example, the display pixel PX can use multiple bits included in the pixel drive data PDD in different orders during the first subframe periods SFRM1 through the third subframe period SFRM3. In this case, the duty cycle (e.g., duty rate) of the PWM signal SPWM for each of the first subframe periods SFRM1 through the third subframe period SFRM3 is the same, and the waveforms of the PWM signals SPWM can be different to each other.

[0164] The first subframe period SFRM1 to the third subframe period SFRM3 can respectively correspond to the first emission period TEM1 to the third emission period TEM3. Each of the first emission period TEM1 to the third emission period TEM3 can correspond to the above reference. Figures 1 to 14 The described emission period TEM. For example, the first emission period TEM1 may include multiple bit emission periods BEM and multiple sub-bit emission periods SUB_BEM. The configurations of the second emission period TEM2 and the third emission period TEM3 may be the same as those of the first emission period TEM1.

[0165] In other words, according to Figure 15 In this embodiment, instead of using a single pixel drive data PDD to determine the logic level of the PWM signal SPWM during a long emission period TEM, a single pixel drive data PDD can be used to determine the logic level of the PWM signal SPWM during multiple short emission period TEMs. In this case, the '1UT' length for each emission period TEM can be minimized, thereby minimizing pseudo-contour effects. However, the scope of this disclosure is not limited thereto.

[0166] Figure 16 This is a block diagram illustrating a display system according to an embodiment of the present disclosure. (Refer to...) Figures 1 to 16 The display system 1000 may include a display device 1100, a processing device 1200, and a memory device 1300.

[0167] The display device 1100 may include a timing control circuit 1140. The display device 1100 may be implemented as described above. Figures 1 to 15 The described display device 100. In this case, the timing control circuit 1140 may correspond to the timing control circuit 140.

[0168] The processing device 1200 may provide frame data D_FRM to the display device 1100. The frame data D_FRM may include pixel driving data PDD for each of the plurality of display pixels PX included in the display device 1100.

[0169] In the embodiments, the processing device 1200 may be one of various types of computing devices such as a central processing unit (CPU), a graphics processing unit (GPU), etc. However, the scope of this disclosure is not limited to a particular type of processing device 1200.

[0170] The processing device 1200 can provide setting values ​​SV to the display device 1100. The display device 1100 can determine a specific method for driving multiple display pixels PX based on frame data D_FRM based on one or more setting values ​​SV.

[0171] For a more detailed example, timing control circuitry 1140 may receive one or more setting values ​​SV. Timing control circuitry 1140 may determine the pixel driving logic (hereinafter referred to as "PDL") corresponding to one or more setting values ​​SV based on accessing the pixel driving logic table TBL_PDL stored in memory device 1300.

[0172] In an embodiment, memory device 1300 may be implemented as a non-volatile memory device such as flash memory. However, the scope of this disclosure is not limited thereto, and memory device 1300 may be implemented as a volatile memory device such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0173] Pixel driving logic (PDL) can be represented as the above reference. Figures 1 to 15 The described method describes a driving method for display pixels PX. For example, pixel driving logic PDL can indicate the timing at which row driver 130 changes the logic level of multiple pixel control signals CTRL. Timing control circuitry 1140 can drive display pixels PX based on the determined pixel driving logic PDL.

[0174] Figure 17 This is an exemplary illustration according to an embodiment. Figure 16 A diagram showing the configuration of the pixel-driven logic table. (Refer to...) Figure 17 , Figure 16 The pixel-driven logic table TBL_PDL can be implemented as the following pixel-driven logic table TBL_PDLa.

[0175] The pixel driving logic table TBL_PDLa may include multiple pixel driving logic PDLs. For example, the pixel driving logic table TBL_PDLa may include first pixel driving logic PDL1 to third pixel driving logic PDL3. Each of the first pixel driving logic PDL1 to third pixel driving logic PDL3 may have different attributes. For example, each of the first pixel driving logic PDL1 to third pixel driving logic PDL3 may correspond to different combinations of the following: i) how many segmented driving cycles PDPs a emission period TEM is divided into (e.g., the number of PDPs); ii) the arrangement of bit emission period BEM and sub-bit emission period SUB_BEM in the emission period TEM (e.g., the arrangement of BEM and SUB_BEM); and iii) the number of bit emission period BEMs to be divided (e.g., the number of BEMs to be divided).

[0176] For a more detailed example, the first pixel driving logic PDL1 can be an operation algorithm used to divide a light emission period TEM into two segmented driving periods PDP; according to the first scheme SCHM_A (e.g., referred to above). Figure 12 The described scheme arranges bit emission periods (BEMs) and sub-bit emission periods (SUB_BEMs) within the emission period (TEM); and divides one bit emission period (BEM) (e.g., the bit emission period BEM corresponding to the MSB) into multiple sub-bit emission periods (SUB_BEMs). The second pixel driving logic (PDL2) can be an operation algorithm for dividing one emission period (TEM) into four segmented driving periods (PDPs); according to the second scheme (SCHM_B, e.g., as described above)... Figure 13 The described scheme arranges bit emission periods (BEMs) and sub-bit emission periods (SUB_BEMs) within the emission period (TEM); and divides four bit emission periods (BEMs) (e.g., the bit emission periods corresponding to the four high bits of the pixel driving data (PDD)) into multiple sub-bit emission periods (SUB_BEMs). The third pixel driving logic (PDL3) can be an operation algorithm for dividing a emission period (TEM) into eight segmented driving periods (PDPs); according to the third scheme (SCHM_C, e.g., as described above)... Figure 14 The described scheme arranges bit emission periods (BEMs) and sub-bit emission periods (SUB_BEMs) within the emission period (TEM); and divides six bit emission period BEMs (e.g., bit emission period BEMs corresponding to the six high bits of pixel drive data (PDD)) into multiple sub-bit emission periods (SUB_BEMs). However, the scope of this disclosure is not limited to the number of pixel drive logic PDLs included in the pixel drive logic table (TBL_PDLa) and the specific properties of each pixel drive logic PDL.

[0177] Each of the multiple pixel-driving logic PDLs included in the pixel-driving logic table TBL_PDLa can correspond to a different pixel-driving logic identifier ID_PDL. For example, the first pixel-driving logic PDL1 to the third pixel-driving logic PDL3 can correspond to pixel-driving logic identifiers ID_PDL'1' to '3', respectively.

[0178] Timing control circuit 1140 may receive a setting value SV from processing device 1200. Timing control circuit 1140 may read a pixel driving logic PDL corresponding to the pixel driving logic identifier ID_PDL indicated by the setting value SV received from memory device 1300. For example, if the received setting value SV includes pixel driving logic identifier ID_PDL'2', then timing control circuit 1140 may read a second pixel driving logic PDL2 from memory device 1300. Timing control circuit 1140 may drive a plurality of display pixels PX by controlling row driver 130 and column driver 120 based on the second pixel driving logic PDL2.

[0179] In other words, according to Figure 17 In one embodiment, the processing device 1200 can change the pixel driving logic PDL used to drive the display pixels PX of the display device 1100 based on the setting value SV. Thus, the processing device 1200 can change the pixel driving logic PDL used to drive the display pixels PX of the display device 1100 according to factors such as the illuminance of the environment to which the display system 1000 is exposed and the needs of the users of the display system 1000.

[0180] Figure 18 This is an exemplary illustration according to an embodiment. Figure 16 A diagram showing the configuration of the pixel-driven logic table. (Refer to...) Figure 18 , Figure 16 The pixel-driven logic table TBL_PDL can be implemented as the following pixel-driven logic table TBL_PDLb.

[0181] The pixel driver logic table TBL_PDLb may include multiple pixel driver logic PDLs. For example, the pixel driver logic table TBL_PDLb may include first pixel driver logic PDL1 through eighth pixel driver logic PDL8. (Refer to previous reference) Figure 17 The descriptions are similar, but each of the first pixel driving logic PDL1 to the eighth pixel driving logic PDL8 may have different attributes.

[0182] The timing control circuit 1140 may receive multiple setting values ​​SV from the processing device 1200. For example, the timing control circuit 1140 may receive first setting values ​​SV1 to third setting values ​​SV3 from the processing device 1200. The timing control circuit 1140 may read pixel driving logic PDL corresponding to the first setting values ​​SV1 to the third setting values ​​SV3 from the memory device 1300. For a more detailed example, when the first setting values ​​SV1 to the third setting values ​​SV3 are '2', '3', and '3' respectively, the timing control circuit 1140 may read a fourth pixel driving logic PDL4 from the memory device 1300. In this case, the timing control circuit 1140 may control the row driver 130 and the column driver 120 based on the fourth pixel driving logic PDL4 to drive multiple display pixels PX.

[0183] In other words, according to Figure 18 In one embodiment, the processing device 1200 can change the pixel driving logic PDL used to drive the display pixels PX of the display device 1100 based on multiple setting values ​​SV. Thus, the processing device 1200 can change the pixel driving logic PDL used to drive the display pixels PX of the display device 1100 according to the illuminance of the environment exposed to the display system 1000, requests from users of the display system 1000, etc.

[0184] For a more concise explanation, Figures 16 to 18 An embodiment is shown in which a display device 1100 selects one of a plurality of pixel driving logic PDLs stored in a memory device 1300 in response to a request from a processing device 1200; however, the scope of this disclosure is not limited thereto. For example, the display device 1100 may be implemented to directly generate pixel driving logic PDLs based on a plurality of setting values ​​SVs provided from the processing device 1200. That is, the scope of this disclosure is not limited to the specific manner in which the pixel driving logic PDLs are changed.

[0185] The foregoing description describes specific embodiments for carrying out this disclosure. However, the scope of this disclosure is not limited thereto and should be determined based on the claims provided below and their equivalents.

Claims

1. A display pixel, comprising: A shift register, which includes multiple serial bit units; Independent bit unit; A source selection multiplexer is configured to generate a pulse width modulation signal based on a first output signal from the shift register and a second output signal from the independent bit cell; as well as The light-emitting circuit is configured to operate based on the pulse width modulation signal. During the first time period when the source selection multiplexer activates the second output signal as the pulse width modulation signal, the shift register is configured to perform a bit cyclic shift operation on the plurality of serial bit units.

2. The display pixel according to claim 1, wherein, The shift register is configured as follows: Between a first time point and a second time point included in a frame period, a first complete cyclic shift operation is performed on the plurality of serial bit units. Between the second and third time points included in the frame period, a second complete cyclic shift operation is performed on the plurality of serial bit units.

3. The display pixel according to claim 2, wherein, The shift register is configured as follows: Between the first time point and the second time point, the bit cyclic shift operation is repeated for the first number of times, the first number of times corresponding to the second number of the plurality of serial bit units.

4. The display pixel according to claim 2, wherein: The waveform of the pulse width modulation signal between the first time point and the second time point is different from the waveform of the pulse width modulation signal between the second time point and the third time point.

5. The display pixel according to claim 4, wherein: The combination of bits used to determine the logic level of the pulse width modulation signal between the first time point and the second time point is different from the combination of bits used to determine the logic level of the pulse width modulation signal between the second time point and the third time point.

6. The display pixel according to claim 2, wherein: The shift register is configured to output the first bit as the first output signal during a second time period between the first time point and the second time point. The shift register is configured to output the first bit as the first output signal during a third time period between the second time point and the third time point. The source selection multiplexer is configured to determine the logic level of the pulse width modulation signal during the second and third time periods based on the first bit.

7. The display pixel according to claim 6, wherein: The first time period is included between the first time point and the second time point. The source selection multiplexer is configured to activate the second output signal as the pulse width modulation signal during a fourth time period included between the second time point and the third time point.

8. The display pixel according to claim 6, wherein: The total duration during which the source select multiplexer activates the second output signal as the pulse width modulation signal during the frame period is twice the total duration during which the source select multiplexer determines the logic level of the pulse width modulation signal based on the first bit.

9. The display pixel according to claim 1, wherein: The plurality of serial bit units includes the first serial bit unit to the nth serial bit unit. The shift register also includes a feedback bit unit that stores the same bits as the first serial bit unit. During the first time period, the shift register is configured to move bits stored in the second serial bit unit to the nth serial bit unit to the first serial bit unit to the (n-1)th serial bit unit, respectively, move bits stored in the feedback bit unit to the nth serial bit unit, and copy bits stored in the first serial bit unit to the feedback bit unit.

10. The display pixel according to claim 1, wherein: The plurality of serial bit units are implemented as a plurality of serial latches connected in series with each other, and The independent bit unit is implemented as an independent latch.

11. The display pixel according to claim 1, wherein, The light-emitting circuit includes: Light-emitting diodes; and A driving transistor configured to operate based on the pulse width modulation signal, the driving transistor being connected between the power supply voltage and the light-emitting diode.

12. A display device, comprising: A column driver that is configured to output multiple bits; Display pixels, which are configured to store the plurality of bits; as well as The line driver is configured as follows: During the first segmented driving cycle, the display pixels are controlled to perform a first light emission operation for a first subset of the plurality of bits; as well as During the second segmented driving cycle, the display pixels are controlled to perform a second emission operation for a second subset of the plurality of bits, the second segmented driving cycle being included in the same frame cycle as the first segmented driving cycle. The first subset and the second subset include two or more common bits.

13. The display device according to claim 12, wherein: The first segmented driving cycle and the second segmented driving cycle are included in a subframe cycle.

14. The display device according to claim 12, wherein: The lengths of the first segmented driving cycle and the second segmented driving cycle are different from each other.

15. The display device according to claim 12, wherein: The plurality of bits includes the first to the nth bit. The display pixels include: A shift register configured to store the first bit to the (n-1)th bit; An independent bit unit, configured to store the nth bit; and The source selection multiplexer includes a first input terminal connected to the shift register, a second input terminal connected to the independent bit unit, and an output terminal for outputting a pulse width modulation signal.

16. The display device according to claim 15, wherein, The two or more common bits include: At least one of the first to the (n-1)th positions and the nth position.

17. The display device according to claim 12, further comprising: A timing control circuit, wherein the timing control circuit is configured to: Receive setting values ​​from the first external device; Receive pixel driving logic corresponding to the set value from a second external device; and The first subset and the second subset are determined based on the pixel-driven logic.

18. A display pixel, comprising: A shift register, configured to store the first and second bits; An independent bit unit, configured to store the third bit; A source selection multiplexer includes a first input terminal connected to the shift register, a second input terminal connected to the independent bit unit, and an output terminal for outputting a pulse width modulation signal. as well as A light-emitting circuit, configured to emit light based on the pulse width modulation signal, in: The source selection multiplexer is configured to determine the logic level of the pulse width modulation signal based on the first bit using the first number; The source selection multiplexer is configured to: determine the logic level of the pulse width modulation signal based on the second bit using a second number; and The first number is different from the second number.

19. The display pixel according to claim 18, wherein, The shift register is configured to perform a bit cyclic shift operation during a first time period in which the logic level of the pulse width modulation signal is determined based on the third bit.

20. The display pixel according to claim 18, wherein: During a frame period, the total duration for which the source select multiplexer determines the logic level of the pulse width modulation signal based on the logic level of the first input terminal is shorter than the total duration for which the source select multiplexer determines the logic level of the pulse width modulation signal based on the logic level of the second input terminal during the frame period.

Images