Display pixel and display device comprising the same

Abstract

According to embodiments of the disclosure, a display pixel and a display device including the same can be provided. The display device includes a column driver, a row driver, and a first display pixel including an in-pixel memory. The column driver controls a first data line and a second data line based on first pixel driving data including a plurality of pixel driving bits, and the row driver controls an operation of the first display pixel. The first display pixel writes one or more pixel driving bits among the plurality of pixel driving bits into the in-pixel memory during a first time period in which the first display pixel performs a first light emitting operation with respect to the first pixel driving data.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2025-0054021 filed with the Korean Intellectual Property Office on April 24, 2025 and Korean Patent Application No. 10-2025-0123160 filed with the Korean Intellectual Property Office on September 1, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor displays. More specifically, this disclosure relates to a display pixel and a display device including the display pixel. Background Technology

[0004] The brightness resolution of a display pixel operating with a pulse width modulation (PWM) scheme can be determined by the level (or degree) of precision of the duty cycle of the PWM signal used to adjust the light emitted by the display pixel.

[0005] Typically, the duty cycle of the PWM signal used to emit light for display pixels can be determined based on multiple pixel drive bits stored in in-pixel memory. Therefore, increasing the brightness resolution of display pixels operating with a PWM scheme may require a larger capacity of in-pixel memory. Consequently, achieving high brightness resolution with small display pixels may be technically difficult. Summary of the Invention

[0006] This disclosure aims to solve the aforementioned technical problems. More specifically, this disclosure relates to a display pixel having a small area and operating at high brightness resolution, and a display device including the display pixel.

[0007] According to one aspect of this disclosure, a display device is provided, comprising: a column driver configured to: receive first pixel driving data including a plurality of pixel driving bits and control a first data line and a second data line based on the first pixel driving data; a first display pixel including in-pixel memory and connected to the first data line and the second data line; and a row driver configured to control the operation of the first display pixel, wherein the first display pixel is configured to write one or more of the plurality of pixel driving bits into the in-pixel memory during a first time period, and during the first time period, the first display pixel performs a first light emission operation corresponding to the first pixel driving data.

[0008] According to another aspect of this disclosure, a display device is provided, comprising: a column driver configured to control one or more data lines based on first pixel driving data, the first pixel driving data including discard data having a first code length and retention data having a second code length; a display pixel connected to one or more of the data lines and including in-pixel memory having a capacity corresponding to the second code length; and a row driver configured to control the display pixel to perform a first emission operation based on the discard data during a first time period, and to control the display pixel to perform a second emission operation based on the retention data during a second time period after the first time period, wherein the in-pixel memory is configured to store the retention data during the second time period.

[0009] According to another aspect of this disclosure, a display pixel is provided, comprising: an in-pixel memory including a shift register and an independent bit cell; a source selection multiplexer configured to generate a pulse width modulation (PWM) signal based on a first output signal from the shift register and a second output signal from the independent bit cell; and a light-emitting circuit configured to perform a first light-emitting operation based on the PWM signal during a first time period during which a data write operation is performed in the in-pixel memory. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0011] Figure 2 To show in more detail Figure 1 A block diagram showing the configuration of the display pixels.

[0012] Figure 3 This is a timing diagram illustrating the driving method of the display pixels according to a comparison example.

[0013] Figure 4 The embodiments according to this disclosure are shown in more detail. Figure 2 A block diagram showing the configuration of the PWM control circuit.

[0014] Figure 5 This is a diagram illustrating the configuration of pixel driving data according to an embodiment of the present disclosure.

[0015] Figure 6 This is a circuit diagram showing in more detail the configuration of display pixels according to embodiments of the present disclosure.

[0016] Figure 7 This is a diagram showing in more detail the configuration of the PWM signal according to an embodiment.

[0017] Figures 8 to 11 This is a timing diagram showing in more detail the operation of a display device according to various embodiments of the present disclosure.

[0018] Figure 12 This is a diagram illustrating the effect in an example scenario where a column driver is implemented to provide pixel drive bits read from external memory to the data line.

[0019] Figure 13 This is a timing diagram illustrating, by way of driving display pixels according to an embodiment.

[0020] Figure 14 This is a timing diagram illustrating the frame period according to an embodiment.

[0021] Figure 15 This is a timing diagram illustrating the frame period according to an embodiment.

[0022] Figure 16 This is a timing diagram illustrating the frame period according to an embodiment.

[0023] Figure 17 This illustrates an embodiment in Figure 16 A diagram showing the state of the PWM signal during the previous light-emitting period.

[0024] Figure 18 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0025] Figure 19 It shows the basis in more detail. Figure 18 A diagram showing the configuration of the PWM signal in an embodiment.

[0026] Figure 20 It shows the basis Figure 19 Timing diagram of the driving method for display pixels in an embodiment. Detailed Implementation

[0027] In the following, embodiments of the present disclosure will be described clearly and in detail so that those skilled in the art can readily practice the present disclosure.

[0028] The components described below can be implemented as various types of software, such as firmware, applications, etc., or as various types of hardware, such as electrical circuits, electronic circuits, processors, etc. However, the scope of this disclosure is not limited thereto, and the components described below can be implemented as a combination of software and hardware.

[0029] Figure 1This is a block diagram illustrating a display device 100 according to an embodiment of the present disclosure. The display device 100 may include a display pixel array 110, a column driver 120, a row driver 130, and timing control circuitry 140. However, the present disclosure is not limited thereto, and therefore, according to embodiments, the display device 100 may include one or more other components.

[0030] In embodiments, the display device 100 may be included in various types of electronic devices, such as monitors, screens, augmented reality (AR) glasses, virtual reality (VR) headsets, etc.

[0031] The display pixel array 110 may include a plurality of display pixels PX. The plurality of display pixels PX may be arranged in a matrix along the row and column directions. However, the scope of this disclosure is not limited thereto, and the plurality of display pixels PX may be arranged in a zigzag pattern.

[0032] Each of the multiple display pixels PX can be connected to one or more data lines DL and one or more control lines CL. For example, display pixels PX arranged in the same row of display pixels can share one or more control lines CL, and display pixels PX arranged in the same column of display pixels can share one or more data lines DL.

[0033] In an embodiment, a display pixel PX arranged in the i-th display pixel row and j-th display pixel column of the display pixel array 110 may be referred to as "PXij". Display pixel PXij may be connected to one or more i-th control lines CL1 and one or more j-th data lines DL2. For example, display pixel PX12 may be connected to one or more first control lines CL1 and one or more second data lines DL2.

[0034] Column driver 120 can control multiple data lines DL. For example, column driver 120 can provide pixel drive data (hereinafter referred to as "PDD") to multiple display pixel columns through multiple data lines DL. For example, column driver 120 can provide different PDDs to multiple display pixel columns.

[0035] The line driver 130 can control multiple control lines CL. For example, the line driver 130 can provide pixel control signals (hereinafter referred to as "CTRL") to multiple display pixel rows via multiple control lines CL. For example, the line driver 130 can provide different CTRLs to multiple display pixel rows.

[0036] The line driver 130 can control multiple display pixels PXs on a per-display-pixel-row basis. For example, the line driver 130 can control the operation of display pixels PXs included in a display pixel row by controlling the logic level of the pixel control signal CTRL provided to the display pixel row. According to an embodiment, the line driver 130 can control the pixel control signal CTRL provided to a display pixel row to control the display pixels PXs included in the display pixel row to receive pixel drive data PDD from the data line DL, or to control the display pixels PXs included in the display pixel row to perform light emission operations based on the pixel drive data PDD.

[0037] The timing control circuit 140 can receive frame data D_FRM from an external device. For example, the external device may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. The timing control circuit 140 can provide the frame data D_FRM to the column driver 120. The frame data D_FRM may include multiple pixel drive data PDDs corresponding to different display pixels PX. The column driver 120 can divide the frame data D_FRM received from the timing control circuit 140 into pixel drive data PDD units and provide them to the display pixel array 110.

[0038] The timing control circuit 140 can control the overall operation of the display device 100. For example, the timing control circuit 140 can control the operating timing of the column driver 120 and the row driver 130.

[0039] In an embodiment, the display device 100 may include out-pixel memory circuitry 150. For example, out-pixel memory circuitry 150 may be located outside the display pixel array 110. Out-pixel memory circuitry 150 may store a portion of each of the plurality of pixel driver data PDDs of frame data D_FRM. For example, out-pixel memory circuitry 150 may temporarily store a portion of each of the plurality of pixel driver data PDDs of frame data D_FRM. For example, timing control circuitry 140 may temporarily store a first portion of each pixel driver data PDD in out-pixel memory circuitry 150 and provide a second portion of each pixel driver data PDD to column driver 120. In this case, column driver 120 may control one or more data lines DL based on bits included in the second portion of each pixel driver data PDD. Subsequently, timing control circuitry 140 may read the first portion of each pixel driver data PDD from out-pixel memory circuitry 150 and provide them to column driver 120. In this case, column driver 120 may control one or more data lines DL based on bits included in the first portion of each pixel driver data PDD. In this way, column driver 120 can provide different portions of a pixel driving data PDD to display pixel PX at different time intervals (e.g., in a time-division manner). However, the scope of this disclosure is not limited thereto. For example, display device 100 may be implemented without external pixel memory circuitry 150, or external pixel memory circuitry 150 may be implemented to store the entire pixel driving data PDD.

[0040] In embodiments, the external memory circuit 150 can be implemented as a volatile memory device, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc. However, the scope of this disclosure is not limited thereto, and the external memory circuit 150 can also be implemented as a non-volatile memory device, such as flash memory.

[0041] According to one embodiment, in the example where the external memory circuit 150 is implemented to store the entire pixel drive data PDD, the external memory circuit 150 may be referred to as a "frame buffer". However, the scope of this disclosure is not limited to these terms.

[0042] Figure 2 To show in more detail Figure 1 A block diagram showing the configuration of the display pixels. (Refer to...) Figure 1 and Figure 2 The display pixel PX may include a pulse width modulation (PWM) control circuit PCC and a light-emitting circuit LEC. The PWM control circuit PCC may include pixel in-pixel memory IPM.

[0043] In embodiments, the in-pixel memory (IPM) may also be referred to as memory-in-pixel. However, the scope of this disclosure is not limited to these terms.

[0044] The PWM control circuit PCC can receive pixel drive data PDD through one or more data lines DL, and can receive multiple pixel control signals CTRL through one or more control lines CL.

[0045] The PWM control circuit PCC can generate a PWM signal SPWM corresponding to the pixel drive data PDD based on multiple pixel control signals CTRL. For example, the PWM control circuit PCC can generate a PWM signal SPWM corresponding to the pixel drive data PDD in response to multiple pixel control signals CTRL.

[0046] The PWM signal SPWM can include multiple bit emission periods (hereinafter referred to as "BEMs") having logic levels corresponding to the values ​​of the pixel drive data PDD. The PWM control circuit PCC can determine the logic level of the PWM signal SPWM during the multiple bit emission periods BEMs based on the bits included in the pixel drive data PDD. For example, the PWM control circuit PCC can store one or more bits included in the pixel drive data PDD into the in-pixel memory IPM based on multiple pixel control signals CTRL, and can determine the logic level of the PWM signal SPWM during the bit emission period BEM based on one or more bits stored in the in-pixel memory IPM. For example, the PWM control circuit PCC can store one or more bits included in the pixel drive data PDD into the in-pixel memory IPM in response to multiple pixel control signals CTRL.

[0047] In an embodiment, each bit included in the pixel-driven data PDD may be referred to as a "pixel-driven bit". However, the scope of this disclosure is not limited to these terms.

[0048] The duty cycle (e.g., duty ratio) of the PWM signal SPWM can be determined based on the magnitude of the pixel drive data PDD. For example, as the size of the pixel drive data PDD increases, the PWM control circuit PCC can generate a PWM signal SPWM that remains high for a larger proportion of the time, and as the size of the pixel drive data PDD decreases, the PWM control circuit PCC can generate a PWM signal SPWM that remains high for a smaller proportion of the time. However, the scope of this disclosure is not limited thereto.

[0049] According to an embodiment, the light-emitting circuit (LEC) can operate based on a PWM signal SPWM. For example, the LEC can operate in response to the PWM signal SPWM. For example, the LEC may include a light-emitting diode that is turned on or off based on the logic level of the PWM signal SPWM.

[0050] The brightness of a display pixel PX as perceived by the human eye (e.g., the brightness of a light-emitting circuit (LEC)) can be determined based on the duration of light emission from the LEC. The duration of light emission from the LEC can also be determined based on pixel drive data PDD. Therefore, to finely adjust the brightness of a display pixel PX (e.g., to drive the display pixel PX with higher brightness resolution), a large-capacity pixel drive data PDD may be required. However, to generate a PWM signal SPWM corresponding to the large-capacity pixel drive data PDD, a large-capacity in-pixel memory (IPM) is typically required. Therefore, it may be technically difficult to achieve high brightness resolution with a small-area display pixel PX.

[0051] According to embodiments of the present disclosure, the display pixel PX can generate a PWM signal SPWM corresponding to a large-capacity pixel drive data PDD based on a relatively small-capacity in-pixel memory (IPM). For example, the capacity of the in-pixel memory (IPM) included in the display pixel PX according to embodiments of the present disclosure can be smaller than the capacity of the pixel drive data PDD. In this case, high brightness resolution can be achieved using a small-area display pixel PX. Therefore, according to embodiments of the present disclosure, high brightness resolution can be achieved using a small area of ​​the display pixel array 110. According to embodiments of the present disclosure, the display device 100 can be miniaturized.

[0052] For a more detailed example, the capacity of the pixel drive data PDD can be greater than the capacity of the in-pixel memory IPM. In this case, the PWM control circuit PCC can store a portion of the pixel drive data PDD (e.g., one or more of a plurality of pixel drive bits) in the in-pixel memory IPM based on (or in response to) multiple pixel control signals CTRL, and can determine the logic level of one or more bit emit cycles BEM based on the stored bits of the pixel drive data PDD. Subsequently, the PWM control circuit PCC can update the in-pixel memory IPM based on another portion included in the pixel drive data PDD (e.g., bits among the plurality of pixel drive bits that have not yet been used to determine the logic level of the PWM signal SPWM). In this case, the PWM control circuit PCC can determine the logic level of one or more bit emit cycles BEM corresponding to the newly stored bits in the in-pixel memory IPM. The operation scheme of displaying a pixel PX in the example case where the capacity of the pixel drive data PDD is greater than the capacity of the in-pixel memory IPM will be described in more detail below.

[0053] Figure 3 This is a timing diagram illustrating the driving method for display pixels according to a comparative example. (See reference...) Figures 1 to 3 A frame period (FRM) can include a data write period (DW) and a light emission period (TEM). The data write period (DW) can precede the light emission period (TEM).

[0054] For the sake of brevity, the following description of an embodiment in which one frame period (FRM) includes a single emission period (TEM) is presented as a representative example, but the scope of this disclosure is not limited thereto. For example, a frame period (FRM) may include multiple subframes, and each subframe may include a single emission period (TEM).

[0055] Display pixel PX can store pixel drive data PDD in pixel in-pixel memory (IPM) during the data write period (DW). For example, column driver 120 can provide bits included in the pixel drive data PDD to display pixel PX via one or more data lines DL. PWM control circuit PCC can store the pixel drive data PDD indicated by one or more data lines DL in pixel in-pixel memory (IPM) based on or in response to multiple pixel control signals CTRL.

[0056] Display pixels (PX) can perform illumination operations based on pixel driving data (PDD) stored in the in-pixel memory (IPM) during the illumination period (TEM). For example, a PWM control circuit (PCC) can perform illumination operations based on or in response to multiple pixel control signals (CTRL) and the pixel driving data (PDD) stored in the IPM. For instance, the PCC can generate a PWM signal (SPWM) based on the pixel driving data (PDD) stored in the IPM. The illumination circuit (LEC) can then perform illumination operations based on the PWM signal (SPWM).

[0057] according to Figure 3 In this embodiment, after the data write operation of writing pixel driving data PDD to the in-pixel memory IPM is completed, the display pixel PX can perform a light emission operation based on the pixel driving data PDD stored in the in-pixel memory IPM. In this case, the brightness resolution of the display pixel PX can be determined based on the pixel driving data PDD stored in the in-pixel memory IPM during the data write period DW. Therefore, the brightness resolution achieved based on the display pixel PX may be limited by the capacity of the in-pixel memory IPM.

[0058] Figure 4 The embodiments according to this disclosure are shown in more detail. Figure 2 A block diagram of the PWM control circuit configuration. (Refer to...) Figures 1 to 4The PWM control circuit PCC may include pixel in-memory (IPM) and source selection multiplexer (MUX_SRC).

[0059] For a more concise explanation, an embodiment with an 8-bit capacity of the in-pixel memory (IPM) is described below as a representative example. However, the scope of this disclosure is not limited thereto. For example, the in-pixel memory (IPM) may have a capacity of less than or greater than 8 bits.

[0060] According to an embodiment, the in-pixel memory (IPM) may include a shift register SR and independent bit units (CIDPs). The shift register SR may include first bit units C1 to seventh bit units C7 and a feedback unit CFB. The independent bit unit CIDP may include an eighth bit unit C8.

[0061] For simplicity, the following description assumes that the in-pixel memory (IPM) comprises a single independent bit cell (CIDP). However, the scope of this disclosure is not limited thereto. For example, the IPM may comprise two or more independent bit cells (CIDPs).

[0062] The shift register SR and the independent bit cell CIDP can be connected to different data lines DL. For example, the shift register SR can be connected between the first data line DLa and the source select multiplexer MUX_SRC, and the independent bit cell CIDP can be connected between the second data line DLb and the source select multiplexer MUX_SRC. That is, the independent bit cell CIDP can be physically and electrically separated from the shift register SR.

[0063] Column driver 120 can provide different subsets of pixel-driven data PDD to shift register SR and independent bit cell CIDP. For example, column driver 120 can allocate multiple pixel-driven bits included in pixel-driven data PDD to first data line DLa and second data line DLb.

[0064] The shift register SR can store multiple pixel drive bits provided from the first data line DLa in the first unit C1 to the seventh unit C7 and the feedback unit CFB. The shift register SR can output a voltage level corresponding to the bit stored in the first unit C1 as an output signal. That is, the logic level of the output signal of the shift register SR can correspond to the bit stored in the first unit C1.

[0065] The Independent Bit Module (CIDP) can store pixel drive bits provided from the second data line DLb. The CIDP can also output a voltage level corresponding to the bit stored in the CIDP as an output signal. In other words, the logic level of the output signal of the CIDP can correspond to the bit stored in the eighth bit module C8.

[0066] The source selection multiplexer MUX_SRC may include a first input terminal connected to the shift register SR and a second input terminal connected to the independent bit unit CIDP. The source selection multiplexer MUX_SRC may also include an output terminal for an output PWM signal SPWM. That is, the source selection multiplexer MUX_SRC can generate the PWM signal SPWM by multiplexing the output signal from the shift register SR and the output signal from the independent bit unit CIDP. In other words, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the output signal from the shift register SR and the output signal from the independent bit unit CIDP.

[0067] Therefore, when the logic level of the PWM signal SPWM is determined based on the bits stored in the independent bit cell CIDP, the output of the shift register SR may not affect the logic level of the PWM signal SPWM. For example, although the logic level of the PWM signal SPWM is determined based on the bits stored in the independent bit cell CIDP, even in the example case where the data stored in the shift register SR changes, the logic level of the PWM signal SPWM can be determined solely based on the bits stored in the eighth bit cell C8. Conversely, although the logic level of the PWM signal SPWM is determined based on the bits stored in the shift register SR, the output of the independent bit cell CIDP may not affect the logic level of the PWM signal SPWM. For example, although the logic level of the PWM signal SPWM is determined based on the bits stored in the shift register SR, even in the example case where the data stored in the independent bit cell CIDP changes, the logic level of the PWM signal SPWM can be determined solely based on the bits stored in the first bit cell C1. Below, based on the characteristics of the display pixel PX described above, a specific scheme for driving the display pixel PX based on pixel drive data PDD, which has a larger capacity than the pixel in-memory IPM, will be described.

[0068] Figure 5 This is a diagram illustrating the configuration of pixel driving data according to an embodiment of the present disclosure. (Refer to...) Figures 1 to 5 Pixel-driven data (PDD) may include multiple pixel-driven bits (D). For example, pixel-driven data (PDD) may include first pixel-driven bits (D1) to thirteenth pixel-driven bits (D13).

[0069] The pixel-driven data (PDD) can include discarded data (D_DSCD) and retained data (D_RTN). Discarded data (D_DSCD) can be data that is deleted after the light used to emit the display pixel (PX) is emitted, and retained data (D_RTN) can be data that is not deleted after the light used to emit the display pixel (PX) is emitted.

[0070] The code length of the reserved data D_RTN can correspond to the capacity of the in-pixel memory (IPM). For example, the reserved data D_RTN may include the sixth pixel driver bit D6 to the thirteenth pixel driver bit D13.

[0071] The code length of the discarded data D_DSCD can correspond to the value obtained by subtracting the capacity of the in-pixel memory (IPM) from the code length of the pixel drive data PDD. For example, the discarded data D_DSCD may include the first pixel drive bits D1 to the fifth pixel drive bits D5.

[0072] In an embodiment, the discarded data D_DSCD can be implemented as the low-order bits of the pixel drive data PDD, and the retained data D_RTN can be implemented as the high-order bits of the pixel drive data PDD. For example, the discarded data D_DSCD can be implemented using the low 5 bits of the pixel drive data PDD, and the retained data D_RTN can be implemented using the high 8 bits of the pixel drive data PDD. The low-order bits of the pixel drive data PDD can be used to determine the logic level of the bit emission period BEM, which has a relatively short duration. Therefore, the discarded data D_DSCD can be quickly discarded from the display pixel PX, and then the retained data D_RTN can be newly stored in the display pixel PX. Furthermore, in the example case where the display pixel PX is implemented to use the retained data D_RTN multiple times to determine the logic level of the PWM signal SPWM (e.g., if the display pixel PX is driven in a subframe manner), even if the discarded data D_DSCD is removed from the display pixel PX, the brightness variation of the display pixel PX can be minimized. However, the scope of this disclosure is not limited thereto.

[0073] The pixel-driven data PDD may include real-time data D_RLTM and buffer data D_BF. Timing control circuitry 140 can store some bits of the pixel-driven data PDD in external memory circuitry 150 and can directly provide other bits of the pixel-driven data PDD to column driver 120. After a certain amount of time, timing control circuitry 140 can read a portion of the pixel-driven data PDD from external memory circuitry 150 and can provide the read bits to column driver 120. In this case, column driver 120 can receive real-time data D_RLTM and buffer data D_BF included in a pixel-driven data PDD at different time points.

[0074] For a more detailed example, the real-time data D_RLTM may include the first pixel driving bits D1 through the twelfth pixel driving bits D12, and the buffered data D_BF may include the thirteenth pixel driving bit D13. However, the scope of this disclosure is not limited thereto.

[0075] In an embodiment, the buffer data D_BF can be implemented as one or more high-order bits of the pixel drive data PDD. For example, the buffer data D_BF may include the thirteenth pixel drive bit D13, which is the most significant bit (MSB) of the pixel drive data PDD.

[0076] In this embodiment, the pixel-driven data PDD may not include the buffered data D_BF. For example, the timing control circuit 140 may directly provide the entire frame data D_FRM provided from an external source to the column driver 120.

[0077] In an embodiment, one or more pixel drive bits D may be included in both real-time data D_RLTM and buffered data D_BF. For example, timing control circuitry 140 may be implemented to provide specific pixel drive bits D to column driver 120 in real time, and may back up specific pixel drive bits D to off-pixel memory circuitry 150. However, the scope of this disclosure is not limited thereto.

[0078] Figure 6 This is a circuit diagram illustrating in more detail the configuration of display pixels according to embodiments of the present disclosure. (Refer to...) Figures 1 to 6 The display pixel PX may include a PWM control circuit PCC and a light-emitting circuit LEC.

[0079] The PWM control circuit PCC may include a feedback multiplexer MUX_FB, a shift register SR, an independent bit cell CIDP, and a source selection multiplexer MUX_SRC.

[0080] The pixel control signal CTRL may include one or more shift register control signals CS_SR, feedback enable signal FB_EN, independent bit cell control signal CS_CIDP, source selection signal SEL_SRC, and PWM enable signal PWM_EN.

[0081] The first input terminal of the feedback multiplexer MUX_FB can be connected to the first data line DLa. The output terminal of the feedback multiplexer MUX_FB can be connected to the first node NA. The first node NA can be connected to the input terminal of the shift register SR. The second input terminal of the feedback multiplexer MUX_FB can be connected to the second node NB. The second node NB can be connected to the output terminal of the shift register SR.

[0082] The feedback multiplexer MUX_FB can operate based on the feedback enable signal FB_EN. For example, the feedback multiplexer MUX_FB can operate in response to the feedback enable signal FB_EN. For example, the feedback multiplexer MUX_FB can determine the logic level of the first node NA based on the logic level of the first data line DLa when the logic level of the feedback enable signal FB_EN is logic low. When the logic level of the feedback enable signal FB_EN is logic high, the feedback multiplexer MUX_FB can determine the logic level of the first node NA based on the logic level of the second input terminal (e.g., the second node NB). For example, when the logic level of the feedback enable signal FB_EN is logic low, the output at the first node NA is based on the first data line DLa, and when the logic level of the feedback enable signal FB_EN is logic high, the output at the first node NA is based on the logic level of the second node NB.

[0083] The shift register SR can be connected between the first node NA and the second node NB. The shift register SR may include a feedback unit CFB and first-bit units C1 to C7 connected in series between the first node NA and the second node NB. The feedback unit CFB can be connected to the first node NA, and the first-bit unit C1 can be connected to the second node NB.

[0084] For a more concise explanation, the following description uses an embodiment where the feedback unit CFB is placed between the feedback multiplexer MUX_FB and the seventh unit C7 as a representative example. However, the scope of this disclosure is not limited thereto. For example, the feedback unit CFB may be placed between the first unit C1 and the source selection multiplexer MUX_SRC.

[0085] The Independent Bit Unit (CIDP) may include an eighth bit unit C8. That is, the Independent Bit Unit (CIDP) can be implemented to store 1 bit. However, the scope of this disclosure is not limited thereto.

[0086] Each of the first unit C1 through the eighth unit C8 and the feedback unit CFB can be implemented as a latch. For example, the first unit C1 through the seventh unit C7 and the feedback unit CFB can be implemented as a latch configured to change the stored bit value based on or in response to the first shift register control signal CS_SR1 through the eighth shift register control signal CS_SR8, respectively. The eighth unit C8 can be implemented as a latch configured to change the stored data value based on or in response to the independent bit unit control signal CS_CIDP. However, the scope of this disclosure is not limited thereto, and each of the first unit C1 through the eighth unit C8 and the feedback unit CFB can be implemented as any type of data storage element, such as a flip-flop. In the example case where each of the first unit C1 through the seventh unit C7 and the feedback unit CFB is implemented as a flip-flop, the first unit C1 through the seventh unit C7 and the feedback unit CFB can be implemented to share a single shift register control signal CS_SR.

[0087] In the embodiments, each of the first unit C1 to the seventh unit C7 may be referred to as a "serial bit unit" or a "serial latch". The eighth unit C8 may be referred to as an "independent bit unit" or an "independent latch". However, the scope of this disclosure is not limited to these terms.

[0088] In an embodiment, the feedback unit CFB may operate based on the eighth shift register control signal CS_SR8. For example, the feedback unit CFB may operate in response to the eighth shift register control signal CS_SR8. From this perspective, the eighth shift register control signal CS_SR8 may also be referred to as the "shift register feedback control signal". However, the scope of this disclosure is not limited to these terms.

[0089] The shift register SR can receive multiple pixel drive bits D from the first data line DLa via the feedback multiplexer MUX_FB based on the first shift register control signals CS_SR1 to the eighth shift register control signals CS_SR8. For example, the shift register SR can sequentially receive multiple pixel drive bits D in response to the first shift register control signals CS_SR1 to the eighth shift register control signals CS_SR8, and store the multiple pixel drive bits D in the first unit C1 to the seventh unit C7 and the feedback unit CFB.

[0090] The Independent Bit Module (CIDP) can store the bit indicated by the second data line DLb. For example, the CIDP can receive and store the pixel drive bit D from the second data line DLb based on or in response to the Independent Bit Module Control (CS_CIDP) signal.

[0091] The logic level of the output signal of the shift register SR corresponds to the bit stored in the first unit C1. The logic level of the output signal of the independent bit unit CIDP corresponds to the bit stored in the eighth unit C8.

[0092] In an embodiment, the shift register SR can perform bit rotation operations on the first unit C1 to the seventh unit C7 based on the control of the row driver 130. For example, in response to the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8, the shift register SR can move bits stored in the second unit C2 to the seventh unit C7 to the first unit C1 to the sixth unit C6, move bits stored in the feedback unit CFB to the seventh unit C7, and copy bits stored in the first unit C1 to the feedback unit CFB. Therefore, bits stored in the first unit C1 to the seventh unit C7 can be rotated (or shifted), and the feedback unit CFB can store the same bits as the first unit C1. However, the scope of this disclosure is not limited thereto.

[0093] In an embodiment, the feedback unit CFB can be used to temporarily store the pixel driver bit D stored in the first unit C1 for bit rotation operations of the shift register SR, or to transfer the pixel driver bit D provided from the feedback multiplexer MUX_FB to the first unit C1 through the seventh unit C7. That is, the feedback unit CFB can be implemented as a temporary storage of pixel driver bits for operations on the shift register SR. However, the scope of this disclosure is not limited thereto.

[0094] In an embodiment, the capacity of the in-pixel memory (IPM) can correspond to the sum of the number of pixel drive bits that can be stored in the shift register SR (e.g., 7, which is the number of bits that can be stored in the first unit C1 to the seventh unit C7) and the number of pixel drive bits that can be stored in the independent bit unit CIDP (e.g., 1, which is the number of bits that can be stored in the eighth unit C8). That is, when determining the capacity of the in-pixel memory (IPM), the number of bits that can be stored in the feedback unit CFB may not be included in the capacity. However, the scope of this disclosure is not limited thereto.

[0095] The first input terminal of the source selection multiplexer MUX_SRC can be connected to the second node NB (or the first unit C1). That is, the first input terminal of the source selection multiplexer MUX_SRC can receive the output signal from the shift register SR.

[0096] The second input terminal of the source selection multiplexer MUX_SRC can be connected to the eighth bit unit C8. That is, the second input terminal of the source selection multiplexer MUX_SRC can receive the output signal from the independent bit unit CIDP.

[0097] The output terminal of the source selection multiplexer MUX_SRC can output a PWM signal SPWM. That is, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the logic level of the first input terminal and the logic level of the second input terminal.

[0098] According to an embodiment, the source selection multiplexer MUX_SRC can operate based on the source selection signal SEL_SRC. For example, the source selection multiplexer MUX_SRC can operate in response to the source selection signal SEL_SRC. For example, when the logic level of the source selection signal SEL_SRC is logic low, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the bits stored in the first bit unit C1. When the logic level of the source selection signal SEL_SRC is logic high, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the bits stored in the eighth bit unit C8.

[0099] In one embodiment, the row driver 130 can control the display pixel PX to sequentially change the pixel drive bits D stored in the first bit unit C1 and the eighth bit unit C8. In this case, the pixel drive bits D used to determine the logic level of the PWM signal SPWM can be changed sequentially. In this way, the row driver 130 can control multiple pixel control signals CTRL to cause the source selection multiplexer MUX_SRC to generate the PWM signal SPWM including multiple bit emit cycles BEM.

[0100] In an embodiment, the row driver 130 can freely determine the time period during which the logic level of the PWM signal SPWM is determined based on the bits stored in the Independent Bit Module (CIDP) (e.g., regardless of the order with other bit emission periods (BEMs)). For example, the row driver 130 can divide the bit emission period (BEM) corresponding to the bits stored in the CIDP into multiple sub-bit emission periods (hereinafter referred to as "SUB_BEM"). Therefore, during a light emission period (TEM), the source selection multiplexer (MUX_SRC) can determine the logic level of the PWM signal SPWM based on the bits stored in the CIDP two or more times. In this case, various problems such as the false contour effect caused by the length of the bit emission period (BEM) can be minimized, thus improving the quality of the image generated by the display device 100. However, the scope of this disclosure is not limited thereto, and the row driver 130 may not divide the bit emission period (BEM) corresponding to the bits stored in the CIDP.

[0101] The light-emitting circuit LEC may include a PWM gate GT_PWM, a first driving transistor DT1, a second driving transistor DT2, and a light-emitting diode ED.

[0102] The PWM gate GT_PWM can gate the PWM signal SPWM based on the PWM enable signal PWM_EN. For example, the PWM gate GT_PWM can gate the PWM signal SPWM in response to the PWM enable signal PWM_EN. For example, in response to the PWM enable signal PWM_EN, the PWM gate GT_PWM can generate a gated PWM signal SPWMgtd by gated the PWM signal SPWM.

[0103] The first driving transistor DT1 and the second driving transistor DT2 can be connected in series between the power supply voltage ELVDD and the light-emitting diode ED. The light-emitting diode ED can be connected to the ground voltage ELVSS. The gate terminal of the first driving transistor DT1 can receive the gated PWM signal SPWMgtd. The gate terminal of the second driving transistor DT2 can receive the bias voltage VBIAS.

[0104] The first driving transistor DT1 can supply the power supply voltage ELVDD to the second driving transistor DT2 during the period when the gated PWM signal SPWMgtd is logic low. In this case, current can be supplied to the light-emitting diode ED through the second driving transistor DT2, and the light-emitting diode ED can be turned on (e.g., generated).

[0105] The first driving transistor DT1 can electrically isolate the power supply voltage ELVDD from the second driving transistor DT2 during the period when the gated PWM signal SPWMgtd is logic high. In this case, the second driving transistor DT2 can be turned off, and therefore the light-emitting diode ED can be turned off. For example, the light-emitting diode ED may not generate light.

[0106] In this embodiment, the first driving transistor DT1 and the second driving transistor DT2 can be implemented as p-channel metal-oxide-semiconductor transistors (PMOS). In this case, the PWM gate GT_PWM can perform a logical NAND operation. For example, the PWM gate GT_PWM can determine the gated PWM signal SPWMgtd as logic high when the PWM enable signal PWM_EN is logic low, and can determine the gated PWM signal SPWMgtd as the opposite logic level of the PWM signal SPWM when the PWM enable signal PWM_EN is logic high. However, the scope of this disclosure is not limited thereto. For example, the first driving transistor DT1 and the second driving transistor DT2 can be implemented as n-channel metal-oxide-semiconductor transistors (NMOS). In this case, the PWM gate GT_PWM can perform a logical AND operation.

[0107] In this embodiment, the light-emitting circuit LEC may not include the second driving transistor DT2. For example, the light-emitting diode ED may be directly connected to the first driving transistor DT1. That is, the scope of this disclosure is not limited to any specific implementation of the light-emitting circuit LEC.

[0108] Figure 7 This is a diagram illustrating in more detail the configuration of the PWM signals according to an embodiment. (Refer to...) Figures 1 to 7 The display pixel (PX) can be operated based on the 13-bit pixel drive data (PDD). For a more concise explanation, the following description uses a configuration including a single emission period (TEM) within a frame period (FRM) as a representative example.

[0109] According to an embodiment, the light-emitting circuit (LEC) emits light during the light-emitting period (TEM) based on the logic level of the PWM signal SPWM. For example, the LEC can determine whether to emit light during the TEM based on the logic level of the PWM signal SPWM. The TEM may include a plurality of bit emission periods (BEMs). Each of the plurality of bit emission periods (BEMs) may correspond to a different bit included in the pixel drive data (PDD). For example, the TEM may include the first emission period (BEM1) to the thirteenth emission period (BEM13) corresponding to the first pixel drive bits D1 to the thirteenth pixel drive bits D13, respectively.

[0110] For a more concise explanation, the following description is a representative example in which the first emission period BEM1 to the thirteenth emission period BEM13 are arranged sequentially within the emission period TEM. However, the scope of this disclosure is not limited thereto. For example, the first emission period BEM1 to the thirteenth emission period BEM13 can be arranged in any order within the emission period TEM.

[0111] Reference Figure 7 The durations of the first transmission period (BEM1) to the thirteenth transmission period (BEM13) can form a geometric series with a common ratio of 2. For example, the duration of the first transmission period (BEM1) can be "1 UT", and the duration of the second transmission period (BEM2) can be "2 UT". Thus, the duration of the thirteenth transmission period (BEM13) can be "4096 UT". However, the scope of this disclosure is not limited to this. For example, the duration of each of the first transmission periods (BEM1) to the thirteenth transmission period (BEM13) can form any type of sequence other than a geometric series.

[0112] In embodiments, "1UT" can be a unit used to describe the relative length of multiple bit transmit cycles (BEMs). However, the scope of this disclosure is not limited to a specific time length "1UT".

[0113] The PWM control circuit PCC can determine the logic level of the PWM signal SPWM for each of the first transmit cycles BEM1 to the eighth transmit cycle BEM8 based on the corresponding pixel drive bit D. For example, the PWM control circuit PCC can determine the logic level of the PWM signal SPWM during the first transmit cycle BEM1 based on the least significant bit (LSB) of the pixel drive data PDD (e.g., the first pixel drive bit D1), and can determine the logic level of the PWM signal SPWM during the thirteenth transmit cycle BEM13 based on the MSB of the pixel drive data PDD (e.g., the thirteenth pixel drive bit D13).

[0114] Figures 8 to 11 This is a timing diagram illustrating in detail the operation of a display device according to various embodiments of the present disclosure. In the following, reference is made to... Figures 1 to 11 The description will be based on Figure 7 The embodiments describe different methods of driving display pixels PX during a frame period (FRM). For a more concise explanation below, it can be assumed that display pixels PX include 8 bits of in-pixel memory (IPM) and operate based on 13 bits of pixel drive data (PDD), and column driver 120 provides the MSB of the pixel drive data PDD (e.g., the thirteenth pixel drive bit D13) to the second data line DLb.

[0115] Reference Figure 8The column driver 120 can output the first pixel driver bit D1 to the twelfth pixel driver bit D12 through the first data line DL1, and can output the thirteenth pixel driver bit D13 through the second data line DLb. That is to say, the column driver 120 can output only one pixel driver bit D through the second data line DLb.

[0116] During the data write period (DW), the display pixel PX can store multiple pixel drive bits D in the shift register SR and the independent bit unit CIDP. During the emission period (TEM), the display pixel PX can perform an emission operation based on the pixel drive bits D stored in the pixel in-pixel memory (IPM). A method for driving the display pixel PX according to an embodiment is described in detail.

[0117] The row driver 130 can set the feedback enable signal FB_EN to logic low during the data write period DW. For example, the row driver 130 can set the feedback enable signal FB_EN to logic low between the first time point t1 and the data write completion time point tDWC. In this case, the feedback multiplexer MUX_FB can be able to provide the logic level indicated by the first data line DLa to the shift register SR.

[0118] For example, between the first time point t1 and the eighth time point t8, the column driver 120 can sequentially provide the first pixel driver bits D1 to the seventh pixel driver bits D7 to the first data line DLa. In this case, the shift register SR can sequentially store the first pixel driver bits D1 to the seventh pixel driver bits D7 via the feedback multiplexer MUX_FB based on the control of the row driver 130.

[0119] According to an embodiment, between a first time point t1 and a second time point t2, column driver 120 may provide a first pixel drive bit D1 to a first data line DLa. Row driver 130 may sequentially switch a first shift register control signal CS_SR1 to an eighth shift register control signal CS_SR8 (e.g., from logic low to logic high, and then back to logic low). In this case, the first pixel drive bit D1 may be stored in the feedback unit CFB.

[0120] Subsequently, between the second time point t2 and the third time point t3, column driver 120 can provide the second pixel drive bit D2 to the first data line DLa. Row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. In this case, the first pixel drive bit D1 stored in the feedback unit CFB can be shifted to the seventh bit unit C7, and the second pixel drive bit D2 can be newly stored in the feedback unit CFB.

[0121] In this way, column driver 120 can sequentially provide the third pixel driver bit D3 to the seventh pixel driver bit D7 to the first data line DLa between the third time point t3 and the eighth time point t8. Row driver 130 can sequentially store the third pixel driver bit D3 to the seventh pixel driver bit D7 in shift register SR by controlling the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. Therefore, at the eighth time point t8, the first pixel driver bit D1 to the sixth pixel driver bit D6 can be stored in the second bit unit C2 to the seventh bit unit C7 respectively, and the seventh bit D7 can be stored in the feedback unit CFB.

[0122] In an embodiment, the point in time at which driving the display pixel PX begins within a frame period (FRM) can be referred to as the drive start point tDBGN. For example, the drive start point tDBGN can refer to the first point in time t1 at which the column driver 120 begins to provide the pixel drive bit D via the first data line DLa.

[0123] For a more concise explanation, Figure 7 A representative embodiment is described in which the row driver 130 sequentially switches all shift register control signals from the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8 whenever a new bit is stored in the shift register SR, but the scope of this disclosure is not limited thereto. For example, between the first time point t1 and the second time point t2, the row driver 130 can store the first pixel drive bit D1 in the feedback unit CFB by switching only the eighth shift register control signal CS_SR8. Similarly, between the second time point t2 and the eighth time point t8, the row driver 130 can store the first pixel drive bits D1 to the seventh pixel drive bits D7 in the shift register SR without switching some of the shift register control signals CS_SR. In this case, the power consumption of the row driver 130 can be minimized.

[0124] The horizontal driver 130 can set the PWM enable signal PWM_EN high during the light-emitting period TEM. For example, the horizontal driver 130 can set the PWM enable signal PWM_EN high between the eighth time point t8 and the sixteenth time point t16. In this case, the PWM gate GT_PWM can determine the logic level of the gated PWM signal SPWMgtd based on the logic level of the PWM signal SPWM. For example, the PWM gate GT_PWM can determine the logic level of the gated PWM signal SPWMgtd by inverting the logic level of the PWM signal SPWM.

[0125] The emission period TEM can include the first emission period BEM1 to the thirteenth emission period BEM13. The source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM for the first emission period BEM1 to the twelfth emission period BEM12 based on the output signal from the shift register SR, and can determine the logic level of the PWM signal SPWM for the thirteenth emission period BEM13 based on the output signal from the independent bit cell CIDP. For example, the row driver 130 can set the source selection signal SEL_SRC to logic low between the eighth time point t8 and the fifteenth time point t15 corresponding to the first emission period BEM1 to the twelfth emission period BEM12, and can set the source selection signal SEL_SRC to logic high between the fifteenth time point t15 and the sixteenth time point t16 corresponding to the thirteenth emission period BEM13.

[0126] During the time period between the eighth time point t8 and the ninth time point t9 corresponding to the first transmission period BEM1, the PWM control circuit PCC can determine the logic level of the PWM signal SPWM based on the first pixel drive bit D1 and write the eighth pixel drive bit D8 into the shift register SR. For example, the column driver 120 can provide the eighth pixel drive bit D8 to the first data line DLa at the eighth time point t8. The row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. In this case, the first pixel drive bits D1 to the seventh pixel drive bits D7 can be stored in the first unit C1 to the seventh unit C7 respectively, and the eighth pixel drive bit D8 can be written into the feedback unit CFB. Furthermore, when the source selection signal SEL_SRC is logic low, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM during the first transmission period BEM1 based on the first pixel drive bit D1 stored in the first unit C1.

[0127] Subsequently, during the time period between the ninth time point t9 and the tenth time point t10 corresponding to the second bit transmission period BEM2, the shift register SR can delete the first pixel drive bit D1 and newly store the ninth pixel drive bit D9, and the PWM control circuit PCC can determine the logic level of the PWM signal SPWM based on the second pixel drive bit D2. For example, the column driver 120 can provide the ninth pixel drive bit D9 to the first data line DLa at the ninth time point t9. The row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. In this case, the first pixel drive bit D1 stored in the first unit C1 can be deleted, the second pixel drive bits D2 to the eighth pixel drive bits D8 stored in the second unit C2 to the seventh unit C7 and the feedback unit CFB can be shifted to the first unit C1 to the seventh unit C7, and the ninth pixel drive bit D9 can be newly stored in the feedback unit CFB. Since the first unit C1 is updated using the second pixel drive bit D2, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the second pixel drive bit D2 during the second bit transmit cycle BEM2.

[0128] In this way, during the time period between the tenth time point t10 and the thirteenth time point corresponding to the third to fifth transmission cycles BEM3 and BEM5, the shift register SR can delete the second pixel driver bits D2 to the fourth pixel driver bits D4 and newly store the tenth to twelfth pixel driver bits D10 to D12. The PWM control circuit PCC can determine the logic level of the PWM signal SPWM based on the third to fifth pixel driver bits D3 to D5 during the third to fifth transmission cycles BEM3 to BEM5, respectively.

[0129] According to one embodiment, the row driver 130 can transition the feedback enable signal FB_EN to logic high at the data write completion time point tDWC. According to another embodiment, after the data write completion time point tDWC, the row driver 130 can maintain the feedback enable signal FB_EN at logic high. In this case, the feedback multiplexer MUX_FB can provide the pixel drive bit D stored in the first unit C1 to the feedback unit CFB.

[0130] During the sixth transmit cycle BEM6, the PWM control circuit PCC can determine the logic level of the PWM signal SPWM based on the sixth pixel drive bit D6. For example, at the thirteenth time point t13, the row driver 130 can switch the first shift register control signal CS_SR1. In this case, the fifth pixel drive bit D5 can be deleted from the first unit C1, and the sixth pixel drive bit D6 stored in the second unit C2 can be newly stored in the first unit C1. Therefore, the logic level of the PWM signal SPWM can be determined based on the sixth pixel drive bit D6.

[0131] After the sixth pixel driver bit D6 is stored in the first unit C1, the row driver 130 can sequentially switch the second shift register control signal CS_SR2 to the seventh shift register control signal CS_SR7 to store the seventh pixel driver bits D2 to D12 in the second unit C2 to the seventh unit C7. Subsequently, the row driver 130 can copy the sixth pixel driver bit D6 stored in the first unit C1 to the feedback unit CFB by switching the eighth shift register control signal CS_SR8.

[0132] Similarly, during the time period between the fourteenth time point t14 and the fifteenth time point t15, corresponding to the seventh transmit cycle BEM7 to the twelfth transmit cycle BEM12, the row driver 130 can sequentially rotate the shift register SR bit by bit. In this way, the logic level of the PWM signal SPWM during the seventh transmit cycle BEM7 to the twelfth transmit cycle BEM12 can be determined based on the seventh pixel drive bit D7 to the twelfth pixel drive bit D12, respectively.

[0133] Simultaneously, before the fifteenth time point t15, column driver 120 can provide the thirteenth pixel drive bit D13 to the second data line DLb. For example, column driver 120 can output the thirteenth pixel drive bit D13 to the second data line DLb between the first time point t1 and the second time point t2. In this case, row driver 130 can switch the independent bit cell control signal CS_CIDP at the first time point t1. In this case, the thirteenth pixel drive bit D13 can be stored in the independent bit cell CIDP. However, this disclosure is not limited to this, so that column driver 120 can provide the thirteenth pixel drive bit D13 to the second data line DLb before the fifteenth time point t15.

[0134] For a more concise explanation, Figure 8An embodiment of column driver 120 outputting the thirteenth pixel drive bit D13 between a first time point t1 and a second time point t2 is shown, but the scope of this disclosure is not limited thereto. For example, column driver 120 may output the thirteenth pixel drive bit D13 at any time period between the first time point t1 and the fifteenth time point t15.

[0135] During the time period between the fifteenth time point t15 and the sixteenth time point t16, corresponding to the thirteenth transmit cycle BEM13, the row driver 130 can set the source selection signal SEL_SRC to logic high. In this case, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the thirteenth pixel drive bit D13 stored in the independent bit cell CIDP.

[0136] In other words, the first pixel driving bits D1 to the fifth pixel driving bits D5 corresponding to the discarded data D_DSCD can be deleted from the pixel in-memory (IPM), while the sixth pixel driving bits D6 to the thirteenth pixel driving bits D13 corresponding to the retained data D_RTN can be left undeleted from the IPM.

[0137] In an embodiment, the line driver 130 can determine each time interval between a first time point t1 and a sixteenth time point t16 as a predetermined length. For example, the line driver 130 can be based on the above reference. Figure 7 The length of the bit emission period (BEM) is described to control the timing of changing the logic level of the multiple pixel control signal (CTRL).

[0138] Next, refer to Figure 9 The column driver 120 can output the sixth pixel driver bits D6 to the twelfth pixel driver bits D12 via the first data line DL1, and can output the first pixel driver bits D1 to the fifth pixel driver bits D5 and the thirteenth pixel driver bit D13 via the second data line DLb. In other words, the column driver 120 can output all discarded data D_DSCD via the second data line DLb. The following will provide a detailed explanation, referencing the above. Figure 8 The differences in the driving methods for the display pixel PX are described.

[0139] The row driver 130 can set the feedback enable signal FB_EN low during the data write period (DW). For example, the row driver 130 can set the feedback enable signal FB_EN low between the twenty-first time point t21 (e.g., the drive start time point tDBGN) and the data write completion time point tDWC. After the data write period (DW) is completed, the row driver 130 can set the feedback enable signal FB_EN high. For example, the row driver 130 can set the feedback enable signal FB_EN high between the data write completion time point tDWC and the twenty-ninth time point t29.

[0140] The row driver 130 can set the PWM enable signal PWM_EN to logic high during the light emission period TEM. For example, the row driver 130 can set the PWM enable signal PWM_EN to logic high between the twenty-first time point t21 and the twenty-ninth time point t29.

[0141] The emission period TEM can include the first emission period BEM1 to the thirteenth emission period BEM13. The row driver 130 can set the source selection signal SEL_SRC to logic high between the twenty-first time point t21 and the twenty-sixth time point t26 corresponding to the first emission period BEM1 to the fifth emission period BEM5; it can set the source selection signal SEL_SRC to logic low between the twenty-sixth time point t26 and the twenty-eighth time point t28 corresponding to the sixth emission period BEM6 to the twelfth emission period BEM12; and it can set the source selection signal SEL_SRC to logic high between the twenty-eighth time point t28 and the twenty-ninth time point t29 corresponding to the thirteenth emission period BEM13.

[0142] The column driver 120 can sequentially provide the first pixel drive bit D1 to the fifth pixel drive bit D5 to the second data line DLb. The display pixel PX can determine the logic level of the PWM signal SPWM during the first transmission period BEM1 to the fifth transmission period BEM5 based on the first pixel drive bit D1 to the fifth pixel drive bit D5, respectively, under the control of the row driver 130.

[0143] According to an embodiment, column driver 120 can provide the first pixel drive bit D1 to the second data line DLb at a twenty-first time point t21. Row driver 130 can store the first pixel drive bit D1 in the independent bit cell CIDP by switching the independent bit cell control signal CS_CIDP at the twenty-first time point t21. In this case, since the source select signal SEL_SRC and the PWM enable signal PWM_EN are logic high, the logic level of the PWM signal SPWM can be directly determined based on the first pixel drive bit D1. In this way, the logic level of the PWM signal SPWM during the first transmit cycle BEM1 can be determined based on the first pixel drive bit D1.

[0144] Similarly, column driver 120 can provide the second pixel drive bit D2 to the fifth pixel drive bit D5 to the second data line DLb from the twenty-second time point t22 to the twenty-fifth time point t25 respectively; therefore, the logic level of the PWM signal SPWM during the second bit transmission period BEM2 to the fifth bit transmission period BEM5 can be determined based on the second pixel drive bit D2 to the fifth pixel drive bit D5 respectively.

[0145] In embodiments, row driver 130 and column driver 120 can be implemented to change the logic level of PWM signal SPWM in real time based on the voltage level of the second data line DLb. For example, row driver 130 can hold the independent bit cell control signal CS_CIDP high during the first transmit cycle BEM1 to the fifth transmit cycle BEM5. Column driver 120 can hold the voltage level of the second data line DLb at a value corresponding to the first pixel drive bits D1 to the fifth pixel drive bits D5 during the first transmit cycle BEM1 to the fifth transmit cycle BEM5. In this case, the logic level of PWM signal SPWM can change based on the voltage level change of the second data line DLb. For example, the logic level of PWM signal SPWM can change immediately in response to a change in the voltage level of the second data line DLb. That is, the scope of this disclosure is not limited to a specific driving method that allows the logic level of PWM signal SPWM to be determined in real time based on the pixel drive bits provided to the display pixel PX via the second data line DLb.

[0146] The column driver 120 can provide the thirteenth pixel drive bit D13 to the second data line DLb before the twenty-eighth time point t28, which is the start of the thirteenth transmit cycle BEM13. For example, between the twenty-sixth time point t26 and the twenty-seventh time point t27, the column driver 120 can output the thirteenth pixel drive bit D13 to the second data line DLb, and the row driver 130 can switch the independent bit cell control signal CS_CIDP. In this case, the thirteenth pixel drive bit D13 can be stored in the independent bit cell CIDP.

[0147] Simultaneously, column driver 120 can provide the sixth pixel driver bit D6 to the twelfth pixel driver bit D12 to the first data line DLa before the twenty-sixth time point t26, which begins the sixth bit transmission cycle BEM6. For example, column driver 120 can provide the sixth pixel driver bit D6 to the first data line DLa at the twenty-first time point t21. Row driver 130 can store the sixth pixel driver bit D6 in shift register SR by sequentially switching the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. Thereafter, in a similar manner, column driver 120 can sequentially provide the seventh pixel driver bit D7 to the twelfth pixel driver bit D12 to the first data line DLa, and row driver 130 can sequentially store the seventh pixel driver bit D7 to the twelfth pixel driver bit D12 in shift register SR by controlling the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. Therefore, before the twenty-sixth time point t26, the second bit unit C2 to the seventh bit unit C7 and the feedback unit CFB can respectively store the sixth pixel driving bit D6 to the twelfth pixel driving bit D12.

[0148] During the time period between the twenty-sixth time point t26 and the twenty-seventh time point t27 corresponding to the sixth bit transmission cycle BEM6, the row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the seventh shift register control signal CS_SR7 to shift the bits stored in the second bit units C2 to the seventh bit units C7 and the feedback unit CFB to the first bit units C1 to the seventh bit units C7, respectively. In this case, the first bit units C1 to the seventh bit units C7 can store the sixth pixel drive bit D6 to the twelfth pixel drive bit D12, and the logic level of the PWM signal SPWM can be determined based on the sixth pixel drive bit D6 stored in the first bit unit C1. The row driver 130 can copy the sixth pixel drive bit D6 stored in the first bit unit C1 to the feedback unit CFB by switching the eighth shift register control signal CS_SR8 after the data write completion time point tDWC (e.g., after the feedback enable signal FB_EN turns to logic high).

[0149] For a more concise explanation, Figure 9 An embodiment is shown in which the sixth pixel drive bit D6 is stored in the second bit cell C2 before the twenty-sixth time point t26, but the scope of this disclosure is not limited thereto. For example, the row driver 130 may be implemented to sequentially switch the first shift register control signal CS_SR1 to the seventh shift register control signal CS_SR7 before the twenty-sixth time point t26, and switch only the eighth shift register control signal CS_SR8 during the sixth bit transmit cycle BEM6.

[0150] During the time period between the twenty-seventh time point t27 and the twenty-eighth time point t28, corresponding to the seventh transmit cycle BEM7 to the twelfth transmit cycle BEM12, the row driver 130 can sequentially shift the shift register SR bit by bit. Therefore, the logic level of the PWM signal SPWM for the seventh transmit cycle BEM7 to the twelfth transmit cycle BEM12 can be determined based on the seventh pixel drive bit D7 to the twelfth pixel drive bit D12, respectively.

[0151] According to the embodiment, in response to the source selection signal SEL_SRC going high at the 28th time point t28, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the 13th pixel drive bit D13.

[0152] according to Figure 9 In this embodiment, the display pixel PX can perform a data write operation during a bit transmission operation. In this case, as referenced above... Figure 8 The described embodiment differs; column driver 120 may not output pixel drive bit D before the first transmit cycle BEM1. Therefore, according to Figure 9 In some embodiments, the time length required from the start of the drive time point tDBGN to the end of the emission period TEM can be reduced (e.g., the time length between the start of the drive time point tDBGN and the twenty-ninth time point t29).

[0153] Next, refer to Figure 10 The column driver 120 can output the first pixel driver bits D1 to D3 and the fifth pixel driver bits D5 to D12 via the first data line DLa, and can output the fourth pixel driver bit D4 and the thirteenth pixel driver bit D13 via the second data line DLb. For brevity, the following explanation will refer to the above. Figure 8 and Figure 9 The differences in the driving methods for the display pixel PX are described.

[0154] The row driver 130 can set the feedback enable signal FB_EN to logic low during the data write period (DW). For example, the row driver 130 can set the feedback enable signal FB_EN to logic low between the thirty-first time point t31 (e.g., the drive start time point tDBGN) and the data write completion time point tDWC. After the data write period (DW) is completed, the row driver 130 can set the feedback enable signal FB_EN to logic high. For example, the row driver 130 can set the feedback enable signal FB_EN to logic high between the data write completion time point tDWC and the forty-sixth time point t46.

[0155] The line driver 130 can set the PWM enable signal PWM_EN to logic high during the light emission period TEM. For example, the line driver 130 can set the PWM enable signal PWM_EN to logic high between the thirty-eighth time point t38 and the forty-sixth time point t46.

[0156] The emission period TEM can include the first emission period BEM1 to the thirteenth emission period BEM13. The line driver 130 can set the source selection signal SEL_SRC to logic low between the thirty-eighth time point t38 and the forty-first time point t41 corresponding to the first emission period BEM1 to the third emission period BEM3; it can set the source selection signal SEL_SRC to logic high between the forty-first time point t41 and the forty-second time point t42 corresponding to the fourth emission period BEM4; it can set the source selection signal SEL_SRC to logic low between the forty-second time point t42 and the forty-fifth time point t45 corresponding to the fifth emission period BEM5 to the twelfth emission period BEM12; and it can set the source selection signal SEL_SRC to logic high between the forty-fifth time point t45 and the forty-sixth time point t46 corresponding to the thirteenth emission period BEM13.

[0157] According to an embodiment, between the thirty-first time point t31 and the thirty-eighth time point t38, the column driver 120 can sequentially provide the first pixel driver bits D1 to D3 and the fifth pixel driver bits D5 to D8 to the first data line DLa. The row driver 130 can control the first shift register control signals CS_SR1 to CS_SR8 to sequentially store the first to third pixel driver bits D1 to D3 and the fifth to eighth pixel driver bits D5 to D8 in the shift register SR. According to an embodiment, the method of storing multiple pixel driver bits D in the shift register SR between the thirty-first time point t31 and the thirty-eighth time point t38 is the same as that described above. Figure 8The time period between the first time point t1 and the eighth time point t8 is described in a similar way, therefore, its detailed description is omitted.

[0158] The column driver 120 can provide the eighth pixel drive bit D8 to the first data line DLa at the thirty-eighth time point t38, and the row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. In this case, the first pixel drive bits D1 to the third pixel drive bits D3 and the fifth pixel drive bits D5 to the ninth pixel drive bits D9 can be stored in the shift register SR; and when the first pixel drive bit D1 is stored in the first unit C1, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM during the first transmit period BEM1 based on the first pixel drive bit D1.

[0159] During the time period between the thirty-ninth time point t39 and the forty-first time point t41, corresponding to the second transmission period BEM2 and the third transmission period BEM3, the shift register SR can delete the second pixel driver bit D2 and the third pixel driver bit D3, and newly store the tenth pixel driver bit D10 and the eleventh pixel driver bit D11. For example, based on the control of the row driver 130, the shift register SR can delete the second pixel driver bit D2 and the third pixel driver bit D3, and newly store the tenth pixel driver bit D10 and the eleventh pixel driver bit D11.

[0160] After the third transmit cycle BEM3 ends, the twelfth pixel driver bit D12 can be newly written into the shift register SR. For example, after the forty-first time point t41, the column driver 120 can provide the twelfth pixel driver bit D12 to the first data line DLa. The row driver 130 can sequentially delete the third pixel driver bit D3 from the shift register SR and newly store the twelfth pixel driver bit D12 in the shift register SR by switching the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8. In this case, the fifth pixel driver bits D5 to the eleventh pixel driver bits D11 can be stored in the first unit C1 to the seventh unit C7 respectively, and the twelfth pixel driver bit D12 can be stored in the feedback unit CFB.

[0161] Column driver 120 can provide the fourth pixel drive bit D4 to the second data line DLb before the forty-first time point t41, which is the start of the fourth bit transmit cycle BEM4. For example, between the thirty-first time point t31 and the thirty-second time point t32, column driver 120 can output the fourth pixel drive bit D4 to the second data line DLb, and row driver 130 can switch the independent bit cell control signal CS_CIDP. In this case, the fourth pixel drive bit D4 can be stored in the independent bit cell CIDP. However, the scope of this disclosure is not limited to a specific time point at which the fourth pixel drive bit D4 is written to the independent bit cell CIDP. For example, the fourth pixel drive bit D4 can be written to the independent bit cell CIDP at any time point between the drive start time point tDBGN and the forty-first time point t41.

[0162] During the time period between the forty-first time point t41 and the forty-second time point t42, which correspond to the fourth bit transmission period BEM4, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM (e.g., the logic level corresponding to the fourth pixel drive bit D4) based on the output signal of the independent bit cell CIDP.

[0163] After time point t42, at the end of the fourth bit transmission cycle BEM4, column driver 120 can provide the thirteenth pixel drive bit D13 to the second data line DLb. Row driver 130 can switch the independent bit cell control signal CS_CIDP. In this case, the fourth pixel drive bit D4 can be deleted from the independent bit cell CIDP, and the thirteenth pixel drive bit D13 can be newly stored.

[0164] In the example case where the most recently deleted pixel drive bit (e.g., the last deleted bit) (e.g., the fifth pixel drive bit D5) from the pixel in-memory (IPM) in the discarded data D_DSCD is stored in the shift register SR, the column driver 120 can terminate the data write operation for the display pixel PX even before the end of the bit emission cycle (e.g., the fifth bit emission cycle BEM5) corresponding to the most recently deleted pixel drive bit (e.g., the last deleted bit) from the pixel in-memory (IPM) in the discarded data D_DSCD. For example, the data write completion time point tDWC can be the time point before the end of the fifth bit emission cycle BEM5.

[0165] In an example where the pixel driver bit (e.g., the fourth pixel driver bit D4) deleted from the in-pixel memory IPM in the second-to-last order in the discarded data D_DSCD is stored at a different location (e.g., independent bit cell CIDP) than the most recently deleted pixel driver bit (e.g., the last deleted bit) (e.g., the fifth pixel driver bit D5) in the discarded data D_DSCD, the time required from the completion of the bit emission cycle (e.g., the fourth bit emission cycle BEM4) corresponding to the pixel driver bit deleted from the in-pixel memory IPM in the second-to-last order in the discarded data D_DSCD to the data write completion time tDWC can be minimized. For example, the line driver 130 can complete the data write operation for the display pixel PX by only switching the independent bit cell control signal CS_CIDP after the completion time of the fourth bit emission cycle BEM4 (e.g., without switching all the first shift register control signals CS_SR1 to the eighth shift register control signal CS_SR8).

[0166] According to an embodiment, between the forty-second time point t42 and the forty-third time point t43 corresponding to the fifth bit transmission period BEM5, the row driver 130 can sequentially switch the first shift register control signal CS_SR1 to the seventh shift register control signal CS_SR7 to move the bits stored in the second bit unit C2 to the seventh bit unit C7 and the feedback unit CFB to the first bit unit C1 to the seventh bit unit C7, respectively. In this case, the first bit unit C1 to the seventh bit unit C7 can store the sixth pixel driver bit D6 to the twelfth pixel driver bit D12, respectively. The row driver 130 can copy the sixth pixel driver bit D6 stored in the first bit unit C1 to the feedback unit CFB by switching the eighth shift register control signal CS_SR8 after the data write completion time point tDWC (e.g., after the feedback enable signal FB_EN turns to logic high).

[0167] During the time period between the forty-third time point t43 and the forty-fifth time point t45, corresponding to the sixth transmit cycle BEM6 to the twelfth transmit cycle BEM12, the row driver 130 can sequentially shift the shift register SR bit by bit. In this way, the logic level of the PWM signal SPWM for the sixth transmit cycle BEM6 to the twelfth transmit cycle BEM12 can be determined based on the sixth pixel drive bit D6 to the twelfth pixel drive bit D12, respectively.

[0168] According to an embodiment, in response to the source selection signal SEL_SRC transitioning to logic high at the forty-fifth time point t45, the source selection multiplexer MUX_SRC can determine the logic level of the PWM signal SPWM based on the thirteenth pixel drive bit D13.

[0169] according to Figure 10 In this embodiment, the total time length for the column driver 120 to provide pixel drive data PDD for display pixel PX to the first data line DL1 and the second data line DL2 is reduced. In other words, according to Figure 10 In some embodiments, the time interval between the drive start time point tDBGN and the data write completion time point tDWC can be reduced. For example, according to reference... Figure 8 In the described embodiment, the data write completion time point tDWC can be reached after the time required for sequential switching of all first shift register control signals CS_SR1 to eighth shift register control signals CS_SR8, starting from the time point when the fourth bit transmit cycle BEM4 is completed, and according to... Figure 10 In one embodiment, the data write completion time point tDWC can be reached after the time required to switch only the independent bit cell control signal CS_CIDP, starting from the time point when the fourth bit transmit cycle BEM4 is completed. For example, according to reference... Figure 9 In the described embodiment, the data write completion time point tDWC can arrive after the completion of the first transmit cycle BEM1 to the fifth transmit cycle BEM5, and according to... Figure 10 In one embodiment, the data write completion time point tDWC can arrive before the start of the fifth bit transmission cycle BEM5. According to embodiments of this disclosure, the time allocated to a display pixel PX for providing pixel drive data PDD for the first data line DL1 and the second data line DL2 can be reduced.

[0170] Next, refer to Figure 11 The column driver 120 can output the fifth pixel driver bit D5 to the twelfth pixel driver bit D12 via the first data line DLa, and can output the first pixel driver bit D1 to the fourth pixel driver bit D4 and the thirteenth pixel driver bit D13 via the second data line DLb. For the sake of brevity, the following explanation will refer to the above. Figures 8 to 10 The differences in the driving methods for the display pixel PX are described.

[0171] The row driver 130 can set the feedback enable signal FB_EN low during the data write period (DW). For example, the row driver 130 can set the feedback enable signal FB_EN low between the 51st time point t51 (e.g., the drive start time point tDBGN) and the data write completion time point tDWC. After the data write period (DW) is completed, the row driver 130 can set the feedback enable signal FB_EN high. For example, the row driver 130 can set the feedback enable signal FB_EN high between the data write completion time point tDWC and the 59th time point t59.

[0172] The line driver 130 can set the PWM enable signal PWM_EN to logic high during the light emission period TEM. For example, the line driver 130 can set the PWM enable signal PWM_EN to logic high between the fifty-first time point t51 and the fifty-ninth time point t59.

[0173] The emission period TEM can include the first emission period BEM1 to the thirteenth emission period BEM13. The line driver 130 can set the source selection signal SEL_SRC to logic high between the fifty-first time point t51 and the fifty-fifth time point t55 corresponding to the first emission period BEM1 to the fourth emission period BEM4; it can set the source selection signal SEL_SRC to logic low between the fifty-fifth time point t55 and the fifty-eighth time point t58 corresponding to the fifth to twelfth emission periods BEM5 to BEM12; and it can set the source selection signal SEL_SRC to logic high between the fifty-eighth time point t58 and the fifty-ninth time point t59 corresponding to the thirteenth emission period BEM13.

[0174] The column driver 120 can sequentially provide the first pixel drive bits D1 to the fourth pixel drive bits D4 to the second data line DLb. The display pixel PX can, based on the row driver 130 and the first pixel drive bits D1 to the fourth pixel drive bits D4, determine the logic level of the PWM signal SPWM during the first transmit cycle BEM1 to the fourth transmit cycle BEM4. The driving method for the display pixel PX between the fifty-first time point t51 and the fifty-fifth time point t55 is the same as described above. Figure 9 The driving method for the display pixel PX between the twenty-first time point t21 and the twenty-fifth time point t25 is similar, therefore, its detailed description is omitted.

[0175] Column driver 120 can provide the thirteenth pixel drive bit D13 to the second data line DLb before the fifty-eighth time point t58, which is the start of the thirteenth transmit cycle BEM13. For example, column driver 120 can output the thirteenth pixel drive bit D13 to the second data line DLb after the fifty-fifth time point t55, and row driver 130 can switch the independent bit cell control signal CS_CIDP. In this case, the thirteenth pixel drive bit D13 can be stored in the independent bit cell CIDP.

[0176] The column driver 120 can provide the fifth pixel driver bits D5 to the twelfth pixel driver bits D12 to the first data line DLa before the fifty-fifth time point t55 at the start of the fifth bit transmission cycle BEM5. For example, the column driver 120 can sequentially provide the fifth pixel driver bits D5 to the twelfth pixel driver bits D12 to the first data line DLa after the fifty-first time point t51. The row driver 130 can store the fifth pixel driver bits D5 to the twelfth pixel driver bits D12 in the shift register SR by controlling the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8.

[0177] Since the source selection signal SEL_SRC transitions to logic low at time t55, the logic level of the PWM signal SPWM during the fifth bit transmission period BEM5 can be determined based on the fifth pixel drive bit D5 stored in the first unit C1.

[0178] During the time period between the fifty-sixth time point t56 and the fifty-seventh time point t57 corresponding to the sixth bit transmission period BEM6, the row driver 130 can shift the bit order stored in the second bit unit C2 to the seventh bit unit C7 and the feedback unit CFB to the first bit unit C1 to the seventh bit unit C7 by switching the first shift register control signal CS_SR1 to the seventh shift register control signal CS_SR7, respectively. In this case, the first bit unit C1 to the seventh bit unit C7 can store the sixth pixel drive bit D6 to the twelfth pixel drive bit D12, respectively, and the logic level of the PWM signal SPWM can be determined based on the sixth pixel drive bit D6 stored in the first bit unit C1. Thereafter, the row driver 130 can copy the sixth pixel drive bit D6 stored in the first bit unit C1 to the feedback unit CFB by switching the eighth shift register control signal CS_SR8.

[0179] The row driver 130 can sequentially shift the shift register SR bit by bit during the time period between the fifty-seventh time point t57 and the fifty-eighth time point t58, corresponding to the seventh bit transmission period BEM7 to the twelfth bit transmission period BEM12. In this way, the logic level of the PWM signal SPWM for the seventh bit transmission period BEM7 to the twelfth bit transmission period BEM12 can be determined based on the seventh pixel drive bit D7 to the twelfth pixel drive bit D12, respectively.

[0180] Since the source selection signal SEL_SRC transitions to logic high at time t58, the logic level of the PWM signal SPWM during the thirteenth transmit cycle BEM13 can be determined based on the thirteenth pixel drive bit D13 stored in the independent bit cell CIDP.

[0181] according to Figure 11 The embodiments, compared with those previously referenced Figure 10 The description differs; display pixel PX can begin data writing immediately at the drive start time point tDBGN. That is, display pixel PX can perform data writing operations simultaneously with bit transmission operations. In this case, the time length for allocating the first data line DLa and the second data line DLb to a single display pixel PX can be minimized.

[0182] For a more concise explanation, Figures 8 to 11 The diagram illustrates that at the start of each bit-emit cycle (BEM), row driver 130 switches either the first shift register control signal CS_SR1 or the independent bit cell control signal CS_CIDP, but the scope of this disclosure is not limited thereto. For example, row driver 130 may be implemented to switch either the first shift register control signal CS_SR1 or the independent bit cell control signal CS_CIDP immediately after the start of each bit-emit cycle (BEM) (e.g., such that the timing of the first shift register control signal CS_SR1 or the independent bit cell control signal CS_CIDP transitioning to logic low coincides with the timing of the start of the bit-emit cycle (BEM) or the sub-bit-emit cycle (SUB_BEM).

[0183] For a more concise explanation, refer to Figures 8 to 11 Various methods for controlling display pixels PX are described exemplarily, but the scope of this disclosure is not limited thereto. For example, based on the display pixel PX having two data paths respectively connected to two data lines DL and these two data paths being independently controlled by a source selection multiplexer MUX_SRC, the row driver 130 and column driver 120 can be... Figures 8 to 11 Various methods, not shown, drive the display pixels PX.

[0184] Figure 12 This is a diagram illustrating the effect in an example scenario where the column driver is implemented to provide pixel drive bits read from external memory to the data lines. (See also...) Figures 1 to 12 Multiple display pixels PX arranged in a display pixel column can share data lines DL. For example, each of display pixels PX11 to PX13 can be connected to a first data line DL1a and a second data line DL2b. Therefore, it may not be possible to provide pixel drive bits D to multiple display pixels PX simultaneously via a single set of data lines DL2.

[0185] The timing control circuit 140 can generate a horizontal synchronization signal HSYNC. The timing control circuit 140 can control the operating timing of the column driver 120 and the row driver 130 based on the horizontal synchronization signal HSYNC. For example, the timing control circuit 140 can align the start time of control over the display pixel rows based on the switching time of the horizontal synchronization signal HSYNC.

[0186] In one embodiment, the timing control circuit 140 can directly provide the horizontal synchronization signal HSYNC to the column driver 120 and the row driver 130. However, the scope of this disclosure is not limited thereto.

[0187] In one embodiment, the timing control circuit 140 may receive a horizontal synchronization signal HSYNC from an external device. However, the scope of this disclosure is not limited thereto.

[0188] For example, column driver 120 and row driver 130 can determine the timing point at which to begin controlling multiple display pixels PX arranged in a column of display pixels based on the control of timing control circuit 140. For example, based on the control of timing control circuit 140, column driver 120 and row driver 130 can begin controlling display pixel PX11 at a first synchronization point tSYNCa, begin controlling display pixel PX21 at a second synchronization point tSYNCb, and begin controlling display pixel PX31 at a third synchronization point tSYNCc.

[0189] To implement column driver 120 in a smaller area, column driver 120 can be implemented to process pixel drive data PDD provided from timing control circuitry 140 in a first-in-first-out (FIFO) manner. For example, column driver 120 may not send pixel drive data PDD for displaying pixel PX21 to the first data line DLa and the second data line DLb until column driver 120 sends pixel drive data PDD for displaying pixel PX11 to the first data line DLa and the second data line DLb. Therefore, column driver 120 may need to provide pixel drive bit D for displaying pixel PX11 to the first data line DLa and the second data line DLb during the first row drive period RDP1 between the first synchronization point tSYNCa and the second synchronization point tSYNCb; and may need to provide pixel drive bit D for displaying pixel PX21 to the first data line DLa and the second data line DLb during the second row drive period RDP2 between the second synchronization point tSYNCb and the third synchronization point tSYNCc.

[0190] For example, column driver 120 and row driver 130 can be implemented as described above. Figure 10The described method controls multiple display pixels PX. In this case, after the first synchronization point tSYNCa, the column driver 120 may need to sequentially send each pixel drive bit D of the pixel drive data PDD for the display pixel PX11 to the first data line DLa and the second data line DLb. For example, the column driver 120 may have to provide the twelfth pixel drive bit D12 to the first data line DLa at the first data write time point tDWa starting from the fourth bit transmission cycle BEM4; and the column driver 120 may have to provide the thirteenth pixel drive bit D13 to the second data line DLb at the second data write time point tDWb starting from the fifth bit transmission cycle BEM5.

[0191] The second data write time point tDWb can be a time point after the second synchronization point tSYNCb. For example, the second data write time point tDWb can be a time point after the first row drive period RDP1. In this case, column driver 120 may be unable to (e.g., disabled) send the thirteenth pixel drive bit D13 at the second data write time point tDWb.

[0192] However, column driver 120 can be implemented to receive the thirteenth pixel drive bit D13 separately from external memory circuitry 150. For example, timing control circuitry 140 can separate the timing of providing the first pixel drive bits D1 to the twelfth pixel drive bits D12 of pixel drive data PDD for displaying pixel PX11 to column driver 120 from the timing of providing the thirteenth pixel drive bit D13 of pixel drive data PDD for displaying pixel PX11 to column driver 120. In this case, column driver 120 can receive the thirteenth pixel drive bit D13 for displaying pixel PX11 after the first row drive period RDP1, and can provide the thirteenth pixel drive bit D13 to the second data line DLb at the second data write time point tDWb.

[0193] In this way, column driver 120 can send buffered data D_BF provided from external memory circuitry 150 to the second data line DLb, regardless of the row drive period RDP corresponding to the display pixel PX. For example, even when the interval between horizontal sync signal HSYNC switching is short, column driver 120 is able to successfully provide buffered data D_BF to the display pixel PX. In other words, in the example case where column driver 120 is implemented to receive a portion of pixel drive data PDD as buffered data D_BF (e.g., from external memory circuitry 150), timing margin for outputting pixel drive data PDD can be ensured.

[0194] To explain more concisely, Figure 12 The column drive 120 and the row drive 130 are as previously referenced. Figure 10 The described method controls representative examples of embodiments with multiple display pixels PX, but the scope of this disclosure is not limited thereto. For example, references are made above to column driver 120 and row driver 130. Figures 8 to 11 In the example case where multiple display pixels PX are controlled in the manner described, the effects of this disclosure can occur similarly.

[0195] In addition, although Figure 12 An exemplary embodiment is shown in which column driver 120 is implemented to receive one pixel driver bit (e.g., the thirteenth pixel driver bit D13) of pixel driver data PDD as buffer data D_BF, but the scope of this disclosure is not limited thereto. For example, column driver 120 may be implemented to receive the entire pixel driver data PDD as real-time data D_RLTM, or it may be implemented to receive two or more pixel driver bits D as buffer data D_BF. That is, the scope of this disclosure is not limited to the number of pixel driver bits included in the buffer data D_BF.

[0196] Figure 13 This is a timing diagram illustrating, exemplarily, a method for driving display pixels according to an embodiment. (Refer to...) Figures 1 to 13 The row driver 130 can drive the bit emission period BEM by dividing the bit emission period BEM corresponding to the pixel driving bit stored in the Independent Bit Unit (CIDP) into two or more sub-bit emission periods SUB_BEM. For a simpler explanation, an embodiment in which the thirteenth emission period BEM13 includes a first sub-bit emission period SUB_BEMa, a second sub-bit emission period SUB_BEMb, and a third sub-bit emission period SUB_BEMc is described below as a representative example. However, this disclosure is not limited thereto, and therefore the number of sub-bit emission periods may be different from three.

[0197] The row driver 130 can determine the order of each of the first sub-bit transmit cycles SUB_BEMa to the third sub-bit transmit cycles SUB_BEMc, regardless of the order of the other transmit cycles BEM. The row driver 130 can arrange the first sub-bit transmit cycles SUB_BEMa to the third sub-bit transmit cycles SUB_BEMc such that they are not consecutive to each other. For example, the row driver 130 can arrange the first sub-bit transmit cycle SUB_BEMa between the tenth transmit cycle BEM10 and the eleventh transmit cycle BEM11, arrange the second sub-bit transmit cycle SUB_BEMb between the eleventh transmit cycle BEM11 and the twelfth transmit cycle BEM12, and arrange the third sub-bit transmit cycle SUB_BEMc after the twelfth transmit cycle BEM12.

[0198] For a more detailed example, the row driver 130 can change the output signal of the shift register SR by sequentially switching the first shift register control signal CS_SR1 to the eighth shift register control signal CS_SR8 in each of the tenth bit transmit cycle BEM10 to the twelfth bit transmit cycle BEM12. The row driver 130 can determine the logic level of the PWM signal SPWM based on the thirteenth pixel drive bit D13 stored in the independent bit cell CIDP by setting the source select signal SEL_SRC to logic high in each of the first sub-bit transmit cycle SUB_BEMa to the third sub-bit transmit cycle SUB_BEMc.

[0199] In the embodiments, the lengths of each of the first sub-bit transmission periods SUB_BEMa to the third sub-bit transmission period SUB_BEMc can be the same or different. For example, the lengths of the first sub-bit transmission periods SUB_BEMa to the third sub-bit transmission periods SUB_BEMc can be "1024UT", "1024UT", and "2048UT", respectively. However, the scope of this disclosure is not limited thereto.

[0200] according to Figure 13 The illustrated embodiment can minimize the technical problems caused by the length of the bit emission period (BEM) corresponding to the pixel driving bit stored in the independent bit unit (CIDP). For example, when the MSB of the pixel driving data (PDD) is stored in the independent bit unit (CIDP), problems caused by the length of the bit emission period (BEM) corresponding to the MSB of the pixel driving data (PDD) can be minimized. In the example case where the thirteenth emission period (BEM) 13 is divided into multiple sub-bit emission periods (SUB_BEM), the time for the display pixel PX to continuously emit light based on the thirteenth pixel driving bit D13 can be minimized, thereby minimizing the false contour effect. Therefore, the display device 100 according to the embodiments of this disclosure can generate higher quality images.

[0201] Figure 14 This is a timing diagram illustrating the frame period according to an embodiment. (Refer to...) Figures 1 to 14 A frame period (FRM) may include one or more subframe periods (SFRMs). For example, a frame period (FRM) may include a first subframe period (SFRM1), a second subframe period (SFRM2), and a third subframe period (SFRM3). However, the scope of this disclosure is not limited thereto, and a frame period (FRM) may include only one subframe period (SFRM).

[0202] In this embodiment, the display pixel PX can operate based on different pixel drive data PDDs in different frame periods (FRMs). Therefore, the waveforms of the PWM signal SPWM in different frame periods (FRMs) can be different. However, the scope of this disclosure is not limited thereto.

[0203] According to an embodiment, in an example case where a frame period (FRM) comprises multiple subframe periods (SFRM), instead of using a pixel drive data (PDD) to determine the logic level of the PWM signal (SPWM) during a single emission period (TEM) of relatively long length, the logic level of the PWM signal (SPWM) can be determined during multiple emission period TEMs of relatively short length. In this case, the “1UT” length of each emission period TEM can be minimized, thus minimizing pseudo-contour effects. However, the scope of this disclosure is not limited thereto. For example, the multiple emission period TEMs may include a first emission period TEM1, a second emission period TEM2, and a third emission period TEM3.

[0204] The first subframe period SFRM1 to the third subframe period SFRM3 can share a single pixel drive data PDD. The first subframe period SFRM1 to the third subframe period SFRM3 can each include a first emission period TEM1 to a third emission period TEM3. During the first emission period TEM1 to the third emission period TEM3, the display pixel PX can perform emission operations based on a single pixel drive data PDD. For example, the display pixel PX can reuse the reserved data D_RTN received in the data write period DW during the first subframe period SFRM1 to the third subframe period SFRM3. In this case, since the display pixel PX can perform emission operations even in the example where the column driver 120 and the row driver 130 do not newly store the pixel drive data PDD in the display pixel PX, the power consumption of the display device 100 can be minimized.

[0205] According to an embodiment, the row driver 130 and the column driver 120 can be referenced previously during the first subframe period SFRM1. Figures 8 to 11 The described method drives the display pixels PX. However, for a more concise explanation below, it can be assumed that the row driver 130 and column driver 120 drive the display pixels PX in the manner previously referenced during the first subframe period SFRM1. Figure 9 The described method drives the display pixel PX. For example, it can be assumed below that the data write period DW is included in the first emission period TEM1. However, the scope of this disclosure is not limited thereto. For example, the data write period DW of the first subframe period SFRM1 may not overlap with the first emission period TEM1.

[0206] During the first emission period TEM1, the display pixel PX can perform emission operations based on both discarded data D_DSCD and retained data D_RTN. For example, the first emission period TEM1 may include the first emission period BEM1 to the fifth emission period BEM5 corresponding to the discarded data D_DSCD and the sixth emission period BEM6 to the thirteenth emission period BEM13 corresponding to the retained data D_RTN.

[0207] During the first emission period TEM1, discarded data D_DSCD can be deleted from the in-pixel memory (IPM). For example, row driver 130 and column driver 120 can delete discarded data D_DSCD from the IPM and write retained data D_RTN to the IPM during the first emission period TEM1. Therefore, at the end of the first subframe period SFRM1, only retained data D_RTN can be stored in the IPM. In other words, discarded data D_DSCD can be lost from the IPM at the end of the first subframe period SFRM1.

[0208] The duration of the first luminescent period TEM1 can be longer than the referenced above. Figure 12 The horizontal synchronization signal HSYNC described has a long switching interval. Therefore, after the first subframe period SFRM1 ends, the column driver 120 may have difficulty providing new pixel drive bits to the display pixel PX.

[0209] Therefore, during the second emission period TEM2 and the third emission period TEM3, the display pixel PX can perform emission operations only for the reserved data D_RTN. For example, each of the second emission period TEM2 and the third emission period TEM3 may include the sixth emission period BEM6 to the thirteenth emission period BEM13, and may exclude the first emission period BEM1 to the fifth emission period BEM5.

[0210] In an embodiment, the duration of the first emission period TEM1 can be longer than the durations of the second emission period TEM2 and the third emission period TEM3.

[0211] In this embodiment, the waveforms of the PWM signal SPWM during the second light-emitting period TEM2 and the third light-emitting period TEM3 may be identical. However, the scope of this disclosure is not limited thereto, and the duty cycles of the PWM signal SPWM during the second light-emitting period TEM2 and the third light-emitting period TEM3 may be the same, but the waveforms of the PWM signal SPWM may be different.

[0212] In other words, according to Figure 14In an example embodiment where a frame period FRM includes multiple subframe periods SFRM, the display pixels PX in the remaining subframe periods SFRM, except for the first subframe period SFRM1, can operate at a relatively low brightness resolution.

[0213] In this embodiment, the discarded data D_DSCD can be implemented as the low-order bit of the pixel-driven data PDD. In this case, the luminance resolution degradation of the display pixel PX during the subframe period SFRM in which the discarded data D_DSCD is lost can be minimized.

[0214] Figure 15 This is a timing diagram illustrating the frame period according to an embodiment. Below, refer to... Figures 1 to 15 Detailed explanation and reference Figure 14 The differences in the frame period FRM described.

[0215] A single frame period (FRM) can include one or more subframe periods (SFRMs). For example, a frame period (FRM) can include first subframe periods (SFRM1) to third subframe periods (SFRM3). First subframe periods (SFRM1) to third subframe periods (SFRM3) can share a single pixel drive data (PDD). First subframe periods (SFRM1) to third subframe periods (SFRM3) can each include a first emission period (TEM1) to a third emission period (TEM3).

[0216] During the first subframe period SFRM1, the row driver 130 and column driver 120 can be referenced above. Figure 14 The method described is similar to controlling the display pixels (PX).

[0217] The second emission period TEM2 may include a first sub-emission period STEM2a and a second sub-emission period STEM2b. The third emission period TEM3 may include a first sub-emission period STEM3a and a second sub-emission period STEM3b.

[0218] During the first sub-illumination periods STEM2a and STEM3a, the display pixel PX can perform illumination operations based on the discarded data D_DSCD. During the second sub-illumination periods STEM2b and STEM3b, the display pixel PX can perform illumination operations based on the retained data D_RTN.

[0219] According to an embodiment, between time point t61 (sixty-first time) and time point t62 (sixty-second time), row driver 130 and column driver 120 can control display pixel PX to perform illumination operations based on discarded data D_DSCD. For example, referring to the above... Figure 9Similar to the description of the time period between the twenty-first time point t21 and the twenty-sixth time point t26, the column driver 120 can sequentially provide one or more pixel driver bits D included in the discarded data D_DSCD to the second data line DLb; and based on the control of the row driver 130, the display pixel PX can determine the logic level of the PWM signal SPWM based on the voltage level of the second data line DLb. In this case, at the sixty-second time point t62 when the first sub-light emission period STEM2a is completed, one pixel driver bit (e.g., the fifth pixel driver bit D5) included in the discarded data D_DSCD can be stored in the independent bit cell CIDP.

[0220] According to an embodiment, between time point t62 (sixty-second time point) and time point t63 (sixty-third time point), row driver 130 and column driver 120 can update the Independent Bit Cell CIDP based on reserved data D_RTN. For example, column driver 120 can provide the thirteenth pixel drive bit D13 to the second data line DLb, and row driver 130 can store the thirteenth pixel drive bit D13 in the Independent Bit Cell CIDP by switching the Independent Bit Cell control signal CS_CIDP.

[0221] Subsequently, between time point t63 (sixty-third time point) and time point t64 (sixty-fourth time point), under the control of line driver 130, display pixel PX can perform light emission operation based on reserved data D_RTN stored in pixel internal memory IPM.

[0222] according to Figure 15 In one embodiment, during each subframe period SFRM, the display pixel PX can perform emission operations based on one or more pixel drive bits included in the discarded data D_DSCD. In this case, the display pixel PX can also operate at a relatively high luminance resolution during the remaining subframe periods SFRM, excluding the first subframe period SFRM1.

[0223] In an embodiment, column driver 120 can control the second data line DLb between sixty-first time point t61 and sixty-third time point t63 based on pixel driver bits D provided from the external memory circuit 150. Therefore, the number of bit emission periods BEMs included in the first sub-emission period STEM2a can be determined based on the number of bits in the buffer data D_BF (and further, the capacity of the external memory circuit 150). For example, in order to include the first emission period BEM1 to the fifth emission period BEM5 in the first sub-emission period STEM2a, the buffer data D_BF may need to include the first pixel driver bits D1 to the fifth pixel driver bits D5 provided via the second data line DLb between sixty-first time point t61 and sixty-second time point t62, and the sixth pixel driver bit D6 provided via the second data line DLb between sixty-second time point t62 and sixty-third time point t63. For another example, in order to include only the fifth emission period BEM5 in the first sub-emission period STEM2a, the buffer data D_BF may need to include the fifth pixel drive bit D5 provided via the second data line DLb between the sixty-first time point t61 and the sixty-second time point t62, and the thirteenth pixel drive bit D13 provided via the second data line DLb between the sixty-second time point t62 and the sixty-third time point t63. In other words, because the off-pixel memory circuit 150 stores a larger amount of buffer data D_BF for each pixel drive data PDD, the display pixel PX can operate at a relatively high luminance resolution in the remaining sub-frame periods SFRM, except for the first sub-frame period SFRM1.

[0224] Figure 16 This is a timing diagram illustrating the frame period according to an embodiment. (Refer to...) Figures 1 to 13 and Figure 16 A frame period (FRM) may include one or more subframe periods (SFRMs). For example, a frame period (FRM) may include a prior control period (PRE) and multiple subframe periods. For example, multiple subframe periods may include a first subframe period (SFRMa), a second subframe period (SFRMb), and a third subframe period (SFRMc). During the prior control period (PRE) and the first to third subframe periods (SFRMa to SFRMc), the display pixel (PX) may operate based on a pixel drive data (PDD). According to an embodiment, the prior control period (PRE) may be referred to as a preliminary control period or an initial control period.

[0225] During the previous control period PRE, the display pixel PX may perform an emission operation based on the discarded data D_DSCD. For example, the previous control period PRE may include a previous emission period TEM_pre for discarding the data D_DSCD. According to an embodiment, the previous emission period TEM_pre may be referred to as the pre-emission period or the initial emission period.

[0226] During the first subframe period SFRMa to the third subframe period SFRMc, the display pixel PX can perform emission operations based on the reserved data D_RTN. For example, the first subframe period SFRMa to the third subframe period SFRMc can each include a first emission period TEMA to a third emission period TEMc for reserving the data D_RTN.

[0227] During the previous light-emitting period TEM_pre, row driver 130 and column driver 120 can sequentially provide each of the multiple pixel drive bits D included in the discarded data D_DSCD to the second data line DLb; and the display pixel PX can determine the logic level of the PWM signal SPWM based on the voltage level of the second data line DLb, according to the control of row driver 130. That is, row driver 130 and column driver 120 can refer to the above... Figure 9 The display pixel PX is driven in a manner described in the time period between the twenty-first time point t21 and the twenty-sixth time point t26. However, the scope of this disclosure is not limited thereto, and the row driver 130 and column driver 120 may also be driven as described above. Figure 8 The time period between the first time point t1 and the thirteenth time point t13 is described in a way that drives the display pixels PX.

[0228] Row driver 130 and column driver 120 can determine the length of the previous emission period TEM_pre based on the code length of the discarded data D_DSCD and the number of subframe periods SFRM included in the frame period FRM. In the example case where the discarded data D_DSCD includes the first pixel driver bits D1 to the fifth pixel driver bits D5, row driver 130 and column driver 120 can determine the length of the previous emission period TEM_pre as the product of the sum of the first emission period BEM1 to the fifth emission period BEM5 (e.g., 31UT) and the number of subframe periods SFRM included in the frame period FRM (e.g., 3). For example, even if the display pixel PX performs emission operation based only on the retained data D_RTN during multiple subframe periods SFRM, the display pixel PX can operate at a high brightness resolution because the display pixel PX performs the emission operation corresponding to the discarded data D_DSCD during the previous control period PRE.

[0229] After the previous emission period TEM_pre is completed, row driver 130 and column driver 120 can store the reserved data D_RTN in the in-pixel memory (IPM). For example, row driver 130 and column driver 120 can store the thirteenth pixel drive bit D13 in the independent bit cell (CIDP).

[0230] For a more concise explanation, Figure 16 The example shown is a discarded data D_DSCD comprising the low-order bits of the pixel-driven data PDD and indicating that pixel PX performs an emission operation corresponding to the discarded data D_DSCD during the previous emission period TEM_pre, but the scope of this disclosure is not limited thereto. For example, the discarded data D_DSCD may include the high-order bits of the pixel-driven data PDD. In this case, the length of the previous emission period TEM_pre may be longer than the length of each subframe period SFRM.

[0231] Figure 17 This illustrates an embodiment in Figure 16 A diagram showing the state of the PWM signal during the previous illumination period. (Refer to...) Figures 1 to 13 as well as Figures 16 to 17 The previous emission period TEM_pre may include multiple extended bit emission periods (XBEMs) for discarding data D_DSCD. For example, the previous emission period TEM_pre may include a first extended bit emission period XBEM1 to a fifth extended bit emission period XBEM5 corresponding to the first pixel driver bit D1 to the fifth pixel driver bit D5, respectively. For example, the previous emission period TEM_pre may include a first extended bit emission period XBEM1 corresponding to the first pixel driver bit D1, a second extended bit emission period XBEM2 corresponding to the second pixel driver bit D2, a third extended bit emission period XBEM3 corresponding to the third pixel driver bit D3, a fourth extended bit emission period XBEM4 corresponding to the fourth pixel driver bit D4, and a fifth extended bit emission period XBEM5 corresponding to the fifth pixel driver bit D5.

[0232] The lengths of the first extended bit transmit period XBEM1 to the fifth extended bit transmit period XBEM5 can correspond to values ​​obtained by multiplying the lengths of the first transmit period BEM1 to the fifth transmit period BEM5 by the number of subframe periods SFRM included in a frame period FRM. For example, the length of the first extended bit transmit period XBEM1 can be "3UT", which is the product of the length of the first transmit period BEM1 and the number of subframe periods SFRM included in a frame period FRM; and the length of the second extended bit transmit period XBEM2 can be "6UT", which is the product of the length of the second transmit period BEM2 and the number of subframe periods SFRM included in a frame period FRM.

[0233] In this way, instead of performing illumination operations based solely on reserved data D_RTN during the illumination period TEM of each subframe period SFRM, the display pixel PX can pre-perform the bit emission operation of discarded data D_DSCD, which would be performed for multiple subframe periods SFRM, during a previous illumination period TEM_pre. In other words, the line driver 130 can determine the total duration for which the display pixel PX is turned on during the previous illumination period TEM_pre based on the number of subframe periods SFRM included in the frame period FRM. In this case, the display pixel PX can be able to operate at a higher brightness resolution.

[0234] For a more concise explanation, Figure 17 A representative example is described where the preceding emission period TEM_pre comprises a plurality of extended bit emission periods XBEMs, each corresponding to a pixel driver bit D included in the discarded data D_DSCD; however, the scope of this disclosure is not limited thereto. For example, the preceding emission period TEM_pre may be implemented to include a plurality of bit emission periods BEMs for each pixel driver bit D included in the discarded data D_DSCD. In a more detailed example, the preceding emission period TEM_pre may include three for each of the first emission period BEM1 to the fifth emission period BEM5.

[0235] Figure 18 This is a block diagram illustrating a display device according to an embodiment of the present disclosure. (Refer to...) Figures 1 to 18 The display device 200 may include a display pixel array 210, a column driver 220, a row driver 230, a timing control circuit 240, and an external pixel memory circuit 250. The configuration and function of the display pixel array 210, the row driver 230, the timing control circuit 240, and the external pixel memory circuit 250 are similar to those described above. Figures 1 to 17 The configuration and function of the display pixel array 110, row driver 130, timing control circuitry 140, and external pixel memory circuitry 150 are described, therefore, their detailed description is omitted.

[0236] Column driver 220 may include pulse generation circuitry GEN_PUL. Pulse generation circuitry GEN_PUL can generate pixel drive pulses (hereinafter referred to as "PUL") having pulse widths corresponding to one or more pixel drive bits D included in pixel drive data PDD. For example, instead of sequentially providing one or more pixel drive bits D to the second data line DLb, column driver 220 can provide pixel drive pulses PUL to the second data line DLb.

[0237] The display pixel PX can generate a PWM signal SPWM based on the pixel drive pulse PUL, and perform a light emission operation based on the PWM signal SPWM.

[0238] Figure 19 It shows the basis in more detail. Figure 18 A diagram illustrating the configuration of the PWM signal in an embodiment. (Refer to...) Figures 1 to 19 The emission period TEM can include a pulse emission period (PULEM) and multiple bit emission periods (BEM).

[0239] The display pixel PX can determine the logic level of the PWM signal SPWM based on the pixel drive pulse PUL during the pulse emission period PULEM.

[0240] Column driver 120 can generate pixel drive pulse PUL based on discarded data D_DSCD. For example, column driver 120 can determine the pulse width of pixel drive pulse PUL based on the value indicated by the pixel drive bit D included in discarded data D_DSCD.

[0241] In other words, column driver 120 can provide the pixel drive pulse PUL instead of discarding data D_DSCD to the second data line DLb. Display pixel PX can perform emission operation based on the pixel drive pulse PUL instead of discarding data D_DSCD. In this case, because the pulse generation circuit GEN_PUL is implemented to finely adjust the pulse width of the pixel drive pulse PUL, display pixel PX can operate at high brightness resolution even in the example case where a small number of pixel drive bits are stored in the in-pixel memory (IPM). For example, because the pulse generation circuit GEN_PUL operates based on a higher frequency clock, it is implemented to adjust the pulse width of the pixel drive pulse PUL in units shorter than 1UT.

[0242] In an embodiment, the duration of the pulse transmit period PULEM can correspond to the sum of the lengths of the bit transmit periods BEM corresponding to the discarded data D_DSCD. For example, the duration of the pulse transmit period PULEM can be "31UT", which is the sum of the first transmit period BEM1 to the fifth transmit period BEM5. However, the scope of this disclosure is not limited thereto. For example, a frame period FRM can include multiple subframe periods SFRM. In this case, compared with the previous reference Figure 16 Similarly, the pulse generation circuit GEN_PUL can also determine the pulse width WD_PUL based on the number of subframe periods SFRM included in the frame period FRM.

[0243] Display pixel PX can perform emission operations based on reserved data D_RTN during multiple bit emission cycles (BEM). For example, display pixel PX can perform emission operations during the sixth bit emission cycle (BEM6) to the thirteenth bit emission cycle (BEM13) in accordance with the above reference. Figures 8 to 11 The emission operation is performed in a similar manner to the description.

[0244] Figure 20 It shows the basis Figure 19 A timing diagram of the display pixel driving method of an embodiment. (Refer to...) Figures 1 to 20 The column driver 120 can provide the pixel drive pulse PUL to the second data line DLb during the time period between a first time point tA and a second time point tB corresponding to the pulse emission period PULEM. In this case, the pulse generation circuit GEN_PUL can obtain or generate the pulse width WD_PUL of the pixel drive pulse PUL based on the pixel drive bits. For example, the pulse generation circuit GEN_PUL can determine the pulse width WD_PUL of the pixel drive pulse PUL based on the values ​​indicated by the first pixel drive bits D1 to the fifth pixel drive bits D5. In the example case where the discarded data D_DSCD is "11010" (e.g., when the first pixel drive bits D1 to the fifth pixel drive bits D5 are "1", "1", "0", "1" and "1" respectively), the pulse generation circuit GEN_PUL can determine the pulse width WD_PUL to be 26UT (e.g., UT), which is the length corresponding to the value of the discarded data D_DSCD. However, the scope of this disclosure is not limited thereto.

[0245] To explain more concisely, Figure 20A representative embodiment is described in which the pixel drive pulse PUL transitions to logic high at a first time point tA and then transitions to logic low at a time point after a time corresponding to the pulse width WD_PUL from the first time point tA, but the scope of this disclosure is not limited thereto. For example, the pixel drive pulse PUL can be implemented to switch more than twice between the first time point tA and the second time point tB (e.g., dividing the pulse width WD_PUL into two or more time periods).

[0246] The row driver 130 can keep the PWM enable signal PWM_EN, the source select signal SEL_SRC, and the independent bit cell control signal CS_CIDP logic high during the pulse transmit cycle PULEM. In this case, the logic level of the PWM signal SPWM can be determined based on the voltage level of the second data line DLb (e.g., the logic level of the pixel drive pulse PUL).

[0247] Column driver 220 can provide at least a portion of the reserved data D_RTN (e.g., pixel drive bits D to be stored in shift register SR) to the first data line DLa during the pulse emission period PULEM. Row driver 130 can store at least some of the reserved data D_RTN in shift register SR by sequentially controlling the first shift register control signals CS_SR1 to the eighth shift register control signal CS_SR8. For example, row driver 130 and column driver 120 can store the sixth pixel drive bits D6 to the twelfth pixel drive bits D12 in shift register SR before the second time point tB. In this case, even in the example where the pixel drive bits are not stored in the in-pixel memory IPM before the start of the sixth bit emission period BEM6 and after the completion of the pulse emission period PULEM, the display pixel PX can still perform emission operation. However, the scope of this disclosure is not limited thereto, and the row driver 130 and column driver 120 can control the display pixel PX to store the sixth pixel driver bits D6 to the twelfth pixel driver bits D12 before the first time point tA, or can control the display pixel PX to store the sixth pixel driver bits D6 to the twelfth pixel driver bits D12 before the start of the sixth bit emission period BEM6 and after the completion of the pulse emission period PULEM.

[0248] After the second time point tB, column driver 120 may provide some of the reserved data D_RTN (e.g., pixel drive bits to be stored in the Independent Bit Module (CIDP)) to the second data line DLb. For example, column driver 120 may provide the thirteenth pixel drive bit D13 to the second data line DLb. Row driver 130 may set the Independent Bit Module (CIDP) control signal CS_CIDP to logic high between the second time point tB and the third time point tC. In this case, the thirteenth pixel drive bit D13 may be stored in the Independent Bit Module (CIDP). That is, row driver 130 and column driver 120 may store the thirteenth pixel drive bit D13 in the Independent Bit Module (CIDP) during the sixth bit emission cycle BEM6. In this case, even in the example where the pixel drive bit is not stored in the in-pixel memory (IPM) before the start of the sixth bit emission cycle BEM6 and after the completion of the pulse emission cycle PULEM, the display pixel PX can still perform emission operation. However, the scope of this disclosure is not limited thereto, and the row driver 130 and column driver 120 can also control the display pixel PX to perform the light emission operation corresponding to the sixth pixel driver D6 after the third time point tC after the thirteenth pixel driver bit D13 is stored in the independent bit cell CIDP.

[0249] The foregoing description describes specific embodiments for carrying out this disclosure. However, the scope of this disclosure is not limited thereto and should be determined based on the claims set forth below and their equivalents.

Claims

1. A display device, comprising: The column driver is configured as follows: Receive first pixel driving data including multiple pixel driving bits, and The first data line and the second data line are controlled based on the first pixel driving data; A first display pixel includes in-pixel memory and is connected to the first data line and the second data line; and A line driver is configured to control the operation of the first display pixel. The first display pixel is configured to write one or more of the plurality of pixel drive bits into the pixel internal memory during a first time period during which the first display pixel performs a first light emission operation corresponding to the first pixel drive data.

2. The display device according to claim 1, further comprising an external pixel memory circuit, wherein the external pixel memory circuit stores a first pixel driving bit among the one or more pixel driving bits. in, The column driver is configured to control the second data line based on the first pixel drive bit provided from the external pixel memory circuitry during a second time period, which is included in the first time period.

3. The display device according to claim 2, further comprising a second display pixel connected to the first data line and the second data line. in, The column driver is also configured to: Receive second pixel driving data corresponding to the same frame period as the first pixel driving data; as well as Based on the second pixel driving data, control the first data line and the second data line, and The second time period is the period after which the column driver is configured to begin providing the second pixel driving data to the first data line or the second data line.

4. The display device according to claim 2, wherein, The first pixel driving bit is the most significant bit (MSB) of the first pixel driving data.

5. The display device according to claim 1, wherein: The first display pixel further includes: The source selection multiplexer is configured to generate a pulse width modulation (PWM) signal; and The light-emitting circuit is configured to operate based on the PWM signal. The pixel-in-memory memory includes: A shift register is connected between the first input terminal of the source selection multiplexer and the first data line; and An independent bit unit is connected between the second input terminal of the source selection multiplexer and the second data line.

6. The display device according to claim 5, wherein, The capacity of the first pixel driving data is greater than the capacity of the pixel internal memory.

7. The display device according to claim 6, wherein, The first pixel driving data includes: Discarded data, including a first plurality of pixel drive bits corresponding to a first subset of the plurality of pixel drive bits; and The retained data includes a second plurality of pixel drive bits corresponding to a second subset of the plurality of pixel drive bits, and The first display pixel is configured to delete the discarded data from its internal memory before the end of the first time period.

8. The display device according to claim 7, wherein: The first pixel driving data includes n pixel driving bits, where n is an integer greater than or equal to 2. The first plurality of pixel driving bits correspond to the lower m bits of the first pixel driving data, where m is an integer greater than or equal to 1, and The second plurality of pixel driving bits correspond to the high (nm) bits of the first pixel driving data.

9. The display device according to claim 7, wherein, The column driver is also configured to: The second pixel driver bit, which is the most recently deleted from the pixel memory, is provided to the first data line.

10. The display device according to claim 9, wherein, The column driver is also configured to: The third pixel driver bit, which is deleted from the pixel memory in the second-to-last order among the first plurality of pixel driver bits, is provided to the second data line.

11. The display device according to claim 6, wherein: The first pixel driving data includes: Discarded data, including a first plurality of pixel drive bits corresponding to a first subset of the plurality of pixel drive bits; and The retained data includes a second plurality of pixel driving bits corresponding to a second subset of the plurality of pixel driving bits, and The column driver is configured as follows: Generate pixel driving pulses based on the discarded data; and The pixel drive pulse is provided to the second data line.

12. The display device according to claim 11, wherein: The column driver is configured to provide the pixel drive pulse to the second data line during a third time period prior to the first time period; as well as The first display pixel is configured to perform a second light emission operation based on the voltage level of the second data line during the third time period.

13. A display device, comprising: A column driver is configured to control one or more data lines based on first pixel driving data, the first pixel driving data including discarded data with a first code length and retained data with a second code length; The display pixel is connected to one or more of the data lines and includes in-pixel memory having a capacity corresponding to the second code length. and A line driver is configured to control the display pixels to perform a first emission operation based on the discarded data during a first time period, and to control the display pixels to perform a second emission operation based on the retained data during a second time period after the first time period. The in-pixel memory is configured to store the reserved data during the second time period.

14. The display device according to claim 13, wherein: The line driver is also configured to control the display pixels to perform a third emission operation based on the reserved data during a third time period following the second time period; and The first total duration for which the display pixel is turned on during the second time period is the same as the second total duration for which the display pixel is turned on during the third time period.

15. The display device according to claim 14, wherein: The first time period, the second time period, and the third time period are included in the first frame period, and The line driver is also configured to determine a third total duration for which the display pixels are enabled during the first time period based on the number of subframes included in the first frame period and the discarded data.

16. The display device of claim 14, further comprising an external pixel memory circuit configured to store a first pixel driving bit included in the discarded data and a second pixel driving bit included in the retained data. in, The column driver is also configured to: During a fourth time period between the second time period and the third time period, the first pixel drive bit is provided to the one or more data lines, and During a fifth time period between the fourth time period and the third time period, the second pixel drive bit is provided to the one or more data lines, and The row driver is further configured as follows: Control the display pixel to perform a fourth light emission operation based on the first pixel driving bit during the fourth time period, and The display pixel is controlled to update its in-pixel memory based on the second pixel driving bit during the fifth time period.

17. The display device according to claim 13, wherein: The display pixels also include: The source selection multiplexer is configured to generate a pulse width modulation (PWM) signal; and The light-emitting circuit is configured to operate based on the PWM signal. The one or more data lines include a first data line and a second data line, and The pixel-in-memory memory includes: A shift register is connected between the first input terminal of the source selection multiplexer and the first data line; and An independent bit unit is connected between the second input terminal of the source selection multiplexer and the second data line.

18. The display device according to claim 17, wherein: The column driver is configured to determine the voltage level of the second data line during the first time period based on the discarded data, and The source selection multiplexer is configured to determine the logic level of the PWM signal during the first time period based on the voltage level of the second data line.

19. A display pixel, comprising: In-pixel memory, including shift registers and independent bit units; A source selection multiplexer is configured to generate a pulse width modulation (PWM) signal based on a first output signal from the shift register and a second output signal from the independent bit unit. and The light-emitting circuit is configured to perform a first light-emitting operation based on the PWM signal during a first time period when a data write operation is performed in the pixel memory.

20. The display pixel according to claim 19, wherein: The light-emitting circuit is also configured to perform a second light-emitting operation based on the PWM signal during a second time period following the first time period. The PWM signal includes multiple bit emission cycles corresponding to different pixel drive bits, and The sum of a first number of bit emission cycles corresponding to the first time period and a second number of bit emission cycles corresponding to the second time period among the plurality of bit emission cycles is greater than the capacity of the pixel internal memory.

Images