Shift register and display panel

Abstract

Embodiments of the present application provide a shift register and a display panel, the shift register comprising an input module, a reverse module, a delay module, a control module, a first output module and a second output module; the input module, the reverse module, the control module and the second output module are electrically connected to a first node, the input module is configured to transmit an input signal to the first node; the reverse module, the control module and the delay module are electrically connected to a second node, the reverse module is configured to transmit the potential of the first node to the second node after reversing, and the control module is configured to control the potential of the first node according to the potential of the second node; the delay module and the first output module are electrically connected to a third node, and the delay module is configured to transmit the potential of the second node to the third node after delaying. The present application only needs a sixth transistor to control the potential of the branch on the shift register, reduces the number of transistors, and is conducive to realizing a narrow frame.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a shift register and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, this application provides a shift register and a display panel, which aims to improve the performance of the display panel.

[0005] This application provides a shift register, including an input module, an inversion module, a delay module, a control module, a first output module, and a second output module;

[0006] The input module, the inverting module, the control module, and the second output module are electrically connected to the first node. The input module is used to transmit the input signal to the first node. The inversion module, the control module, and the delay module are electrically connected to the second node. The inversion module is used to invert the potential of the first node and transmit it to the second node. The control module controls the potential of the first node according to the potential of the second node. The delay module and the first output module are electrically connected to the third node. The delay module is used to delay the transmission of the potential of the second node to the third node. The first output module is used to respond to the potential output gate signal of the third node, and / or the second output module is used to respond to the potential output gate signal of the first node.

[0007] In one specific embodiment, the input module includes a first transistor and a second transistor, wherein the transistor type of the first transistor is opposite to that of the second transistor; The first terminal of the first transistor and the first terminal of the second transistor are electrically connected and connected to the input signal. The second terminals of the first transistor and the second terminal of the second transistor are both electrically connected to the first node. The gate of the first transistor is connected to the first clock signal, and the gate of the second transistor is connected to the second clock signal. The first clock signal and the second clock signal are inverse signals of each other. Optionally, the reverse module includes a fourth transistor and a fifth transistor, wherein the fourth transistor is an N-type transistor and the fifth transistor is a P-type transistor; The first terminal of the fifth transistor is connected to a first voltage, and the first terminal of the fourth transistor is connected to a second voltage. The voltage value of the first voltage is greater than the voltage value of the second voltage. The second terminals of both the fifth and fourth transistors are electrically connected to the second node, and the gates of both the fifth and fourth transistors are electrically connected to the first node. Optionally, the delay module includes a sixth transistor, the first terminal of the sixth transistor is electrically connected to the second node, the second terminal of the sixth transistor is electrically connected to the third node, and the gate of the sixth transistor is connected to a third clock signal. Optionally, the control module includes a seventh transistor, an eighth transistor, and a second capacitor. The first terminal of the seventh transistor is connected to a first voltage, the first terminal of the eighth transistor is connected to a third clock signal, the second terminals of the seventh transistor, the second terminals of the eighth transistor, and the first terminal of the second capacitor are electrically connected to a fourth node, the gate of the seventh transistor is electrically connected to the second node, and the gate of the eighth transistor and the second terminal of the second capacitor are both electrically connected to the first node. Optionally, the first output module includes a tenth transistor and a third capacitor. The first terminal of the tenth transistor is connected to a fourth clock signal, the second terminal of the tenth transistor is the output terminal of the tenth transistor, the gate of the tenth transistor is electrically connected to the third node, the first terminal of the third capacitor is electrically connected to the gate of the tenth transistor, and the second terminal of the third capacitor is electrically connected to the second terminal of the tenth transistor. The second output module includes an eleventh transistor. The first terminal of the eleventh transistor is connected to a second voltage, the second terminal of the eleventh transistor is the output terminal of the eleventh transistor, and the gate of the eleventh transistor is electrically connected to the first node.

[0008] In one specific embodiment, the input module further includes a first capacitor, the first terminal of the first capacitor is connected to a second voltage, and the second terminal of the first capacitor is electrically connected to a first node.

[0009] In one specific embodiment, it further includes a first protection module and a second protection module; The first protection module is located between the connection path of the delay module and the first output module. The first protection module is electrically connected to the delay module at the third node, and the first protection module is electrically connected to the first output module at the fifth node. The first output module is used to respond to the potential output gate signal of the fifth node. The second protection module is located between the connection path of the input module and the second output module. The second protection module is electrically connected to the input module at the first node, and the second protection module is electrically connected to the second output module at the sixth node. The control module controls the potential of the sixth node according to the potential of the second node, and the second output module is used to output a gate signal in response to the potential of the sixth node. Optionally, the gate of the tenth transistor is electrically connected to the fifth node, the gate of the eighth transistor and the second terminal of the second capacitor are both electrically connected to the sixth node, and the gate of the eleventh transistor is electrically connected to the sixth node.

[0010] In one specific embodiment, the first protection module includes a ninth transistor, the first terminal of the ninth transistor is electrically connected to the third node, the second terminal of the ninth transistor is electrically connected to the fifth node, and the gate of the ninth transistor is connected to a second voltage. The second protection module includes a third transistor, the first terminal of which is electrically connected to the first node, the second terminal of which is electrically connected to the sixth node, and the gate of which is connected to a second voltage.

[0011] This application provides another shift register, including an input module, an inversion module, a delay module, a control module, a first output module, and a second output module; The input module, the inverting module, the control module, and the second output module are electrically connected to the first node. The input module is used to transmit the input signal to the first node, and the control module controls the potential of the first node according to the output potential of the second output module. The inverting module and the delay module are electrically connected to the second node. The inverting module is used to invert the potential of the first node and transmit it to the second node. The delay module and the first output module are electrically connected to the third node. The delay module is used to delay the transmission of the potential of the second node to the third node. The first output module is used to respond to the potential output gate signal of the third node, and / or the second output module is used to respond to the potential output gate signal of the first node.

[0012] In one specific embodiment, the input module includes a first transistor and a second transistor, wherein the transistor type of the first transistor is opposite to that of the second transistor; The first terminal of the first transistor and the first terminal of the second transistor are electrically connected and connected to the input signal. The second terminals of the first transistor and the second terminal of the second transistor are both electrically connected to the first node. The gate of the first transistor is connected to the first clock signal, and the gate of the second transistor is connected to the second clock signal. The first clock signal and the second clock signal are inverse signals of each other. Optionally, the reverse module includes a fourth transistor and a fifth transistor, wherein the fourth transistor is an N-type transistor and the fifth transistor is a P-type transistor; The first terminal of the fifth transistor is connected to a first voltage, and the first terminal of the fourth transistor is connected to a second voltage. The voltage value of the first voltage is greater than the voltage value of the second voltage. The second terminals of both the fifth and fourth transistors are electrically connected to the second node, and the gates of both the fifth and fourth transistors are electrically connected to the first node. Optionally, the delay module includes a sixth transistor, the first terminal of the sixth transistor is electrically connected to the second node, the second terminal of the sixth transistor is electrically connected to the third node, and the gate of the sixth transistor is connected to a third clock signal. Optionally, the first output module includes a tenth transistor and a third capacitor. The first terminal of the tenth transistor is connected to a fourth clock signal, the second terminal of the tenth transistor is the output terminal of the tenth transistor, the gate of the tenth transistor is electrically connected to the third node, the first terminal of the third capacitor is electrically connected to the gate of the tenth transistor, and the second terminal of the third capacitor is electrically connected to the second terminal of the tenth transistor. The second output module includes an eleventh transistor, the first terminal of the eleventh transistor is connected to a second voltage, the second terminal of the eleventh transistor is the output terminal of the eleventh transistor, and the gate of the eleventh transistor is electrically connected to the first node. Optionally, the control module includes a fourth capacitor, the first terminal of which is electrically connected to the first node, and the second terminal of which is electrically connected to the second terminal of the eleventh transistor.

[0013] In one specific embodiment, the input module further includes a first capacitor, the first terminal of the first capacitor is connected to a second voltage, and the second terminal of the first capacitor is electrically connected to a first node.

[0014] In one specific embodiment, it further includes a first protection module and a second protection module; The first protection module is located between the connection path of the delay module and the first output module. The first protection module is electrically connected to the delay module at the third node, and the first protection module is electrically connected to the first output module at the fifth node. The first output module is used to respond to the potential output gate signal of the fifth node. The second protection module is located between the connection path of the input module and the second output module. The second protection module is electrically connected to the input module at the first node and to the second output module at the sixth node. The control module controls the potential of the sixth node according to the output potential of the second output module. The second output module is used to output a gate signal in response to the potential of the sixth node. Optionally, the gate of the tenth transistor is electrically connected to the fifth node, the gate of the eleventh transistor is electrically connected to the sixth node, and the first terminal of the fourth capacitor is electrically connected to the sixth node. Optionally, the first protection module includes a ninth transistor, the first terminal of the ninth transistor is electrically connected to the third node, the second terminal of the ninth transistor is electrically connected to the fifth node, and the gate of the ninth transistor is connected to a second voltage. The second protection module includes a third transistor, the first terminal of which is electrically connected to the first node, the second terminal of which is electrically connected to the sixth node, and the gate of which is connected to a second voltage.

[0015] This application also provides a display panel including a gate driving circuit, which includes a plurality of cascaded shift registers as described above.

[0016] The technical solution provided in this application embodiment only requires a sixth transistor to control the branch potential of the shift register. Compared with the prior art, which requires multiple transistors to control the branch potential of the shift register, the number of transistors is reduced, the layout space is reduced, and it is beneficial to achieve a narrow bezel.

[0017] It should be understood that the description in this section is not intended to identify key or important features of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a type of shift register in the prior art; Figure 2 A shift register architecture diagram provided in this application embodiment; Figure 3 A shift register structure diagram provided in an embodiment of this application; Figure 4 Another shift register structure diagram provided in this application embodiment; Figure 5 This application provides another shift register architecture diagram; Figure 6 Another shift register structure diagram provided in this application embodiment; Figure 7 A timing diagram of a shift register driver provided in an embodiment of this application; Figure 8 This application provides another shift register architecture diagram; Figure 9 Another shift register structure diagram provided in this application embodiment; Figure 10 Another shift register structure diagram provided in this application embodiment; Figure 11 This application provides another shift register architecture diagram; Figure 12Another shift register structure diagram provided in this application embodiment; Figure 13 This is a schematic diagram of a display panel structure provided in an embodiment of this application; Figure 14 This is a schematic diagram of the multi-stage shift register driving timing provided in an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0023] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0024] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Moreover, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. Connections may include direct connections or indirect connections. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor is turned on when its gate is connected to a high level and turned off when its gate is connected to a low level.

[0025] Figure 1 This is a type of shift register in the prior art, such as Figure 1 As shown, the upper branch of this shift register requires transistors M2_1 and M2_2 for control, while the lower branch requires transistors M4 and M5 and capacitor Cst2 for control. This results in a large number of transistors and a complex structure in the shift register, leading to insufficient array layout space and a large bezel on the display panel. To address this technical problem, this application provides a solution that effectively resolves the issue.

[0026] This application provides a shift register. Figure 2 A shift register architecture diagram provided for an embodiment of this application, such as... Figure 2As shown, the shift register includes an input module 101, an inverting module 102, a delay module 103, a control module 1041, a first output module 105, and a second output module 106. Specifically, the first terminal of the input module 101 is connected to the input signal SIN. The second terminal of the input module 101, the first terminal of the inverting module 102, the first terminal of the control module 1041, and the control terminal of the second output module 106 are electrically connected to the first node N1. The input module 101 is used to transmit the input signal SIN to the first node N1. The second terminal of the inverting module 102, the second terminal of the control module 1041, and the first terminal of the delay module 103 are electrically connected to the second node N2. The inverting module 102 is used to invert the potential of the first node N1 and transmit it to the second node N2. The control module 1041 controls the potential of the first node N1 according to the potential of the second node N2. The inverting module 102 inverts the input potential before outputting it. For example, the inverting module 102 inverts a high input level to a low output level, or vice versa. Therefore, the potential of the first node N1 is always opposite to that of the second node N2. Furthermore, the regulating module 1041 can lower or maintain the potential of the first node N1 based on the potential of the second node N2, enabling the second output module 106 to output normally. The second terminal of the delay module 103 and the control terminal of the first output module 105 are electrically connected to the third node N3. The delay module 103 is used to delay the transmission of the potential of the second node N2 to the third node N3, achieving row-by-row staggered transmission. The output terminals of both the first output module 105 and the second output module 106 are electrically connected to the output terminal of the shift register. The first output module 105 is used to output a gate signal Vout to the output terminal of the shift register in response to the potential of the third node N3, and / or the second output module 106 is used to output a gate signal Vout to the output terminal of the shift register in response to the potential of the first node N1. In this embodiment, the first output module 105 is controlled to turn on and off by the delay module 103, which simplifies the circuit structure and facilitates the implementation of a narrow bezel.

[0027] In one embodiment, Figure 3 A shift register structure diagram provided for an embodiment of this application, such as... Figure 3 As shown, the input module 101 includes a first transistor T1 and a second transistor T2 connected in parallel, wherein the transistor type of the first transistor T1 is opposite to that of the second transistor T2.

[0028] The first terminal of the first transistor T1 and the first terminal of the second transistor T2 are electrically connected and connected to the input signal SIN. The second terminals of the first transistor T1 and the second terminal of the second transistor T2 are both electrically connected to the first node N1. The gate of the first transistor T1 is connected to the first clock signal SCK1, and the gate of the second transistor T2 is connected to the second clock signal SCK1B. The first clock signal SCK1 and the second clock signal SCK1B are inverse signals, that is, at any time, the level of the first clock signal SCK1 and the level of the second clock signal SCK1B are opposite. Since the transistor types of the first transistor T1 and the second transistor T2 are opposite, the first transistor T1 and the second transistor T2 are always turned on and off simultaneously. In this embodiment, the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor. As can be seen from the characteristics of transistors, P-type transistors have a stronger driving capability for high levels, while N-type transistors have a stronger driving capability for low levels. When the input signal SIN is low, the second transistor T2 can transmit without loss, and when the input signal SIN is high, the first transistor T1 can transmit without loss. Regardless of whether the input signal SIN is high or low, this embodiment can transmit the input signal SIN to the first node N1 without loss, avoiding voltage loss.

[0029] Continue to refer to Figure 3 The reverse module 102 includes a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 is an N-type transistor, and the fifth transistor T5 is a P-type transistor. The first terminal of the fifth transistor T5 is connected to a first voltage, and the first terminal of the fourth transistor T4 is connected to a second voltage. The first voltage is greater than the second voltage. The second terminals of both the fifth transistor T5 and the fourth transistor T4 are electrically connected to a second node N2. The gates of both the fifth transistor T5 and the fourth transistor T4 are electrically connected to a first node N1. When the first node N1 is low, the fourth transistor T4 is off, and the fifth transistor T5 is on, transmitting the first voltage to the second node N2. When the first node N1 is high, the fourth transistor T4 is on, and the fifth transistor T5 is off, transmitting the second voltage to the second node N2, thus completing the reverse function. For example, the first voltage is a high level VGH, and the second voltage is a low level VGL.

[0030] Continue to refer to Figure 3The delay module 103 includes a sixth transistor T6. Exemplarily, the sixth transistor T6 is a P-type transistor. The first terminal of the sixth transistor T6 is electrically connected to the second node N2, and the second terminal of the sixth transistor T6 is electrically connected to the third node N3. The gate of the sixth transistor T6 is connected to a third clock signal SCK2, which delays the conduction of the sixth transistor T6. This embodiment requires only one transistor to control the on / off state of the first output module 105, simplifying the circuit structure and facilitating a narrow bezel effect.

[0031] Continue to refer to Figure 3 The control module 1041 includes a seventh transistor T7, an eighth transistor T8, and a second capacitor C2. For example, both the seventh transistor T7 and the eighth transistor T8 are P-type transistors. The first terminal of the seventh transistor T7 is connected to a first voltage, and the first terminal of the eighth transistor T8 is connected to a third clock signal SCK2. The second terminals of the seventh transistor T7, the eighth transistor T8, and the first terminal of the second capacitor C2 are electrically connected to the fourth node N4. The gate of the seventh transistor T7 is electrically connected to the second node N2, and the gate of the eighth transistor T8 and the second terminal of the second capacitor C2 are both electrically connected to the first node N1. When the potential of the fourth node N4 remains unchanged, the potential of the first node N1 is maintained through the second capacitor C2, so that the second output module 106 outputs stably. When the third clock signal SCK2 is transmitted to the fourth node N4, the third clock signal SCK2 jumps from a high level to a low level. Through the coupling effect of the second capacitor C2, the potential of the first node N1 is pulled down, making the potential of the first node N1 even lower, enhancing the driving capability of the second output module 106 and reducing the output voltage loss.

[0032] Continue to refer to Figure 3 The first output module 105 includes a tenth transistor T10 and a third capacitor C3. For example, the tenth transistor T10 is a P-type transistor. The first terminal of the tenth transistor T10 is connected to the fourth clock signal SCK3, and the second terminal of the tenth transistor T10 is its output terminal. The output terminal of the tenth transistor T10 is electrically connected to the output terminal of the shift register. The gate of the tenth transistor T10 is electrically connected to the third node N3. The first terminal of the third capacitor C3 is electrically connected to the gate of the tenth transistor T10, and the second terminal of the third capacitor C3 is electrically connected to the second terminal of the tenth transistor T10. When the fourth clock signal SCK3 is high, the tenth transistor T10 can output the high level of the fourth clock signal SCK3 without loss. When the fourth clock signal SCK3 transitions from high to low, the gate potential of the tenth transistor T10 is pulled down through the coupling effect of the third capacitor C3, enhancing the driving capability of the tenth transistor T10, reducing the low-level loss of the output fourth clock signal SCK3, and improving the quality of the gate signal Vout.

[0033] The second output module 106 includes an eleventh transistor T11. For example, the eleventh transistor T11 is a P-type transistor. The first terminal of the eleventh transistor T11 is connected to a second voltage, the second terminal of the eleventh transistor T11 is the output terminal of the eleventh transistor T11, the output terminal of the eleventh transistor T11 is electrically connected to the output terminal of the shift register, and the gate of the eleventh transistor T11 is electrically connected to the first node N1.

[0034] In one embodiment, Figure 4 Another shift register structure diagram provided in this application embodiment, such as Figure 4 As shown, the input module 101 also includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to a second voltage, and the second terminal of the first capacitor C1 is electrically connected to the first node N1. The potential of the first node N1 is maintained by the first capacitor C1, thereby extending the duration of the potential of the first node N1.

[0035] In one embodiment, Figure 5 Another shift register architecture diagram provided for embodiments of this application, such as Figure 5 As shown, the shift register also includes a first protection module 107 and a second protection module 108. Specifically, the first protection module 107 is located between the connection path of the delay module 103 and the first output module 105. The first terminal of the first protection module 107 is electrically connected to the second terminal of the delay module 103 at the third node N3, and the second terminal of the first protection module 107 is electrically connected to the control terminal of the first output module 105 at the fifth node N5. The first output module 105 is used to output the gate signal Vout in response to the potential of the fifth node N5.

[0036] The second protection module 108 is located between the connection path of the input module 101 and the second output module 106. The first end of the second protection module 108 is electrically connected to the second end of the input module 101 at the first node N1. The second end of the second protection module 108 is electrically connected to the control end of the second output module 106 at the sixth node N6. The control module 1041 controls the potential of the sixth node N6 according to the potential of the second node N2. The second output module 106 is used to output the gate signal Vout in response to the potential of the sixth node N6.

[0037] Specifically, the gate of the tenth transistor T10 is electrically connected to the fifth node N5, the gate of the eighth transistor T8 and the second terminal of the second capacitor C2 are both electrically connected to the sixth node N6, and the gate of the eleventh transistor T11 is electrically connected to the sixth node N6.

[0038] In one embodiment, Figure 6 Another shift register structure diagram provided in this application embodiment, such as Figure 6As shown, the first protection module 107 includes a ninth transistor T9. For example, the ninth transistor T9 is a P-type transistor. The first terminal of the ninth transistor T9 is electrically connected to the third node N3, and the second terminal of the ninth transistor T9 is electrically connected to the fifth node N5. The gate of the ninth transistor T9 is connected to a second voltage. By setting the ninth transistor T9, the extremely low level of the fifth node N5 can be prevented from being transmitted to the sixth transistor T6, thereby protecting the sixth transistor T6 from damage.

[0039] The second protection module 108 includes a third transistor T3. For example, the third transistor T3 is a P-type transistor. The first terminal of the third transistor T3 is electrically connected to the first node N1, and the second terminal of the third transistor T3 is electrically connected to the sixth node N6. The gate of the third transistor T3 is connected to a second voltage. By setting the third transistor T3, the extremely low level of the sixth node N6 can be prevented from being transmitted to the first transistor T1, thereby protecting the first transistor T1 from damage.

[0040] In one embodiment, Figure 7 This application provides a timing diagram of a shift register driver, which is illustrated below in conjunction with an embodiment of the present application. Figure 7 right Figure 6 The working process of the shift register shown is described.

[0041] Phase 1 (t1): Input signal SIN is high (VGH), first clock signal SCK1 is low (VGL), second clock signal SCK1B is high (VGH), first transistor T1 and second transistor T2 are both turned on. The high level (VGH) of input signal SIN is transmitted to the first node N1, and the potential of the first node N1 becomes high (VGH). The high level (VGH) of the first node N1 is transmitted through the third transistor T3 to the sixth node N6, and the potential of the sixth node N6 becomes high (VGH). The eighth transistor T8 turns off in response to the high level (VGH) of the sixth node N6, and the eleventh transistor T11 turns off in response to the high level (VGH) of the sixth node N6. The fifth transistor T5 turns off in response to the high level (VGH) of the first node N1. When transistor GH is turned off, transistor T4 turns on in response to the high level VGH of node N1. Transistor T4 transmits the second voltage to node N2, where the second voltage is low level VGL. Transistor T7 turns on in response to the low level VGL of node N2. Transistor T7 transmits the first voltage to node N4, where the first voltage is high level VGH. The potential of node N4 is high level VGH, and the third clock signal SCK2 is high level VGH. Transistor T6 is turned off, and the sixth transistor T6 is delayed in turning on by the third clock signal SCK2. During this stage, the potential of node N2 cannot be transmitted to node N3 and node N5, and transistor T10 is delayed in turning on. During this stage, transistors T10 and T11 are both turned off, and the gate signal Vout output by the shift register remains low level as in the previous stage.

[0042] In the second stage t2: the input signal SIN remains high at VGH, the first clock signal SCK1 transitions to high at VGH, the second clock signal SCK1B transitions to low at VGL, the first transistor T1 and the second transistor T2 are both turned off, the first node N1 remains high at VGH through the first capacitor C1, the high level VGH of the first node N1 is transmitted to the sixth node N6 through the third transistor T3, the potential of the sixth node N6 becomes high at VGH, the eighth transistor T8 turns off in response to the high level VGH of the sixth node N6, the eleventh transistor T11 turns off in response to the high level VGH of the sixth node N6; the fifth transistor T5 turns off in response to the high level VGH of the first node N1, the fourth transistor T4 turns on in response to the high level VGH of the first node N1, and the... Transistor T4 transmits the second voltage to node N2, where it is low (VGL). Transistor T7 turns on in response to the low VGL at node N2, transmitting the first voltage to node N4, where it is high (VGH). Node N4's potential is also high (VGH). The third clock signal SCK2 transitions to low (VGL), turning on transistor T6. The low VGL at node N2 is then transmitted through transistors T6 and T9 to node N5, where it is low (VGL). Transistor T10 turns on in response to the low VGL at node N5, outputting the fourth clock signal SCK3 to the shift register's output as the gate signal Vout. During this phase, the fourth clock signal SCK3 is high (VGH), therefore the shift register's output gate signal Vout is also high (VGH).

[0043] In the third stage (t3): the input signal SIN transitions to low level VGL, the first clock signal SCK1 transitions to low level VGL, and the second clock signal SCK1B transitions to high level VGH. Both the first transistor T1 and the second transistor T2 are turned on. The low level VGL of the input signal SIN is transmitted to the first node N1, and the potential of the first node N1 becomes low level VGL. The low level VGL of the first node N1 is transmitted through the third transistor T3 to the sixth node N6, and the potential of the sixth node N6 becomes low level VGL. The eighth transistor T8 responds to the low level VGL of the sixth node N6 and turns on. The third clock signal SCK2 transitions to high level VGH. The eighth transistor T8 transmits the high level VGH of the third clock signal SCK2 to the fourth node N4, and the potential of the fourth node N4 becomes high level VGH. The eleventh transistor T11 responds to the sixth node... When N6 is low (VGL), it turns on and outputs the second voltage. The fourth transistor T4 turns off in response to the low VGL of the first node N1, and the fifth transistor T5 turns on in response to the low VGL of the first node N1. The fifth transistor T5 transmits the first voltage to the second node N2, where the first voltage is high (VGH). The potential of the second node N2 is also high (VGH). The seventh transistor T7 turns off in response to the high VGH of the second node N2. The third clock signal SCK2 is high (VGH), the sixth transistor T6 turns off, and the tenth transistor T10 remains on. The fourth clock signal SCK3 changes from high (VGH) to low (VGL). Through the coupling effect of the third capacitor C3, the potential of the fifth node N5 is pulled down to a level lower than the low VGL, enhancing the driving capability of the tenth transistor T10 and outputting the fourth clock signal SCK3. During this stage, both the tenth transistor T10 and the eleventh transistor T11 are turned on, the second voltage is low level VGL, and the fourth clock signal SCK3 is also low level VGL. Therefore, the gate signal Vout output by the shift register is low level VGL.

[0044] In stage t4: the input signal SIN remains low (VGL), the first clock signal SCK1 transitions to high (VGH), and the second clock signal SCK1B transitions to low (VGL). Both the first transistor T1 and the second transistor T2 are turned off. The first node N1 maintains a low (VGL) level through the first capacitor C1. This low (VGL) level of node N1 is transmitted to the sixth node N6 via the third transistor T3, causing the potential of the sixth node N6 to become low (VGL). The eighth transistor T8 turns on in response to the low (VGL) level of the sixth node N6. The third clock signal SCK2 transitions from high (VGH) to low (VGL), and the potential of the fourth node N4 also transitions from high (VGH) to low (VGL). Through the coupling effect of the second capacitor C2, the potential of the sixth node N6 is pulled down to below the low (VG) level. The potential of L enhances the driving capability of the eleventh transistor T11, outputting the second voltage. The fourth transistor T4 turns off in response to the low level VGL of the first node N1, and the fifth transistor T5 turns on in response to the low level VGL of the first node N1. The fifth transistor T5 transmits the first voltage to the second node N2, where the first voltage is a high level VGH, and the potential of the second node N2 is a high level VGH. The seventh transistor T7 turns off in response to the high level VGH of the second node N2. The third clock signal SCK2 is a low level VGL, and the sixth transistor T6 turns on. The high level VGH of the second node N2 is transmitted to the fifth node N5 through the sixth transistor T6 and the ninth transistor T9, where the potential of the fifth node N5 is a high level VGH. The tenth transistor T10 turns off in response to the high level VGH of the fifth node N5. During this stage, the second voltage is a low level VGL, therefore the gate signal Vout output by the shift register is a low level VGL.

[0045] The driving timing after the fourth stage t4 of the current display frame repeats the timing of the third stage t3 and the fourth stage t4. That is, the timing of the fifth stage is the same as the timing of the third stage t3, the timing of the sixth stage is the same as the timing of the fourth stage t4, the timing of the seventh stage is the same as the timing of the third stage t3, the timing of the eighth stage is the same as the timing of the fourth stage t4, and so on (not shown in the figure) until the end of the current display frame.

[0046] In this embodiment, only one sixth transistor T6 is needed to control the potential of the upper branch of the shift register (where the upper branch refers to the branch electrically connected to the gate of the tenth transistor T10). Compared with the prior art, which requires multiple transistors to control the potential of the upper branch of the shift register, the number of transistors is reduced, the layout space is reduced, and it is beneficial to achieve a narrow bezel.

[0047] This application provides another shift register. Figure 8 Another shift register architecture diagram provided for embodiments of this application, such as Figure 8As shown, the shift register includes an input module 101, an inverting module 102, a delay module 103, a control module 1042, a first output module 105, and a second output module 106. Specifically, the first terminal of the input module 101 is connected to the input signal SIN. The second terminal of the input module 101, the first terminal of the inverting module 102, the first terminal of the control module 1042, and the control terminal of the second output module 106 are electrically connected to the first node N1. The input module 101 is used to transmit the input signal SIN to the first node N1. The control module 1042 controls the potential of the first node N1 according to the potential of the output terminal of the second output module 106. The second terminal of the inverting module 102 and the first terminal of the delay module 103 are electrically connected to the second node N2. The inverting module 102 is used to invert the potential of the first node N1 and transmit it to the second node N2. For example, the inverting module 102 inverts the input high level to a low level output, or the inverting module 102 inverts the input low level to a high level output. Therefore, the potential of the first node N1 and the potential of the second node N2 are always opposite. The second terminal of the delay module 103 and the control terminal of the first output module 105 are electrically connected to the third node N3. The delay module 103 is used to delay the transmission of the potential of the second node N2 to the third node N3. The output terminals of the first output module 105 and the second output module 106 are both electrically connected to the output terminal of the shift register. The first output module 105 is used to output a gate signal Vout to the output terminal of the shift register in response to the potential of the third node N3, and / or the second output module 106 is used to output a gate signal Vout to the output terminal of the shift register in response to the potential of the first node N1.

[0048] In one embodiment, Figure 9 Another shift register structure diagram provided in this application embodiment, such as Figure 9 As shown, the input module 101 includes a first transistor T1 and a second transistor T2 connected in parallel, wherein the transistor type of the first transistor T1 is opposite to that of the second transistor T2.

[0049] The first terminal of the first transistor T1 and the first terminal of the second transistor T2 are electrically connected and connected to the input signal SIN. The second terminals of the first transistor T1 and the second terminal of the second transistor T2 are both electrically connected to the first node N1. The gate of the first transistor T1 is connected to the first clock signal SCK1, and the gate of the second transistor T2 is connected to the second clock signal SCK1B. The first clock signal SCK1 and the second clock signal SCK1B are inverse signals, that is, at any time, the level of the first clock signal SCK1 and the level of the second clock signal SCK1B are opposite. Since the transistor types of the first transistor T1 and the second transistor T2 are opposite, the first transistor T1 and the second transistor T2 are always turned on and off simultaneously. In this embodiment, the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor. As can be seen from the characteristics of transistors, P-type transistors have a stronger driving capability for high levels, while N-type transistors have a stronger driving capability for low levels. When the input signal SIN is low, the second transistor T2 can transmit without loss, and when the input signal SIN is high, the first transistor T1 can transmit without loss. Regardless of whether the input signal SIN is high or low, this embodiment can transmit the input signal SIN to the first node N1 without loss, avoiding voltage loss.

[0050] Continue to refer to Figure 9 The reverse module 102 includes a fourth transistor T4 and a fifth transistor T5. The fourth transistor T4 is an N-type transistor, and the fifth transistor T5 is a P-type transistor. The first terminal of the fifth transistor T5 is connected to a first voltage, and the first terminal of the fourth transistor T4 is connected to a second voltage. The first voltage is greater than the second voltage. The second terminals of both the fifth transistor T5 and the fourth transistor T4 are electrically connected to the second node N2. The gates of both the fifth transistor T5 and the fourth transistor T4 are electrically connected to the first node N1. When the first node N1 is low, the fourth transistor T4 is off, and the fifth transistor T5 is on, transmitting the first voltage to the second node N2. When the first node N1 is high, the fourth transistor T4 is on, and the fifth transistor T5 is off, transmitting the second voltage to the second node N2, thus completing the reverse function.

[0051] Continue to refer to Figure 9 The delay module 103 includes a sixth transistor T6. For example, the sixth transistor T6 is a P-type transistor. The first terminal of the sixth transistor T6 is electrically connected to the second node N2, the second terminal of the sixth transistor T6 is electrically connected to the third node N3, and the gate of the sixth transistor T6 is connected to the third clock signal SCK2.

[0052] The control module 1042 includes a fourth capacitor C4. The first terminal of the fourth capacitor C4 is electrically connected to the first node N1, and the second terminal of the fourth capacitor C4 is electrically connected to the output terminal of the second output module 106. When the potential of the output terminal of the second output module 106 remains unchanged, that is, when the potential of the shift register output terminal remains unchanged, the potential of the first node N1 is maintained through the fourth capacitor C4, so that the second output module 106 outputs stably. When the potential of the shift register output terminal jumps from high level to low level, the potential of the first node N1 is pulled down through the coupling effect of the fourth capacitor C4, so that the potential of the first node N1 becomes lower, thereby enhancing the driving capability of the second output module 106 and reducing the output voltage loss.

[0053] Continue to refer to Figure 9 The first output module 105 includes a tenth transistor T10 and a third capacitor C3. For example, the tenth transistor T10 is a P-type transistor. The first terminal of the tenth transistor T10 is connected to the fourth clock signal SCK3, and the second terminal of the tenth transistor T10 is its output terminal. The output terminal of the tenth transistor T10 is electrically connected to the output terminal of the shift register. The gate of the tenth transistor T10 is electrically connected to the third node N3. The first terminal of the third capacitor C3 is electrically connected to the gate of the tenth transistor T10, and the second terminal of the third capacitor C3 is electrically connected to the second terminal of the tenth transistor T10. When the fourth clock signal SCK3 is high, the tenth transistor T10 can output the high level of the fourth clock signal SCK3 without loss. When the fourth clock signal SCK3 transitions from high to low, the gate potential of the tenth transistor T10 is pulled down through the coupling effect of the third capacitor C3, enhancing the driving capability of the tenth transistor T10, reducing the low-level loss of the output fourth clock signal SCK3, and improving the quality of the gate signal Vout.

[0054] The second output module 106 includes an eleventh transistor T11. For example, the eleventh transistor T11 is a P-type transistor. The first terminal of the eleventh transistor T11 is connected to a second voltage, and the second terminal of the eleventh transistor T11 is the output terminal of the eleventh transistor T11, that is, the output terminal of the second output module 106. The output terminal of the eleventh transistor T11 is electrically connected to the output terminal of the shift register, and the gate of the eleventh transistor T11 is electrically connected to the first node N1.

[0055] In one embodiment, Figure 10 Another shift register structure diagram provided in this application embodiment, such as Figure 10 As shown, the input module 101 also includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to a second voltage, and the second terminal of the first capacitor C1 is electrically connected to the first node N1. The potential of the first node N1 is maintained by the first capacitor C1, thereby extending the duration of the potential of the first node N1.

[0056] In one embodiment, Figure 11 Another shift register architecture diagram provided for embodiments of this application, such as Figure 11 As shown, the shift register also includes a first protection module 107 and a second protection module 108. Specifically, the first protection module 107 is located between the connection path of the delay module 103 and the first output module 105. The first terminal of the first protection module 107 is electrically connected to the second terminal of the delay module 103 at the third node N3, and the second terminal of the first protection module 107 is electrically connected to the control terminal of the first output module 105 at the fifth node N5. The first output module 105 is used to output the gate signal Vout in response to the potential of the fifth node N5.

[0057] The second protection module 108 is located between the connection path of the input module 101 and the second output module 106. The first end of the second protection module 108 is electrically connected to the second end of the input module 101 at the first node N1. The second end of the second protection module 108 is electrically connected to the control end of the second output module 106 at the sixth node N6. The control module 1042 controls the potential of the sixth node N6 according to the potential of the output end of the second output module 106. The second output module 106 outputs a gate signal Vout in response to the potential of the sixth node N6.

[0058] Specifically, the gate of the tenth transistor T10 is electrically connected to the fifth node N5, the gate of the eleventh transistor T11 is electrically connected to the sixth node N6, and the first terminal of the fourth capacitor C4 is electrically connected to the sixth node N6.

[0059] In one embodiment, Figure 12 Another shift register structure diagram provided in this application embodiment, such as Figure 12 As shown, the first protection module 107 includes a ninth transistor T9. For example, the ninth transistor T9 is a P-type transistor. The first terminal of the ninth transistor T9 is electrically connected to the third node N3, and the second terminal of the ninth transistor T9 is electrically connected to the fifth node N5. The gate of the ninth transistor T9 is connected to a second voltage. By setting the ninth transistor T9, the extremely low level of the fifth node N5 can be prevented from being transmitted to the sixth transistor T6, thereby protecting the sixth transistor T6 from damage.

[0060] The second protection module 108 includes a third transistor T3. For example, the third transistor T3 is a P-type transistor. The first terminal of the third transistor T3 is electrically connected to the first node N1, and the second terminal of the third transistor T3 is electrically connected to the sixth node N6. The gate of the third transistor T3 is connected to a second voltage. By setting the third transistor T3, the extremely low level of the sixth node N6 can be prevented from being transmitted to the first transistor T1, thereby protecting the first transistor T1 from damage.

[0061] In one embodiment, Figure 7 The driving timing shown also applies. Figure 12 The shift register shown below, in conjunction with Figure 7 right Figure 12 The working process of the shift register shown is described.

[0062] In the first stage (t1): the input signal SIN is high (VGH), the first clock signal SCK1 is low (VGL), and the second clock signal SCK1B is high (VGH). Both the first transistor T1 and the second transistor T2 are turned on. The high level (VGH) of the input signal SIN is transmitted to the first node N1, causing the potential of node N1 to become high (VGH). This high level (VGH) is then transmitted through the third transistor T3 to the sixth node N6, causing the potential of node N6 to become high (VGH). The eleventh transistor T11 turns off in response to the high level (VGH) of node N6. The fifth transistor T5 turns off in response to the high level (VGH) of node N1, and the fourth transistor T4 turns on in response to the high level (VGH) of node N1. The fourth transistor T4 transmits the second voltage to the second node N2, where the second voltage is low (VGL). The third clock signal SCK2 is high (VGH), and the sixth transistor T6 turns off. In this stage, both the tenth transistor T10 and the eleventh transistor T11 are turned off, and the gate signal Vout output by the shift register remains low as in the previous stage.

[0063] In the second stage t2: the input signal SIN remains high (VGH), the first clock signal SCK1 transitions to high (VGH), and the second clock signal SCK1B transitions to low (VGL). Both the first transistor T1 and the second transistor T2 are turned off. The first node N1 maintains a high level (VGH) through the first capacitor C1. This high level (VGH) of the first node N1 is transmitted to the sixth node N6 via the third transistor T3, causing the potential of the sixth node N6 to become high (VGH). The eleventh transistor T11 turns off in response to the high level (VGH) of the sixth node N6; the fifth transistor T5 also turns off in response to the high level (VGH) of the first node N1. The fourth transistor T4 turns on in response to the high level VGH of the first node N1, transmitting the second voltage to the second node N2, where the second voltage is low level VGL. The third clock signal SCK2 transitions to low level VGL, and the sixth transistor T6 turns on. The low level VGL of the second node N2 is transmitted to the fifth node N5 through the sixth transistor T6 and the ninth transistor T9, where the potential of the fifth node N5 is low level VGL. The tenth transistor T10 turns on in response to the low level VGL of the fifth node N5, outputting the fourth clock signal SCK3 to the output of the shift register as the gate signal Vout. During this stage, the fourth clock signal SCK3 is high level VGH, therefore the gate signal Vout output by the shift register is high level VGH.

[0064] In the third stage (t3): the input signal SIN transitions to a low level (VGL), the first clock signal SCK1 transitions to a low level (VGL), and the second clock signal SCK1B transitions to a high level (VGH). Both the first transistor T1 and the second transistor T2 are turned on. The low level (VGL) of the input signal SIN is transmitted to the first node N1, causing the potential of the first node N1 to become low (VGL). This low level (VGL) of the first node N1 is then transmitted through the third transistor T3 to the sixth node N6, causing the potential of the sixth node N6 to become low (VGL). The eleventh transistor T11 turns on in response to the low level (VGL) of the sixth node N6, outputting the second voltage. The fourth transistor T4 turns off in response to the low level (VGL) of the first node N1, and the fifth transistor T5 turns off in response to the low level (VGH) of the first node N1. When transistor L is turned on, the fifth transistor T5 transmits the first voltage to the second node N2, where the first voltage is high (VGH). The potential of the second node N2 is also high (VGH), and the third clock signal SCK2 is high (VGH). The sixth transistor T6 is turned off, and the tenth transistor T10 remains on. The fourth clock signal SCK3 transitions from high (VGH) to low (VGL). Through the coupling effect of the third capacitor C3, the potential of the fifth node N5 is pulled down to a level lower than VGL, enhancing the driving capability of the tenth transistor T10 and outputting the fourth clock signal SCK3. Simultaneously, through the coupling effect of the fourth capacitor C4, the potential of the sixth node N6 is pulled down to a level lower than VGL, enhancing the driving capability of the eleventh transistor T11. During this stage, both the tenth transistor T10 and the eleventh transistor T11 are on, the second voltage is low (VGL), and the fourth clock signal SCK3 is also low (VGL). Therefore, the gate signal Vout output by the shift register is low (VGL).

[0065] In stage 4 (t4): the input signal SIN remains low (VGL), the first clock signal SCK1 transitions to high (VGH), and the second clock signal SCK1B transitions to low (VGL). Both the first transistor T1 and the second transistor T2 are turned off. The first node N1 maintains a low (VGL) level through the first capacitor C1. This low (VGL) level of the first node N1 is transmitted to the sixth node N6 via the third transistor T3. The potential of the sixth node N6 is low (VGL). The eleventh transistor T11 turns on in response to the low (VGL) level of the sixth node N6, outputting the second voltage. The fourth transistor T4 responds to the first stage... When the low-level VGL of node N1 is turned off, the fifth transistor T5 turns on in response to the low-level VGL of node N1. Transmitting the first voltage to node N2, this first voltage is a high-level VGH. The potential of node N2 is also a high-level VGH. The third clock signal SCK2 is a low-level VGL, and the sixth transistor T6 turns on. The high-level VGH of node N2 is transmitted to node N5 through the sixth transistor T6 and the ninth transistor T9. The potential of node N5 is also a high-level VGH. The tenth transistor T10 turns off in response to the high-level VGH of node N5. During this stage, the eleventh transistor T11 outputs a second voltage, which is a low-level VGL. Therefore, the gate signal Vout output by the shift register is a low-level VGL.

[0066] The driving timing after the fourth stage t4 of the current display frame repeats the timing of the third stage t3 and the fourth stage t4. That is, the timing of the fifth stage is the same as the timing of the third stage t3, the timing of the sixth stage is the same as the timing of the fourth stage t4, the timing of the seventh stage is the same as the timing of the third stage t3, the timing of the eighth stage is the same as the timing of the fourth stage t4, and so on (not shown in the figure) until the end of the current display frame.

[0067] In this embodiment, only one sixth transistor T6 is needed to control the upper branch potential of the shift register, and one capacitor is needed to control the lower branch potential of the shift register (where the upper branch refers to the branch electrically connected to the gate of the tenth transistor T10, and the lower branch refers to the branch electrically connected to the gate of the eleventh transistor T11). Compared with the prior art, which requires multiple transistors to control the upper and lower branch potentials of the shift register, the number of transistors is reduced, the circuit structure is simplified, the layout space is further reduced, and it is easier to achieve a narrow bezel.

[0068] It should be noted that the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node N5, and the sixth node N6 in the embodiments of this application do not refer to specific structures, but rather represent electrical connection paths between structures. A node may include one electrical connection path or multiple intersecting electrical connection paths, and the potentials in the same node are the same.

[0069] This application embodiment also provides a display panel. Figure 13 This is a schematic diagram of a display panel structure provided in an embodiment of this application, such as... Figure 13As shown, the display panel 200 includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA is provided with a plurality of pixel circuits PIX, which are arranged in an array. The non-display area NA is provided with a gate driving circuit, which includes a plurality of shift registers as described in the above embodiment. The plurality of shift registers are cascaded. The input terminal of the nth-stage shift register is electrically connected to the output terminal of the (n-1)th-stage shift register. The input terminal of the first-stage shift register is connected to the input signal SIN. Each stage shift register is electrically connected to a row of pixel circuits PIX. For example, the first-stage shift register SR1 is electrically connected to the first row of pixel circuits PIX, the second-stage shift register SR2 is electrically connected to the second row of pixel circuits PIX, the third-stage shift register SR3 is electrically connected to the third row of pixel circuits PIX, and the fourth-stage shift register SR4 is electrically connected to the fourth row of pixel circuits PIX. The non-display area NA is also provided with a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, and a sixth clock signal line CLK6. The first clock signal line CLK1 transmits the first clock signal SCK1, the second clock signal line CLK2 transmits the second clock signal SCK1B, the third clock signal line CLK3 transmits the third clock signal SCK2, the fourth clock signal line CLK4 transmits the fifth clock signal SCK2B, the fifth clock signal line CLK5 transmits the fourth clock signal SCK3, and the sixth clock signal line CLK6 transmits the sixth clock signal SCK4. In this embodiment, signal terminal 1 of the first-stage shift register SR1 is electrically connected to the first clock signal line CLK1, signal terminal 2 of the first-stage shift register SR1 is electrically connected to the second clock signal line CLK2, signal terminal 3 of the first-stage shift register SR1 is electrically connected to the third clock signal line CLK3, and signal terminal 4 of the first-stage shift register SR1 is electrically connected to the fifth clock signal line CLK5; signal terminal 1 of the second-stage shift register SR2 is electrically connected to the third clock signal line CLK3, signal terminal 2 of the second-stage shift register SR2 is electrically connected to the fourth clock signal line CLK4, signal terminal 3 of the second-stage shift register SR2 is electrically connected to the first clock signal line CLK1, and signal terminal 4 of the second-stage shift register SR2 is electrically connected to the sixth clock signal line CLK6.The subsequent shift registers are electrically connected to the clock signal lines in a cyclical manner, repeating the method used for the first-stage shift register SR1 and the second-stage shift register SR2. That is, the odd-numbered shift registers are electrically connected to the clock signal lines in the same way as the first-stage shift register SR1, and the even-numbered shift registers are electrically connected to the clock signal lines in the same way as the second-stage shift register SR2. For example, the third-stage shift register SR3 is electrically connected to the clock signal lines in the same way as the first-stage shift register SR1, and the fourth-stage shift register SR4 is electrically connected to the clock signal lines in the same way as the second-stage shift register SR2.

[0070] In one embodiment, Figure 14 This is a schematic diagram of the multi-stage shift register driving timing provided in an embodiment of this application, as shown below. Figure 14 As shown, the first clock signal SCK1 and the second clock signal SCK1B are inverted signals, the third clock signal SCK2 and the fifth clock signal SCK2B are inverted signals, the first clock signal SCK1 and the third clock signal SCK2 are spaced half a clock cycle apart, and the fourth clock signal SCK3 and the sixth clock signal SCK4 are spaced half a clock cycle apart, thereby realizing the shifted output of the gate signal Vout. For example... Figure 14 The output gate signal Vout of the seven-stage shift register is shown, with gate signals Vout1 to Vout7 shifted and output.

[0071] The display panel 200 of this application embodiment can be applied to mobile phones, or to any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This application embodiment does not make any special limitations on this.

[0072] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0073] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A shift register, characterized in that, It includes an input module, an inversion module, a delay module, a control module, a first output module, and a second output module; The input module, the inversion module, the control module, and the second output module are electrically connected to the first node, and the input module is used to transmit the input signal to the first node; The reverse module, the control module, and the delay module are electrically connected to the second node. The reverse module is used to reverse the potential of the first node and transmit it to the second node. The control module controls the potential of the first node according to the potential of the second node. The delay module and the first output module are electrically connected to the third node, and the delay module is used to delay the transmission of the potential of the second node to the third node; The first output module is used to respond to the potential output gate signal of the third node, and / or the second output module is used to respond to the potential output gate signal of the first node.

2. The shift register according to claim 1, characterized in that, The input module includes a first transistor and a second transistor, wherein the transistor type of the first transistor is opposite to that of the second transistor; The first terminal of the first transistor and the first terminal of the second transistor are electrically connected and connected to the input signal. The second terminals of the first transistor and the second terminal of the second transistor are both electrically connected to the first node. The gate of the first transistor is connected to the first clock signal, and the gate of the second transistor is connected to the second clock signal. The first clock signal and the second clock signal are inverse signals of each other. Preferably, the reverse module includes a fourth transistor and a fifth transistor, wherein the fourth transistor is an N-type transistor and the fifth transistor is a P-type transistor; The first terminal of the fifth transistor is connected to a first voltage, the first terminal of the fourth transistor is connected to a second voltage, the voltage value of the first voltage is greater than the voltage value of the second voltage, the second terminals of the fifth transistor and the fourth transistor are both electrically connected to the second node, and the gates of the fifth transistor and the fourth transistor are both electrically connected to the first node. Preferably, the delay module includes a sixth transistor, the first terminal of the sixth transistor is electrically connected to the second node, the second terminal of the sixth transistor is electrically connected to the third node, and the gate of the sixth transistor is connected to a third clock signal; Preferably, the control module includes a seventh transistor, an eighth transistor, and a second capacitor. The first terminal of the seventh transistor is connected to the first voltage, the first terminal of the eighth transistor is connected to the third clock signal, the second terminals of the seventh transistor, the second terminals of the eighth transistor, and the first terminal of the second capacitor are electrically connected to a fourth node, the gate of the seventh transistor is electrically connected to the second node, and the gate of the eighth transistor and the second terminal of the second capacitor are both electrically connected to the first node. Preferably, the first output module includes a tenth transistor and a third capacitor. The first terminal of the tenth transistor is connected to a fourth clock signal, the second terminal of the tenth transistor is the output terminal of the tenth transistor, the gate of the tenth transistor is electrically connected to the third node, the first terminal of the third capacitor is electrically connected to the gate of the tenth transistor, and the second terminal of the third capacitor is electrically connected to the second terminal of the tenth transistor. The second output module includes an eleventh transistor, the first terminal of which is connected to the second voltage, the second terminal of which is the output terminal, and the gate of which is electrically connected to the first node.

3. The shift register according to claim 2, characterized in that, The input module further includes a first capacitor, the first terminal of which is connected to the second voltage, and the second terminal of which is electrically connected to the first node.

4. The shift register according to claim 2, characterized in that, It also includes a first protection module and a second protection module; The first protection module is located between the connection path of the delay module and the first output module. The first protection module is electrically connected to the delay module at the third node, and the first protection module is electrically connected to the first output module at the fifth node. The first output module is used to output the gate signal in response to the potential of the fifth node. The second protection module is located between the connection path of the input module and the second output module. The second protection module is electrically connected to the input module at the first node, and the second protection module is electrically connected to the second output module at the sixth node. The control module controls the potential of the sixth node according to the potential of the second node, and the second output module is used to output the gate signal in response to the potential of the sixth node. Preferably, the gate of the tenth transistor is electrically connected to the fifth node, the gate of the eighth transistor and the second terminal of the second capacitor are both electrically connected to the sixth node, and the gate of the eleventh transistor is electrically connected to the sixth node.

5. The shift register according to claim 4, characterized in that, The first protection module includes a ninth transistor, the first terminal of which is electrically connected to the third node, the second terminal of which is electrically connected to the fifth node, and the gate of which is connected to the second voltage; The second protection module includes a third transistor, the first terminal of which is electrically connected to the first node, the second terminal of which is electrically connected to the sixth node, and the gate of which is connected to the second voltage.

6. A shift register, characterized in that, It includes an input module, an inversion module, a delay module, a control module, a first output module, and a second output module; The input module, the inverting module, the control module, and the second output module are electrically connected to the first node. The input module is used to transmit the input signal to the first node, and the control module controls the potential of the first node according to the output potential of the second output module. The inversion module and the delay module are electrically connected to the second node. The inversion module is used to invert the potential of the first node and transmit it to the second node. The delay module and the first output module are electrically connected to the third node, and the delay module is used to delay the transmission of the potential of the second node to the third node; The first output module is used to respond to the potential output gate signal of the third node, and / or the second output module is used to respond to the potential output gate signal of the first node.

7. The shift register according to claim 6, characterized in that, The input module includes a first transistor and a second transistor, wherein the transistor type of the first transistor is opposite to that of the second transistor; The first terminal of the first transistor and the first terminal of the second transistor are electrically connected and connected to the input signal. The second terminals of the first transistor and the second terminal of the second transistor are both electrically connected to the first node. The gate of the first transistor is connected to the first clock signal, and the gate of the second transistor is connected to the second clock signal. The first clock signal and the second clock signal are inverse signals of each other. Preferably, the reverse module includes a fourth transistor and a fifth transistor, wherein the fourth transistor is an N-type transistor and the fifth transistor is a P-type transistor; The first terminal of the fifth transistor is connected to a first voltage, the first terminal of the fourth transistor is connected to a second voltage, the voltage value of the first voltage is greater than the voltage value of the second voltage, the second terminals of the fifth transistor and the fourth transistor are both electrically connected to the second node, and the gates of the fifth transistor and the fourth transistor are both electrically connected to the first node. Preferably, the delay module includes a sixth transistor, the first terminal of the sixth transistor is electrically connected to the second node, the second terminal of the sixth transistor is electrically connected to the third node, and the gate of the sixth transistor is connected to a third clock signal; Preferably, the first output module includes a tenth transistor and a third capacitor. The first terminal of the tenth transistor is connected to a fourth clock signal, the second terminal of the tenth transistor is the output terminal of the tenth transistor, the gate of the tenth transistor is electrically connected to the third node, the first terminal of the third capacitor is electrically connected to the gate of the tenth transistor, and the second terminal of the third capacitor is electrically connected to the second terminal of the tenth transistor. The second output module includes an eleventh transistor, the first terminal of which is connected to the second voltage, the second terminal of which is the output terminal, and the gate of which is electrically connected to the first node. Preferably, the control module includes a fourth capacitor, the first terminal of the fourth capacitor being electrically connected to the first node, and the second terminal of the fourth capacitor being electrically connected to the second terminal of the eleventh transistor.

8. The shift register according to claim 7, characterized in that, The input module further includes a first capacitor, the first terminal of which is connected to the second voltage, and the second terminal of which is electrically connected to the first node.

9. The shift register according to claim 7, characterized in that, It also includes a first protection module and a second protection module; The first protection module is located between the connection path of the delay module and the first output module. The first protection module is electrically connected to the delay module at the third node, and the first protection module is electrically connected to the first output module at the fifth node. The first output module is used to output the gate signal in response to the potential of the fifth node. The second protection module is located between the connection path of the input module and the second output module. The second protection module is electrically connected to the input module at the first node, and the second protection module is electrically connected to the second output module at the sixth node. The control module controls the potential of the sixth node according to the output potential of the second output module. The second output module is used to output the gate signal in response to the potential of the sixth node. Preferably, the gate of the tenth transistor is electrically connected to the fifth node, the gate of the eleventh transistor is electrically connected to the sixth node, and the first terminal of the fourth capacitor is electrically connected to the sixth node. Preferably, the first protection module includes a ninth transistor, the first terminal of the ninth transistor is electrically connected to the third node, the second terminal of the ninth transistor is electrically connected to the fifth node, and the gate of the ninth transistor is connected to the second voltage; The second protection module includes a third transistor, the first terminal of which is electrically connected to the first node, the second terminal of which is electrically connected to the sixth node, and the gate of which is connected to the second voltage.

10. A display panel, comprising a gate driving circuit, characterized in that, The gate drive circuit includes a plurality of cascaded shift registers as described in any one of claims 1-5 or as described in any one of claims 6-9.

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