Display driving method, display driving system, chip and electronic device

Abstract

The application discloses a display driving method, a display driving system, a chip and an electronic device. The display driving method comprises the following steps: receiving display data and acquiring the frequency of the display data; monitoring the frequency of the display data and judging whether the frequency meets a preset condition; when the preset condition is met, starting a bidirectional communication mode, and sending a TE signal encoded by a phase offset; receiving display data in response to the TE signal, the display data matching a refresh timing, and displaying a picture at a reduced refresh rate; wherein the preset condition comprises that the frequency of the display data is continuously lower than a preset critical frame rate threshold for n vertical synchronization periods, and n is a positive integer and n is greater than or equal to 1. The application can realize adaptive dynamic refresh rate adjustment without relying on a frame memory, and significantly reduces the hardware cost. The application also has a stepwise frame rate adjustment scheme, which can gradually reduce the refresh rate, and avoids picture tearing and display abnormalities caused by a sudden drop in frequency.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display driving method, a display driving system, a chip, and an electronic device. Background Technology

[0002] With the continuous development of display technology, people's requirements for screen refresh rates are also increasing. More and more OLED (Organic Light-Emitting Diode) display panels capable of supporting high refresh rates have emerged. However, the energy consumption problem brought about by high refresh rates is gradually becoming more prominent. To balance display effect and energy consumption, some mobile electronic devices can adaptively adjust the refresh rate according to the displayed content and usage scenario. For example, they can display static images at a lower refresh rate and dynamic images at a higher refresh rate, realizing intelligent switching of refresh rates under different display scenarios. The dynamic refresh rate adjustment function of the display panel has become a key to energy saving and consumption reduction in mobile devices.

[0003] In existing solutions, the mainstream approach adopts a Command Mode architecture, which integrates a frame memory inside the display driver chip (DDIC). By caching complete frame data locally, the display driver chip can autonomously control the refresh timing, decoupling the screen refresh from the data transmission to the host computer. This allows it to maintain a low refresh rate static display even without host computer intervention.

[0004] However, the aforementioned technologies have significant drawbacks. The frame memory integrated into the display driver chip leads to a significant increase in chip area and hardware cost. While the Video Mode architecture can eliminate the need for a frame memory in the display driver chip, the lack of a local frame memory for caching creates a strong coupling between the display panel's refresh cycle and the host computer's image data update cycle. The display driver chip cannot independently maintain the refresh sequence without the host computer, and there are coordination control defects between the display driver chip and the host computer. For example, if the host computer unilaterally reduces the image transmission frequency, it will cause the critical display parameter compensation mechanism to be interrupted, resulting in inaccurate compensation, misalignment, and chromaticity coordinate shifts. Summary of the Invention

[0005] The purpose of this invention is to provide a display driving method, display driving system, chip, and electronic device to achieve collaboration between the display driving chip and the host computer without including a frame memory, thereby achieving adaptive refresh rate control.

[0006] According to one aspect of the present invention, a display driving method is provided, comprising: receiving display data and acquiring the frequency of the display data; monitoring the frequency of the display data and determining whether it meets a preset condition; when the preset condition is met, activating a bidirectional communication mode and sending a TE signal encoded by a phase offset; receiving display data in response to the TE signal, wherein the display data is matched with a refresh timing sequence to reduce the refresh rate for displaying the image; wherein the preset condition includes the frequency of the display data being continuously lower than a preset critical frame rate threshold for n vertical synchronization cycles, where n is a positive integer and n≥1.

[0007] The above-described display driving method, wherein reducing the refresh rate for display includes: gradually reducing the refresh rate according to a preset stepped frame rate adjustment scheme; wherein the timing of each level switching is encoded by the phase offset of the TE signal, different phase offsets correspond to different target refresh rates or switching commands, and the host computer responds and transmits the corresponding display data within the allowed timing window based on the TE signal.

[0008] Optionally, receiving display data in response to the TE signal, and matching the display data with the refresh timing, further includes performing corresponding display parameter compensation, which includes at least one of: ESTV duty cycle compensation, Gamma lookup table interpolation update, and initial voltage compensation.

[0009] Optionally, after sending the TE signal encoded with phase offset, the method further includes monitoring whether the host computer responds; if the host computer does not respond, an exception handling process is triggered.

[0010] Optionally, the anomaly is classified according to the period m during which the host computer fails to respond to the TE signal, and differentiated anomaly handling operations are performed according to the anomaly level, where m is a positive integer and m≥1.

[0011] Optionally, the exception handling operation includes at least one of the following: reporting the exception code to the host computer and performing fault diagnosis, switching to internal frequency insertion mode and disabling compensation, and switching to variable refresh rate mode.

[0012] According to another aspect of the present invention, a display driving system is provided, including a host computer and a display panel. The display panel includes a display driving chip and a display screen. The display driving chip does not include a frame memory. The display driving chip includes: a frame rate monitoring module, configured to receive display data from the host computer, monitor the frequency of the display data, and output a trigger signal when the frequency meets a preset condition; a TE generation module, connected to the frame rate monitoring module, configured to initiate a bidirectional communication mode with the host computer according to the trigger signal, generate a TE signal with a corresponding phase offset, and send it to the host computer; an adaptive compensation module, connected to the frame rate monitoring module, configured to compensate display parameters according to a target refresh rate during refresh rate switching; and an exception handling module, connected to the frame rate monitoring module, configured to perform exception handling when the host computer does not respond to the TE signal; wherein the display driving chip can match the update time of the display data responding to the TE signal with its own refresh timing and drive the display screen to display an image.

[0013] Optionally, the TE generation module generates a TE signal with corresponding phase offset according to a preset stepped frame rate adjustment scheme to achieve a gradual reduction in refresh rate.

[0014] Optionally, the adaptive compensation module includes: an ESTV duty cycle compensation circuit for maintaining a stable light emission duty cycle at different refresh rates; a Gamma lookup table interpolation engine for smoothing the transition brightness curve between different refresh rates; and an initial voltage compensation circuit for compensating for initial voltage drift caused by refresh rate changes.

[0015] Optionally, the anomaly handling module is used to classify anomalies according to the period m during which the host computer continuously fails to respond to the TE signal, and to perform differentiated anomaly handling operations according to the anomaly level, wherein m is a positive integer and m≥1.

[0016] According to another aspect of the present invention, a display driver chip is provided. The display driver chip is a frameless memory architecture chip, and the display driver chip includes: a frame rate monitoring module, configured to receive display data from a host computer, monitor the frequency of the display data, and output a trigger signal when the frequency meets a preset condition; a TE generation module, connected to the frame rate monitoring module, configured to initiate a bidirectional communication mode with the host computer according to the trigger signal, generate a TE signal with a corresponding phase offset, and send it to the host computer; an adaptive compensation module, connected to the frame rate monitoring module, configured to compensate display parameters according to a target refresh rate during refresh rate switching; and an exception handling module, connected to the frame rate monitoring module, configured to perform exception handling when the host computer does not respond to the TE signal.

[0017] According to another aspect of the present invention, an electronic device is also provided, comprising the above-described display driver chip and a display screen driven by the display driver chip, the display screen comprising an organic light-emitting diode display screen.

[0018] This invention overcomes the technical bottleneck of strong coupling between refresh cycle and data update in traditional Video Mode architecture by establishing a bidirectional communication mode between the display driver chip and the host computer in a frame-memory-free display driver chip. It achieves adaptive dynamic refresh rate adjustment without relying on a frame memory, significantly reducing chip area and hardware cost. By monitoring the display data frequency and sending a TE signal encoded with phase offset when preset conditions are met, precise matching between the host computer's image sending timing and the display driver chip's refresh timing is achieved. Combined with a stepped frame rate adjustment scheme, the refresh rate can be smoothly reduced step by step, avoiding screen tearing and display abnormalities caused by sudden frequency drops, thus achieving seamless refresh rate switching in a frame-memory-free architecture.

[0019] Furthermore, this invention integrates adaptive compensation mechanisms such as ESTV duty cycle compensation, Gamma lookup table interpolation update, and initial voltage compensation during refresh rate switching. This effectively suppresses problems such as chromaticity coordinate shift, brightness flicker, and inaccurate emission duty cycle caused by display parameter drift at low refresh rates, ensuring display consistency and image quality stability across multiple refresh rates. In addition, by monitoring the host computer's response to the TE signal and implementing tiered anomaly handling, differentiated recovery strategies can be executed based on the non-response period in the event of communication anomalies. This significantly improves the system's robustness and recoverability, thereby effectively reducing display panel power consumption and extending the battery life of mobile devices while ensuring display reliability. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0021] Figure 1 A flowchart illustrating a display driving method according to an embodiment of the present invention is shown;

[0022] Figure 2 This diagram illustrates the structure of a display driving system according to an embodiment of the present invention.

[0023] Figure 3 This diagram illustrates the timing relationship between the TE signal phase shift and the host computer response in the display driving method according to an embodiment of the present invention.

[0024] Figure 4 A timing diagram showing the relationship between the TE signal phase offset and the refresh rate step switching in the display driving method of this embodiment of the invention;

[0025] Figure 5The flowchart illustrates the abnormal classification processing in the display driving method of this embodiment of the invention. Detailed Implementation

[0026] The present invention will now be described in more detail with reference to the accompanying drawings. To facilitate understanding of this application, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application may be implemented in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0027] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0028] In the description of this application, the words "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. "And / or" in this document describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. "Connection" describes a connection relationship between related objects. For example, A and B are connected, which can indicate a direct connection between A and B, or an indirect connection between A and B through other devices / units / modules. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0029] Furthermore, the same reference numerals in the figures denote the same or similar structures, thus repeated descriptions of them will be omitted. That is, the various parts in this specification are described using a combination of parallel and progressive methods, with each part focusing on its differences from the others. Similar or identical parts can be referred to interchangeably. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.

[0030] This application describes many specific details of the invention, such as the specific structure, dimensions, connection relationships, and techniques of the modules, in order to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0031] This invention can be presented in various forms, some of which will be described below.

[0032] Figure 1 The flowchart illustrates a display driving method according to an embodiment of the present invention. This display driving method can be applied to a display system composed of a display driving chip without frame memory. The display driving method includes the following steps:

[0033] In step S10, display data is received and the frequency of the display data is obtained; specifically, the display data includes, for example, an image frame signal, which is received by the display driver chip from the host computer, and the frequency of the image frame signal is obtained.

[0034] In step S20, the frequency of the displayed data is monitored and it is determined whether it meets the preset conditions. Specifically, the display driver chip monitors and determines the frequency of the image frame signal sent by the host computer. The preset conditions include: the frequency of the image frame signal is continuously lower than the preset critical frame rate threshold F_threshold for n vertical synchronization cycles, where n is a positive integer and n≥1. That is, within n consecutive vertical synchronization cycles, the image sending frequency of the host computer is continuously lower than the critical frame rate threshold F_threshold. The critical frame rate threshold F_threshold is, for example, 10Hz-90Hz.

[0035] In step S30, a bidirectional communication mode is activated, and a TE (Tearing Effect) signal encoded with phase offset is sent. Specifically, when the monitoring result meets the preset conditions, the display driver chip actively activates the bidirectional communication mode with the host computer, encodes the phase offset of the TE signal, and sends the TE signal encoded with phase offset to the host computer to transmit the refresh rate adjustment request and target refresh rate information to the host computer.

[0036] In step S40, does the host computer respond? Specifically, if there is no abnormality, the host computer is woken up by the TE signal sent by the display driver chip and responds to its frequency reduction request (refresh rate adjustment request) according to the phase offset of the TE signal.

[0037] In step S50, the display data is matched with the refresh timing, and the refresh rate is reduced for screen display. Specifically, if the host computer responds to the frequency reduction request, the host computer responds and transmits the corresponding display data (including image frame signals) within the allowed timing window according to the phase offset of the TE signal. The display driver chip matches the update time of the image frame signal with its own refresh timing according to the phase offset after the TE signal is encoded, and performs corresponding display parameter compensation.

[0038] Furthermore, to avoid the impact of sudden frequency drops on display quality, a stepped frame rate adjustment method can be used for frequency reduction. The specific steps and the corresponding frequencies can be configured through preset parameters. For example, a 5-step frame rate adjustment method can be used to reduce the frequency from 90Hz to 1Hz. The refresh rate can be reduced step by step in the order of 90Hz, 60Hz, 30Hz, 15Hz, and 1Hz. Other stepped sequences can also be configured according to the display panel and drive capability. The timing of each step switching is encoded by the phase offset of the rising edge of the TE signal. Different phase offsets correspond to different target refresh rates or switching commands, enabling the host computer to identify the refresh rate intention of the display driver chip without additional dedicated control lines. The timing of the stepped switching is encoded by the phase offset of the TE signal. The host computer responds to the TE signal within the allowed timing window and transmits the corresponding display data, thereby gradually reducing the refresh rate according to the preset steps and completing the corresponding image display, so that the refresh rate eventually reaches the target frequency.

[0039] Of course, during the frequency reduction process, the display driver chip needs to continuously monitor whether the host computer responds to the frequency reduction request; if the host computer responds normally, it will continue to execute the current step or enter the next step of refresh rate switching.

[0040] In step S60, the exception is handled in a graded manner. Specifically, if the host computer fails to respond within the agreed time, the exception handling process is triggered, and the exception is handled in a graded manner according to the exception level to ensure the stability and recoverability of the display system.

[0041] Figure 2A schematic diagram of the structure of a display driving system according to an embodiment of the present invention is shown. The display driving system includes a host computer 100 and a display panel 200. The display panel 200 includes a display driving chip 210 and a display screen 220. The display driving chip 210 is provided with a frame rate monitoring module 211, an adaptive compensation module 212, a TE generation module 213, and an exception handling module 214. The frame rate monitoring module 211 is connected to the adaptive compensation module 212, the TE generation module 213, and the exception handling module 214 respectively. The host computer 100 sends display data containing image frame signals to the display driving chip 210 of the display panel 200. The display driving chip 210 sends TE signals or exception signals to the host computer 100 in a timely manner according to the situation. The frame rate monitoring module 211 in the display driver chip 210 monitors the frequency of the display data from the host computer 100 (equivalent to monitoring the frequency of the image frame signal). When the frequency is not greater than the critical frame rate threshold, it outputs a trigger signal to the adaptive compensation module 212 and the TE generation module 213. The TE generation module 213 generates a TE signal with a corresponding phase offset according to the current refresh rate and outputs the TE signal to the host computer 100 to start the bidirectional communication mode. The frame rate monitoring module 211 continuously monitors the display data. When the host computer 100 responds normally to the frequency reduction request, it sends a trigger signal to the TE generation module 213. The TE generation module 213 continues to generate a TE signal with a corresponding phase offset according to the preset stepped frame rate adjustment scheme. During the refresh rate step switching process, the adaptive compensation module 212 pre-compensates the display parameters according to the target refresh rate. This compensation includes ESV duty cycle compensation, Gamma lookup table interpolation update, and initial voltage compensation. ESTV duty cycle compensation is used to maintain a stable luminous duty cycle at different refresh rates. The Gamma lookup table interpolation engine is used to smooth the brightness curve transition between different refresh rates. The initial voltage compensation circuit is used to compensate for the initial voltage drift caused by refresh rate changes. Through these pre-compensations, the display driver chip can achieve seamless refresh rate switching in a video mode architecture without frame memory, and suppress screen flicker and color shift that may occur at low refresh rates. When the host computer 100 does not respond to the frequency reduction request, the frame rate monitoring module 211 provides an abnormal indication to the abnormality handling module 214. The abnormality handling module 214 performs tiered processing when communication is abnormal, and feeds back the abnormal signal (including the abnormal code) to the host computer when a specific level of abnormality is triggered. The display screen 220 receives the drive signal output by the display driver chip 210 to complete the screen display.

[0042] Figure 3 This diagram illustrates the timing relationship between the TE signal phase shift and the host computer response in the display driving method of this embodiment of the invention; as shown... Figure 3As shown, for the host computer 100, each frame of display data sent by the host computer 100 includes, for example, VS (Vertical Sync), VBP (Vertical Back Porch), Frame (effective image data area), and VFP (Vertical Front Porch), where Frame n represents the image frame signal of the nth frame. LPM (Low Power Mode) indicates that the host computer 100 is in a low power mode. LP11 and ULPS are two low power states of the host computer 100, used to save power when high-speed data transmission is not required. Host IRQProcessing indicates the process by which the host computer 100 processes interrupt requests (IRQs) from the display driver chip 210.

[0043] For the display panel, Frame represents the image frame signal of the current frame, Frame n represents the image frame signal of the nth frame, and Frame n ARP Active indicates that the display panel enters adaptive refresh mode in the nth frame. Update Deadline represents the data update deadline, that is, the host computer 100 needs to respond to the frequency reduction request (TE signal) of the display driver chip 210 in the display panel within the time period T1, and provide the display data of the corresponding n+1th frame to the display driver chip 210. Specifically, the display driver chip 210 sends the TE signal at a time T2 away from the data update deadline. The host computer 100 is woken up from the low power state at time T3 according to the rising edge of the TE signal and provides the display data of the n+1th frame to the display driver chip 210 according to the TE signal. The display driver chip 210 matches the update time of the image frame signal Frame n+1 of the n+1th frame with its own refresh timing and performs corresponding display parameter compensation. At the corresponding update time before the data update deadline, it drives the display 220 of the display panel 200 to display the image.

[0044] Figure 4This diagram illustrates the timing relationship between the TE signal phase offset and refresh rate step switching in the display driving method of this embodiment of the invention. Skip EM, for example, represents skipping the emission cycle. When reducing the refresh rate, skipping the emission control signal (EM) of certain frames reduces the number of pixel illuminations, thereby reducing power consumption. Refresh (refresh cycle) refers to the effective period for actually performing display refresh. Ext-VFP refers to blanking extension, for example, inserting a longer blanking period so that the display panel does not refresh for a longer time, thereby reducing the refresh rate. During Ext-VFP, emission (EM) can be turned off or skipped, thereby reducing the power consumption of the OLED display. Figure 4 As can be seen, at refresh rates of 120Hz and 90Hz, the display panel 200 is in VRR (Variable Refresh Rate) mode, with a critical frame rate threshold F_threshold of, for example, 90Hz. For instance, if the frequency of the image frame signal does not exceed 90Hz within one (vertical synchronization) cycle, the display driver chip 210 initiates bidirectional communication mode, and the display panel 200 switches to ARP (Adaptive Refresh Panel) mode, generating a corresponding TE signal. The phase position of the TE signal shifts according to the current refresh rate step. The different time intervals in the figure represent the phase shift of the TE signal relative to the starting position of the display frame at different steps. Starting from 90Hz, the refresh rate can be progressively reduced in the order of 72Hz, 60Hz, 51.4Hz, 51.4Hz, 10Hz, and 1Hz. As the refresh rate decreases progressively, the display driver chip 210 can further reduce power consumption by skipping some light emission. The phase shift and blanking expansion of the TE signal corresponding to each refresh rate are pre-configured to ensure timing consistency at different target refresh rates. By adjusting the phase offset of the TE signal, the host computer 100 responds to it, enabling the display driver chip 210 to align its refresh timing with the data update timing of the host computer 100 when the image sending frequency (image frame signal frequency) of the host computer 100 decreases, and to perform corresponding compensation, so as to avoid screen tearing or compensation interruption caused by the mismatch between the refresh cycle and the data update cycle.

[0045] When the host computer 100 fails to respond to the TE signal, i.e., fails to respond to the downgrade request, the display driver chip 210 triggers the exception handling module and records the exception code to the status register. Specifically, the exception can be classified according to the period m (where m is a positive integer greater than or equal to 1) of the continuous failure of the host computer 100 to respond to the TE signal, and differentiated exception handling operations can be performed according to the exception level, such as... Figure 5As shown, when the host computer 100 fails to respond to the TE signal for two consecutive cycles (m=2), the anomaly is classified as a low-level anomaly. Anomaly handling operation S61 is executed, reporting the anomaly code to the host computer 100 and performing fault diagnosis. Specifically, the display driver chip 210 reports the anomaly code to the host computer 100 via the MIPI interface, where the host computer 100 performs fault diagnosis and recovery. When 2 < m ≤ 8, the anomaly is classified as a medium-level anomaly. Anomaly operation S62 is executed, switching to internal frequency black frame insertion mode and disabling compensation. Specifically, internal frequency black frame insertion mode is, for example, a protection mode for ARP bidirectional communication anomalies. In ARP mode, due to bidirectional communication anomalies, the display panel 200 no longer relies on image data sent by the host computer 100. Instead, it uses the refresh timing generated internally by the display driver chip 210 to insert black frames into the display screen and disables the compensation circuit to maintain a basic display state, waiting for the host computer to check for errors and restore communication. When m > 8, the exception is classified as a high-level exception, and exception operation S63 is executed to switch to variable refresh rate mode. Specifically, when the host computer 100 does not respond to the frequency reduction request of the TE signal for more than 8 consecutive cycles, the display driver chip 210 in the display panel 200 closes the bidirectional communication and returns to the variable refresh rate mode controlled by the host computer 100 in one direction, giving up energy saving and adaptive compensation to maintain the display.

[0046] This invention overcomes the technical bottleneck of strong coupling between refresh cycle and data update in traditional Video Mode architecture by establishing a bidirectional communication mode between the display driver chip and the host computer in a frame-memory-free display driver chip. It achieves adaptive dynamic refresh rate adjustment without relying on a frame memory, significantly reducing chip area and hardware cost. By monitoring the display data frequency and sending a TE signal encoded with phase offset when preset conditions are met, precise matching between the host computer's image sending timing and the display driver chip's refresh timing is achieved. Combined with a stepped frame rate adjustment scheme, the refresh rate can be smoothly reduced step by step, avoiding screen tearing and display abnormalities caused by sudden frequency drops, thus achieving seamless refresh rate switching in a frame-memory-free architecture.

[0047] Furthermore, this invention integrates adaptive compensation mechanisms such as ESTV duty cycle compensation, Gamma lookup table interpolation update, and initial voltage compensation during refresh rate switching. This effectively suppresses problems such as chromaticity coordinate shift, brightness flicker, and inaccurate emission duty cycle caused by display parameter drift at low refresh rates, ensuring display consistency and image quality stability across multiple refresh rates. In addition, by monitoring the host computer's response to the TE signal and implementing tiered anomaly handling, differentiated recovery strategies can be executed based on the non-response period in the event of communication anomalies. This significantly improves the system's robustness and recoverability, thereby effectively reducing display panel power consumption and extending the battery life of mobile devices while ensuring display reliability.

[0048] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A display driving method, characterized in that, include: The frequency at which display data is received and acquired; Monitor the frequency of the displayed data and determine whether it meets preset conditions; When the preset conditions are met, the bidirectional communication mode is activated, and a TE signal encoded with phase offset is sent. Receive display data in response to the TE signal, the display data being matched with the refresh timing to reduce the refresh rate for screen display; The preset conditions include the frequency of the displayed data being continuously lower than the preset critical frame rate threshold for n vertical synchronization cycles, where n is a positive integer and n≥1.

2. The display driving method according to claim 1, characterized in that, The reduction of refresh rate for screen display includes: The refresh rate is gradually reduced according to the preset stepped frame rate adjustment scheme; The timing of each level switch is encoded by the phase offset of the TE signal. Different phase offsets correspond to different target refresh rates or switching commands. The host computer responds and transmits the corresponding display data within the allowed timing window based on the TE signal.

3. The display driving method according to claim 1, characterized in that, The receiving of display data in response to the TE signal, and the matching of the display data with the refresh timing, further includes performing corresponding display parameter compensation, which includes at least one of: ESTV duty cycle compensation, Gamma lookup table interpolation update, and initial voltage compensation.

4. The display driving method according to claim 1, characterized in that, After sending the TE signal encoded with phase offset, the process also includes monitoring whether the host computer responds; if the host computer does not respond, an exception handling procedure is triggered.

5. The display driving method according to claim 4, characterized in that, The anomaly is classified according to the period m during which the host computer fails to respond to the TE signal, and differentiated anomaly handling operations are performed according to the anomaly level, where m is a positive integer and m≥1.

6. The display driving method according to claim 5, characterized in that, The exception handling operations include at least one of the following: reporting the exception code to the host computer and performing fault diagnosis, switching to internal frequency black insertion mode and disabling compensation, and switching to variable refresh rate mode.

7. A display driving system, characterized in that, The system includes a host computer and a display panel. The display panel includes a display driver chip and a display screen. The display driver chip does not include a frame memory. The display driver chip includes: The frame rate monitoring module is used to receive display data from the host computer, monitor the frequency of the display data, and output a trigger signal when the frequency meets a preset condition. The TE generation module, connected to the frame rate monitoring module, is used to initiate a bidirectional communication mode with the host computer according to the trigger signal, generate a TE signal with a corresponding phase offset, and send it to the host computer. An adaptive compensation module, connected to the frame rate monitoring module, is used to compensate display parameters according to the target refresh rate during refresh rate switching. An exception handling module, connected to the frame rate monitoring module, is used to perform exception handling when the host computer does not respond to the TE signal; The display driver chip can match the update time of the display data in response to the TE signal with its own refresh timing, and drive the display screen to display the image.

8. The display driving system according to claim 7, characterized in that, The TE generation module generates a TE signal with corresponding phase offset according to a preset stepped frame rate adjustment scheme, so as to achieve a gradual reduction in refresh rate.

9. The display driving system according to claim 7, characterized in that, The adaptive compensation module includes: The ESTV duty cycle compensation circuit is used to maintain the stability of the light emission duty cycle at different refresh rates. Gamma lookup table interpolation engine is used to smoothly transition brightness curves between different refresh rates; The initial voltage compensation circuit is used to compensate for the initial voltage drift caused by changes in refresh rate.

10. The display driving system according to claim 7, characterized in that, The anomaly handling module is used to classify anomalies according to the period m during which the host computer continuously fails to respond to the TE signal, and to perform differentiated anomaly handling operations according to the anomaly level, where m is a positive integer and m≥1.

11. A display driver chip, characterized in that, The display driver chip is a frameless memory architecture chip, and the display driver chip includes: The frame rate monitoring module is used to receive display data from the host computer, monitor the frequency of the display data, and output a trigger signal when the frequency meets a preset condition. The TE generation module, connected to the frame rate monitoring module, is used to initiate a bidirectional communication mode with the host computer according to the trigger signal, generate a TE signal with a corresponding phase offset, and send it to the host computer. An adaptive compensation module, connected to the frame rate monitoring module, is used to compensate display parameters according to the target refresh rate during refresh rate switching. An exception handling module, connected to the frame rate monitoring module, is used to perform exception handling when the host computer does not respond to the TE signal.

12. An electronic device, characterized in that, It includes the display driver chip as described in claim 11, and a display screen driven by the display driver chip, the display screen including an organic light-emitting diode display screen.

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