Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a display area and a non-display area, and further comprises a substrate provided with a driving layer on one side, the driving layer comprising a pixel driving circuit in the display area, and a light-emitting functional layer on the driving layer, the light-emitting functional layer comprising a pixel in the display area, the pixel comprising a light-emitting module, the light-emitting module being matchedly connected to the pixel driving circuit, the pixel driving circuit comprising a storage module, a driving module, a switching module and a light-emitting control module, the storage module being electrically connected to the switching module and the driving module, the switching module being electrically connected to the driving module, the driving module being electrically connected to the light-emitting control module, the light-emitting control module being electrically connected to the light-emitting module, and the light-emitting control module being configured to receive a global control signal and stop all the light-emitting modules from emitting light when receiving a global EM signal. In this way, all the pixels are in a non-light-emitting state in the idle stage.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) and LED-based display panels are widely used in consumer electronics products such as mobile phones due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream in display devices. However, when used in near-eye devices with very high PPI requirements (such as AR / VR), they face problems of uneven display and poor uniformity. Summary of the Invention

[0003] The purpose of this invention is to provide a display panel and a display device, which can improve the display effect.

[0004] Therefore, this application adopts the following technical solution:

[0005] A display panel includes: a display area, and a non-display area located at least on one side of the periphery of the display area, the non-display area including a bonding area;

[0006] The display panel also includes a substrate, a driving layer, and a light-emitting functional layer;

[0007] A driving layer is provided on one side of the substrate.

[0008] The driving layer includes pixel driving circuits located in the display area.

[0009] A light-emitting functional layer is disposed on the side of the driving layer away from the substrate. The light-emitting functional layer includes pixels located in the display area. Each pixel includes a light-emitting module, and the light-emitting module is matched and connected to the pixel driving circuit.

[0010] The pixel driving circuit includes a storage module, a driving module, a switching module, and a light-emitting control module.

[0011] The storage module is electrically connected to the switch module and the drive module; the switch module is electrically connected to the drive module, the drive module is electrically connected to the light emission control module, the light emission control module is electrically connected to the light emission module, and the light emission control module is configured to receive a global control signal, and when it receives a global EM signal, it causes all the light emission modules to stop emitting light.

[0012] In one embodiment, the driving module is a driving transistor, the switching module is a switching transistor, the light-emitting control module is a light-emitting control transistor, and the storage module is a storage capacitor;

[0013] The first terminal of the driving transistor is electrically connected to the power supply terminal ELVDD and the first terminal of the storage capacitor;

[0014] The gate of the driving transistor is electrically connected to the second terminal of the storage capacitor and the second terminal of the switching transistor. The first terminal of the switching transistor is electrically connected to the data line to receive the written data voltage. The gate of the switching transistor is electrically connected to the scan line.

[0015] The first electrode of the light-emitting control transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the light-emitting control transistor is electrically connected to the anode of the light-emitting module, and the cathode of the light-emitting module is electrically connected to ground.

[0016] The gate of the light-emitting control transistor is used to receive the global EM signal. The light-emitting control transistor is configured to enter the Porch interval, at which point all light-emitting modules stop emitting light.

[0017] In one embodiment, the driving transistor, the switching transistor, and the light-emitting control transistor are all low-temperature polycrystalline silicon transistors.

[0018] In one embodiment, the bonding area is bonded to an analog driver chip, and the non-display area includes a scan driver circuit, the scan driver circuit including at least one first scan driver circuit.

[0019] The first scan driving circuit includes multiple first shift registers and a cascading control module. The first shift registers are cascaded, and the cascading control module is set on the cascading path of the first shift register in each stage. The cascading control module is configured to stop the first shift register from cascading down to the current row when entering the Porch interval, and to continue scanning down after the Porch interval ends.

[0020] In one embodiment, each of the first shift registers in the display panel includes a register input and a register output.

[0021] Preferably, the cascading control module is configured between two first shift registers. When the cascading control signal is turned off, it disconnects the connection between the output of the current register and the input of the next register, thereby blocking the step-by-step transmission path of the scan signal and cutting off the downward transmission of the scan signal conduction potential.

[0022] In one embodiment, the transmission control module includes transistors;

[0023] Preferably, the gate of the transistor is shorted to the first electrode via a trace;

[0024] Preferably, the gate and source terminals of the transistor are shorted by a trace;

[0025] Preferably, the transistor is a low-temperature polycrystalline silicon transistor.

[0026] Based on the same inventive concept, this application proposes a display device comprising the aforementioned display panel.

[0027] The non-display area of ​​the display panel is provided with a bonding area, which is equipped with an analog driver IC and a bonding component. The bonding component is used to connect the driver module.

[0028] In one embodiment, the display panel has a pixel density (PPI, pixels per inch) greater than 800;

[0029] Preferably, the pixel density of the display panel is greater than 1000;

[0030] Preferably, the analog driver IC is obtained by using a low-temperature polysilicon or metal oxide process;

[0031] Preferably, the bonding component is used to provide voltage and data voltage to the analog driver IC;

[0032] Preferably, the driving module is an FPGA-based driving module.

[0033] The advantages of this invention are as follows: The display device proposed in this application uses a combination of analog driver IC and driver module to drive the display panel, thus meeting its display requirements. Furthermore, through topology optimization of its pixel driving circuit, including a driving transistor, a switching transistor, and a light-emitting control transistor for light emission control, the light-emitting control transistor is positioned between the driving transistor and the light-emitting module, and its gate is connected to receive a global EM signal. The light-emitting control transistor is configured to turn off the EM signal reception during the porch interval. Through the coordination of the global EM signal and the cascade control module, the pixels of the display panel simultaneously do not emit light during the porch interval, and the first scan driving circuit (GIP) stops scanning to the next cascade. This avoids the problem of abnormal display and grayscale anomalies caused by the inability to properly send pattern data during the porch interval in high PPI applications. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a display panel according to an embodiment of this application;

[0036] Figure 2 This is a cross-sectional schematic diagram of the display panel according to an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of the pixel driving circuit of the display panel according to an embodiment of this application;

[0038] Figure 4 This is a functional schematic diagram of the scanning drive circuit of the display panel in an embodiment of this application;

[0039] Figure 5 The timing diagram for driving the display panel in this embodiment of the application;

[0040] Figure 6 This is a schematic diagram of the functional modules of the display device according to an embodiment of this application. Detailed Implementation

[0041] The following description, with reference to the accompanying drawings, illustrates preferred embodiments of the present invention, demonstrating its implementability. These embodiments provide a complete overview of the invention for those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein.

[0042] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. The dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component. To make the illustrations clearer, the thickness of components is appropriately exaggerated in some places in the drawings.

[0043] Furthermore, the following descriptions of the embodiments of the invention are made with reference to the accompanying illustrations, illustrating specific embodiments in which the invention can be implemented. Directional terms used in this invention, such as "upper," "lower," "front," "rear," "left," "right," "inner," "outer," and "side," are merely directional references to the accompanying drawings. Therefore, the use of directional terms is for better and clearer explanation and understanding of the invention, and does not indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] When a component is described as being "on" another component, the component may be placed directly on the other component; alternatively, there may be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "installed to" or "connected to" another component, both can be understood as being directly "installed" or "connected" to, or as being indirectly "installed to" or "connected to" another component via an intermediate component.

[0045] Users have increasingly higher demands for OLED displays, one of which is high PPI (pixel per inch) to achieve increasingly detailed images. OLED displays are widely used in consumer electronics due to their vibrant colors, fast response times, and low power consumption. With the development of AR / VR technology, these near-eye displays also have very high PPI requirements, typically above 800, and even reaching 1000+. This makes designing OLED display panels quite difficult. Currently, the mainstream pixel driving circuit topologies in OLED display panels are 7T1C, 8T1C, and 8T2C circuits. These use a large number of transistors, resulting in a large driving layer area. When used in near-eye displays, this leads to low manufacturing yields and high costs, limiting their application.

[0046] The applicant improved the structure of the existing display panel, specifically by adjusting the topology of the pixel driving circuit of the display panel and selecting a 2T1C circuit. During actual testing, the applicant found that the 2T1C circuit could not compensate for the trigger threshold Vth when driving, which resulted in the OLED display panel showing unevenness and poor uniformity between display panels. Therefore, this type of circuit cannot be directly applied to display panels for near-eye display.

[0047] To this end, the applicant conducted further research on the 2T1C circuit and found that, ideally, a digital driver chip could be used to drive the display if the trigger threshold Vth is compensated. Digital driving divides a frame into several time segments, controlling the grayscale display by controlling the length of the light-emitting segment of each pixel within a frame. Unlike conventional progressive scanning, digital driving involves interleaved writing across different rows. There are no clear frame boundaries when the digital driver chip is in operation; after the low-order bits of each frame are written, the high-order bits are still being written, and after the high-order bits are written, the low-order bits have already begun writing the data for the next frame. Due to technological limitations, there are currently very few available resources for OLED digital driver ICs, making this method unavailable for widespread implementation at present.

[0048] Based on this, the applicant improved the driving circuit of the display panel, adopting a combination of analog driver IC and driver module to drive the display panel (for near-eye display) to meet its display requirements. The scanning driving circuit includes a scanning driving circuit located in the non-display area and a pixel driving circuit located in the display area. The scanning driving circuit includes cascaded shift registers, each stage of which is connected to a scan line and provides a scan signal to the corresponding row of pixels through the scan line. Each column of pixels is connected to a data line. During screen display, data is written to each pixel driving circuit by scanning line by line. That is, the shift register provides a scan signal to the pixel driving circuit of its corresponding row through the scan line. During the conduction potential duration corresponding to the scan signal, the data voltage on the data line is transmitted to the corresponding pixel driving circuit to realize data writing. Each pixel is displayed according to the data voltage. When the scan line provides a cutoff potential, the voltage on the data line cannot be transmitted to the corresponding pixel driving circuit, and no data is written.

[0049] The display panel and display device proposed in this application will now be described with reference to the accompanying drawings.

[0050] like Figure 1 The above is a schematic diagram of the display panel according to an embodiment of this application.

[0051] The display panel 100 includes a display area 110 (also referred to as area A) and a non-display area 120 (also referred to as bezel area / NA area) located at least on one side of the periphery of the display area 110. The non-display area 120 is provided with a bonding area (not shown), which is used to mount an analog driver IC and bonding components in subsequent processes. This bonding area is provided with pads / soldering terminals. The bonding component is a flexible driver component (Driver FPC; the flexibility of FPC allows it to be bent and folded, adapting to narrow bezels and irregularly shaped screens (such as punch-hole screens and curved screens), reducing module thickness). One end has at least one first pad for connecting to the pad / soldering terminal in the bonding area, and the other end has at least one second pad for connecting the driver module. Preferably, the second pad is used to fix a connection terminal, through which the driver module is connected (e.g., the driver module is provided with matching connection terminals, and pluggable quick connection is achieved through the insertion and removal of the connection terminals). This bonding area houses an analog driver chip (also known as an analog IC; the number can be set according to actual needs, such as one or two chips). Voltage and data are supplied to the analog driver chip via flexible driving components. Placing the analog driver chip in the bonding area of ​​the display panel facilitates efficient layout, reduces parasitic capacitance, and meets the requirements for high-speed, low-latency data transmission in high-PPI applications. Preferably, the analog IC can achieve compatibility with the flexible substrate using low-temperature polysilicon (LTPS) or metal-oxide-semiconductor (IGZO) processes. This bonding area can be bent to the back side (the back of the display area) in subsequent processes.

[0052] In one embodiment, the display area 110 includes an array of light-emitting units 111, each light-emitting unit including multiple pixels, such as red pixels, green pixels, and blue pixels. This embodiment does not limit the arrangement of the red, green, and blue pixels. Each pixel is matched with a pixel driving circuit and a light-emitting module.

[0053] like Figure 2 As shown Figure 1 A cross-sectional view of the display panel.

[0054] In the thickness direction (z direction), the display panel includes a substrate 130, a driving layer 140, and a light-emitting functional layer 150.

[0055] The substrate 130 covers the display area and the non-display area. It is a flexible substrate and its material can be selected from polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), etc. The material can also be a mixture of the above materials. The substrate 130 can also be a rigid substrate, such as glass.

[0056] The driving layer 140 is disposed on one side of the substrate 130. The driving layer 140 includes a pixel driving circuit located in the display area, which is matched and connected to the corresponding pixel and drives the light-emitting module to emit light through it, as well as a scan driving circuit disposed in the non-display area.

[0057] The scan drive circuit includes cascaded shift registers and can operate in single-sided or double-sided drive mode. Each shift register is connected to a scan line and provides a scan signal to the corresponding row of pixels. Each column of pixels is connected to a data line. A pixel drive circuit, together with a light-emitting module, constitutes a pixel. Multiple pixels, such as a combination of three pixels, form a light-emitting unit, and the combination of multiple light-emitting units achieves color display. During screen display, data is written to each pixel drive circuit through a line-by-line scan. That is, the shift register provides a scan signal to the pixel drive circuit through the scan line. Corresponding to the duration of the scan signal's on-potential, the data voltage on the data line is transmitted to the corresponding pixel drive circuit to achieve data writing (this data processing process is also called the Porch interval). Each pixel displays according to the data voltage. When the scan line provides a cutoff potential, the data voltage on the data line cannot be transmitted to the corresponding pixel drive circuit, and no data is written.

[0058] In one embodiment, the scan driving circuit can be disposed on the driving layer below the pixel driving circuit, such as in the center of the display area. By placing the scan driving circuit within the display area, the width of the non-display area can be reduced, achieving a narrow bezel. This also simplifies the routing of the scan lines.

[0059] In one embodiment, the scan driving circuit includes: at least one first scan driving circuit, the first scan driving circuit including a plurality of first shift registers and a cascading control module, the first shift registers being cascaded, the cascading control module being disposed on the cascading path of the first shift register in each stage, the cascading control module being configured to cause the first shift register to stop cascading scanning downwards when entering the Porch interval, stopping at the current row, and continuing to scan downwards after the Porch interval ends.

[0060] The driving layer includes a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and an interlayer insulating film layer disposed between adjacent conductive film layers. The combination of traces in the semiconductor layer and the first metal layer forms a transistor; the combination of traces in the first metal layer and the second metal layer forms a storage capacitor; multiple signal lines with different orientations are provided in the third and fourth metal layers, or in the second, third, and fourth metal layers. Corresponding signal lines are electrically connected to the transistors and storage capacitors, thereby forming a pixel driving circuit in the display area, as well as scan lines, data lines, and a scan driving circuit.

[0061] The display panel includes a display area and a non-display area located at least on one side of the periphery of the display area, the non-display area including a bonding area; the display panel also includes a substrate, a driving layer and a light-emitting functional layer; a driving layer is disposed on one side of the substrate, the driving layer including a pixel driving circuit located in the display area, and a light-emitting functional layer is disposed on the side of the driving layer away from the substrate, the light-emitting functional layer including pixels located in the display area, each pixel including a light-emitting module, and the light-emitting module being matched and connected to the pixel driving circuit.

[0062] The display area includes an array of pixels, each pixel being matched with a pixel driving circuit and a light-emitting module. Each pixel driving circuit includes a storage module, a driving module, a switching module, and a light-emitting control module. The storage module is electrically connected to the switching module and the driving module; the switching module is electrically connected to the driving module; the driving module is electrically connected to the light-emitting control module; and the light-emitting control module is electrically connected to the light-emitting modules. The light-emitting control module is configured to stop all light-emitting modules from emitting light when it receives a global EM signal.

[0063] In one embodiment, the pixel driving circuit has a driving module that is a driving transistor, a switching module that is a switching transistor, a light-emitting control module that is a light-emitting control transistor, and a storage module that is a storage capacitor. The light-emitting control transistor is located between the driving transistor and the light-emitting module (OLED), and its gate terminal is connected to receive a global control signal (global EM signal). That is, the light-emitting control transistor is controlled by the same EM signal (also called the global EM signal). When the light-emitting control transistor is configured to be in the porch range, the EM signal is turned off, and all light-emitting modules stop emitting light. That is, at this time, all pixels in the entire display area are in a non-light-emitting state.

[0064] The timing sequence of global EM signal changes during each frame display on the display panel is as follows: Figure 5 As shown, Figure 5 The display shows the changes in the global EM signal across three consecutive frames. In each frame, the global EM signal is low in the AA region (light emission stage, where the pixel driving circuit may include a pre-charging stage, a data writing stage, and a light emission stage), and high in the porch region (preparation stage) (at which point all OLEDs stop emitting light). In other embodiments, in each frame, the global EM signal is high in the AA region (light emission stage) and low in the porch region (preparation stage) (at which point all OLEDs stop emitting light). Preferably, both the switching transistor and the light emission control transistor can be P-type transistors, fabricated using a low-temperature polysilicon (LTPS) process, forming an LTPS pixel driving circuit.

[0065] In one embodiment, the topology of the pixel driving circuit is as follows: Figure 3As shown, the pixel driving circuit includes 3 transistors and 1 storage capacitor (that is, a light-emitting control transistor T3 that receives global EM signal control is set on the basis of the 2T1C topology), and the specific connection is as follows.

[0066] Transistor T1 is the driving transistor, transistor T2 is the switching transistor, transistor T3 is used for light emission control (also called light emission control transistor T3), and CSt is the storage capacitor.

[0067] The first terminal of transistor T1 is electrically connected to the power supply terminal ELVDD and the first terminal of the storage capacitor CSt. The gate of transistor T1 is electrically connected to the second terminal of the storage capacitor CSt and the second terminal of transistor T2. The first terminal of transistor T2 is electrically connected to the data line to receive the written data voltage. The gate of transistor T2 is electrically connected to the scan line.

[0068] The first terminal of transistor T3 is electrically connected to the second terminal of transistor T1. The second terminal of transistor T3 is electrically connected to the anode of the OLED diode (light-emitting module). The cathode of the OLED diode (light-emitting module) is electrically connected to ground (ELVSS). The gate of transistor T3 is electrically connected to an enable signal to receive the EM signal (global EM signal). During the light-emitting phase (AA region), the EM signal is on. When entering the pitch region, the EM signal is off, all transistors T3 are turned off, and all OLED diodes (i.e., the light-emitting modules) stop emitting light.

[0069] When the row strobe signal SCAN is valid, the switch T2 is turned on, and the data voltage is transferred to the gate of the drive transistor T2. At the same time, the upper plate of the storage capacitor CSt is charged. During the row scan time, the storage capacitor is charged to the corresponding gray level voltage.

[0070] When the scan signal SCAN is invalid, due to the presence of the storage capacitor CSt, V DATA The light can still be held at the gate of transistor T1, and a certain current can be maintained on the OLED diode, allowing the OLED to continuously emit light. Through this design, a transistor T3 is set in the pixel driving circuit to control the light emission. This transistor T3 is controlled by the same EM signal (also called the global EM signal) and configured so that in the pulse interval, when the EM signal is off, transistor T3 is turned off, so all pixels stop emitting light; that is, at this time, the pixels in the entire display area are in a non-illuminating state. The timing of the change of the global EM signal during each frame display is as follows: Figure 5 As shown, in each frame, the global EM signal is low in the AA area (light emission stage) and high in the porch area (preparation stage) (at which time all OLEDs stop emitting light).

[0071] like Figure 4The diagram shown is a functional schematic of the scanning drive circuit provided in an embodiment of this application.

[0072] The scan driving circuit includes at least one first scan driving circuit. The description will take an example where the scan driving circuit includes only one first scan driving circuit. When the scan driving circuit includes multiple first scan driving circuits, the multiple first scan driving circuits can have the same topology.

[0073] The first scan drive circuit includes: multiple first shift registers 10, which are cascaded together, and a cascade control module 20. The cascade control module 20 is set on the cascade path of the first shift register in each stage (used to control whether the first shift register of this stage scans to the next stage; whenever the Porch interval is entered, the first shift register can stop scanning to the next stage and stop at the current row; when the Porch interval ends, it will continue to scan downwards).

[0074] Each first shift register 10 includes a register input terminal and a register output terminal. Each cascade control module 20 is connected to its corresponding first shift register, and the control terminals of each cascade control module 20 are connected to the cascade control signal. It can be understood that when each level of the first shift register 10 is cascaded, during the process of each first shift register outputting the scan signal stage by stage, the conduction potential of the scan signal at this stage is transmitted to the next level first shift register 10 as the start signal of the next level first shift register 10, triggering the next level first shift register 10 to continue outputting the conduction potential of the scan signal, thereby realizing the sequential shifting of the scan signal conduction pulse. Whenever the Porch interval is entered, the first shift register 10 can stop transmitting the scan to the next level, stopping at the current row. When the Porch interval ends, it continues to drive the scan downwards. Within the Porch interval, the output voltage is not output to the pixel circuit.

[0075] It should be noted that when the first shift registers of each level are cascaded in sequence, the first shift register of this level and the first shift register of the next level are respectively the first shift register of the i-th level and the first shift register of the (i+1)-th level in the first scan drive circuit 100, where i is a positive integer.

[0076] The cascading control module 20 is located between the two first shift registers 10. When the cascading control signal is turned off, it disconnects the connection between the output terminal 12 of the current register and the input terminal 11 of the next-level register, blocking the step-by-step transmission path of the scan signal and cutting off the downward transmission of the scan signal's conduction potential. The cascading control signal controls the switching state of the cascading control module to control whether the conduction potential of the scan signal output by the first shift register 10 can be transmitted step-by-step. By cutting off the transmission of the scan signal's conduction potential to the next-level first shift register 10, abnormal image data of some pixels can be avoided, resulting in abnormal display. Compared with the prior art, the embodiments of the present invention can enable the display panel to meet the display quality requirements in high PPI situations. In one embodiment, the cascading control module 20 includes a transistor whose gate and source terminals are shorted by a trace, at which point the transistor acts as a switch. The structure is simple, and the response speed is fast, achieving nanosecond-level response. The transistor is an LTPS (Low Temperature Polycrystalline Silicon) transistor. The transistor can be obtained by patterning during the fabrication of the driving layer. No additional process is required in the manufacturing process. For example, it can be obtained graphically by adjusting the pattern of the mask.

[0077] The first shift register 10 includes VGH, VGL, CLK1 / CLK2 / STV ports and an output terminal. The VGH and VGL ports are responsible for voltage driving, while the CLK1 and CLK2 ports are used for timing control (for step-by-step triggering, such as CLK1 high level activating odd-numbered GOAs and outputting VGH to the corresponding gate line, CLK2 high level activating even-numbered GOAs and outputting VGH to the next gate line, with CLK1 and CLK2 being 180° out of phase). The STV port is used for initialization (Start Vertical Signal, STV pulse triggers the first shift register of the first stage; at the beginning of each frame, STV sends a pulse signal to activate the first-stage GOA unit, and subsequent cascaded GOA units are triggered sequentially by the output of the previous stage and the clock signal; the pulse width of STV must match the CLK signal to ensure that the first row of gate lines is correctly turned on). Through their coordinated operation, the gate lines are turned on / off in sequence, enabling high-resolution, high-refresh-rate display. The output terminal is directly connected to the gate line and is responsible for outputting drive signals to control the corresponding transistor (such as...). Figure 3 The transistor T2 in the implementation is turned on / off. Data voltage can be written after transistor T2.

[0078] In one embodiment, the first shift register 10 (GOA) drives the gate line to turn on the transistor, controlling the current writing in the pixel driving circuit. The first shift register 10 is responsible for driving the gate line line by line.

[0079] In this exemplary embodiment, by setting the cascading control module 20, the driver IC output voltage is not output to the pixel driver circuit in the porch region (the porch region is used for data processing / data mapping). This design solves the problem that the analog driver IC needs the porch region for data processing, and in the porch region, the analog IC cannot output pattern data normally and can only maintain a certain fixed voltage. During this period, if the first scan driving circuit (GIP) continues to pass down to the next level, it will cause abnormal image data of some pixels, resulting in display abnormalities.

[0080] In this exemplary embodiment, the pixel driving circuit of the display panel, through the coordination of the global control signal (global EM signal) and the cascade control module, ensures that the pixels of the display panel do not emit light simultaneously in the porch interval, and the first scan driving circuit (GIP) stops the downward cascade scanning (no pixel scanning is performed in the porch interval, which is the blank stage after all rows of pixels have been scanned). This allows the pattern data to be written normally, and the data of each bit is correctly maintained in the ratio of 1:2:4:8... (taking 4-bit data as an example, the time of each frame is divided into 1, 2, 4, and 8 parts according to the ratio). Thus, in high PPI situations, the problem of abnormal display and grayscale caused by the inability to send pattern data normally due to the porch interval (empty stage) should be avoided.

[0081] In this exemplary embodiment, the first scan driving circuit is used to control the data writing process of each pixel driving circuit. The scan signals output by the first shift registers at each stage can serve as the second control signals required by the pixel driving circuit to control the process of writing data voltage to the gate of transistor T1. Other control signals required by the pixel driving circuit can be provided by other scan driving circuits in the display panel. For example, the scan driving circuit may also include a second scan driving circuit for providing a global control signal EM to each row of pixel driving circuits. The first scan driving circuit is used to control the data writing process of each pixel driving circuit, and the scan signals output by the first shift registers at each stage can be located within the display area, thereby reducing the width of the non-display area and achieving a narrow bezel. Preferably, the first scan driving circuit can be located in the center of the display area, or on one or both sides of the display area. When the scan driving circuit includes multiple second scan driving circuits, the multiple second scan driving circuits can have the same topology.

[0082] It should be noted that the display panel can also include other functional structures. For example, the display panel can also include an identification structure to provide fingerprint recognition functionality. For instance, the identification structure can be a touch panel or a touch layer. The touch panel can be bonded to the display panel, or the touch layer can be directly fabricated on the encapsulation layer of the display panel, which facilitates a thinner and lighter design for the display panel.

[0083] In one embodiment, the display panel may also integrate a filter structure (COE structure) to facilitate a thinner and lighter design of the display panel.

[0084] Based on the same inventive concept, this application also provides a display device, see [link to relevant documentation]. Figure 6 The display device can be an XR / VR / AR / MR device. The display device includes the display surface 100 provided in the above embodiments of this application. The display panel is a near-eye display panel with a resolution greater than 800, preferably greater than 1000 PPI (pixels per inch).

[0085] The non-display area 120 of the display panel 100 has a bonding area, which houses an analog driver IC (chip) 220 and bonding components 200. The placement of the analog driver chip in the bonding area reduces the need for external circuit boards, facilitates efficient layout, minimizes parasitic capacitance, and meets the requirements for high-speed, low-latency data transmission in high-PPI applications. It also reduces signal attenuation, shortens the transmission path between the analog driver IC and pixels, lowers signal loss, and improves color accuracy and response speed. During manufacturing, the analog IC can achieve compatibility with the flexible substrate using low-temperature polysilicon (LTPS) or metal oxide (such as IGZO) processes.

[0086] The bonding component 200 is connected to the driver module 300 (such as a driver module based on an FPGA module / chip). The analog driver IC includes an AA area (light emission control area) and a porch area (where data processing algorithms can be performed). One end of the bonding component 200 is bonded to the bonding area of ​​the non-display area of ​​the display panel to provide voltage and data to the analog driver IC (e.g., a high potential of 7V makes the display area black, and a low potential of 1V makes the display area bright). The other end (e.g., via connector 210) needs to be connected to the driver module 300. If connected to the driver module via a connector, the driver module needs to preprocess the pattern data, send the data to the analog driver IC in sequence, and then cooperate with the first shift registers (also known as GIP timing) of each stage to display the pattern correctly on the display area. When entering the porch interval (the DDIC enters the porch after sending a frame of data (also known as data voltage), and then the EM is immediately disconnected), all pixels in the entire area (display area) do not emit light at the same time, and the GIP stops scanning to the next level, so that the pattern data can be written normally, and the data of each bit is correctly maintained at the ratio of 1:2:4:8..., thus ensuring that the screen is displayed normally. This approach utilizes a combination of analog driver ICs and FPGA-based driver modules (with data mapping pre-configured in the FPGA module) to digitally drive high-PPI display panels while meeting requirements for response speed, power consumption, and image display quality, as well as near-eye display requirements.

[0087] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0088] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A display panel, characterized in that, Includes: a display area, and at least a non-display area located on one side of the periphery of the display area; The display panel also includes a substrate, a driving layer, and a light-emitting functional layer; A driving layer is provided on one side of the substrate; The driving layer includes a pixel driving circuit located in the display area; A light-emitting functional layer is disposed on the side of the driving layer away from the substrate. The light-emitting functional layer includes pixels located in the display area. Each pixel includes a light-emitting module. The light-emitting module is matched and connected to the pixel driving circuit. The pixel driving circuit includes a storage module, a driving module, a switching module, and a light-emitting control module. The storage module is electrically connected to the switch module and the drive module; The switch module is electrically connected to the drive module, the drive module is electrically connected to the light emission control module, the light emission control module is electrically connected to the light emission module, and the light emission control module is configured to cause all the light emission modules to stop emitting light when receiving a global EM signal.

2. The display panel as claimed in claim 1, characterized in that, The driving module is a driving transistor, the switching module is a switching transistor, the light-emitting control module is a light-emitting control transistor, and the storage module is a storage capacitor; The first terminal of the driving transistor is electrically connected to the power supply terminal ELVDD and the first terminal of the storage capacitor; The gate of the driving transistor is electrically connected to the second terminal of the storage capacitor and the second terminal of the switching transistor. The first terminal of the switching transistor is electrically connected to the data line to receive the written data voltage. The gate of the switching transistor is electrically connected to the scan line. The first electrode of the light-emitting control transistor is electrically connected to the second electrode of the driving transistor, the second electrode of the light-emitting control transistor is electrically connected to the anode of the light-emitting module, and the cathode of the light-emitting module is electrically connected to ground. The gate of the light-emitting control transistor is used to receive the global EM signal. The light-emitting control transistor is configured to enter the Porch interval, at which point all light-emitting modules stop emitting light.

3. The display panel as described in claim 2, characterized in that, The driving transistor, the switching transistor, and the light-emitting control transistor are all low-temperature polycrystalline silicon transistors.

4. The display panel as described in any one of claims 1-3, characterized in that, The non-display area includes a binding area, which is bound to an analog driver chip; The non-display area includes a scan driving circuit, which includes at least one first scan driving circuit. The first scan driving circuit includes multiple first shift registers and a cascading control module. The first shift registers are cascaded, and the cascading control module is set on the cascading path of the first shift register in each stage. The cascading control module is configured to stop the first shift register from cascading down to the current row when entering the Porch interval, and to continue scanning down after the Porch interval ends.

5. The display panel as claimed in claim 4, characterized in that, Each of the first shift registers includes a register input and a register output; Preferably, the cascading control module is configured between two first shift registers. When the cascading control signal is turned off, it disconnects the connection between the output of the current register and the input of the next register, thereby blocking the step-by-step transmission path of the scan signal and cutting off the downward transmission of the scan signal conduction potential.

6. The display panel as claimed in claim 5, characterized in that, The cascade control module includes transistors; Preferably, the gate of the transistor is shorted to the first electrode via a trace; Preferably, the gate and source terminals of the transistor are shorted by a trace; Preferably, the transistor is a low-temperature polycrystalline silicon transistor.

7. The display panel as claimed in claim 4, characterized in that, The scanning drive circuit includes a second scanning drive circuit, which is used to provide a global EM signal to each row of pixel drive circuits.

8. The display panel as claimed in claim 4, characterized in that, The first scanning drive circuit is located in the middle of the display area, or on one or both sides of the display area.

9. A display device, characterized in that, Including the display panel as described in any one of claims 1-8, The non-display area of ​​the display panel is provided with a bonding area, which is equipped with an analog driver IC and a bonding component. The bonding component is used to connect the driver module.

10. The display device as claimed in claim 9, characterized in that, The pixel density of the display panel is greater than 800; Preferably, the pixel density of the display panel is greater than 1000; Preferably, the analog driver IC is obtained by using a low-temperature polysilicon or metal oxide process; Preferably, the bonding component is used to provide voltage and data voltage to the analog driver IC; Preferably, the driving module is an FPGA-based driving module.

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