Display device and display panel

Abstract

Embodiments of the present disclosure relate to a display apparatus in which at least three sub-pixels corresponding to the same color and adjacent in a row direction among a plurality of sub-pixels are connected to the same data line, and one white sub-pixel among two white sub-pixels adjacent in the row direction is designed to have a flip structure, thereby effectively reducing the number of data channels.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0054635, filed on April 25, 2025, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display panel and a display device including the display panel. Background Technology

[0004] Recently, organic light-emitting display devices have attracted much attention as display devices. They use organic light-emitting diodes (OLEDs) as their own light-emitting elements, thus having the advantages of fast response speed, high luminous efficiency, high brightness and wide viewing angle.

[0005] The increasing demand for high resolution and large area in these display devices has led to a continuous increase in the number of data channels in the data drive circuitry.

[0006] However, as the number of data channels supplying data voltage in a display device increases, the manufacturing cost of the data drive circuit increases, and the size of the bezel area connected to each data channel increases. Therefore, efforts are continuing to reduce the number of data channels.

[0007] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that is not part of the prior art. Summary of the Invention

[0008] Embodiments of this disclosure may provide a display device and display panel that can effectively reduce the number of data channels by sharing the same data lines between adjacent unit pixels in the row direction.

[0009] Embodiments of this disclosure can provide a display device and a display panel that can minimize the occurrence of vertical line defects caused by brightness deviation and drive with low power by designing a plurality of color sub-pixels with a 1:2 flip structure and a plurality of white sub-pixels with a 1:1 flip structure on the display panel.

[0010] Embodiments of this disclosure may provide a display device and a display panel that can optimize the driving operation of multiple white sub-pixels with a 1:1 flip-chip structure by additionally setting a dummy gate line between the data driving circuit and the first row and driving at least one white sub-pixel in the first row through the dummy gate line.

[0011] Embodiments of this disclosure may provide a display device and display panel that can reduce the weight of the display device, lower manufacturing costs, and ensure space margin by minimizing the number of data channels.

[0012] Embodiments of this disclosure may provide a display device and display panel that can shorten the time for sensing subpixels by sensing multiple colors in a single scan operation.

[0013] Embodiments of this disclosure can provide a display device and display panel that can minimize RC delay caused by data line sharing by optimizing the arrangement and connection structure of multiple sub-pixels and data lines / gate lines, thereby achieving frame inversion drive to ensure charging characteristics and improving heat dissipation characteristics.

[0014] The purposes of the embodiments disclosed herein are not limited to those set forth herein, and other purposes not mentioned herein will be apparent to those skilled in the art from the following description.

[0015] A display device according to an embodiment of the present disclosure includes: a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels disposed thereon; a gate driving circuit for driving the plurality of gate lines; and a data driving circuit for supplying data voltage to the plurality of data lines. The plurality of sub-pixels includes a plurality of white sub-pixels corresponding to white and a plurality of colored sub-pixels corresponding to a plurality of colors other than white. At least three sub-pixels of the same color that are adjacent in the row direction are connected to the same data line. One of the two adjacent white sub-pixels in the row direction may have a flip-chip structure in which the position of the light-emitting region and the position of the sub-pixel circuit section are reversed.

[0016] A display panel according to an embodiment of the present invention includes: a plurality of unit pixels disposed in the row closest to the data driving circuit, and each unit pixel including a white sub-pixel and at least one color sub-pixel; a plurality of gate lines respectively connected to at least one corresponding unit pixel among the plurality of unit pixels; and a plurality of data lines respectively connected to at least one corresponding unit pixel among the plurality of unit pixels, wherein the plurality of unit pixels may include a first unit pixel, a second unit pixel, a third unit pixel, a fourth unit pixel, a fifth unit pixel, and a sixth unit pixel.

[0017] The multiple data lines may include a first white data line, at least one first color data line, a second white data line, and at least one second color data line. The first white data line and at least one first color data line are each connected to a white sub-pixel and at least one color sub-pixel in the first unit pixel to the third unit pixel, and the second white data line and at least one second color data line are each connected to a white sub-pixel and at least one color sub-pixel in the fourth unit pixel to the sixth unit pixel.

[0018] One of the two adjacent white sub-pixels in the first to sixth unit pixels has an inverted structure in which the position of the light-emitting area and the position of the sub-pixel circuit section are reversed.

[0019] According to embodiments of the present disclosure, a display device and display panel can be provided that can effectively reduce the number of data channels by sharing the same data line between adjacent unit pixels in the row direction.

[0020] According to embodiments of the present disclosure, a display device and a display panel can be provided that can minimize the occurrence of vertical line defects caused by brightness deviation and drive with low power by designing a plurality of color sub-pixels with a 1:2 flip-chip structure and a plurality of white sub-pixels with a 1:1 flip-chip structure on the display panel.

[0021] According to embodiments of the present disclosure, a display device and a display panel can be provided that optimize the driving operation of a plurality of white sub-pixels with a 1:1 flip-chip structure by additionally providing a dummy gate line between the data driving circuit and the first row and driving at least one white sub-pixel disposed in the first row through the dummy gate line.

[0022] According to embodiments of the present disclosure, a display device and a display panel can be provided that can reduce the weight of the display device, lower manufacturing costs, and ensure space margin by minimizing the number of data channels.

[0023] According to embodiments of the present disclosure, a display device and a display panel can be provided that can shorten the time for sensing subpixels by sensing multiple colors in a single scan operation.

[0024] According to embodiments of this disclosure, a display device and display panel can be provided that can minimize RC delay caused by data line sharing by optimizing the arrangement and connection structure of multiple sub-pixels and data lines / gate lines, achieve frame inversion drive to ensure charging characteristics, and improve heat dissipation characteristics.

[0025] The effects of this disclosure are not limited to those described above, and other effects will be apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0026] This disclosure will be more fully understood from the following detailed description and accompanying drawings, which are provided for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0027] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 This is a diagram illustrating an example of a sub-pixel according to an embodiment of the present disclosure.

[0029] Figure 3 and Figure 4 This is a diagram illustrating a unit pixel in a display device according to an embodiment of the present disclosure.

[0030] Figure 5 This is a diagram illustrating an example of the arrangement relationship of subpixels according to an embodiment of the present disclosure.

[0031] Figure 6 and Figure 7 This is a diagram illustrating a vertical line defect observed in a display device according to an embodiment of the present disclosure.

[0032] Figures 8 to 11 This is a diagram illustrating an example of the driving order of subpixels according to an embodiment of the present disclosure. Detailed Implementation

[0033] In the following description, numerous specific details are set forth for ease of explanation, so as to provide a comprehensive understanding of various embodiments or implementations of the invention. Throughout this document, "embodiment" and "implementation" are interchangeable terms and are non-limiting examples of apparatuses or methods employing one or more inventive concepts disclosed herein. However, it will be apparent that various embodiments may be implemented without these specific details or may employ one or more equivalent arrangements. In other instances, to avoid unnecessarily obscuring the various embodiments, some known structures and apparatuses are shown in block diagram form. Furthermore, the various embodiments may differ but are not necessarily mutually exclusive. For example, a particular shape, configuration, and feature of one embodiment may be used or implemented in another embodiment without departing from the inventive concept.

[0034] Unless otherwise stated, the illustrated embodiments should be understood as providing various detailed features in certain ways in which the inventive concept can be practically applied. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) in the various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0035] The use of sections and / or cross sections in the accompanying drawings is generally provided to clearly show the boundaries between adjacent elements. Therefore, the presence or absence of sections or cross sections in the drawings does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scales, commonalities between illustrated elements, and / or any other features, properties, characteristics, etc., of the elements, unless otherwise stated. Furthermore, the size and relative dimensions of elements in the drawings may be exaggerated for clarity and / or descriptive purposes. When an embodiment can be implemented in different ways, the specific sequence of processes may differ from the order in which they are described. For example, two processes described consecutively may be performed substantially simultaneously or in the reverse order of description. Additionally, the same reference numerals denote the same elements.

[0036] When an element (e.g., a layer) is described as being “on,” “connected to,” or “joined to” another element or layer, it may be directly located on, connected to, or joined to that other element or layer, or there may be intermediate elements or layers. However, when an element or layer is described as being directly located on,” “directly connected to,” or “directly joined to” another element or layer, there are no intermediate elements or layers. Therefore, the term “connection” may refer to a physical, electrical, and / or fluid connection, with or without intermediate elements. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be understood to refer only to X, only to Y, only to Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. In this document, the term “and / or” includes any and all combinations associated with the listed items.

[0037] Although the terms “first,” “second,” etc., are used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element without departing from the teachings of this disclosure.

[0038] Spatial relative terms, such as “below,” “under,” “below,” “lower than,” “above,” “higher than,” “above,” “above,” “higher than,” “side” (e.g., “sidewall”), etc., may be used herein for descriptive purposes and thus to describe the relationship between one element and another shown in the figures. Spatial relative terms are intended to cover different orientations of the device during use, operation, and / or manufacture, in addition to those shown in the figures. For example, if the device in the figures is flipped over, the orientation of those elements described as “below” or “under” other elements or features becomes “above” other elements or features. Therefore, the example term “below” can cover both “above” and “below” orientations. Furthermore, the device may be positioned in other orientations (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0039] The terminology used herein is intended to describe particular embodiments and is not intended to be limiting. The singular forms of “a,” “an,” and “the” as used herein are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms “comprising” and / or “including” are used in this specification to indicate the presence of the listed features, integers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. It should also be noted that, as used herein, the terms “approximately,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and as those skilled in the art will understand, these terms are used to account for the inherent biases in measurements, calculations, and / or the values ​​provided.

[0040] The various embodiments described herein are illustrated with cross-sectional and / or exploded views, which are schematic illustrations of idealized embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to factors such as manufacturing techniques and / or tolerances are entirely to be expected. Consequently, the embodiments disclosed herein should not be construed as being limited to the specific shapes of the described regions, but should include shape deviations due to factors such as the manufacturing process. Thus, the regions shown in the figures may have schematic characteristics, and their shapes do not necessarily reflect the actual shapes of regions within the device, and are therefore not necessarily limiting.

[0041] In conventional practice in this field, some embodiments are described and illustrated in the accompanying drawings as functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented via electronic (or optical) circuitry (such as logic circuits, discrete components, microprocessors, hardwired circuits, storage elements, wiring connections, etc.), which can be formed using semiconductor manufacturing techniques or other manufacturing processes. In the case of blocks, units, and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled by software (e.g., microcode) to perform the various functions discussed herein, and optionally driven by firmware and / or software. It should also be considered that each block, unit, and / or module may be implemented by dedicated hardware, or by a combination of dedicated hardware, to perform certain functions, combined with a processor (e.g., one or more programmed microprocessors and their associated circuitry) to perform other functions. Furthermore, in some embodiments, each block, unit, and / or module may be physically separated into two or more interacting and independent blocks, units, and / or modules without departing from the scope of the inventive concept. Furthermore, blocks, units, and / or modules in some embodiments may be physically combined into more complex blocks, units, and / or modules without departing from the scope of the inventive concept.

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. For example, terms defined in common dictionaries shall be interpreted as having a meaning consistent with the context of the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless otherwise expressly defined in the text.

[0043] In the following, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0044] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0045] Reference Figure 1 According to embodiments of the present disclosure, the display device 100 may include a display panel 110 and a driving circuit for driving the display panel 110.

[0046] The driving circuit may include a data driving circuit 120 and a gate driving circuit 130. The display device 100 may also include a controller 140 that controls the data driving circuit 120 and the gate driving circuit 130.

[0047] The display panel 110 may include multiple sub-pixels SP connected to multiple data lines DL and multiple gate lines GL.

[0048] according to Figure 1For example, multiple gate lines GL extend in the row direction (e.g., horizontal direction), and multiple data lines DL may extend in the column direction (e.g., vertical direction).

[0049] For example, multiple sub-pixels SP may include multiple white sub-pixels corresponding to white and multiple colored sub-pixels corresponding to multiple colors other than white.

[0050] For example, a color subpixel may include a red subpixel, a green subpixel, and a blue subpixel, respectively, corresponding to red, green, and blue.

[0051] However, embodiments of this disclosure are not limited thereto, and the plurality of sub-pixels SP may also include at least one sub-pixel corresponding to another color other than white, red, green and blue (e.g. magenta, yellow, cyan and so on).

[0052] In a set of multiple subpixels SP, a white subpixel and three color subpixels corresponding to different colors can form a unit pixel. Here, the white subpixel and the three color subpixels of a unit pixel can be set sequentially in the row direction.

[0053] In the following text, for ease of description, the three color subpixels of a unit pixel may be referred to as the first color subpixel, the second color subpixel, and the third color subpixel.

[0054] According to embodiments of the present disclosure, at least three sub-pixels in sub-pixels SP that correspond to the same color and are adjacent in the row direction can be connected to the same data line.

[0055] According to an embodiment, the same data line can be set in three adjacent unit pixels in the row direction among multiple unit pixels.

[0056] In addition, each of the multiple unit pixels may have at least three gate lines GL.

[0057] The controller 140 can supply the data control signal DCS to the data drive circuit 120 to control the operating timing of the data drive circuit 120. In addition, the controller 140 can supply the gate control signal GCS to the gate drive circuit 130 to control the operating timing of the gate drive circuit 130.

[0058] The controller 140 can control the start of scanning operations according to the timing sequence performed in each frame, convert input image data from an external source (e.g., host system 150) into image data DATA suitable for the data signal format used in the data drive circuit 120, supply the image data DATA to the data drive circuit 120, and control data driving at appropriate times according to the scanning timing sequence.

[0059] Specifically, the controller 140 can receive various timing signals, including the vertical synchronization signal VSYNC, the horizontal synchronization signal HSYNC, the data enable signal DE, and the clock signal CLK, as well as input image data from an external source (e.g., the host system 150), and generate various control signals DCS and GCS for controlling the data drive circuit 120 and the gate drive circuit 130, and output the various control signals DCS and GCS to the data drive circuit 120 and the gate drive circuit 130.

[0060] In order to control the gate drive circuit 130, the controller 140 can output various gate control signals GCS, including the gate start pulse GSP, the gate shift clock GSC, and the gate output enable signal GOE.

[0061] In order to control the data drive circuit 120, the controller 140 can output various data control signals DCS, including, for example, the source start pulse SSP, the source sampling clock SSC, and the source output enable signal SOE.

[0062] The controller 140 can be implemented as a component separate from the data drive circuit 120, or the controller 140 together with the data drive circuit 120 can be implemented as an integrated circuit.

[0063] The data driving circuit 120 can receive image data DATA from the controller 140 and supply data voltage to multiple data lines DL, thereby driving the multiple data lines DL. Here, the data driving circuit 120 can be described as a source driving circuit.

[0064] The data drive circuit 120 may include one or more source driver integrated circuits (SDICs).

[0065] For example, each source driver integrated circuit (SDIC) can be connected to the display panel 110 via tape-on-board (TAB) packaging, or via chip-on-glass (COG) or chip-on-panel (COP) bonding pads of the display panel 110, or via chip-on-film (COF) packaging and connection to the display panel 110.

[0066] The gate drive circuit 130 can output a gate signal with an on-state voltage level or a gate signal with an off-state voltage level according to the control of the controller 140. The gate drive circuit 130 can sequentially drive multiple gate lines GL by sequentially supplying the gate signal with the on-state voltage level to multiple gate lines GL.

[0067] The gate driving circuit 130 can be connected to the display panel 110 via a TAB connection, or to the bonding pads of the display panel 110 via a COG or COP connection, or to the display panel 110 via a COF connection. Alternatively, the gate driving circuit 130 can be formed in the non-display area NDA of the display panel 110 as a gate in-panel (GIP) connection. The gate driving circuit 130 can be disposed on the substrate SUB or connected to the substrate SUB. In other words, a GIP-type gate driving circuit 130 can be disposed in the non-display area NDA of the substrate SUB. A COG-type or COF-type gate driving circuit 130 can be connected to the substrate SUB.

[0068] At least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be configured not to overlap with the plurality of sub-pixels SP or to overlap with all or part of the plurality of sub-pixels SP.

[0069] When a specific gate line GL is activated by the gate drive circuit 130, the data drive circuit 120 can convert the image data DATA received from the controller 140 into an analog data voltage and supply it to multiple data lines DL.

[0070] The data driving circuit 120 can be connected to one side (e.g., the top or bottom) of the display panel 110. Depending on the driving scheme or panel design, the data driving circuit 120 can be connected to both sides (e.g., the top and bottom) of the display panel 110 or two or more of the four sides of the display panel 110.

[0071] The gate drive circuit 130 can be connected to one side of the display panel 110 (e.g., the left or right side). Depending on the driving scheme or panel design, the gate drive circuit 130 can be connected to both sides (e.g., the left and right sides) of the display panel 110 or two or more of the four sides of the display panel 110.

[0072] The controller 140 may be a timing controller used in common display technologies, a control device capable of performing other control functions as well as the functions of a timing controller, or a control device other than a timing controller, or it may be a circuit within a control device. The controller 140 may be implemented as various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or processors.

[0073] The controller 140 can be mounted on a printed circuit board or flexible printed circuit and can be electrically connected to the data drive circuit 120 and the gate drive circuit 130 via the printed circuit board or flexible printed circuit.

[0074] The display device 100 according to the embodiments of the present disclosure may be a display including a backlight unit (e.g., a liquid crystal display), or it may be a self-emissive display (e.g., an organic light-emitting diode (OLED) display, a quantum dot display, or a micro light-emitting diode (LED) display).

[0075] According to embodiments of this disclosure, when the display device 100 is an OLED display, each sub-pixel SP may include a self-emissive organic light-emitting diode (OLED) as a light-emitting element. According to embodiments of this disclosure, when the display device 100 is a quantum dot display, each sub-pixel SP may include a light-emitting element formed of quantum dots, where quantum dots are self-emissive semiconductor crystals. If the display device 100 according to embodiments of this disclosure is a micro-LED display, then each sub-pixel SP may include a self-emissive micro-LED formed of inorganic materials as a light-emitting element.

[0076] The display panel 110 according to embodiments of the present disclosure may have a top-emitting structure or a bottom-emitting structure, and in some cases, may have a dual-sided emitting structure.

[0077] Figure 2 This is a diagram illustrating an example of a sub-pixel according to an embodiment of the present disclosure.

[0078] Reference Figure 2 According to embodiments of the present disclosure, a sub-pixel SP may include a light-emitting element ED and a sub-pixel circuit section SPC.

[0079] The sub-pixel circuit section SPC may include a driving transistor DRT for driving the light-emitting element ED, a scanning transistor SCT connected to a first node N1 of the driving transistor DRT, a sensing transistor SENT connected to a second node N2 of the driving transistor DRT, and a storage capacitor Cst for maintaining a constant voltage during a frame.

[0080] The light-emitting element ED may include a pixel electrode PE and a common electrode CE, and may also include a light-emitting layer EL located between the pixel electrode PE and the common electrode CE.

[0081] The pixel electrode PE of the light-emitting element ED can be an electrode set in each sub-pixel SP, and the common electrode CE can be an electrode set in all sub-pixels SP.

[0082] For example, the pixel electrode PE can be the anode, and the common electrode CE can be the cathode. Conversely, the pixel electrode PE can be the cathode, and the common electrode CE can be the anode.

[0083] The common electrode CE of the light-emitting element ED can be connected to the low-potential voltage line VSSL to which a low-potential voltage EVSS is applied.

[0084] For example, the light-emitting element ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot light-emitting element.

[0085] The driving transistor DRT is a transistor used to drive the light-emitting element ED, and may include a first node N1, a second node N2 and a third node N3.

[0086] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT, and can be electrically connected to the source node or drain node of the scanning transistor SCT.

[0087] The second node N2 of the driving transistor DRT can be either the source node or the drain node of the driving transistor DRT, and can be electrically connected to the pixel electrode PE of the light-emitting element ED.

[0088] The third node N3 of the driving transistor DRT can be either the drain node or the source node of the driving transistor DRT, and can be electrically connected to the high-potential voltage line VDDL that supplies the high-potential power supply voltage EVDD.

[0089] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0090] The scanning transistor SCT is controlled by the gate signal and can be positioned between the first node N1 of the driving transistor DRT and the data line DL.

[0091] The scanning transistor SCT is turned on by a gate signal with a turn-on voltage level supplied from the gate line GL, and the data voltage VDATA supplied from the data line DL can be passed to the first node N1 of the driving transistor DRT.

[0092] The sensing transistor SENT is controlled by a gate signal and can be positioned between the second node N2 of the driving transistor DRT and the sensing line SL.

[0093] In other words, the sensing transistor SENT is turned on by a gate signal with a turn-on voltage level supplied from the gate line GL, and the connection between the sensing line SL and the second node N2 of the driving transistor DRT can be controlled.

[0094] like Figure 2As shown, the gate node SE of the sensing transistor SENT is connected to the gate line GL. Therefore, the sensing transistor SENT is turned on by a gate signal with a turn-on voltage level, and the reference voltage supplied through the sensing line SL can be passed to the second node N2 of the driving transistor DRT.

[0095] Furthermore, the sensing transistor SENT is turned on by a gate signal with a turn-on voltage level, and the voltage of the second node N2 of the driving transistor DRT can be transferred to the sensing line SL.

[0096] The function of the sensing transistor SENT to transfer the voltage of the second node N2 to the sensing line SL can be used during the driving process for sensing the feature values ​​of the sub-pixel SP (e.g., the threshold voltage of the driving transistor DRT, mobility, etc.). In this case, the voltage transferred to the sensing line SL can be a voltage used to calculate the feature values ​​of the sub-pixel SP or a voltage reflecting the feature values ​​of the sub-pixel SP.

[0097] according to Figure 2 For example, the scan transistor SCT and the sensing transistor SENT can be connected to the same gate line GL.

[0098] On the other hand, the scan transistor SCT and the sensing transistor SENT can also be connected to different gate lines GL. In this case, the scan transistor SCT can control the connection between the data line DL and the first node N1 of the driving transistor DRT by receiving a scan gate signal with a conduction voltage level from a scan gate line of the type GL, and the sensing transistor SENT can control the connection between the sensing line SL and the second node N2 of the driving transistor DRT by receiving a sensing gate signal with a conduction voltage level from a sensing gate line of the type GL.

[0099] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. In embodiments of this disclosure, for ease of description, each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT is illustrated as n-type.

[0100] Figure 2 The structure of the sub-pixel SP shown is only an example and can be varied by further including one or more transistors or one or more capacitors.

[0101] Figure 3 and Figure 4 This is a diagram illustrating a unit pixel in a display device according to an embodiment of the present disclosure.

[0102] exist Figure 3 and Figure 4For ease of description, a unit pixel PXL located in the first row closest to the data driving circuit 120 is illustrated and described.

[0103] Reference Figure 3 A unit pixel PXL can be designed as a four-subpixel structure, which includes a white subpixel SPW, a first color subpixel SP1 corresponding to the first color, a second color subpixel SP2 corresponding to the second color, and a third color subpixel SP3 corresponding to the third color.

[0104] For example, the first color can be red, the second color can be green or blue, and the third color can be blue or green.

[0105] Alternatively, the first color can be green, the second color can be red or blue, and the third color can be blue or red.

[0106] Alternatively, the first color can be blue, the second color can be green or red, and the third color can be red or green.

[0107] In the following text, for ease of description, the first color sub-pixel SP1 is exemplified as the red sub-pixel, the second color sub-pixel SP2 is exemplified as the green sub-pixel, and the third color sub-pixel SP3 is exemplified as the blue sub-pixel.

[0108] according to Figure 3 For example, the first color sub-pixel SP1, the second color sub-pixel SP2, the white sub-pixel SPW, and the third color sub-pixel SP3 can be sequentially arranged in a unit pixel PXL in the row direction. However, the embodiments of this disclosure are not limited to this, and the positions of any one of the first color sub-pixel SP1, the second color sub-pixel SP2, the third color sub-pixel SP3, and the white sub-pixel SPW can be interchanged.

[0109] Each of the first color sub-pixel SP1, the second color sub-pixel SP2, the white sub-pixel SPW, and the third color sub-pixel SP3 may include a light-emitting region EA and a sub-pixel circuit section SPC located above or below the light-emitting region EA. Figure 3 The luminescent region EA in the image corresponds to Figure 2 The area where the light-emitting element (ED) is located.

[0110] Each of the first color sub-pixel SP1, the second color sub-pixel SP2, the white sub-pixel SPW, and the third color sub-pixel SP3 can be designed to have a normal arrangement structure in which the sub-pixel circuit section SPC is disposed below the light-emitting area EA, or an inverted structure in which the sub-pixel circuit section SPC is disposed above the light-emitting area EA.

[0111] According to an embodiment, one of the first color sub-pixels SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 in a unit pixel PXL can be designed to have an inverted structure, and the remaining two color sub-pixels can be designed to have a normal arrangement structure.

[0112] according to Figure 3 For example, the first color subpixel SP1 and the third color subpixel SP3 can be designed to have a normal arrangement structure, and the second color subpixel SP2 can be designed to have an inverted structure.

[0113] according to Figure 3 For example, a single pixel PXL can be connected to multiple data lines CDL1, CDL2, WDL and CDL3, a high-potential voltage line VDDL, and a sensing line SL.

[0114] The multiple data lines CDL1, CDL2, WDL and CDL3 connected to a unit pixel PXL may include a first color data line CDL1 connected to a first color sub-pixel SP1, a second color data line CDL2 connected to a second color sub-pixel SP2, a white data line WDL connected to a white sub-pixel SPW, and a third color data line CDL3 connected to a third color sub-pixel SP3.

[0115] For example, when the first color sub-pixel SP1, the second color sub-pixel SP2, and the third color sub-pixel SP3 are red, green, and blue sub-pixels respectively, the first color data line CDL1, the second color data line CDL2, and the third color data line CDL3 can be red, green, and blue data lines respectively.

[0116] according to Figure 3 For example, the first color data line CDL1 and the second color data line CDL2 can be set in the area between the other side of the first color sub-pixel SP1 and one side of the second color sub-pixel SP2, and the white data line WDL and the third color data line CDL3 can be set in the area between the other side of the white sub-pixel SPW and one side of the third color sub-pixel SP3.

[0117] The high-potential voltage line VDDL can be set in the region adjacent to one side of the first color sub-pixel SP1 and the region adjacent to the other side of the third color sub-pixel SP3.

[0118] The high-potential voltage line VDDL can be connected to the sub-pixel circuit section SPC of each sub-pixel SP1, SP2, SPW and SP3 through at least one first branch line.

[0119] The sensing line SL can be set in the area between the other side of the second color sub-pixel SP2 and one side of the white sub-pixel SPW, and can be connected to the second branch line that passes through the light-emitting area EA of each of the first color sub-pixel SP1, the second color sub-pixel SP2, the white sub-pixel SPW and the third color sub-pixel SP3.

[0120] In other words, the sensing line SL can be connected to the sub-pixel circuit section SPC in each sub-pixel SP1, SP2, SPW and SP3 via a second branch line passing through the light-emitting area EA.

[0121] For example, the second branch line can be a transparent line and can be set in a different layer than the multiple data lines CDL1, CDL2, WDL and CDL3.

[0122] A single pixel PXL can have three different gate lines GL1, GL2 and GL3.

[0123] according to Figure 3 For example, the second color sub-pixel SP2 and the white sub-pixel SPW can be connected to the first gate line GL1, the first color sub-pixel SP1 can be connected to the second gate line GL2, and the third color sub-pixel SP3 can be connected to the third gate line GL3.

[0124] Reference Figure 4 The display panel 110 according to an embodiment of the present disclosure may further include a dummy gate line GL0. Here, the dummy gate line GL0 may be disposed between the data driving circuit 120 and the first gate line GL1.

[0125] according to Figure 4 For example, four different gate lines GL0, GL1, GL2 and GL3 can be set in a single pixel PXL set in the first row.

[0126] according to Figure 4 For example, the white sub-pixel SPW can be connected to the dummy gate line GL0, the third color sub-pixel SP3 can be connected to the first gate line GL1, the second color sub-pixel SP2 can be connected to the second gate line GL2, and the first color sub-pixel SP1 can be connected to the third gate line GL3.

[0127] Figure 5 This is a diagram illustrating an example of the arrangement relationship of subpixels according to an embodiment of the present disclosure.

[0128] Reference Figure 5 According to embodiments of the present disclosure, subpixels arranged in the first row among a plurality of subpixels can form a first pixel group PG1, and subpixels arranged in the second row can form a second pixel group PG2.

[0129] according to Figure 5 For example, the first pixel group PG1 may include a first unit pixel (R1, G1, W1, B1), a second unit pixel (R2, G2, W2, B2), a third unit pixel (R3, G3, W3, B3), a fourth unit pixel (R4, G4, W4, B4), a fifth unit pixel (R5, G5, W5, B5), and a sixth unit pixel (R6, G6, W6, B6).

[0130] In addition, the second pixel group PG2 may include the seventh unit pixel (R7, G7, W7, B7), the eighth unit pixel (R8, G8, W8, B8), the ninth unit pixel (R9, G9, W9, B9), the tenth unit pixel (R10, G10, W10, B10), the eleventh unit pixel (R11, G11, W11, B11), and the twelfth unit pixel (R12, G12, W12, B12).

[0131] exist Figure 5 For ease of description, only the first to twelfth unit pixels arranged in a 2×6 matrix are shown. According to embodiments of this disclosure, the arrangement of the first to twelfth unit pixels arranged in a 2×6 matrix can be repeated on the display panel 110.

[0132] According to an embodiment, three adjacent unit pixels in each of the plurality of unit pixels in the first pixel group PG1 and the second pixel group PG2 can share the same data line.

[0133] according to Figure 5 For example, the multiple data lines corresponding to the first pixel group PG1 and the second pixel group PG2 may include a first red data line RDL1, a first green data line GDL1, a first white data line WDL1, a first blue data line BDL1, a second red data line RDL2, a second green data line GDL2, a second white data line WDL2, and a second blue data line BDL2.

[0134] For example, the first unit pixel to the third unit pixel and the seventh unit pixel to the ninth unit pixel can share the first red data line RDL1, the first green data line GDL1, the first white data line WDL1 and the first blue data line BDL1.

[0135] In addition, pixels from the fourth unit to the sixth unit and pixels from the tenth unit to the twelfth unit can share the second red data line RDL2, the second green data line GDL2, the second white data line WDL2, and the second blue data line BDL2.

[0136] According to an embodiment, each of the multiple data lines may include three sub-data lines, which branch to supply data voltage to each of three sub-pixels that correspond to the same color and are adjacent in the row direction.

[0137] according to Figure 5 For example, the first red data line RDL1 is connected to the first red channel pad in the data driver circuit 120 and branches into three sub-lines, and each of the three sub-lines can be set in the first unit pixel and the seventh unit pixel, the second unit pixel and the eighth unit pixel, and the third unit pixel and the ninth unit pixel.

[0138] Therefore, the first red data line RDL1 can provide the data voltage supplied from the first red channel pad to each of the first red sub-pixel R1, the second red sub-pixel R2, the third red sub-pixel R3, the seventh red sub-pixel R7, the eighth red sub-pixel R8, and the ninth red sub-pixel R9.

[0139] The first green data line GDL1 is connected to the first green channel pad in the data driver circuit 120 and branches into three sub-lines. Each of the three sub-lines can be set in the first unit pixel and the seventh unit pixel, the second unit pixel and the eighth unit pixel, and the third unit pixel and the ninth unit pixel.

[0140] Therefore, the first green data line GDL1 can provide the data voltage supplied from the first green channel pad to each of the first green sub-pixel G1, the second green sub-pixel G2, the third green sub-pixel G3, the seventh green sub-pixel G7, the eighth green sub-pixel G8, and the ninth green sub-pixel G9.

[0141] The first white data line WDL1 is connected to the first white channel pad in the data driver circuit 120 and branches into three sub-lines. Each of the three sub-lines can be set in the first unit pixel and the seventh unit pixel, the second unit pixel and the eighth unit pixel, and the third unit pixel and the ninth unit pixel.

[0142] Therefore, the first white data line WDL1 can provide the data voltage supplied from the first white channel pad to each of the first white sub-pixel W1, the second white sub-pixel W2, the third white sub-pixel W3, the seventh white sub-pixel W7, the eighth white sub-pixel W8, and the ninth white sub-pixel W9.

[0143] The first blue data line BDL1 is connected to the first blue channel pad in the data driver circuit 120 and branches into three sub-lines. Each of the three sub-lines can be set in the first unit pixel and the seventh unit pixel, the second unit pixel and the eighth unit pixel, and the third unit pixel and the ninth unit pixel.

[0144] Therefore, the first blue data line BDL1 can provide the data voltage supplied from the first blue channel pad to each of the first blue sub-pixel B1, the second blue sub-pixel B2, the third blue sub-pixel B3, the seventh blue sub-pixel B7, the eighth blue sub-pixel B8, and the ninth blue sub-pixel B9.

[0145] The second red data line RDL2 is connected to the second red channel pad in the data driver circuit 120 and branches into three sub-lines. Each of the three sub-lines can be set in the fourth and tenth unit pixels, the fifth and eleventh unit pixels, and the sixth and twelfth unit pixels.

[0146] Therefore, the second red data line RDL2 can provide the data voltage supplied from the second red channel pad to each of the fourth red sub-pixel R4, the fifth red sub-pixel R5, the sixth red sub-pixel R6, the tenth red sub-pixel R10, the eleventh red sub-pixel R11, and the twelfth red sub-pixel R12.

[0147] The second green data line GDL2 is connected to the second green channel pad in the data driver circuit 120 and branches into three sub-lines. Each of the three sub-lines can be set in the fourth and tenth unit pixels, the fifth and eleventh unit pixels, and the sixth and twelfth unit pixels.

[0148] Therefore, the second green data line GDL2 can supply the data voltage from the second green channel pad to each of the fourth green sub-pixel G4, the fifth green sub-pixel G5, the sixth green sub-pixel G6, the tenth green sub-pixel G10, the eleventh green sub-pixel G11, and the twelfth green sub-pixel G12.

[0149] The second white data line WDL2 is connected to the second white channel pad in the data driver circuit 120 and branches into three sub-lines. Each of the three sub-lines can be set in the fourth and tenth unit pixels, the fifth and eleventh unit pixels, and the sixth and twelfth unit pixels.

[0150] Therefore, the second white data line WDL2 can provide the data voltage supplied from the second white channel pad to each of the fourth white sub-pixel W4, the fifth white sub-pixel W5, the sixth white sub-pixel W6, the tenth white sub-pixel W10, the eleventh white sub-pixel W11, and the twelfth white sub-pixel W12.

[0151] The second blue data line BDL2 is connected to the second blue channel pad in the data driver circuit 120 and branches into three sub-lines. Each of the three sub-lines can be set in the fourth and tenth unit pixels, the fifth and eleventh unit pixels, and the sixth and twelfth unit pixels.

[0152] Therefore, the second blue data line BDL2 can provide the data voltage supplied from the second blue channel pad to each of the fourth blue sub-pixel B4, the fifth blue sub-pixel B5, the sixth blue sub-pixel B6, the tenth blue sub-pixel B10, the eleventh blue sub-pixel B11, and the twelfth blue sub-pixel B12.

[0153] According to an embodiment, multiple white sub-pixels can be designed to have a 1:1 inverted structure, in which one of two adjacent white sub-pixels has an inverted structure and the other white sub-pixel has a normal arrangement structure.

[0154] according to Figure 5 For example, the first white sub-pixel W1, the third white sub-pixel W3, and the fifth white sub-pixel W5 in the first pixel group PG1 can be designed to have an inverted structure, and the second white sub-pixel W2, the fourth white sub-pixel W4, and the sixth white sub-pixel W6 can be designed to have a normal arrangement structure.

[0155] According to an embodiment, multiple color subpixels can be designed to have a 1:2 inverted structure, in which one of three color subpixels corresponding to the same color and adjacent in the row direction has an inverted structure, and the other two color subpixels have a normal arrangement structure.

[0156] according to Figure 5 For example, the second red sub-pixel R2 and the fifth red sub-pixel R5 in the red sub-pixels R1 to R6 in the first pixel group PG1 can be designed to have an inverted structure, and the first red sub-pixel R1, the third red sub-pixel R3, the fourth red sub-pixel R4 and the sixth red sub-pixel R6 can be designed to have a normal arrangement structure.

[0157] Furthermore, the first green sub-pixel G1 and the fourth green sub-pixel G4, which are located in the first pixel group PG1, can be designed to have an inverted structure, and the second green sub-pixel G2, the third green sub-pixel G3, the fifth green sub-pixel G5 and the sixth green sub-pixel G6 can be designed to have a normal arrangement structure.

[0158] Furthermore, the third blue sub-pixel B3 and the sixth blue sub-pixel B6 among the blue sub-pixels B1 to B6 in the first pixel group PG1 can be designed to have an inverted structure, and the first blue sub-pixel B1, the second blue sub-pixel B2, the fourth blue sub-pixel B4 and the fifth blue sub-pixel B5 can be designed to have a normal arrangement structure.

[0159] according to Figure 5 For example, the first pixel group PG1 and the second pixel group PG2 may have a dummy gate line GL0 and the first gate line GL1 to the sixth gate line GL6.

[0160] The dummy gate line GL0 can be connected to at least one of the white sub-pixels W1 to W6 located in the first pixel group PG1.

[0161] Specifically, the dummy gate line GL0 can be connected to at least one white sub-pixel with an inverted structure among the white sub-pixels W1 to W6 in the first pixel group PG1.

[0162] according to Figure 5 For example, the dummy gate line GL0 can be connected to the third white sub-pixel W3 in the third unit pixel of the first unit pixel to the sixth unit pixel in the first pixel group PG1, but the embodiments of this disclosure are not limited thereto.

[0163] According to an embodiment, the straight-line distance between the sub-pixel circuit section SPC of the white sub-pixel connected to the dummy gate line GL0 and the data driving circuit 120 can be shorter than the straight-line distance between the sub-pixel circuit section SPC of another white sub-pixel in the first pixel group PG1 and the data driving circuit 120.

[0164] In other words, the sub-pixel circuit section SPC of the third white sub-pixel W3 connected to the dummy gate line GL0 can be configured to be closer to the data drive circuit 120 than the sub-pixel circuit sections SPC of the other white sub-pixels W1, W2, W4, W5 and W6 in the first pixel group PG1.

[0165] according to Figure 5For example, the first gate line GL1 can be connected to the first green sub-pixel G1, the first white sub-pixel W1, the second red sub-pixel R2, the third blue sub-pixel B3, the fourth green sub-pixel G4, the fifth red sub-pixel R5, the fifth white sub-pixel W5, and the sixth blue sub-pixel B6 in the first pixel group PG1.

[0166] The second gate line GL2 can be connected to the first red sub-pixel R1, the second white sub-pixel W2, the second blue sub-pixel B2, the third green sub-pixel G3, the fourth red sub-pixel R4, the fifth blue sub-pixel B5, the sixth green sub-pixel G6, and the sixth white sub-pixel W6 in the first pixel group PG1.

[0167] The third gate line GL3 can be connected to the first blue sub-pixel B1, the second green sub-pixel G2, the third red sub-pixel R3, the fourth white sub-pixel W4, the fourth blue sub-pixel B4, the fifth green sub-pixel G5, and the sixth red sub-pixel R6 in the first pixel group PG1, as well as the ninth white sub-pixel W9 in the second pixel group PG2.

[0168] The fourth gate line GL4 can be connected to the seventh green sub-pixel G7, the seventh white sub-pixel W7, the eighth red sub-pixel R8, the ninth blue sub-pixel B9, the tenth green sub-pixel G10, the eleventh red sub-pixel R11, the eleventh white sub-pixel W11, and the twelfth blue sub-pixel B12 in the second pixel group PG2.

[0169] The fifth gate line GL5 can be connected to the seventh red sub-pixel R7, the eighth white sub-pixel W8, the eighth blue sub-pixel B8, the ninth green sub-pixel G9, the tenth red sub-pixel R10, the eleventh blue sub-pixel B11, the twelfth green sub-pixel G12, and the twelfth white sub-pixel W12 in the second pixel group PG2.

[0170] The sixth gate line GL6 can be connected to the seventh blue sub-pixel B7, the eighth green sub-pixel G8, the ninth red sub-pixel R9, the tenth white sub-pixel W10, the tenth blue sub-pixel B10, the eleventh green sub-pixel G11, and the twelfth red sub-pixel R12 in the second pixel group PG2.

[0171] Figure 6 and Figure 7 This is a diagram illustrating a vertical line defect observed in a display device according to an embodiment of the present disclosure.

[0172] Specifically, Figure 6 An example of a 1:1 interval vertical line defect is shown, as observed through display panel 110. Figure 7 An example of a 1:2 interval vertical line defect is shown, as observed through display panel 110.

[0173] Reference Figure 6 and Figure 7 As the interval between bright and dark lines becomes larger (e.g., 1:2 interval) instead of equal interval (i.e., 1:1 interval), the vertical line defects observed through the display panel 110 inevitably increase, and when the grayscale is the same, the perceived level of this defect is greater in the grayscale state than in the color (RGB) state.

[0174] In other words, in a display device 100 based on four subpixels, the perceived level of a vertical line defect can be determined by the white subpixel that has the greatest influence on the brightness of the displayed image.

[0175] Therefore, the display device 100 according to embodiments of the present disclosure can be designed such that by designing white sub-pixels with a 1:1 inverted structure to drive white sub-pixels in a regular manner, the occurrence of vertical line defects can be minimized. Furthermore, by designing a plurality of color sub-pixels with a 1:2 inverted structure, the occurrence of vertical line defects can be further minimized.

[0176] Figures 8 to 11 This is a diagram illustrating an example of the driving order of subpixels according to an embodiment of the present disclosure.

[0177] Specifically, Figure 8 An example of the driving order of the first red sub-pixel R1 to the twenty-fourth red sub-pixel R24 set along the row and column directions is shown, and Figure 9 An example of the driving order of the first green sub-pixel G1 to the twenty-fourth green sub-pixel G24 set along the row and column directions is shown.

[0178] also, Figure 10 An example of the driving order of the first white sub-pixel W1 to the twenty-fourth white sub-pixel W24 set along the row and column directions is shown, and Figure 11 An example of the driving order of the first blue sub-pixel B1 to the twenty-fourth blue sub-pixel B24 set along the row and column directions is shown.

[0179] Reference Figures 8 to 11 In the display device 100 according to an embodiment of the present disclosure, at least one sub-pixel can be driven (e.g., charged and emitted light) when a data voltage is supplied through a data line connected to at least one of the plurality of sub-pixels and a gate signal having an on-state voltage level is applied through a gate line connected to at least one sub-pixel.

[0180] according to Figure 8For example, when a gate signal with a conduction voltage level, supplied with data voltage through the first red data line RDL1 and the second red data line RDL2, is sequentially applied to the first gate line GL1 to the twelfth gate line GL12, the second red sub-pixel R2 and the fifth red sub-pixel R5, the first red sub-pixel R1 and the fourth red sub-pixel R4, the third red sub-pixel R3 and the sixth red sub-pixel R6, the eighth red sub-pixel R8 and the eleventh red sub-pixel R11, and the seventh red sub-pixel, respectively connected to the first gate line GL1 to the twelfth gate line GL12, are respectively connected to the second red sub-pixel R2 and the fifth red sub-pixel R5, the first red sub-pixel R1 and the fourth red sub-pixel R4, the third red sub-pixel R3 and the sixth red sub-pixel R6, the eighth red sub-pixel R8 and the eleventh red sub-pixel R11, and the seventh red sub-pixel R4. R7 and the tenth red sub-pixel R10, the ninth red sub-pixel R9 and the twelfth red sub-pixel R12, the fourteenth red sub-pixel R14 and the seventeenth red sub-pixel R17, the thirteenth red sub-pixel R13 and the sixteenth red sub-pixel R16, the fifteenth red sub-pixel R15 and the eighteenth red sub-pixel R18, the twentieth red sub-pixel R20 and the twenty-third red sub-pixel R23, the nineteenth red sub-pixel R19 and the twenty-second red sub-pixel R22, as well as the twenty-first red sub-pixel R21 and the twenty-fourth red sub-pixel R24 can be driven sequentially.

[0181] according to Figure 9 For example, when a gate signal with a conduction voltage level, supplied with data voltage through the first green data line GDL1 and the second green data line GDL2, is sequentially applied to the first gate line GL1 to the twelfth gate line GL12, the first green sub-pixel G1 and the fourth green sub-pixel G4, the third green sub-pixel G3 and the sixth green sub-pixel G6, the second green sub-pixel G2 and the fifth green sub-pixel G5, the seventh green sub-pixel G7 and the tenth green sub-pixel G10, and the ninth green sub-pixel G12, respectively, are connected to the first gate line GL1 to the twelfth gate line GL12. The 9th and twelfth green sub-pixels G12, the eighth green sub-pixel G8 and the eleventh green sub-pixel G11, the thirteenth green sub-pixel G13 and the sixteenth green sub-pixel G16, the fifteenth green sub-pixel G15 and the eighteenth green sub-pixel G18, the fourteenth green sub-pixel G14 and the seventeenth green sub-pixel G17, the nineteenth green sub-pixel G19 and the twenty-second green sub-pixel G22, the twenty-first green sub-pixel G21 and the twenty-fourth green sub-pixel G24, as well as the twentieth green sub-pixel G20 and the twenty-third green sub-pixel G23 can be driven sequentially.

[0182] according to Figure 10For example, when a gate signal with a conduction voltage level, supplied with data voltage through the first white data line WDL1 and the second white data line WDL2, is sequentially applied to the dummy gate line GL0 and the first gate line GL1 to the twelfth gate line GL12, the third white sub-pixel W3, the first white sub-pixel W1 and the fifth white sub-pixel W5, the second white sub-pixel W2 and the sixth white sub-pixel W6, the ninth white sub-pixel W9 and the fourth white sub-pixel W4, and the seventh white sub-pixel W7, respectively, are connected to the dummy gate line GL0 and the first gate line GL1 to the twelfth gate line GL12. The eleventh white sub-pixel W11, the eighth white sub-pixel W8, the twelfth white sub-pixel W12, the fifteenth white sub-pixel W15, the tenth white sub-pixel W10, the thirteenth white sub-pixel W13, the seventeenth white sub-pixel W17, the fourteenth white sub-pixel W14, the eighteenth white sub-pixel W18, the twenty-first white sub-pixel W21, the sixteenth white sub-pixel W16, the nineteenth white sub-pixel W19, the twenty-third white sub-pixel W23, the twentieth white sub-pixel W20, the twenty-fourth white sub-pixel W24, and the twenty-second white sub-pixel W22 can be driven sequentially.

[0183] according to Figure 11 For example, when a gate signal with a conduction voltage level, supplied via the first blue data line BDL1 and the second blue data line BDL2, is sequentially applied to the first gate line GL1 to the twelfth gate line GL12, the third blue sub-pixel B3 and the sixth blue sub-pixel B6, the second blue sub-pixel B2 and the fifth blue sub-pixel B5, the first blue sub-pixel B1 and the fourth blue sub-pixel B4, the ninth blue sub-pixel B9 and the twelfth blue sub-pixel B12, and the eighth blue sub-pixel, respectively, are connected to the first gate line GL1 to the twelfth gate line GL12. B8 and the eleventh blue sub-pixel B11, the seventh blue sub-pixel B7 and the tenth blue sub-pixel B10, the fifteenth blue sub-pixel B15 and the eighteenth blue sub-pixel B18, the fourteenth blue sub-pixel B14 and the seventeenth blue sub-pixel B17, the thirteenth blue sub-pixel B13 and the sixteenth blue sub-pixel B16, the twenty-first blue sub-pixel B21 and the twenty-fourth blue sub-pixel B24, the twentieth blue sub-pixel B20 and the twenty-third blue sub-pixel B23, as well as the nineteenth blue sub-pixel B19 and the twenty-second blue sub-pixel B22 can be driven sequentially.

[0184] According to an embodiment, at least two sub-pixels among the red, green, white, and blue sub-pixels connected to the same gate line can be driven in the same timing sequence.

[0185] The display device according to embodiments of the present disclosure can be described as follows.

[0186] A display device according to an embodiment of the present disclosure includes: a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels disposed thereon; a gate driving circuit for driving the plurality of gate lines; and a data driving circuit for supplying data voltage to the plurality of data lines. The plurality of sub-pixels includes a plurality of white sub-pixels corresponding to white and a plurality of colored sub-pixels corresponding to a plurality of colors other than white. At least three sub-pixels of the same color and adjacent in the row direction are connected to the same data line. One of two adjacent white sub-pixels in the row direction may have an inverted structure where the position of the light-emitting region and the position of the sub-pixel circuit section are reversed. The remaining white sub-pixel of the two adjacent white sub-pixels in the row direction may have a normal arrangement structure where the light-emitting region is located above the sub-pixel circuit section.

[0187] One of the three adjacent color subpixels corresponding to the same color in the row direction can have an inverted structure, and the remaining two color subpixels of the three adjacent color subpixels in the row direction can have a normal arrangement structure.

[0188] Multiple gate lines may include a first gate line and a dummy gate line disposed between the data driving circuit and the first gate line.

[0189] At least one white sub-pixel with a flip-chip structure, located in the first row of white sub-pixels closest to the data driving circuit, can be connected to a dummy gate line.

[0190] The straight-line distance between the sub-pixel circuit section of the white sub-pixel connected to the dummy gate line and the data driving circuit can be shorter than the straight-line distance between the sub-pixel circuit section of the other white sub-pixels in the first row (excluding the white sub-pixels connected to the dummy gate line) and the data driving circuit.

[0191] A white sub-pixel and three colored sub-pixels corresponding to different colors form a unit pixel, and the three colored sub-pixels in the unit pixel may include a first colored sub-pixel corresponding to a first color, a second colored sub-pixel corresponding to a second color, and a third colored sub-pixel corresponding to a third color.

[0192] At least three different gate lines can be set in a single pixel.

[0193] The sub-pixels in the first row of the plurality of sub-pixels form a first pixel group, the sub-pixels in the second row of the plurality of sub-pixels form a second pixel group, and the plurality of gate lines may include dummy gate lines disposed in the first pixel group and the second pixel group, as well as the first gate line to the sixth gate line.

[0194] The first pixel group includes a first unit pixel to a sixth unit pixel arranged sequentially in the row direction, and the white sub-pixel in the third unit pixel among the first unit pixel to the sixth unit pixel can be connected to a dummy gate line.

[0195] One of the first, second, and third color subpixels can have an inverted structure.

[0196] Within a single pixel, the first color sub-pixel, the second color sub-pixel, the white sub-pixel, and the third color sub-pixel can be set sequentially in the row direction.

[0197] On the display panel, high-potential voltage lines may be provided in the area adjacent to one side of the first color sub-pixel and in the area adjacent to the other side of the third color sub-pixel, and sensing lines may be provided in the area between the other side of the second color sub-pixel and one side of a white sub-pixel.

[0198] The sensing line can be connected to a branch line that passes through the light-emitting area of ​​each of the first color sub-pixel, the second color sub-pixel, a white sub-pixel, and the third color sub-pixel.

[0199] Each of the multiple data lines may include three sub-data lines, which branch to supply data voltage to each of three sub-pixels that correspond to the same color and are adjacent in the row direction.

[0200] Multiple color subpixels may include multiple red subpixels corresponding to red, multiple green subpixels corresponding to green, and multiple blue subpixels corresponding to blue.

[0201] The multiple data lines may include at least one white data line connected to multiple white sub-pixels, at least one red data line connected to multiple red sub-pixels, at least one green data line connected to multiple green sub-pixels, and at least one blue data line connected to multiple blue sub-pixels.

[0202] A display panel according to an embodiment of the present disclosure includes: a plurality of unit pixels disposed in a row closest to a data driving circuit, and each unit pixel including a white sub-pixel and at least one color sub-pixel; a plurality of gate lines respectively connected to at least one corresponding unit pixel among the plurality of unit pixels; and a plurality of data lines respectively connected to at least one corresponding unit pixel among the plurality of unit pixels, wherein the plurality of unit pixels may include a first unit pixel, a second unit pixel, a third unit pixel, a fourth unit pixel, a fifth unit pixel, and a sixth unit pixel sequentially disposed in the row closest to the data driving circuit.

[0203] The multiple data lines may include a first white data line, at least one first color data line, a second white data line, and at least one second color data line. The first white data line and at least one first color data line are respectively connected to the white sub-pixel and at least one color sub-pixel in the first unit pixel to the third unit pixel. The second white data line and at least one second color data line are respectively connected to the white sub-pixel and at least one color sub-pixel in the fourth unit pixel to the sixth unit pixel.

[0204] One of the two adjacent white sub-pixels in the first to sixth unit pixels has an inverted structure in which the position of the light-emitting area and the position of the sub-pixel circuit section are reversed, and the remaining white sub-pixel in the two adjacent white sub-pixels has a normal arrangement structure in which the light-emitting area is located above the sub-pixel circuit section.

[0205] One of the three adjacent color sub-pixels corresponding to the same color in the first to sixth unit pixels can have an inverted structure, and the remaining two color sub-pixels in the three adjacent color sub-pixels have a normal arrangement structure.

[0206] The multiple gate lines include a first gate line to a third gate line and a dummy gate line disposed between the data driving circuit and the first gate line, and the dummy gate line can be connected to the white sub-pixel in the third unit pixel.

[0207] Although certain specific embodiments and implementations have been described herein, other embodiments and improvements will also be apparent from this specification. Therefore, the concept of the invention is not limited to these specific embodiments, but includes the broader scope of the appended claims, and covers various modifications and equivalents that are obvious to those skilled in the art.

Claims

1. A display device, comprising: The display panel has multiple gate lines, multiple data lines, and multiple sub-pixels. A gate driving circuit that drives the plurality of gate lines; as well as The data driving circuit supplies data voltage to the multiple data lines. The plurality of sub-pixels includes a plurality of white sub-pixels corresponding to white and a plurality of colored sub-pixels corresponding to various colors other than white. Among these, at least three sub-pixels of the same color and adjacent in the row direction are connected to the same data line, and Among the plurality of white sub-pixels, one of two adjacent white sub-pixels in the row direction has an inverted structure in which the position of the light-emitting area and the position of the sub-pixel circuit section are reversed.

2. The display device according to claim 1, wherein, One of the three adjacent color sub-pixels of the plurality of color sub-pixels corresponding to the same color in the row direction has the inverted structure, and the remaining two color sub-pixels of the three adjacent color sub-pixels in the row direction have the normal arrangement structure.

3. The display device according to claim 1, wherein, The plurality of gate lines include a first gate line and a dummy gate line disposed between the data driving circuit and the first gate line.

4. The display device according to claim 3, wherein, At least one white sub-pixel of the plurality of white sub-pixels, which is located in the first row closest to the data driving circuit and has the flip-chip structure, is connected to the dummy gate line.

5. The display device according to claim 4, wherein, The straight-line distance between the sub-pixel circuit section of the white sub-pixel connected to the dummy gate line and the data driving circuit is shorter than the straight-line distance between the sub-pixel circuit sections of the other white sub-pixels in the first row (excluding the white sub-pixel connected to the dummy gate line) and the data driving circuit.

6. The display device according to claim 4, wherein, One white sub-pixel and three colored sub-pixels corresponding to different colors form a unit pixel, and The three color sub-pixels in the unit pixel include a first color sub-pixel corresponding to a first color, a second color sub-pixel corresponding to a second color, and a third color sub-pixel corresponding to a third color.

7. The display device according to claim 6, wherein, The unit pixel has at least three different gate lines.

8. The display device according to claim 7, wherein, The sub-pixels arranged in the first row among the plurality of sub-pixels form a first pixel group, and the sub-pixels arranged in the second row among the plurality of sub-pixels form a second pixel group. The plurality of gate lines include the dummy gate lines disposed in the first pixel group and the second pixel group, as well as the first gate line to the sixth gate line.

9. The display device according to claim 8, wherein, The first pixel group includes a first unit pixel to a sixth unit pixel arranged sequentially in the row direction, and Wherein, the white sub-pixel of the third unit pixel among the first unit pixel to the sixth unit pixel is connected to the dummy gate line.

10. The display device according to claim 6, wherein, One of the first, second, and third color sub-pixels has the inverted structure.

11. The display device according to claim 6, wherein, In the unit pixel, the first color sub-pixel, the second color sub-pixel, the white sub-pixel, and the third color sub-pixel are arranged sequentially in the row direction.

12. The display device according to claim 11, wherein, On the display panel, a high-potential voltage line is provided in an area adjacent to one side of the first color sub-pixel and in an area adjacent to the other side of the third color sub-pixel, and a sensing line is provided in an area located between the other side of the second color sub-pixel and one side of the white sub-pixel.

13. The display device according to claim 12, wherein, The sensing line is connected to a branch line that passes through the light-emitting area of ​​each of the first color sub-pixel, the second color sub-pixel, the white sub-pixel, and the third color sub-pixel.

14. The display device according to claim 1, wherein, Each of the multiple data lines includes three sub-data lines, which branch to supply the data voltage to each of three sub-pixels that correspond to the same color and are adjacent in the row direction.

15. The display device according to claim 14, wherein, The plurality of color sub-pixels includes a plurality of red sub-pixels corresponding to red, a plurality of green sub-pixels corresponding to green, and a plurality of blue sub-pixels corresponding to blue.

16. The display device according to claim 15, wherein, The plurality of data lines include at least one white data line connected to the plurality of white sub-pixels, at least one red data line connected to the plurality of red sub-pixels, at least one green data line connected to the plurality of green sub-pixels, and at least one blue data line connected to the plurality of blue sub-pixels.

17. A display panel, comprising: Multiple unit pixels are arranged in the row closest to the data driving circuit, and each unit pixel includes a white sub-pixel and at least one colored sub-pixel; Multiple gate lines, each of which is connected to at least one corresponding unit pixel among the multiple unit pixels; as well as Multiple data lines, each connected to at least one corresponding unit pixel among the multiple unit pixels. The plurality of unit pixels includes a first unit pixel, a second unit pixel, a third unit pixel, a fourth unit pixel, a fifth unit pixel, and a sixth unit pixel. The plurality of data lines include a first white data line, at least one first color data line, a second white data line, and at least one second color data line. The first white data line and the at least one first color data line are respectively connected to the white sub-pixel and at least one color sub-pixel in the first unit pixel to the third unit pixel. The second white data line and the at least one second color data line are respectively connected to the white sub-pixel and at least one color sub-pixel in the fourth unit pixel to the sixth unit pixel. Among them, one of the two adjacent white sub-pixels in the first unit pixel to the sixth unit pixel has an inverted structure in which the position of the light-emitting area and the position of the sub-pixel circuit section are reversed.

18. The display panel according to claim 17, wherein, One of the three adjacent color sub-pixels corresponding to the same color among the first unit pixel to the sixth unit pixel has the inverted structure, and the remaining two color sub-pixels among the three adjacent color sub-pixels have the normal arrangement structure.

19. The display panel according to claim 17, wherein, The plurality of gate lines includes a first gate line to a third gate line and a dummy gate line disposed between the data driving circuit and the first gate line, and The dummy gate line is connected to the white sub-pixel in the third unit pixel.

Images