Gate driving circuit and display panel

Abstract

The application discloses a kind of gate drive circuit and display panel, belong to display technical field.Gate drive circuit includes: input module, including first node;Two first output modules, the first input end of two first output modules is respectively connected to second clock signal and third clock signal, and second input end is all connected to first level signal;First output module is used to output the signal of its first input end or second input end according to the level of first node;The level of the pulse of second clock signal and third clock signal is identical, and pulse has no overlap in time;The level of first level signal is different from the level of the pulse of second clock signal;Second output module is used to output first level signal when first output module outputs the signal of its first input end, and output second level signal when first output module outputs the signal of its second input end.The embodiment of the application provides composite gate drive circuit capable of outputting different gate drive signals.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) displays and flat panel displays based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream display devices. However, current display panels have relatively wide bezels. Summary of the Invention

[0003] This invention provides a gate driving circuit and a display panel. By providing a composite gate driving circuit capable of outputting different gate driving signals, it is beneficial to achieve a narrow bezel.

[0004] In a first aspect, embodiments of the present invention provide a gate driving circuit, comprising:

[0005] An input module includes a first node, the input module being used to control the level of the first node according to a first clock signal and an input signal;

[0006] Two first output modules are connected to the first node; the first input terminals of the two first output modules are respectively connected to a second clock signal and a third clock signal, and the second input terminals of the two first output modules are each connected to a first level signal; the first output module is used to output the signal connected to its first or second input terminal according to the level of the first node; wherein, the pulse levels of the second clock signal and the third clock signal are the same, and the pulses of the third clock signal and the second clock signal do not overlap in time; the level of the first level signal is different from the pulse level of the second clock signal;

[0007] The second output module is connected to the first node and receives the first level signal and the second level signal; the second output module is used to output the first level signal when the first output module outputs the signal received at its first input terminal, and to output the second level signal when the first output module outputs the signal received at its second input terminal; wherein, the level of the second level signal is the same as the level of the pulse of the second clock signal.

[0008] Optionally, the input module further includes: a second node; the input module is also configured to control the level of the second node to be inversely related to the level of the first node; the first output module includes:

[0009] The first output unit has its control terminal connected to the first node, its input terminal connected to the first input terminal of the first output module, and its output terminal connected to the output terminal of the first output module. The first output unit is used to turn on or off according to the level of its control terminal.

[0010] The second output unit has its control terminal connected to the second node, its input terminal connected to the second input terminal of the first output module, and its output terminal connected to the output terminal of the first output module. The second output unit is used to turn on or off according to the level of its control terminal.

[0011] Preferably, the first output unit includes: a first transistor and a first capacitor; the gate of the first transistor is connected to the control terminal of the first output unit, the first electrode of the first transistor is connected to the input terminal of the first output unit, and the second electrode of the first transistor is connected to the output terminal of the first output unit; the first capacitor is connected between the gate and the second electrode of the first transistor.

[0012] The second output unit includes: a second transistor, the gate of the second transistor being connected to the control terminal of the second output unit, the first terminal of the second transistor being connected to the input terminal of the second output unit, and the second terminal of the second transistor being connected to the output terminal of the second output unit; the first transistor and the second transistor have the same channel type.

[0013] Optionally, the first output module further includes: a transmission protection unit, connected between the first node and the control terminal of the first output unit, and connected to the second level signal;

[0014] Preferably, the transmission protection unit includes a third transistor connected between the first node and the control terminal of the first output unit, and the gate of the third transistor is connected to the second level signal.

[0015] Optionally, the first output module further includes: a first transmission control unit, connected between the first node and the control terminal of the first output unit, and connected to the first level signal, the first frequency control signal, and the second frequency control signal; the first transmission control unit is configured to, when responding to the first frequency control signal to control the connection between the first node and the control terminal of the first output unit, not transmit the first level signal to the control terminal of the first output unit in response to the second frequency control signal, and when responding to the first frequency control signal to control the disconnection between the first node and the control terminal of the first output unit, transmit the first level signal to the control terminal of the first output unit in response to the second frequency control signal, so that the first output unit turns off in response to the first level signal;

[0016] Preferably, the first transmission control unit includes:

[0017] The first transmission subunit is connected between the control terminal of the first node and the first output unit, and the control terminal of the first transmission subunit is connected to the first frequency control signal.

[0018] The second transmission subunit is connected to the control terminal of the first output unit and is connected to the first level signal and the second frequency control signal. It is used to control whether to transmit the first level signal to the control terminal of the first output unit according to the second frequency control signal.

[0019] Preferably, the first frequency control signal maintains the on level of the first transmission subunit in each display frame, and the second frequency control signal maintains the off level of the second transmission subunit in each display frame, so that the frequency of the output signal of the first output module is the same as the frequency of the voltage of the first node.

[0020] Alternatively, in at least a partial display frame, the first frequency control signal jumps to the cutoff level of the first transmission subunit before the level of the first node jumps to the on level of the first output unit, and the second frequency control signal jumps to the on level of the second transmission subunit before the level of the first node jumps to the on level of the first output unit, such that the frequency of the output signal of the first output module is lower than the frequency of the voltage of the first node.

[0021] Preferably, the first transmission subunit includes a fourth transistor; the fourth transistor is connected between the control terminal of the first node and the first output unit, and the gate of the fourth transistor is connected to the first frequency control signal;

[0022] The second transmission sub-unit includes: a fifth transistor; the gate of the fifth transistor is connected to the second frequency control signal, the first terminal of the fifth transistor is connected to the first level signal, and the second terminal of the fifth transistor is connected to the control terminal of the first output unit;

[0023] Preferably, the fourth transistor and the fifth transistor have the same channel type, and the first frequency control signal and the second frequency control signal are inverted signals.

[0024] Optionally, the input module further includes: a second node; the input module is also configured to control the level of the second node to be inversely proportional to the level of the first node; the second output module includes:

[0025] The third output unit has its control terminal connected to the first node, its input terminal connected to the first level signal, and its output terminal connected to the output terminal of the second output module. The third output unit is used to turn on or off according to the level of its control terminal.

[0026] The fourth output unit has its control terminal connected to the second node, its input terminal connected to the second level signal, and its output terminal connected to the output terminal of the second output module. The fourth output unit is used to turn on or off according to the level of its control terminal.

[0027] Preferably, the third output unit includes: a sixth transistor and a second capacitor; the gate of the sixth transistor is connected to the control terminal of the third output unit, the first terminal of the sixth transistor is connected to the first level signal, and the second terminal of the sixth transistor is connected to the output terminal of the third output unit; the second capacitor is connected between the gate and the first terminal of the sixth transistor.

[0028] The fourth output unit includes: a seventh transistor; the gate of the seventh transistor is connected to the control terminal of the fourth output unit, the first terminal of the seventh transistor is connected to the second level signal, and the second terminal of the seventh transistor is connected to the output terminal of the fourth output unit; the sixth transistor has the same channel type as the seventh transistor.

[0029] Optionally, the second output module further includes:

[0030] A potential control unit is connected to the control terminals of the first node, the second node, and the fourth output unit, respectively, and receives a first level signal and a third level signal. The potential control unit is used to transmit the first level signal to the control terminal of the fourth output unit when the level of the second node is at the first level, and to transmit the third level signal to the control terminal of the fourth output unit when the level of the second node is at the second level. The first level signal has the first level, the second level signal has the second level, and the levels of the first level, the second level, and the third level signal decrease sequentially.

[0031] Preferably, the potential control unit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the first terminals of the eighth transistor and the ninth transistor are both connected to the first level signal; the gate of the eighth transistor is connected to the second node; the gate of the ninth transistor is connected to the first node; the second terminal of the eighth transistor is connected to the second terminal of the tenth transistor and the gate of the eleventh transistor; the second terminal of the ninth transistor is connected to the second terminal of the eleventh transistor, the gate of the tenth transistor, and the control terminal of the fourth output unit; the first terminals of the tenth transistor and the eleventh transistor are both connected to the third level signal; the eighth transistor and the ninth transistor have the same channel type; the eighth transistor and the tenth transistor have different channel types; and the tenth transistor and the eleventh transistor have the same channel type.

[0032] Optionally, the second output module further includes: a second transmission control unit, which is connected to the control terminals of the first node, the second node, and the third output unit respectively, and is connected to a first frequency control signal; the second transmission control unit is used to control whether the control terminals of the first node and the third output unit are connected according to the level of the second node and the first frequency control signal.

[0033] Preferably, the second transmission control unit includes:

[0034] The third transmission subunit is connected between the first node and the control terminal of the third output unit;

[0035] A frequency control subunit, the control terminal of which is connected to the second node, the input terminal of which is connected to the first frequency control signal, and the output terminal of which is connected to the control terminal of the third transmission subunit;

[0036] Preferably, the first frequency control signal maintains the conduction level of the third transmission subunit in each display frame, so that the frequency of the output signal of the second output module is the same as the frequency of the voltage of the first node;

[0037] Alternatively, in at least a partial display frame, the first frequency control signal jumps to the cutoff level of the third transmission subunit before the level of the first node jumps to the on level of the first output unit, so that the frequency of the output signal of the second output module is lower than the frequency of the voltage of the first node.

[0038] Preferably, the third transmission subunit includes: a twelfth transistor connected between the first node and the control terminal of the third output unit, and the gate of the twelfth transistor is connected to the output terminal of the frequency control subunit;

[0039] The frequency control subunit includes: a thirteenth transistor; the gate of the thirteenth transistor is connected to the second node, the first terminal of the thirteenth transistor is connected to the first frequency control signal, and the second terminal of the thirteenth transistor is connected to the output terminal of the frequency control subunit;

[0040] Preferably, the second transmission control unit further includes: a storage subunit, including a third capacitor; one end of the third capacitor is connected to the control terminal of the third transmission subunit, and the other end of the third capacitor is connected to a DC signal;

[0041] Preferably, the first level signal or the second level signal is multiplexed into the DC signal;

[0042] Preferably, the level of the DC signal is different from the cutoff level of the third transmission subunit;

[0043] Preferably, the second transmission control unit further includes one of an output subunit and a level control subunit; the control terminal of the output subunit is connected to the control terminal of the third transmission subunit, the input terminal of the output subunit is connected to the second level signal, and the output terminal of the output subunit is connected to the output terminal of the third output unit; the conduction level of the output subunit is different from the conduction level of the third transmission subunit; the control terminal of the level control subunit is connected to the second node, the input terminal of the level control subunit is connected to the first level signal, and the output terminal of the level control subunit is connected to the control terminal of the third output unit; wherein, the level of the first level signal is the cutoff level of the third control subunit;

[0044] Preferably, the output sub-unit includes: a fourteenth transistor; the gate of the fourteenth transistor is connected to the control terminal of the third transmission sub-unit, the first terminal of the fourteenth transistor is connected to the second level signal, and the output terminal of the fourteenth transistor is connected to the output terminal of the third output unit;

[0045] The level control subunit includes: a fifteenth transistor; the gate of the fifteenth transistor is connected to the second node, the first terminal of the fifteenth transistor is connected to the first level signal, and the second terminal of the fifteenth transistor is connected to the control terminal of the third output unit.

[0046] Optionally, the input module includes:

[0047] An input unit is connected to the input signal and the first clock signal respectively; the input unit is used to control whether to output the input signal according to the first clock signal.

[0048] The first inverting unit is connected to the output terminal of the input unit; the first inverting unit is used to invert the level of the output terminal of the input unit and then output it.

[0049] The second inverting unit is connected to the output terminal of the first inverting unit and the first node, respectively; the second inverting unit is used to invert the level output by the first inverting unit and provide it to the first node;

[0050] A switching unit is connected between the output terminal of the input unit and the first node, and is connected to the first clock signal; the switching unit is used to turn on or off according to the first clock signal; the on-state level of the switching unit is different from the on-state level of the input unit;

[0051] Preferably, the input unit includes a sixteenth transistor; the gate of the sixteenth transistor is connected to the first clock signal, the first terminal of the sixteenth transistor is connected to the input signal, and the second terminal of the sixteenth transistor is connected to the output terminal of the input unit;

[0052] The first inverting unit includes a seventeenth transistor and an eighteenth transistor with different channel types; the gates of the seventeenth transistor and the eighteenth transistor are both connected to the output terminal of the input unit; the first terminal of the seventeenth transistor is connected to the first level signal, the first terminal of the eighteenth transistor is connected to the second level signal, and the second terminals of the seventeenth transistor and the eighteenth transistor are both connected to the output terminal of the first inverting unit.

[0053] The second inverting unit includes a nineteenth transistor and a twentieth transistor with different channel types; the gates of the nineteenth transistor and the twentieth transistor are both connected to the output terminal of the first inverting unit; the first terminal of the nineteenth transistor is connected to the first level signal, the first terminal of the twentieth transistor is connected to the second level signal, and the second terminals of the nineteenth transistor and the twentieth transistor are both connected to the first node;

[0054] The switching unit includes: a twenty-first transistor connected between the output terminal of the input unit and the first node, and the gate of the twenty-first transistor is connected to the first clock signal; the sixteenth transistor has a different channel type than the twenty-first transistor.

[0055] Preferably, the level of the first level signal is higher than the level of the second level signal; the sixteenth transistor, the seventeenth transistor, and the nineteenth transistor are all P-type transistors, and the eighteenth transistor, the twentieth transistor, and the twenty-first transistor are all N-type transistors;

[0056] Preferably, the second output module includes: a third inverting unit; the input terminal of the third inverting unit is connected to the first node, and the output terminal of the third inverting unit is connected to the output terminal of the second output module.

[0057] Secondly, embodiments of the present invention also provide a display panel, including: the gate driving circuit provided in any embodiment of the present invention.

[0058] Optionally, the display panel includes multiple cascaded gate drive circuits; the display panel also includes a start signal line;

[0059] The start signal line is connected to the first-stage gate driving circuit to provide an input signal to the first-stage gate driving circuit; the first node of each stage of the gate driving circuit is connected to the next stage of the gate driving circuit to provide an input signal to the next stage of the gate driving circuit.

[0060] Preferably, the first output module of the gate driving circuit includes a first transmission control unit, and the second output module includes a second transmission control unit; the display panel further includes a first frequency control signal line and a second frequency control signal line; the first frequency control signal line is used to transmit a first frequency control signal to the first transmission control unit and the first transmission control unit in each of the gate driving circuits, and the second frequency control signal line is used to provide a second frequency control signal to the first transmission control unit in each of the gate driving circuits;

[0061] Preferably, when the display panel displays at a uniform refresh rate across the entire screen, the first frequency signal and the second frequency signal maintain a constant level in each display frame;

[0062] When the display panel displays at least two display zones with different refresh rates, both the first frequency signal and the second frequency signal undergo level transitions in at least a portion of the display frames.

[0063] The gate driving circuit provided in this embodiment of the invention includes an input module, two first output modules, and one second output module, and is connected to three clock signals. The input module can control the potential of the first node based on the first clock signal, providing conditions for controlling the output state of the three output modules. According to the potential of the first node, the first first output module can output the pulse of the second clock signal as the pulse of the first gate driving signal, and the second first output module can output the pulse of the third clock signal as the pulse of the second gate driving signal. By setting the pulse levels of the second and third clock signals to be the same and staggered in time, the gate driving circuit can output a pair of gate driving signals with the same pulse level and pulses appearing in a time-division manner. Furthermore, according to the potential of the first node, the second output module can output the pulse of the third gate driving signal, which is composed of a first level signal, at the same time as the first output module outputs its connected clock signal. This makes the pulse width of the third gate driving signal wider than the other two gate driving signals. Since the level of the first level signal is different from the pulse levels of the second and third clock signals, the pulse level of the third gate driving signal is different from the other two gate driving signals. Therefore, this invention provides a composite gate driving circuit capable of outputting three gate driving signals with different pulse widths, different pulse levels, or different pulse output times to meet the different driving requirements of pixel circuits. Furthermore, all three output modules are controlled based on the level of the first node, meaning they share the same input module. Compared to using three independently configured gate driving circuits to provide these three signals, this effectively simplifies the structure of the gate driving circuit and facilitates the implementation of narrow bezels in display panels.

[0064] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0066] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0067] Figure 2 This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention;

[0068] Figure 3 This is a schematic diagram of the structure of an input module provided in an embodiment of the present invention;

[0069] Figure 4 This is a schematic diagram of another input module provided in an embodiment of the present invention;

[0070] Figure 5 This is a schematic diagram of the structure of a first output module provided in an embodiment of the present invention;

[0071] Figure 6 This is a schematic diagram of another first output module provided in an embodiment of the present invention;

[0072] Figure 7 This is a schematic diagram of the structure of a second output module provided in an embodiment of the present invention;

[0073] Figure 8 This is a schematic diagram of another second output module provided in an embodiment of the present invention;

[0074] Figure 9 This is a schematic diagram of the structure of another second output module provided in an embodiment of the present invention;

[0075] Figure 10 This is a schematic diagram of the structure of another second output module provided in an embodiment of the present invention;

[0076] Figure 11 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0077] Figure 12 This is a schematic diagram of another first output module provided in an embodiment of the present invention;

[0078] Figure 13 This is a schematic diagram of the structure of another second output module provided in an embodiment of the present invention;

[0079] Figure 14This is a schematic diagram of the structure of another second output module provided in an embodiment of the present invention;

[0080] Figure 15 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0081] Figure 16 This is a schematic diagram of the driving timing of another gate driving circuit provided in an embodiment of the present invention;

[0082] Figure 17 This is a schematic diagram of the driving timing of another gate driving circuit provided in an embodiment of the present invention;

[0083] Figure 18 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0084] Figure 19 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0085] Figure 20 This is a schematic diagram of the driving timing of a multi-stage gate driving circuit provided in an embodiment of the present invention;

[0086] Figure 21 This is a schematic diagram of the driving timing of another multi-stage gate driving circuit provided in an embodiment of the present invention. Detailed Implementation

[0087] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0088] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0089] As mentioned in the background section, current display panels have relatively wide bezels. The main reason for this technical problem is that with the continuous development of display technology, the application range of display panels is becoming increasingly wide, and people's requirements for display panels are also increasing. Display panels include pixel circuits and gate drive circuits that provide gate drive signals to the pixel circuits. To drive the pixel circuits to complete processes such as reset, data writing, threshold compensation, and light emission, different gate drive signals are usually required for different functional modules in the pixel circuit. At least one of the pulse width, pulse time, and pulse level differs between these different gate drive signals. This necessitates the use of multiple sets of gate drive circuits in the gate drive module of related technologies, and the structures of the gate drive circuits used to provide different gate drive signals are also different, resulting in a complex structure of the gate drive module and making it difficult to reduce the bezel area of ​​the display panel.

[0090] To address the aforementioned problems, this invention provides a gate driving circuit that can provide three different gate driving signals through three output modules, satisfying various driving requirements of pixel circuits and facilitating the realization of narrow bezels in display panels. The structure of this gate driving circuit is described below.

[0091] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention. See also... Figure 1 The gate driving circuit includes an input module 10, two first output modules (a first first output module 201 and a second first output module 202), and a second output module 30. The input terminal of the input module 10 serves as the input terminal of the gate driving circuit, receiving the input signal GIN. The output terminal of the first first output module 201 serves as the first output terminal of the gate driving circuit, outputting a first gate driving signal POUT1. The output terminal of the second first output module 202 serves as the second output terminal of the gate driving circuit, outputting a second gate driving signal POUT2. The output terminal of the second output module 30 serves as the third output terminal of the gate driving circuit, outputting a third gate driving signal NOUT.

[0092] The input module 10 includes a first node Q, which is connected to an input signal GIN and a first clock signal CK1. The input module 10 controls the level of the first node Q according to the first clock signal CK1 and the input signal GIN. Two first output modules are both connected to the first node Q. The first input terminals of the two first output modules are connected to a second clock signal CK2 and a third clock signal CK3, respectively, and the second input terminals of the two first output modules are both connected to a first level signal VGH. The first output module outputs the signal connected to its first or second input terminal according to the level of the first node Q. The pulse levels of the second clock signal CK2 and the third clock signal CK3 are the same, and the pulses of the third clock signal CK3 and the second clock signal CK2 do not overlap in time. The level of the first level signal VGH is different from the pulse level of the second clock signal CK2. For example, the pulse levels of the second clock signal CK2 and the third clock signal CK3 are the effective levels of the first gate drive signal POUT1 and the second gate drive signal POUT2, respectively, and the level of the first level signal VGH is the ineffective level of the first gate drive signal POUT1 and the second gate drive signal POUT2. The effective level of any gate drive signal is the on-level of the functional module connected to the gate drive signal, and the ineffective level is the off-level of the functional module connected to the gate drive signal. For example, if the functional module connected to the gate drive signal includes a P-type transistor, its on-level is low and its off-level is high. The second output module 30 is connected to the first node Q and connected to the first level signal VGH and the second level signal VGL. The second output module 30 is used to output the first level signal VGH when the first output module outputs the signal connected to its first input terminal, and to output the second level signal VGL when the first output module outputs the signal connected to its second input terminal. The level of the second level signal VGL is the same as the level of the pulse of the second clock signal CK2, and the level of the second level signal VGL is different from the level of the first level signal VGH. For example, the first level signal VGH is high and the second level signal VGL is low. It is understood that in the various embodiments of the present invention, the difference between the two levels means that one level is high and the other level is low, which can also be referred to as the two levels being inversely related.

[0093] Figure 2 This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention. (Combined with...) Figure 1 and Figure 2 The driving process of this gate drive circuit is as follows:

[0094] Input module 10 determines the level of first node Q within any pulse period of the first clock signal CK1 based on the level of input signal GIN during the pulse phase of that pulse period. For example, it controls the voltage VQ of first node Q to maintain the level of input signal GIN during the pulse phase of that pulse period in any pulse period. Figure 2 In the first clock signal CK1, during the pulse phase T11 of the first pulse period T1, the input signal GIN is at a low level, and the input module 10 controls the first node Q to remain at a low level during this first pulse period T1. During the pulse phase T21 of the second pulse period T2 of the first clock signal CK1, the input signal GIN is at a high level, and the input module 10 controls the first node Q to remain at a high level during this second pulse period T2. That is to say, the voltage VQ of the first node Q is actually a pulse signal with the same frequency as the input signal GIN.

[0095] The first output module can be in the pulse phase of the voltage VQ at the first node Q (corresponding to...). Figure 2 During the first pulse period T1, in response to the pulse level of the first node Q, the clock signal connected to the first input terminal of the first output module is output, and in other stages, the first level signal VGH connected to the second input terminal of the first output module is output. Therefore, during the pulse phase of the voltage VQ of the first node Q, the first output module 201 outputs the second clock signal CK2 as the first gate drive signal POUT1, and during this phase, the first output module 201 can output one pulse of the second clock signal CK2; simultaneously, the second output module 202 outputs the third clock signal CK3 as the second gate drive signal POUT2, and during this phase, the second output module 202 can output one pulse of the third clock signal CK3; in other stages, both the first gate drive signal POUT1 and the second gate drive signal POUT2 maintain the level of the first level signal VGH. Since the pulse levels of the second clock signal CK2 and the third clock signal CK3 are the same, and the pulses of the third clock signal CK3 and the second clock signal CK2 do not overlap in time, the first gate drive signal POUT1 and the second gate drive signal POUT2 are a set of gate drive signals with the same pulse level and pulse time-division output.

[0096] The second output module 30 can be used during the pulse phase of the voltage VQ at the first node Q (corresponding to...). Figure 2During the first pulse period T1, i.e., the phase in which the first output module outputs its input clock signal, the second output module 30 outputs the first level signal VGH as the third gate drive signal NOUT in response to the pulse level of the first node Q. In other phases, i.e., the phase in which the first output module outputs the first level signal VGH, the second output module 30 outputs the second level signal VGL. This makes the pulse level of the third gate drive signal NOUT different from the pulse levels of the first gate drive signal POUT1 and the second gate drive signal POUT2. Furthermore, since the second output module 30 continuously outputs the first level signal VGH throughout the entire pulse phase of the first node Q, the pulse width of the third gate drive signal NOUT is equal to the pulse period of the first clock signal CK1, which is wider than the pulse widths of both the first gate drive signal POUT1 and the second gate drive signal POUT2.

[0097] Therefore, among the three gate drive signals output by the three output modules in this gate drive circuit, there are two signals with the same pulse level and pulse-division multiplexing, and one signal with a different pulse level and wider pulse width than the other two signals. This set of gate drive signals can meet various driving requirements of the pixel circuit. For example, the first gate drive signal POUT1 and the second gate drive signal POUT2 can be used to drive P-type switching transistors in the pixel circuit, excluding the light-emitting control transistor. They can also be provided to different P-type switching transistors in the same pixel circuit. For instance, the first gate drive signal POUT1 can drive the gate reset transistor, and the second gate drive signal POUT2 can drive the data write transistor. The third gate drive signal NOUT can be used to drive the light-emitting control transistor or N-type switching transistors other than the light-emitting control transistor.

[0098] In summary, the gate driving circuit provided in this embodiment of the invention includes an input module 10, two first output modules and one second output module 30, and is connected to three clock signals. Input module 10 can control the potential of the first node Q based on the first clock signal CK1, providing conditions for controlling the output state of the three output modules. According to the potential of the first node Q, the first output module 201 can output the pulse of the second clock signal CK2 as the pulse of the first gate drive signal POUT1, and the second output module 202 can output the pulse of the third clock signal CK3 as the pulse of the second gate drive signal POUT2. By setting the pulse levels of the second clock signal CK2 and the third clock signal CK3 to be the same and staggered in time, the gate drive circuit can output a pair of gate drive signals with the same pulse level and pulses appearing in time division. According to the potential of the first node Q, the second output module 30 can output the pulse of the first level signal VGH to form the third gate drive signal NOUT while the first output module outputs the clock signal it has received. This makes the pulse width of the third gate drive signal NOUT wider than the other two gate drive signals. Since the level of the first level signal VGH is different from the pulse levels of the second clock signal CK2 and the third clock signal CK3, the pulse level of the third gate drive signal NOUT is different from the other two gate drive signals. Therefore, this embodiment of the invention provides a composite gate driving circuit capable of outputting three gate driving signals with different pulse widths, different pulse levels, or different pulse output times to meet the different driving requirements of pixel circuits. Furthermore, all three output modules are controlled based on the level of the first node Q, meaning the three output modules share the same input module 10. Compared to using three independently configured gate driving circuits to provide these three signals, this effectively simplifies the structure of the gate driving circuit and facilitates the realization of narrow bezels in the display panel.

[0099] Based on the above embodiments, optionally, such as Figure 2 As shown, the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 can all be set to be pulse signals with the same waveform, and the initial pulses of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3 do not overlap in time and appear sequentially.

[0100] For example, the first level signal VGH has a first level, and the second level signal VGL has a second level; each clock signal is a pulse signal that alternates between the first level and the second level, and each clock signal pulse has a second level. It is understood that in the various embodiments of the present invention, the first level and the second level only represent two state quantities of the signal level, and do not mean that the first level or the second level has a specific value throughout the text. In the following embodiments of the present invention, the example of the first level being high relative to the second level is used for illustration.

[0101] The specific structures that each module in the gate drive circuit may have are described below, but this is not intended to limit the invention.

[0102] Figure 3 This is a schematic diagram of the structure of an input module provided in an embodiment of the present invention. See also: Figure 3 In one embodiment, the input module 10 may optionally include a second node QB; the input module 10 is also used to control the level of the second node QB to be inversely phase with the level of the first node Q. Each output module can have its output state controlled by the cooperation of the first node Q and the second node QB. For example, the first output module can control whether to output the signal connected to the first input terminal according to the level of the first node Q, and control whether to output the signal connected to the first input terminal according to the level of the second node QB; the second output module 30 can control whether to output the first level signal VGH according to the level of the first node Q, and control whether to output the second level signal VGL according to the level of the second node QB.

[0103] For details, see Figure 3 The input module 10 may include an input unit 110, a first inverting unit 120, a second inverting unit 130, and a switching unit 140. The input unit 110 is connected to an input signal GIN and a first clock signal CK1; the input unit 110 controls whether to output the input signal GIN according to the first clock signal CK1. The first inverting unit 120 is connected to the output terminal of the input unit 110; the first inverting unit 120 inverts the output level of the input unit 110 before outputting it. The second inverting unit 130 is connected to the output terminal of the first inverting unit 120 and a first node Q; the second inverting unit 130 inverts the output level of the first inverting unit 120 and provides it to the first node Q. The switching unit 140 is connected between the output terminal of the input unit 110 and the first node Q, and is connected to the first clock signal CK1; the switching unit 140 is turned on or off according to the first clock signal CK1. The conduction level of the switch unit 140 is different from that of the input unit 110; that is, the on / off states of the switch unit 140 and the input unit 110 are opposite.

[0104] Specifically, in the input module 10, when the input unit 110 is turned on in response to the first clock signal CK1 (see [reference]...), Figure 2 During the pulse phase of the first clock signal CK1, the switching unit 140 turns off in response to the first clock signal CK1. At this time, the input signal GIN is transmitted to the output terminal of the input unit 110. The first inverting unit 120 inverts the input signal GIN as the level output of the second node QB, and the second inverting unit 130 inverts the level of the second node QB as the level output of the first node Q. This allows the input module 10 to control the levels of the first node Q and the second node QB according to the level of the input signal GIN. When the switching unit 140 turns on in response to the first clock signal CK1 (see...), the switching unit 140 turns off in response to the first clock signal CK1 (see...). Figure 2 During the period excluding the pulse phase of the first clock signal CK1, the input unit 110 turns off in response to the first clock signal CK1 to prevent the input signal GIN from being transmitted into the input module 10. At this time, the level change of the input signal GIN will not affect the output state of the input module 110. Since the switching unit 140 is turned on, the first inverting unit 120 and the second inverting unit 130 are cross-coupled to form a latch, which can maintain the level of the second node QB and the first node Q unchanged.

[0105] Figure 4 This is a schematic diagram of another input module provided in an embodiment of the present invention. See also... Figure 4 In one embodiment, the input unit 110 may optionally include a sixteenth transistor M16; the gate of the sixteenth transistor M16 is connected to a first clock signal CK1, the first terminal of the sixteenth transistor M16 is connected to an input signal GIN, and the second terminal of the sixteenth transistor M16 is connected to the output terminal of the input unit 110. The sixteenth transistor M16 is turned on or off according to the first clock signal CK1.

[0106] The first inverting unit 120 includes a seventeenth transistor M17 and an eighteenth transistor M18 with different channel types; the gates of the seventeenth transistor M17 and the eighteenth transistor M18 are both connected to the output terminal of the input unit 110; the first terminal of the seventeenth transistor M17 is connected to a first level signal VGH, the first terminal of the eighteenth transistor M18 is connected to a second level signal VGL, and the second terminals of the seventeenth transistor M17 and the eighteenth transistor M18 are both connected to the output terminal of the first inverting unit 120.

[0107] The second inverting unit 130 includes a nineteenth transistor M19 and a twentieth transistor M20 with different channel types; the gate of the nineteenth transistor M19 and the gate of the twentieth transistor M20 are both connected to the output terminal of the first inverting unit 120; the first terminal of the nineteenth transistor M19 is connected to a first level signal VGH, the first terminal of the twentieth transistor M20 is connected to a second level signal VGL, and the second terminals of the nineteenth transistor M19 and the twentieth transistor M20 are both connected to the first node Q.

[0108] The switching unit 140 includes: a twenty-first transistor M21, connected between the output terminal of the input unit 110 and the first node Q, and the gate of the twenty-first transistor M21 is connected to the first clock signal CK1; the sixteenth transistor M16 has a different channel type than the twenty-first transistor M21, so as to ensure that the sixteenth transistor M16 and the twenty-first transistor M21 have different on / off states under the control of the same clock signal.

[0109] For example, the level of the first level signal VGH is higher than the level of the second level signal VGL; the sixteenth transistor M16, the seventeenth transistor M17 and the nineteenth transistor M19 are all P-type transistors, and the eighteenth transistor M18, the twentieth transistor M20 and the twenty-first transistor M21 are all N-type transistors.

[0110] In one embodiment, the first output module may optionally include two transistors with different channel types. The gates of both transistors are connected to a first node Q. The first electrode of one transistor is connected to the first input terminal of the first output module, and the first electrode of the other transistor is connected to the second input terminal of the first output module. The second electrodes of both transistors are connected to the output terminals of the first output module. Thus, because the two transistors have different channel types, their on / off states differ under the control of the first node Q, satisfying the functional requirement of the first output module to output the signal connected to its first output terminal or second input terminal according to the level of the first node Q. For example, the first electrode of a transistor with an on-state level the same as the pulse level of the first node Q can be connected to the first input terminal of the first output module so that the clock signal connected to the first input terminal is output during the pulse phase of the first node Q.

[0111] Figure 5 This is a schematic diagram of the structure of a first output module provided in an embodiment of the present invention. See also... Figure 5In another embodiment, optionally, the first output module 20 includes a first output unit 210 and a second output unit 220. It is understood that there is no distinction between the first and second first output modules here; the two first output modules essentially have the same circuit structure, differing only in the clock signal connected to their first input terminals and the waveform of the signal output from their output terminals. The circuit structure of the first output module 20 is described here, with the signal connected to its first input terminal labeled as a first-type clock signal CK, and the signal output from its output terminal labeled as a first-type gate drive signal POUT. It is understood that for the first first output module, the first-type clock signal CK is the second clock signal CK2, and the first-type gate drive signal POUT is the first gate drive signal POUT1; for the second first output module, the first-type clock signal CK is the third clock signal CK3, and the first-type gate drive signal POUT is the second gate drive signal POUT2.

[0112] Specifically, the control terminal of the first output unit 210 is connected to the first node Q, the input terminal of the first output unit 210 is connected to the first input terminal of the first output module 20, and the output terminal of the first output unit 210 is connected to the output terminal of the first output module 20. The first output unit 210 is used to control whether to output the first type clock signal CK as the first type gate drive signal POUT according to the level of its control terminal.

[0113] The control terminal of the second output unit 220 is connected to the second node QB, the input terminal of the second output unit 220 is connected to the second input terminal of the first output module 20, and the output terminal of the second output unit 220 is connected to the output terminal of the first output module 20. The second output unit 220 is used to control whether to output the first level signal VGH as the first type gate drive signal POUT according to the level of its control terminal.

[0114] Figure 6 This is a schematic diagram of another first output module provided in an embodiment of the present invention. See also... Figure 6 Based on the above embodiments, optionally, the first output unit 210 includes: a first transistor M1 and a first capacitor C1; the gate of the first transistor M1 is connected to the control terminal of the first output unit 210, the first electrode of the first transistor M1 is connected to the input terminal of the first output unit 210, and the second electrode of the first transistor M1 is connected to the output terminal of the first output unit 210; the first capacitor C1 is connected between the gate and the second electrode of the first transistor M1. In this first output unit 210, the first transistor M1 is turned on or off in response to its gate level, and the first capacitor C1 controls the gate level of the first transistor M1 through coupling.

[0115] For example, the first transistor M1 is a P-type transistor, and the pulse of the first type clock signal CK has a low level. When the first node Q is low, the first transistor M1 is turned on to output the first type clock signal CK. When the falling edge of the first type clock signal CK appears, the first capacitor C1 couples the level transition to the gate of the first transistor M1, making the gate level of the first transistor M1 even lower, which can make the first transistor M1 conduct more fully and ensure that the low-level pulse of the first type clock signal CK is reliably output.

[0116] The second output unit 220 includes a second transistor M2. The gate of the second transistor M2 is connected to the control terminal of the second output unit 220, the first terminal of the second transistor M2 is connected to the input terminal of the second output unit 220, and the second terminal of the second transistor M2 is connected to the output terminal of the second output unit 220. The second transistor M2 turns on or off in response to its gate level. For example, the first transistor M1 and the second transistor M2 have the same channel type, such as both being P-type transistors.

[0117] See also Figure 6 Optionally, based on the above embodiments, the first output module 20 further includes a transmission protection unit 230. The transmission protection unit 230 is connected between the first node Q and the control terminal of the first output unit 210, and is connected to a second level signal VGL. As can be seen from the above analysis, due to the coupling effect of the first capacitor C1, the level of the control terminal of the first output unit 210 will differ from the level of the first node Q, for example, it may be an extremely low level lower than the level of the first node Q. By setting the transmission protection unit 230, this extremely low level can be prevented from being transmitted to the first node Q, thus stabilizing the level of the first node Q and preventing the transistors connected to the first node Q from experiencing excessive voltage stress.

[0118] Specifically, the transmission protection unit 230 may include a third transistor M3, which is connected between the first node Q and the control terminal of the first output unit 210, and the gate of the third transistor M3 is connected to the second level signal VGL. For example, the third transistor M3 may be a P-type transistor.

[0119] Figure 7 This is a schematic diagram of the structure of a second output module provided in an embodiment of the present invention. See also... Figure 7 In one embodiment, optionally, the second output module 30 includes a third inverting unit 310; the input terminal of the third inverting unit 310 is connected to the first node Q, and the output terminal of the third inverting unit 310 is connected to the output terminal of the second output module 30. Thus, the second output module 30 can obtain the third gate drive signal NOUT by inverting the level of the first node Q.

[0120] Specifically, the third inverting unit 310 may include a 22nd transistor M22 and a 23rd transistor M23 with different channel types; the gates of both the 22nd transistor M22 and the 23rd transistor M23 are connected to the first node Q; the first terminal of the 22nd transistor M22 is connected to a first level signal VGH; the first terminal of the 23rd transistor M23 is connected to a second level signal VGL; and the second terminals of both the 22nd transistor M22 and the 23rd transistor M23 are connected to the output terminal of the second output module 30. For example, the 22nd transistor M22 is a P-type transistor, and the 23rd transistor M23 is an N-type transistor.

[0121] Figure 8 This is a schematic diagram of another second output module provided in an embodiment of the present invention. See also... Figure 8 In another embodiment, the second output module 30 may optionally include a third output unit 330 and a fourth output unit 340.

[0122] The third output unit 330 has its control terminal connected to the first node Q, its input terminal connected to the first level signal VGH, and its output terminal connected to the output terminal of the second output module 30. The third output unit 330 controls whether to output the first level signal VGH as the third gate drive signal NOUT based on the level of its control terminal. The fourth output unit 340 has its control terminal connected to the second node QB, its input terminal connected to the second level signal VGL, and its output terminal connected to the output terminal of the second output module 30. The fourth output unit 340 controls whether to output the second level signal VGL as the third gate drive signal NOUT based on the level of its control terminal.

[0123] Figure 9 This is a schematic diagram of another second output module provided in an embodiment of the present invention. See also... Figure 9 Based on the above embodiments, optionally, the third output unit 330 includes: a sixth transistor M6 and a second capacitor C2; the gate of the sixth transistor M6 is connected to the control terminal of the third output unit 330, the first terminal of the sixth transistor M6 is connected to a first level signal VGH, and the second terminal of the sixth transistor M6 is connected to the output terminal of the third output unit 330; the second capacitor C2 is connected between the gate and the first terminal of the sixth transistor M6. The sixth transistor M6 is used to turn on or off according to its gate level, and the second capacitor C2 serves as a storage capacitor to maintain the gate level of the sixth transistor M6.

[0124] The fourth output unit 340 includes a seventh transistor M7. The gate of the seventh transistor M7 is connected to the control terminal of the fourth output unit 340, the first terminal of the seventh transistor M7 is connected to a second-level signal VGL, and the second terminal of the seventh transistor M7 is connected to the output terminal of the fourth output unit 340. The seventh transistor M7 is used to turn on or off according to its gate level. For example, the sixth transistor M6 and the seventh transistor M7 have the same channel type, such as both being P-type transistors.

[0125] See also Figure 9 Optionally, based on the above embodiments, the second output module 30 further includes a potential control unit 320. The potential control unit 320 is connected to the control terminals of the first node Q, the second node QB, and the fourth output unit 340, and is connected to a first level signal VGH and a third level signal VGL2. The potential control unit 340 is used to transmit the first level signal VGH to the control terminal of the fourth output unit 340 when the level of the second node QB is at the first level, and to transmit the third level signal VGL2 to the control terminal of the fourth output unit 340 when the level of the second node QB is at the second level.

[0126] In this embodiment, the on-state level of the fourth output unit 340 is lower than its off-state level; in other words, the seventh transistor M7 is a P-type transistor. The first level signal VGH has a first level, the second level signal VGL has a second level, and the levels of the first level, the second level, and the third level signal VGL2 decrease sequentially. This configuration in this embodiment is primarily to provide a third level signal VGL2, which is lower than the second level signal VGL, to the control terminal of the fourth output unit 340 when it is necessary to control the fourth output unit 340 to be on. This ensures that the voltage difference between the gate and the first electrode of the seventh transistor M7 is negative, thereby guaranteeing that the seventh transistor M7 can be fully turned on, thus outputting the second level signal VGL without loss.

[0127] Figure 10 This is a schematic diagram of another second output module provided in an embodiment of the present invention. See also... Figure 10Specifically, the potential control unit 320 includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11; the first terminal of the eighth transistor M8 and the first terminal of the ninth transistor M9 are both connected to a first level signal VGH, the gate of the eighth transistor M8 is connected to the second node QB, and the gate of the ninth transistor M9 is connected to the first node Q; the second terminal of the eighth transistor M8 is connected to the second terminal of the tenth transistor M10 and the gate of the eleventh transistor M11, respectively; the second terminal of the ninth transistor M9 is connected to the second terminal of the eleventh transistor M11, the gate of the tenth transistor M10, and the control terminal of the fourth output unit 340, respectively; the first terminals of the tenth transistor M10 and the eleventh transistor M11 are both connected to a third level signal VGL2.

[0128] Among them, the eighth transistor M8 and the ninth transistor M9 have the same channel type, the eighth transistor M8 and the tenth transistor M10 have different channel types, and the tenth transistor M10 and the eleventh transistor M11 have the same channel type. For example, the eighth transistor M8 and the ninth transistor M9 are both P-type transistors, and the tenth transistor M10 and the eleventh transistor M11 are both N-type transistors.

[0129] This embodiment is equivalent to using four transistors to form a level conversion circuit structure, which can stably provide the third level signal VGL2 to the control terminal of the fourth output unit 340. It does not require a charge pump circuit, and does not require the level transition of the clock signal coupled by a capacitor to provide an extremely low level to the control terminal of the fourth output unit 340. This can avoid level fluctuations at the control terminal of the fourth output unit 340 caused by capacitive coupling, and improve the output stability of the fourth output unit 340.

[0130] Figure 11 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 11 The paper presents a complete circuit structure for a gate drive circuit, for example, using... Figure 4 The input module shown Figure 6 The first output module shown and Figure 10 The second output module shown is configured as follows. To easily distinguish the two first output modules, a "-1" suffix is ​​added to the reference numerals of each component in the first first output module 201, and a "-2" suffix is ​​added to the reference numerals of each component in the second first output module 202. The driving timing of this gate drive circuit can still be found in [reference needed]. Figure 2 The working process of each module has been explained in the above embodiments, and the driving timing of the gate driving circuit will not be described in detail here.

[0131] The above embodiments exemplify the structure and operation of a composite gate drive circuit capable of providing three gate drive signals. In the above circuit structure, the frequency of each gate drive signal output by the gate drive circuit is the same as the frequency of the input signal GIN. Based on the above embodiments, by making some modifications / additions to the structure of the first output module and the second output module, the gate drive circuit can also support partitioned multi-frequency drive function. By adding a frequency control signal, the frequency of each gate drive signal can be controlled, and the frequency of any gate drive signal can be controlled to be equal to or lower than the frequency of the input signal GIN as needed.

[0132] The structure of each output module supporting the multi-frequency drive function is described below. It is understood that the structure and operation of input module 10 remain unchanged.

[0133] Figure 12 This is a schematic diagram of another first output module provided in an embodiment of the present invention. See also... Figure 12 In one embodiment, optionally, in addition to having a first output unit 210 and a second output unit 220, the first output module 20 further includes a first transmission control unit 240. The first transmission control unit 240 is connected between the first node Q and the control terminal of the first output unit 210, and is connected to a first level signal VGH, a first frequency control signal SW1, and a second frequency control signal SW2.

[0134] Specifically, the first transmission control unit 240 is configured to, when controlling the connection between the first node Q and the control terminal of the first output unit 210 in response to the first frequency control signal SW1, not transmit the first level signal VGH to the control terminal of the first output unit 210 in response to the second frequency control signal SW2, so that the first output unit 210 can be turned on or off according to the level of the first node Q. Furthermore, the first transmission control unit 240 is also configured to, when controlling the connection between the first node Q and the control terminal of the first output unit 210 in response to the first frequency control signal SW1, transmit the first level signal VGH to the control terminal of the first output unit 210 in response to the second frequency control signal SW2, so that the first output unit 210 is turned off in response to the first level signal VGH; wherein the level of the first level signal VGH is the cutoff level of the first output unit 210.

[0135] Therefore, during the pulse phase of the first node Q, if the first transmission unit 240 controls the first node Q to connect with the control terminal of the first output unit 210, the first output unit 210 can normally output its input clock signal, resulting in a pulse in the gate drive signal output by the first output module 20. During the pulse phase of the first node Q, if the first transmission unit 240 controls the first node Q to disconnect from the control terminal of the first output unit 210, the first output unit 210 remains off, resulting in no pulse in the gate drive signal output by the first output module 20. Based on this, if the first output unit 210 can normally output its input clock signal during each pulse phase of the first node Q, the frequency of the obtained gate drive signal is consistent with the frequency of the input signal GIN; if the first output unit 210 cannot output its input clock signal during at least some pulse phases of the first node Q, the frequency of the obtained gate drive signal is less than the frequency of the input signal GIN.

[0136] See also Figure 12 Based on the above embodiments, optionally, the first transmission control unit 240 includes: a first transmission subunit 241 and a second transmission subunit 242. The first transmission subunit 241 is connected between the first node Q and the control terminal of the first output unit 210, and the control terminal of the first transmission subunit 241 is connected to a first frequency control signal SW1. The second transmission subunit 242 is connected to the control terminal of the first output unit 210 and is connected to a first level signal VGH and a second frequency control signal SW2.

[0137] The first transmission subunit 241 controls whether the first node Q and the control terminal of the first output unit 210 are connected according to the first frequency control signal SW1. The second transmission subunit 242 controls whether the first level signal VGH is transmitted to the control terminal of the first output unit 210 according to the second frequency control signal SW2. The first transmission subunit 241 and the second transmission subunit 242 will not be turned on at the same time to avoid level competition at the control terminal of the first output unit 210. For example, the on / off states of the first transmission subunit 241 and the second transmission subunit 242 are opposite.

[0138] Based on the above embodiments, optionally, by controlling the first frequency control signal SW1 to maintain the on level of the first transmission subunit 241 in each display frame, and the second frequency control signal SW2 to maintain the off level of the second transmission subunit 242 in each display frame, the frequency of the output signal of the first output module 20 can be made the same as the frequency of the voltage of the first node Q, that is, the same as the frequency of the input signal GIN. By controlling the first frequency control signal SW1 to jump to the off level of the first transmission subunit 241 before the level of the first node Q jumps to the on level of the first output unit 210 (that is, before the pulse phase of the first node Q) in at least some display frames, and the second frequency control signal SW2 to jump to the on level of the second transmission subunit 242 before the level of the first node Q jumps to the on level of the first output unit 241, the frequency of the output signal of the first output module 20 is lower than the frequency of the voltage of the first node Q, that is, lower than the frequency of the input signal GIN.

[0139] Understandably, in each display frame, before the pulse phase of the first node Q begins, it is necessary to determine whether the first output module 20 needs to output the input clock signal, and accordingly control the level of the first frequency control signal SW1 and the second frequency control signal SW2. After that, the first frequency control signal SW1 and the second frequency control signal SW2 need to maintain a constant level until the pulse phases of the second clock signal CK2 and the third clock signal CK3 in the pulse phase of the first node Q are completed, so as to ensure that the first output module 20 can fully output / not output the pulse of the input clock signal in the display frame.

[0140] See also Figure 12 Based on the above embodiments, optionally, the first transmission subunit 241 includes: a fourth transistor M4; the fourth transistor M4 is connected between the first node Q and the control terminal of the first output unit 210, and the gate of the fourth transistor M4 is connected to a first frequency control signal SW1. The fourth transistor M4 is used to turn on or off according to the first frequency control signal SW1.

[0141] The second transmission subunit 242 includes a fifth transistor M5; the gate of the fifth transistor M5 is connected to a second frequency control signal SW2, the first terminal of the fifth transistor M5 is connected to a first level signal VGH, and the second terminal of the fifth transistor M5 is connected to the control terminal of the first output unit 210. The fifth transistor M5 is used to turn on or off according to the second frequency control signal SW2.

[0142] For example, the fourth transistor M4 and the fifth transistor M5 have the same channel type, and the first frequency control signal SW1 and the second frequency control signal SW2 are inverted signals. For instance, both the fourth transistor M4 and the fifth transistor M5 are P-type transistors.

[0143] Figure 13 This is a schematic diagram of another second output module provided in an embodiment of the present invention. See also... Figure 13 In one embodiment, based on the third output unit 330 and the fourth output unit 340, or further including the potential control unit 320, the second output module 30 also includes a second transmission control unit 350. The second transmission control unit 350 is connected to the control terminals of the first node Q, the second node QB, and the third output unit 330, and is connected to a first frequency control signal SW1. The second transmission control unit 350 is used to control whether the first node Q and the control terminal of the third output unit 330 are connected according to the level of the second node QB and the first frequency control signal SW1, thereby controlling whether the third output unit 30 can output a first level signal VGH to control whether there is a pulse in the third gate drive signal NOUT, thus realizing frequency control of the third gate drive signal NOUT.

[0144] See also Figure 13 In one embodiment, optionally, the second transmission control unit 350 includes a third transmission subunit 351 and a frequency control subunit 352. The third transmission subunit 351 is connected between the first node Q and the control terminal of the third output unit 330; the control terminal of the frequency control subunit 352 is connected to the second node QB, the input terminal of the frequency control subunit 352 is connected to the first frequency control signal SW1, and the output terminal of the frequency control subunit 352 is connected to the control terminal of the third transmission subunit 351.

[0145] In this configuration, when the frequency control subunit 352 responds to the on-state of the second node QB, it provides the first frequency control signal SW1 to the control terminal of the third transmission subunit 351. When the frequency control subunit 352 responds to the off-state of the second node QB, the control terminal of the third transmission subunit 351 can maintain the level before the frequency control subunit 352 was turned off. The third transmission subunit 351 is used to turn on or off according to the level of its control terminal. When the third transmission subunit 351 is on, the control terminal of the first node Q and the third output unit 330 are connected, and the third output unit 330 can turn on or off according to the level of the first node Q. When the third transmission subunit 351 is off, the control terminal of the first node Q and the third output unit 330 are disconnected, and the control terminal of the third output unit 330 maintains the level before the third transmission subunit 351 was turned off.

[0146] In this configuration, the frequency control subunit 352 is turned off during the pulse phase of the first node Q and turned on during other periods. Therefore, in any display frame, before the pulse phase of the first node Q begins, the first frequency control signal SW1 needs to be controlled to change to the required level so that when the frequency control subunit 352 is turned on, this level can be transmitted to the control terminal of the third transmission subunit 351, ensuring that the third transmission subunit 351 can be correctly controlled during the pulse phase of the first node Q. It is understood that if the third transmission subunit 351 remains off during the pulse phase of the first node Q, the pulse level of the first node Q cannot be transmitted to the control terminal of the third output unit 330. Therefore, the third output unit 330 cannot be turned on during the pulse phase of the first node Q and cannot output the first level signal VGH. This results in no pulse for the third gate drive signal NOUT in the display frame, making the frequency of the third gate drive signal NOUT lower than the frequency of the input signal GIN.

[0147] Specifically, by controlling the first frequency control signal SW1 to maintain the on level of the third transmission subunit 330 in each display frame, the frequency of the output signal of the second output module 30 can be made the same as the frequency of the voltage of the first node Q, that is, the same as the frequency of the input signal GIN. By controlling the first frequency control signal SW1 to jump to the off level of the third transmission subunit 330 before the level of the first node Q jumps to the on level of the first output unit (that is, before the pulse phase of the first node Q begins) in at least some display frames, the frequency of the output signal of the second output module is made lower than the frequency of the voltage of the first node Q, that is, lower than the frequency of the input signal GIN.

[0148] See also Figure 13 Based on the above embodiments, optionally, the third transmission subunit 351 includes a twelfth transistor M12, which is connected between the first node Q and the control terminal of the third output unit 330, and the gate of the twelfth transistor M12 is connected to the output terminal of the frequency control subunit 352. The twelfth transistor M12 is used to turn on or off according to its gate level.

[0149] The frequency control subunit 352 includes a thirteenth transistor M13; the gate of the thirteenth transistor M13 is connected to the second node QB, the first terminal of the thirteenth transistor M13 is connected to the first frequency control signal SW1, and the second terminal of the thirteenth transistor M13 is connected to the output terminal of the frequency control subunit 352. The thirteenth transistor M13 is used to turn on or off according to its gate level.

[0150] For example, both the twelfth transistor M12 and the thirteenth transistor M13 are P-type transistors.

[0151] Optionally, based on the above embodiments, the second transmission control unit 350 further includes a storage subunit 353. The storage subunit 353 is connected to the control terminal of the third transmission subunit 351 and is used to maintain the voltage level of the third transmission subunit 351.

[0152] Specifically, the third transmission subunit 351 includes a third capacitor C3; one end of the third capacitor C3 is connected to the control terminal of the third transmission subunit 351, and the other end of the third capacitor C3 is connected to a DC signal VD. For example, the first level signal VGH or the second level signal VGL can be multiplexed into a DC signal VD to simplify the wiring of the display panel.

[0153] Based on the above embodiments, optionally, the level of the DC signal VD can be set to be different from the cutoff level of the third transmission subunit 351. In this way, during the period when the third transmission subunit 351 is turned off, a voltage difference exists across the third capacitor C3, resulting in better level maintenance compared to the case where the levels on both sides of the third capacitor C3 are the same. For example, the twelfth transistor M12 is a P-type transistor, which can multiplex the second level signal VGL into the DC signal VD.

[0154] Based on the above embodiments, please continue to refer to Figure 13 In one embodiment, optionally, the second transmission control unit 350 may also include an output subunit 354. The control terminal of the output subunit 354 is connected to the control terminal of the third transmission subunit 351, the input terminal of the output subunit 354 is connected to the second level signal VGL, and the output terminal of the output subunit 354 is connected to the output terminal of the third output unit 330. The conduction level of the output subunit 354 is different from that of the third transmission subunit 351. Therefore, when the third transmission subunit 351 is off, the output subunit 354 is on, forcibly controlling the third gate drive signal NOUT to be the second level signal VGL, ensuring that the third gate drive signal NOUT has no pulses; when the third transmission subunit 351 is on, the output subunit 354 is off, avoiding level conflicts at the output terminal of the third output unit 330.

[0155] Furthermore, the output sub-unit 354 includes a fourteenth transistor M14; the gate of the fourteenth transistor M14 is connected to the control terminal of the third transmission sub-unit 351, the first terminal of the fourteenth transistor M14 is connected to the second level signal VGL, and the output terminal of the fourteenth transistor M14 is connected to the output terminal of the third output unit 330. The fourteenth transistor M14 has a different channel type than the twelfth transistor M12; for example, the twelfth transistor M12 is a P-type transistor, and the fourteenth transistor M14 is an N-type transistor.

[0156] Figure 14This is a schematic diagram of another second output module provided in an embodiment of the present invention. See also... Figure 14 In another embodiment, optionally, the second transmission control unit 350 may also include a level control subunit 355. The control terminal of the level control subunit 355 is connected to the second node QB, the input terminal of the level control subunit 355 is connected to the first level signal VGH, and the output terminal of the level control subunit 355 is connected to the control terminal of the third output unit 330. The level of the first level signal VGH is the cutoff level of the third control subunit 330. The conduction level of the level control subunit 355 is the same as the conduction level of the frequency control subunit 352. This configuration allows the level control subunit 355 to be turned on outside the pulse phase of the first node Q, transmitting the first level signal VGH to the control terminal of the third output unit 330, thereby reliably turning off the third output unit 330 outside the pulse phase of the first node Q and preventing erroneous output. Furthermore, when the third transmission subunit 351 is turned off, since the level control subunit 355 has already transmitted the first level signal VGH to the control terminal of the third output unit 330 before the pulse phase of the first node Q begins, it can be ensured that the level of the first level signal VGH can be maintained when the control terminal of the third output unit 330 is floating during the pulse phase of the first node Q, thereby enabling the third output unit 330 to be reliably turned off and realizing the correct control of the frequency of the third gate drive signal NOUT.

[0157] Furthermore, the level control subunit 355 includes: a fifteenth transistor M15; the gate of the fifteenth transistor M15 is connected to the second node QB, the first terminal of the fifteenth transistor M15 is connected to the first level signal VGH, and the second terminal of the fifteenth transistor M15 is connected to the control terminal of the third output unit 330. The fifteenth transistor M15 and the thirteenth transistor M13 have the same channel type, for example, both are P-type transistors.

[0158] Figure 15 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 15 The paper presents a complete circuit structure for a gate drive circuit, for example, using... Figure 4 The input module shown Figure 12 The first output module 20 shown and Figure 13 The second output module 30 shown is configured as follows. To easily distinguish the two first output modules, a "-1" suffix is ​​added to the reference numerals of each component in the first first output module 201, and a "-2" suffix is ​​added to the reference numerals of each component in the second first output module 202. The driving timing of this gate drive circuit, under normal gate drive signal output pulse conditions, can be found in [reference needed]. Figure 16In this circuit, the first frequency control signal SW1 remains low, and the second frequency control signal SW2 remains high. When none of the gate drive signals output pulses, the driving timing of this gate drive circuit can be found in [reference needed]. Figure 17 Specifically, before the start of the pulse phase T0 of the voltage at the first node Q (i.e., one pulse cycle of the first clock signal CK1 containing the pulse of the input signal GIN), the first frequency control signal SW1 jumps to a high level, and the second frequency control signal SW2 jumps to a low level. This continues until the pulse phases of the second clock signal CK2 and the third clock signal CK3 have both ended in T0, at which point the first frequency control signal SW1 can jump to a low level, and the second frequency control signal SW2 can jump to a high level. The working process of each module has been explained in the above embodiments; therefore, the driving timing of the gate drive circuit will not be elaborated upon further here.

[0159] It should be noted that any of the above transistors can be MOS transistors, P-type transistors can be PMOS transistors, and N-type transistors can be NMOS transistors. Thus, the embodiments of the present invention are equivalent to providing a composite gate drive circuit based on CMOS technology, and a circuit structure that supports multi-frequency partitioning can be selected according to actual needs.

[0160] This invention also provides a display panel, including: the gate driving circuit provided in any embodiment of this invention, which has corresponding beneficial effects.

[0161] Figure 18 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also... Figure 18 The display panel may include cascaded multi-stage gate drive circuits 100; the display panel also includes a start signal line LS.

[0162] Specifically, the display panel may include a display area AA and a non-display area NAA surrounding the display area AA. Each gate driving circuit 100 may be disposed in the non-display area NAA, and a pixel circuit (not shown in the figure) may be disposed in the display area AA. The gate driving circuit 100 may be used to provide various gate driving signals to the pixel circuit, such as providing a first gate driving signal POUT1, a second gate driving signal POUT2, and a third gate driving signal NOUT. Among them, the start signal line LS is connected to the first-stage gate driving circuit 100, providing the first-stage gate driving circuit 100 with an input signal GIN; the first node Q of each stage gate driving circuit 100 is connected to the next stage gate driving circuit 100, providing the next stage gate driving circuit 100 with an input signal GIN.

[0163] Figure 19 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. See also... Figure 19Based on the above embodiments, optionally, the first output module of the gate driving circuit includes a first transmission control unit, and the second output module includes a second transmission control unit. The display panel also includes a first frequency control signal line LSW1 and a second frequency control signal line LSW2, both of which are connected to each gate driving circuit 100. The first frequency control signal line LSW1 is used to transmit a first frequency control signal SW1 to the first transmission control unit in each gate driving circuit 100, and the second frequency control signal line LSW2 is used to provide a second frequency control signal SW2 to the first transmission control unit in each gate driving circuit 100.

[0164] Based on the above embodiments, optionally, the display panel may further include multiple clock signal lines, for example, six clock signal lines, wherein three clock signal lines are used to provide the required first clock signal, second clock signal, and third clock signal to the odd-numbered gate driving circuit 100, and the other three clock signal lines are used to provide the required first clock signal, second clock signal, and third clock signal to the even-numbered gate driving circuit 100; wherein the waveform of the first clock signal required by the odd-numbered gate driving circuit 100 may overlap with the waveform of the third clock signal required by the even-numbered gate driving circuit 100. See details [link to documentation]. Figure 20 and Figure 21 The odd-numbered gate driving circuit 100 provides the required first clock signal, second clock signal, and third clock signal, denoted as CK1-1, CK2-1, and CK3-1, respectively. The even-numbered gate driving circuit 100 provides the required first clock signal, second clock signal, and third clock signal, denoted as CK1-2, CK2-2, and CK3-2, respectively. By setting the first clock signal CK1-1 required by the odd-numbered gate driving circuit 100 to be consistent with the third clock signal CK3-2 required by the even-numbered gate driving circuit 100, and the third clock signal CK3-1 required by the odd-numbered gate driving circuit 100 to be consistent with the first clock signal CK1-2 required by the even-numbered gate driving circuit 100, the step-by-step transmission relationship of the pulses of each gate driving signal can be guaranteed.

[0165] Furthermore, the first clock signal CK1-1 required by the odd-numbered gate driving circuit 100 and the third clock signal CK3-2 required by the even-numbered gate driving circuit 100 can be transmitted using the same clock signal line, and the third clock signal CK3-1 required by the odd-numbered gate driving circuit 100 and the first clock signal CK1-2 required by the even-numbered gate driving circuit 100 can be transmitted using the same clock signal line. In this way, only four clock signal lines are required, which can simplify the wiring of the display panel. For example, the display panel includes: a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; the first, second, and third clock signal lines are all connected to odd-level gate driving circuits, and provide a first clock signal CK1-1, a second clock signal CK2-1, and a third clock signal CK3-1 to the odd-level gate driving circuits, respectively; the third, fourth, and first clock signal lines are all connected to even-level gate driving circuits, and provide a first clock signal CK1-2, a second clock signal CK2-2, and a third clock signal CK3-3 to the even-level gate driving circuits, respectively. The clock signals transmitted in the first, second, third, and fourth clock signal lines have the same waveform, the initial pulses do not overlap in time and appear sequentially, and the second pulse of the clock signal transmitted by the first clock signal line is located after the initial pulse of the clock signal transmitted by the fourth clock signal line.

[0166] Figure 20 and Figure 21 The example provides the output signals of a four-stage gate drive circuit 100, where the first gate drive signal of the k-th stage is denoted as POUT1-k, the second gate drive signal of the k-th stage is denoted as POUT2-k, and the third gate drive signal of the k-th stage is denoted as NOUT-k, where 1 ≤ k ≤ 4. It is understood that... Figure 20 and Figure 21 In this context, GIN represents the input signal of the first-stage gate drive circuit.

[0167] When the display panel is showing the image at a uniform refresh rate across the entire screen, the first frequency signal SW1 and the second frequency signal SW2 maintain a constant level in each display frame. (See also...) Figure 20 The display frame shown has the first frequency signal SW1 kept at a low level, the second frequency signal SW2 kept at a high level, and each stage of the gate drive signal has a pulse. The frequency of each stage of the gate drive signal is consistent with the frequency of the first stage input signal GIN.

[0168] When the display panel displays in at least two display zones with different refresh rates, both the first frequency signal SW1 and the second frequency signal SW2 undergo level transitions in at least a portion of the display frames. See also Figure 21In the displayed frame, the first frequency signal SW1 and the second frequency signal SW2 undergo a potential transition before the pulse phase of the first node Q of the second-stage gate drive circuit begins, resulting in no pulses in the gate drive signal starting from the second-stage gate drive circuit. Furthermore, the first frequency signal SW1 and the second frequency signal SW2 undergo another potential transition before the pulse phase of the first node Q of the fourth-stage gate drive circuit begins, restoring output pulses in the gate drive signal starting from the fourth-stage gate drive circuit. This ensures that at least some of the gate drive circuits output gate drive signals with different frequencies, enabling multi-frequency zoned display along the column direction of the display panel.

[0169] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0170] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, include: An input module includes a first node, the input module being used to control the level of the first node according to a first clock signal and an input signal; Both first output modules are connected to the first node; the first input terminals of the two first output modules are respectively connected to the second clock signal and the third clock signal, and the second input terminals of the two first output modules are both connected to the first level signal. The first output module is used to output a signal connected to its first input terminal or second input terminal according to the level of the first node; wherein, the pulse levels of the second clock signal and the third clock signal are the same, and the pulses of the third clock signal and the second clock signal do not overlap in time; the level of the first level signal is different from the pulse level of the second clock signal. The second output module is connected to the first node and receives the first level signal and the second level signal; the second output module is used to output the first level signal when the first output module outputs the signal received at its first input terminal, and to output the second level signal when the first output module outputs the signal received at its second input terminal; wherein, the level of the second level signal is the same as the level of the pulse of the second clock signal.

2. The gate driving circuit according to claim 1, characterized in that, The input module further includes: a second node; the input module is also used to control the level of the second node to be inversely related to the level of the first node; the first output module includes: The first output unit has its control terminal connected to the first node, its input terminal connected to the first input terminal of the first output module, and its output terminal connected to the output terminal of the first output module. The first output unit is used to turn on or off according to the level of its control terminal. The second output unit has its control terminal connected to the second node, its input terminal connected to the second input terminal of the first output module, and its output terminal connected to the output terminal of the first output module. The second output unit is used to turn on or off according to the level of its control terminal. Preferably, the first output unit includes: a first transistor and a first capacitor; the gate of the first transistor is connected to the control terminal of the first output unit, the first electrode of the first transistor is connected to the input terminal of the first output unit, and the second electrode of the first transistor is connected to the output terminal of the first output unit; the first capacitor is connected between the gate and the second electrode of the first transistor. The second output unit includes: a second transistor, the gate of the second transistor being connected to the control terminal of the second output unit, the first terminal of the second transistor being connected to the input terminal of the second output unit, and the second terminal of the second transistor being connected to the output terminal of the second output unit; the first transistor and the second transistor have the same channel type.

3. The gate driving circuit according to claim 2, characterized in that, The first output module further includes: a transmission protection unit, connected between the first node and the control terminal of the first output unit, and connected to the second level signal; Preferably, the transmission protection unit includes a third transistor connected between the first node and the control terminal of the first output unit, and the gate of the third transistor is connected to the second level signal.

4. The gate driving circuit according to claim 2, characterized in that, The first output module further includes: a first transmission control unit, connected between the first node and the control terminal of the first output unit, and connected to the first level signal, the first frequency control signal, and the second frequency control signal; the first transmission control unit is configured to, when responding to the first frequency control signal to control the connection between the first node and the control terminal of the first output unit, not transmit the first level signal to the control terminal of the first output unit in response to the second frequency control signal, and when responding to the first frequency control signal to control the disconnection between the first node and the control terminal of the first output unit, transmit the first level signal to the control terminal of the first output unit in response to the second frequency control signal, so that the first output unit turns off in response to the first level signal; Preferably, the first transmission control unit includes: The first transmission subunit is connected between the control terminal of the first node and the first output unit, and the control terminal of the first transmission subunit is connected to the first frequency control signal. The second transmission subunit is connected to the control terminal of the first output unit and is connected to the first level signal and the second frequency control signal. It is used to control whether to transmit the first level signal to the control terminal of the first output unit according to the second frequency control signal. Preferably, the first frequency control signal maintains the on level of the first transmission subunit in each display frame, and the second frequency control signal maintains the off level of the second transmission subunit in each display frame, so that the frequency of the output signal of the first output module is the same as the frequency of the voltage of the first node. Alternatively, in at least a partial display frame, the first frequency control signal jumps to the cutoff level of the first transmission subunit before the level of the first node jumps to the on level of the first output unit, and the second frequency control signal jumps to the on level of the second transmission subunit before the level of the first node jumps to the on level of the first output unit, such that the frequency of the output signal of the first output module is lower than the frequency of the voltage of the first node. Preferably, the first transmission subunit includes a fourth transistor; the fourth transistor is connected between the control terminal of the first node and the first output unit, and the gate of the fourth transistor is connected to the first frequency control signal; The second transmission sub-unit includes: a fifth transistor; the gate of the fifth transistor is connected to the second frequency control signal, the first terminal of the fifth transistor is connected to the first level signal, and the second terminal of the fifth transistor is connected to the control terminal of the first output unit; Preferably, the fourth transistor and the fifth transistor have the same channel type, and the first frequency control signal and the second frequency control signal are inverted signals.

5. The gate driving circuit according to claim 1, characterized in that, The input module further includes: a second node; the input module is also used to control the level of the second node to be inversely related to the level of the first node; the second output module includes: The third output unit has its control terminal connected to the first node, its input terminal connected to the first level signal, and its output terminal connected to the output terminal of the second output module. The third output unit is used to turn on or off according to the level of its control terminal. The fourth output unit has its control terminal connected to the second node, its input terminal connected to the second level signal, and its output terminal connected to the output terminal of the second output module. The fourth output unit is used to turn on or off according to the level of its control terminal. Preferably, the third output unit includes: a sixth transistor and a second capacitor; the gate of the sixth transistor is connected to the control terminal of the third output unit, the first terminal of the sixth transistor is connected to the first level signal, and the second terminal of the sixth transistor is connected to the output terminal of the third output unit; the second capacitor is connected between the gate and the first terminal of the sixth transistor. The fourth output unit includes: a seventh transistor; the gate of the seventh transistor is connected to the control terminal of the fourth output unit, the first terminal of the seventh transistor is connected to the second level signal, and the second terminal of the seventh transistor is connected to the output terminal of the fourth output unit; the sixth transistor has the same channel type as the seventh transistor.

6. The gate driving circuit according to claim 5, characterized in that, The second output module also includes: A potential control unit is connected to the control terminals of the first node, the second node, and the fourth output unit, respectively, and receives a first level signal and a third level signal. The potential control unit is used to transmit the first level signal to the control terminal of the fourth output unit when the level of the second node is at the first level, and to transmit the third level signal to the control terminal of the fourth output unit when the level of the second node is at the second level. The first level signal has the first level, the second level signal has the second level, and the levels of the first level, the second level, and the third level signal decrease sequentially. Preferably, the potential control unit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the first terminals of the eighth transistor and the ninth transistor are both connected to the first level signal; the gate of the eighth transistor is connected to the second node; the gate of the ninth transistor is connected to the first node; the second terminal of the eighth transistor is connected to the second terminal of the tenth transistor and the gate of the eleventh transistor; the second terminal of the ninth transistor is connected to the second terminal of the eleventh transistor, the gate of the tenth transistor, and the control terminal of the fourth output unit; the first terminals of the tenth transistor and the eleventh transistor are both connected to the third level signal; the eighth transistor and the ninth transistor have the same channel type; the eighth transistor and the tenth transistor have different channel types; and the tenth transistor and the eleventh transistor have the same channel type.

7. The gate driving circuit according to claim 5 or 6, characterized in that, The second output module further includes: a second transmission control unit, which is connected to the control terminals of the first node, the second node, and the third output unit respectively, and is connected to a first frequency control signal; the second transmission control unit is used to control whether the control terminals of the first node and the third output unit are connected according to the level of the second node and the first frequency control signal. Preferably, the second transmission control unit includes: The third transmission subunit is connected between the first node and the control terminal of the third output unit; A frequency control subunit, wherein the control terminal of the frequency control subunit is connected to the second node, the input terminal of the frequency control subunit is connected to the first frequency control signal, and the output terminal of the frequency control subunit is connected to the control terminal of the third transmission subunit; Preferably, the first frequency control signal maintains the on level of the third transmission subunit in each display frame, so that the frequency of the output signal of the second output module is the same as the frequency of the voltage of the first node; Alternatively, in at least a partial display frame, the first frequency control signal jumps to the cutoff level of the third transmission subunit before the level of the first node jumps to the on level of the first output unit, so that the frequency of the output signal of the second output module is lower than the frequency of the voltage of the first node. Preferably, the third transmission subunit includes: a twelfth transistor connected between the first node and the control terminal of the third output unit, and the gate of the twelfth transistor is connected to the output terminal of the frequency control subunit; The frequency control subunit includes: a thirteenth transistor; the gate of the thirteenth transistor is connected to the second node, the first terminal of the thirteenth transistor is connected to the first frequency control signal, and the second terminal of the thirteenth transistor is connected to the output terminal of the frequency control subunit; Preferably, the second transmission control unit further includes: a storage subunit, including a third capacitor; one end of the third capacitor is connected to the control terminal of the third transmission subunit, and the other end of the third capacitor is connected to a DC signal; Preferably, the first level signal or the second level signal is multiplexed into the DC signal; Preferably, the level of the DC signal is different from the cutoff level of the third transmission subunit; Preferably, the second transmission control unit further includes one of an output subunit and a level control subunit; the control terminal of the output subunit is connected to the control terminal of the third transmission subunit, the input terminal of the output subunit is connected to the second level signal, and the output terminal of the output subunit is connected to the output terminal of the third output unit; the conduction level of the output subunit is different from the conduction level of the third transmission subunit; the control terminal of the level control subunit is connected to the second node, the input terminal of the level control subunit is connected to the first level signal, and the output terminal of the level control subunit is connected to the control terminal of the third output unit; wherein, the level of the first level signal is the cutoff level of the third control subunit; Preferably, the output sub-unit includes: a fourteenth transistor; the gate of the fourteenth transistor is connected to the control terminal of the third transmission sub-unit, the first terminal of the fourteenth transistor is connected to the second level signal, and the output terminal of the fourteenth transistor is connected to the output terminal of the third output unit; The level control subunit includes: a fifteenth transistor; the gate of the fifteenth transistor is connected to the second node, the first terminal of the fifteenth transistor is connected to the first level signal, and the second terminal of the fifteenth transistor is connected to the control terminal of the third output unit.

8. The gate driving circuit according to claim 1, characterized in that, The input module includes: An input unit is connected to the input signal and the first clock signal respectively; the input unit is used to control whether to output the input signal according to the first clock signal. The first inverting unit is connected to the output terminal of the input unit; the first inverting unit is used to invert the level of the output terminal of the input unit and then output it. The second inverting unit is connected to the output terminal of the first inverting unit and the first node, respectively; the second inverting unit is used to invert the level output by the first inverting unit and provide it to the first node; A switching unit is connected between the output terminal of the input unit and the first node, and is connected to the first clock signal; the switching unit is used to turn on or off according to the first clock signal; the on-state level of the switching unit is different from the on-state level of the input unit; Preferably, the input unit includes a sixteenth transistor; the gate of the sixteenth transistor is connected to the first clock signal, the first terminal of the sixteenth transistor is connected to the input signal, and the second terminal of the sixteenth transistor is connected to the output terminal of the input unit; The first inverting unit includes a seventeenth transistor and an eighteenth transistor with different channel types; the gates of the seventeenth transistor and the eighteenth transistor are both connected to the output terminal of the input unit; the first terminal of the seventeenth transistor is connected to the first level signal, the first terminal of the eighteenth transistor is connected to the second level signal, and the second terminals of the seventeenth transistor and the eighteenth transistor are both connected to the output terminal of the first inverting unit. The second inverting unit includes a nineteenth transistor and a twentieth transistor with different channel types; the gates of the nineteenth transistor and the twentieth transistor are both connected to the output terminal of the first inverting unit; the first terminal of the nineteenth transistor is connected to the first level signal, the first terminal of the twentieth transistor is connected to the second level signal, and the second terminals of the nineteenth transistor and the twentieth transistor are both connected to the first node; The switching unit includes: a twenty-first transistor connected between the output terminal of the input unit and the first node, and the gate of the twenty-first transistor is connected to the first clock signal; the sixteenth transistor has a different channel type than the twenty-first transistor. Preferably, the level of the first level signal is higher than the level of the second level signal; the sixteenth transistor, the seventeenth transistor, and the nineteenth transistor are all P-type transistors, and the eighteenth transistor, the twentieth transistor, and the twenty-first transistor are all N-type transistors; Preferably, the second output module includes: a third inverting unit; the input terminal of the third inverting unit is connected to the first node, and the output terminal of the third inverting unit is connected to the output terminal of the second output module.

9. A display panel, characterized in that, include: The gate drive circuit according to any one of claims 1-8.

10. The display panel according to claim 9, characterized in that, The display panel includes multiple cascaded gate drive circuits; the display panel also includes a start signal line; The start signal line is connected to the first-stage gate driving circuit to provide an input signal to the first-stage gate driving circuit; the first node of each stage of the gate driving circuit is connected to the next stage of the gate driving circuit to provide an input signal to the next stage of the gate driving circuit. Preferably, the first output module of the gate driving circuit includes a first transmission control unit, and the second output module includes a second transmission control unit; the display panel further includes a first frequency control signal line and a second frequency control signal line; the first frequency control signal line is used to transmit a first frequency control signal to the first transmission control unit and the first transmission control unit in each of the gate driving circuits, and the second frequency control signal line is used to provide a second frequency control signal to the first transmission control unit in each of the gate driving circuits; Preferably, when the display panel displays at a uniform refresh rate across the entire screen, the first frequency signal and the second frequency signal maintain a constant level in each display frame; When the display panel displays at least two display zones with different refresh rates, both the first frequency signal and the second frequency signal undergo level transitions in at least a portion of the display frames.

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