Gate driving circuit, gate driving module and display panel

Abstract

The application discloses a kind of gate drive circuit, gate drive module and display panel, belong to display technical field.Gate drive circuit includes: input module;Locking module is for according to the level output first power signal or second power signal of the output end of input module, and whether the output state of this locking module is controlled according to first clock signal whether locking;The voltage of first power signal is lower than the voltage of second power signal;Output module includes first output unit and second output unit;Second output unit accesses second power signal;First output unit includes first transistor, the output end of locking module is connected to the gate of first transistor, the first pole of first transistor accesses third power signal, and the second pole of first transistor is connected to signal output end;First transistor is N-type transistor, and the voltage of third power signal is lower than the voltage of first power signal.The application embodiment can improve the output stability of gate drive circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit, a gate driving module, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) displays and flat panel displays based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide application range, becoming the mainstream display devices. However, current display panels suffer from unstable output in the gate driving circuit, affecting the display effect. Summary of the Invention

[0003] This invention provides a gate driving circuit, a gate driving module, and a display panel to improve the output stability of the gate driving circuit, thereby improving the display effect of the display panel.

[0004] In a first aspect, embodiments of the present invention provide a gate driving circuit, comprising:

[0005] An input module is connected to the signal input terminal of the gate drive circuit and receives a first clock signal; the input module is used to control whether to output the signal received at the signal input terminal according to the first clock signal.

[0006] A latch module is connected to the output terminal of the input module and is respectively connected to the first clock signal, the first power signal, and the second power signal; the latch module is used to output the first power signal or the second power signal according to the level of the output terminal of the input module, and to control whether to latch the output state of the latch module according to the first clock signal; the voltage of the first power signal is lower than the voltage of the second power signal;

[0007] The output module includes a first output unit and a second output unit; the second output unit is connected to the output terminal of the latch module and the signal output terminal of the gate drive circuit, and is connected to the second power supply signal; the first output unit includes a first transistor, the gate of the first transistor is connected to the output terminal of the latch module, the first terminal of the first transistor is connected to the third power supply signal, and the second terminal of the first transistor is connected to the signal output terminal; the first transistor is an N-type transistor, and the voltage of the third power supply signal is lower than the voltage of the first power supply signal.

[0008] Optionally, the second output unit includes: a second transistor; the gate of the second transistor is connected to the output terminal of the latch module, the first terminal of the second transistor is connected to the second power supply signal, and the second terminal of the second transistor is connected to the signal output terminal; the second transistor is a P-type transistor;

[0009] Preferably, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

[0010] Optionally, the input module includes: a third transistor; the gate of the third transistor is connected to the first clock signal, the first terminal of the third transistor is connected to the signal input terminal, and the second terminal of the third transistor is connected to the output terminal of the input module;

[0011] Preferably, the input module further includes: a fourth transistor; the gate of the fourth transistor is connected to a second clock signal, the first terminal of the fourth transistor is connected to the signal input terminal, and the second terminal of the fourth transistor is connected to the output terminal of the input module; the third transistor has a different channel type from the fourth transistor, and the second clock signal is the inverted signal of the first clock signal;

[0012] Preferably, the third transistor is a PMOS transistor and the fourth transistor is an NMOS transistor.

[0013] Optionally, the latching module includes:

[0014] A first inverter, the control terminal of the first inverter is connected to the output terminal of the input module, the first input terminal of the first inverter is connected to the first power signal, the second input terminal of the first inverter is connected to the second power signal, and the output terminal of the first inverter is connected to the output terminal of the latch module.

[0015] The second inverter has its control terminal connected to the output terminal of the first inverter, its first input terminal connected to the first power signal, and its second input terminal connected to the second power signal.

[0016] A latch control unit is connected between the output terminal of the input module and the output terminal of the second inverter, and the control terminal of the latch control unit is connected to the first clock signal; the on / off states of the latch control unit and the input module are different.

[0017] Optionally, the first inverter includes a fifth transistor and a sixth transistor; the gates of the fifth transistor and the sixth transistor are both connected to the control terminal of the first inverter; the first terminal of the fifth transistor is connected to the first input terminal of the first inverter; the first terminal of the sixth transistor is connected to the second input terminal of the first inverter; the second terminals of the fifth transistor and the sixth transistor are both connected to the output terminal of the first inverter; the fifth transistor and the sixth transistor have different channel types.

[0018] The second inverter includes a seventh transistor and an eighth transistor; the gates of the seventh transistor and the eighth transistor are both connected to the control terminal of the second inverter; the first terminal of the seventh transistor is connected to the first input terminal of the second inverter; the first terminal of the eighth transistor is connected to the second input terminal of the second inverter; the second terminals of the seventh transistor and the eighth transistor are both connected to the output terminal of the second inverter; the seventh transistor and the eighth transistor have different channel types.

[0019] The latch control unit includes: a ninth transistor; the gate of the ninth transistor is connected to the first clock signal, the first terminal of the ninth transistor is connected to the output terminal of the input module, and the second terminal of the ninth transistor is connected to the output terminal of the second inverter;

[0020] Preferably, the input module includes: a third transistor; the gate of the third transistor is connected to the first clock signal, the first terminal of the third transistor is connected to the signal input terminal, and the second terminal of the third transistor is connected to the output terminal of the input module; the third transistor has a different channel type than the ninth transistor;

[0021] Preferably, the latch control unit further includes: a tenth transistor, the gate of the tenth transistor being connected to a second clock signal, the first terminal of the tenth transistor being connected to the output terminal of the input module, and the second terminal of the tenth transistor being connected to the output terminal of the second inverter; the ninth transistor and the tenth transistor have different channel types, and the second clock signal is the inverted signal of the first clock signal;

[0022] Preferably, the third transistor, the sixth transistor, the eighth transistor, and the tenth transistor are all PMOS transistors, and the fifth transistor, the seventh transistor, and the ninth transistor are all NMOS transistors.

[0023] Optionally, the gate drive circuit further includes: a reset module, connected to the output terminal of the latch module, and respectively connected to a reset control signal and a reset signal;

[0024] Preferably, the operation of the display panel where the gate driving circuit is located includes a power-on stage and a display stage; the reset module is used to transmit the reset signal to the output terminal of the latch module in response to the reset control signal in the power-on stage, and to stop transmitting the reset signal to the output terminal of the latch module in response to the reset control signal in the display stage.

[0025] Preferably, the effective level of the gate drive signal output by the signal output terminal is the same as the voltage of the third power supply signal, and the first power supply signal is multiplexed as the reset signal; or, the effective level of the gate drive signal output by the signal output terminal is the same as the voltage of the second power supply signal, and the second power supply signal is multiplexed as the reset signal; wherein, the effective level of the gate drive signal is the level at which the module connected to the gate drive signal is turned on.

[0026] Optionally, the reset module includes: an eleventh transistor, the gate of the eleventh transistor being connected to the reset control signal, the first terminal of the eleventh transistor being connected to the reset signal, and the second terminal of the eleventh transistor being connected to the output terminal of the latch module;

[0027] Preferably, the eleventh transistor is a PMOS transistor.

[0028] Secondly, embodiments of the present invention also provide a gate driving module, including: the gate driving circuit provided in any embodiment of the present invention.

[0029] Optionally, the gate driving module further includes: a start signal line; and the gate driving module includes a plurality of cascaded gate driving circuits;

[0030] The signal input terminal of the first-stage gate driving circuit is connected to the starting signal line, and the signal input terminal of each subsequent stage of the gate driving circuit is connected to the signal output terminal of the previous stage of the gate driving circuit. Alternatively, the latch module of the gate driving circuit includes a first inverter, a second inverter, and a latch control unit, and the signal input terminal of each subsequent stage of the gate driving circuit is connected to the output terminal of the second inverter in the previous stage of the gate driving circuit.

[0031] Thirdly, embodiments of the present invention also provide a display panel, including: a gate driving module provided in any embodiment of the present invention;

[0032] Preferably, the display panel includes at least two gate driving modules; each gate driving module is provided with a corresponding start signal line; the start signals transmitted by the start signal lines in any two gate driving modules have different pulse widths and / or different pulse levels.

[0033] The gate driving circuit provided in this embodiment of the invention, by setting an input module, a latch module, and an output module, can control the level of the gate driving signal according to the level of the input signal when the input module is turned on in response to the first clock signal, and latch the level of the gate driving signal when the input module is turned off in response to the first clock signal, thereby realizing waveform control of the gate driving signal. The latching based on the latch module stabilizes the output voltage of the latch module, thereby stabilizing the output state of the output module. Furthermore, an N-type first transistor is used to form the first output unit to control whether the low level in the gate driving signal is output. By providing a high level of the second power supply signal to the gate of the first transistor, the first transistor can be fully turned on. Compared with the all-P-type TFT scheme in related technologies, this embodiment of the invention does not require a bootstrap capacitor to provide an extremely low voltage to the gate of the first transistor. That is, this embodiment of the invention does not require a capacitor at the output of the latch module, which avoids voltage fluctuations at the output of the latch module due to level jumps in the clock signal coupled by the capacitor, thus avoiding affecting the stable output of the output module. Furthermore, by providing a third power supply signal with a lower voltage than the first power supply signal to the first terminal of the first transistor, this embodiment of the invention ensures that the voltage difference between the gate and the first terminal of the first transistor is less than zero when the first transistor is turned off. This allows for a more thorough turn-off of the first transistor, especially in cases where the first transistor exhibits a negative threshold voltage bias, thus guaranteeing reliable turn-off. This reduces leakage current and improves the voltage stability of the gate drive signal. Therefore, this embodiment of the invention enhances the output stability of the gate drive circuit and improves the display effect of the display panel.

[0034] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of a gate drive circuit in related technologies;

[0037] Figure 2 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0038] Figure 3This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the driving timing of another gate driving circuit provided in an embodiment of the present invention;

[0042] Figure 7 This is a schematic diagram of the driving timing of another gate driving circuit provided in an embodiment of the present invention;

[0043] Figure 8 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0044] Figure 9 This is a schematic diagram of the driving timing of another gate driving circuit provided in an embodiment of the present invention;

[0045] Figure 10 This is a schematic diagram of the driving timing of another gate driving circuit provided in an embodiment of the present invention;

[0046] Figure 11 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0047] Figure 12 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0048] Figure 13 This is a schematic diagram of the structure of a gate driving module provided in an embodiment of the present invention;

[0049] Figure 14 This is a schematic diagram of another gate driving module provided in an embodiment of the present invention;

[0050] Figure 15 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0053] As noted in the background section, current gate drive circuits suffer from output instability. The reasons for this problem are briefly explained below. Figure 1 This is a schematic diagram of a gate drive circuit in related technologies. See also... Figure 1 In related technologies, the gate drive circuit typically includes multiple thin-film transistors (TFTs) of the same communication type and multiple capacitors. Figure 1 Taking a 10T3C architecture gate drive circuit, which includes 10 transistors and 3 capacitors, as an example, due to the advantages of LTPS (Low Temperature Poly-Silicon) TFTs such as high mobility and stable characteristics, current gate drive circuits are usually based on P-type TFTs. However, this circuit has the following problems:

[0054] ① Output step exists: The transistor connected to the input signal IN is directly connected to the lower output transistor. When the clock signal ECK1 and the input signal IN are both low, the lower output transistor starts to conduct and the gate drive signal GOUT starts to drop. However, the lower output transistor can only be fully turned on when the clock signal ECK2 is low, so that the gate drive signal OUT reaches the low level of the first power supply signal VGL.

[0055] ② Because a low level of the first power supply signal VGL is used to output the P-type TFT, in order for the lower output transistor to be fully turned on, an extremely low voltage (denoted as Super VGL) lower than the first power supply signal VGL needs to be provided to the gate of the lower output transistor (i.e., node N1). To generate Super VGL, capacitor C01 needs to be used for bootstrapping at node N1 to couple the level transition of the clock signal ECK2 to node N1. Therefore, node N1 will continuously experience voltage ripples, affecting the output state of the lower output transistor.

[0056] ③ The upper output transistor is used to output the high level of the second power supply signal VGH. In order to control the gate voltage of the upper output transistor, the bootstrap of capacitor C02 is used to couple the level transition of the clock signal ECK2 to node N2, causing continuous ripple and affecting the output state of the upper output transistor.

[0057] In summary, in related technologies, controlling the gate voltage of the two output transistors by capacitively coupling the clock signal level will cause the gate voltage of the two output transistors to be unstable, resulting in the gate drive signal OUT waveform being prone to ripples and having stepped voltages, which can easily lead to problems such as uneven display (mura) and affect the display effect.

[0058] To address the above problems, embodiments of the present invention provide a gate driving circuit. Figure 2 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention. See also... Figure 2 The gate drive circuit includes an input module 110, a latch module 120, and an output module 130.

[0059] The input module 110 is connected to the signal input terminal GIN of the gate drive circuit and is connected to the first clock signal CK1. The input module 110 is used to control whether to output the signal input terminal GIN according to the first clock signal CK1. The latch module 120 is connected to the output terminal of the input module 110 and is connected to the first clock signal CK1, the first power signal VGL, and the second power signal VGH respectively. The latch module 120 is used to output the first power signal VGL or the second power signal VGH according to the level of the output terminal of the input module 110, and to control whether to latch the output state of the latch module 120 according to the first clock signal CK1. The output module 130 includes a first output unit 131 and a second output unit 132. The second output unit 132 is connected to the output terminal QB of the latch module 120 and the signal output terminal GOUT of the gate drive circuit, and is connected to the second power signal VGH. The second output unit 132 is used to control whether to transmit the second power signal VGH to the signal output terminal GOUT as a gate drive signal according to the level of the output terminal QB of the latch module 120. The first output unit 131 includes a first transistor M1. The gate of the first transistor M1 is connected to the output terminal QB of the latch module 120. The first terminal of the first transistor M1 is connected to the third power supply signal VGL2, and the second terminal of the first transistor M2 is connected to the signal output terminal GOUT. The first transistor M1 is used to control whether to transmit the third power supply signal VGL2 to the signal output terminal GOUT as a gate drive signal based on the level of its gate. The first transistor M1 is an N-type transistor; the voltage of the first power supply signal VGL is lower than the voltage of the second power supply signal VGH, and the voltage of the third power supply signal VGL2 is lower than the voltage of the first power supply signal VGL.

[0060] The input module 110 can be turned on or off according to the level of the first clock signal CK1 to control whether the input signal connected to the signal input terminal GIN is transmitted to the output terminal of the input module 110. The latch module 120 can determine whether it has entered the latch state according to the level of the first clock signal CK1. When it has not entered the latch state, the latch module 120 can control the level of the output terminal QB of the latch module 120 according to the level of the output terminal of the input module 110. When it has entered the latch state, the latch module 120 controls the level of the output terminal QB of the latch module 120 to maintain the level when it entered the latch state. In the output module 130, the first output unit 131 and the second output unit 132 are both turned on or off according to the level of the output terminal QB of the latch module 120. When the first output unit 131 is turned on, it transmits the low level of the third power supply signal VGL2 to the signal output terminal GOUT. When the second output unit 132 is turned on, it transmits the high level of the second power supply signal VGH to the signal output terminal GOUT, thereby realizing the level control of the gate drive signal. It is understood that the first output unit 131 and the second output unit 132 will not be turned on simultaneously; for example, their on / off states are opposite to avoid direct high / low level conduction that could damage the circuit. For example, the level of the third power supply signal VGL2 is a low level in the gate drive signal, and its voltage value can be adjusted according to actual needs. It is understood that the voltage of the third power supply signal VGL2 is lower than the voltage of the first power supply signal VGL, which is beneficial for making the voltage difference between the gate and the first electrode of the first transistor M1 negative when the first transistor M1 is turned off, thus making the first transistor M1 turn off more thoroughly. The third power supply signal VGL2 only needs to be slightly negative compared to the first power supply signal VGL, and the magnitude of the third power supply signal VGL2 does not need to reach the level of the extremely low voltage Super VGL in related technologies, to avoid the first transistor M1 being subjected to excessive voltage stress.

[0061] For example, the operation of this gate drive circuit is as follows:

[0062] When the input module 110 is turned on in response to the first clock signal CK1, the latch module 120 does not enter the latching state in response to the first clock signal CK1. At this time, the input module 110 directly outputs the input signal connected to the signal input terminal GIN; the latch module 120 controls the level of the output terminal QB of the latch module 120 according to the level of the output terminal of the input module 110, specifically, it can control the first power signal VGL or the second power signal VGH to be transmitted to the output terminal QB of the latch module 120 according to the level of the output terminal of the input module 110; the output module 130 controls the level of the gate drive signal according to the level of the output terminal QB of the latch module 120, specifically, it can control the first output unit 131 to be turned on or the second output unit 132 to be turned on.

[0063] When input module 110 turns off in response to the first clock signal CK1, latch module 120 enters latching state in response to the first clock signal CK1. At this time, the input signal connected to signal input terminal GIN cannot be transmitted to latch module 120, and even if the input signal level changes, it will not affect the output state of latch module 120; output terminal QB of latch module 120 maintains the level before latch module 120 enters latching state, therefore, the gate drive signal output by output module 130 also maintains the level before latch module 120 enters latching state.

[0064] In summary, by configuring an input module 110, a latch module 120, and an output module 130, this gate drive circuit can control the level of the gate drive signal according to the level of the input signal when the input module 110 is turned on in response to the first clock signal CK1, and latch the level of the gate drive signal when the input module 110 is turned off in response to the first clock signal CK1, thereby achieving waveform control of the gate drive signal. The latching based on the latch module 120 stabilizes the output voltage QB of the latch module 120, thereby stabilizing the output state of the output module 130. Furthermore, the first output unit 131 is constructed using an N-type first transistor M1 to control whether the low level in the gate drive signal is output. By providing a high level of the second power supply signal VGH to the gate of the first transistor M1, the first transistor M1 can be fully turned on. Compared with the all-P-type TFT scheme in related technologies, this embodiment of the invention does not require setting a bootstrap capacitor to provide an extremely low voltage to the gate of the first transistor M1. That is, this embodiment of the invention does not require setting a capacitor at the output terminal QB of the latch module 120, which can avoid voltage fluctuations at the output terminal QB of the latch module 120 due to level jumps in the capacitor-coupled clock signal, thus avoiding affecting the stable output of the output module 130. Furthermore, by providing a third power signal VGL2, which is lower than the first power signal VGL, to the first electrode of the first transistor M1, this embodiment of the invention ensures that the voltage difference between the gate and the first electrode of the first transistor M1 is less than 0 when the first transistor M1 is turned off. This allows the first transistor M1 to be turned off more completely, especially in cases where the first transistor M1 exhibits a negative threshold voltage bias, ensuring reliable turn-off of the first transistor M1. This reduces leakage current and improves the voltage stability of the gate drive signal. Therefore, this embodiment of the invention improves the output stability of the gate drive circuit and enhances the display effect of the display panel.

[0065] Based on the above embodiments, optionally, the gate drive circuit can be entirely composed of MOS transistors. For example, the input module 110, latch module 120, and output module 130 are all composed of MOS transistors. Furthermore, depending on the functional requirements of each module, the gate drive circuit can include both NMOS and PMOS transistors to form a CMOS gate drive circuit, eliminating the need for capacitors. This results in a simple gate drive circuit structure, fewer components, and less layout space. Moreover, since no capacitors are required, the power consumption of the gate drive circuit is low, and the output gate drive signal has no step voltage and is stable without voltage fluctuations. The specific structure and operation of this gate drive circuit will be described below.

[0066] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. See also... Figure 3 Based on the above embodiments, optionally, the latch module 120 includes: a first inverter 121, a second inverter 122, and a latch control unit 123. The control terminal of the first inverter 121 is connected to the output terminal of the input module 110. The first input terminal of the first inverter 121 is connected to a first power signal VGL, and the second input terminal is connected to a second power signal VGH. The output terminal of the first inverter 121 is connected to the output terminal QB of the latch module 120. The control terminal of the second inverter 122 is connected to the output terminal of the first inverter 121. The first input terminal of the second inverter 122 is connected to the first power signal VGL, and the second input terminal is connected to the second power signal VGH. The latch control unit 123 is connected between the output terminal of the input module 110 and the output terminal QB of the second inverter 122, and the control terminal of the latch control unit 123 is connected to a first clock signal CK1. The latch control unit 123 and the input module 110 have different on / off states.

[0067] Specifically, when the latch control unit 123 is turned on, the first inverter 121 and the second inverter 122 are cross-coupled, causing the latch module 120 to enter a latching state, latching the output state of the latch module 120 and keeping the level of the output terminal QB of the latch module 120 constant. When the latch control unit 123 is turned off, the first inverter 121 can invert the level output by the output module 110 and output it to the output terminal QB of the latch module 120. The latch control unit 123 and the input module 110 have different on / off states, for example, by setting the latch control unit 123 and the input module 110 to include transistors of different channel types. By setting the latch control unit 123 and the input module 110 to have different on / off states, the latch module 120 can take corresponding actions according to the level of the input signal when the input module 110 is turned on, and enter the latching state in a timely manner when the input module 110 is turned off, avoiding the floating of its output terminal QB, so as to stabilize the level of the output terminal QB when the input module 110 is turned off.

[0068] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. See also... Figure 4 Based on the above embodiments, optionally, the second output unit 132 includes: a second transistor M2; the gate of the second transistor M2 is connected to the output terminal QB of the latch module 120, the first terminal of the second transistor M2 is connected to the second power supply signal VGH, and the second terminal of the second transistor M2 is connected to the signal output terminal GOUT; the second transistor M2 is a P-type transistor. This configuration causes the output module 130 to form an inverter structure, capable of inverting the level of the output terminal QB of the latch module 120 as a gate drive signal.

[0069] For example, both the first transistor M1 and the second transistor M2 are MOS transistors, such as the first transistor M1 being an NMOS transistor and the second transistor M2 being a PMOS transistor.

[0070] Based on the above embodiments, optionally, the input module 110 includes: a third transistor M3; the gate of the third transistor M3 is connected to a first clock signal CK1, the first terminal of the third transistor M3 is connected to the signal input terminal GIN, and the second terminal of the third transistor M3 is connected to the output terminal of the input module 110. The third transistor M3 is used to turn on or off according to the level connected to its gate. In this embodiment, the input module 110 is configured with a single transistor, making the structure of the input module 110 simple and easy to implement.

[0071] Based on the above embodiments, optionally, the first inverter 120 includes: a fifth transistor M5 and a sixth transistor M6; the gates of both the fifth transistor M5 and the sixth transistor M6 are connected to the control terminal of the first inverter 121, and then connected to the output terminal of the input module 110; the first terminal of the fifth transistor M5 is connected to the first input terminal of the first inverter 121, and connected to the first power supply signal VGL; the first terminal of the sixth transistor M6 is connected to the second input terminal of the first inverter 121, and connected to the second power supply signal VGH; the second terminals of both the fifth transistor M5 and the sixth transistor M6 are connected to the output terminal of the first inverter 121, and then connected to the output terminal QB of the latch module 120; the fifth transistor M5 and the sixth transistor M6 have different channel types. For example, both the fifth transistor M5 and the sixth transistor M6 are MOS transistors, such as the fifth transistor M5 being an NMOS transistor and the sixth transistor M6 being a PMOS transistor.

[0072] The second inverter 122 includes a seventh transistor M7 and an eighth transistor M8. The gates of both transistors M7 and M8 are connected to the control terminal of the second inverter 122, and subsequently to the output terminal QB of the latch module 120. The first terminal of the seventh transistor M7 is connected to the first input terminal of the second inverter 122, receiving a first power supply signal VGL. The first terminal of the eighth transistor M8 is connected to the second input terminal of the second inverter 122, receiving a second power supply signal VGH. The second terminals of both transistors M7 and M8 are connected to the output terminal of the second inverter 122. The seventh transistor M7 and the eighth transistor M8 have different channel types. For example, both transistors M7 and M8 are MOS transistors; for instance, transistor M7 is an NMOS transistor, and transistor M8 is a PMOS transistor.

[0073] The latch control unit 123 includes a ninth transistor M9; the gate of the ninth transistor M9 is connected to a first clock signal CK1, the first terminal of the ninth transistor M9 is connected to the output terminal of the input module 110, and the second terminal of the ninth transistor M9 is connected to the output terminal of the second inverter 122. The ninth transistor M9 and the third transistor M3 have different channel types. For example, both the ninth transistor M9 and the third transistor M3 are MOS transistors, such as the ninth transistor M9 being an NMOS transistor and the third transistor M3 being a PMOS transistor.

[0074] Figure 5 This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention. (Combined with...) Figure 4 and Figure 5 Taking the process of shifting the high-level pulse of the input signal IN into the output by the gate driving circuit as an example, the driving process of the gate driving circuit includes:

[0075] In the first stage T1: the first clock signal CK1 is low and the input signal IN is high; the third transistor M3 is turned on, transmitting the high level of the input signal IN to the output of the input module 110; the first inverter 121 inverts the output level of the input module 110, outputting the low level of the first power supply signal VGL, making the voltage VQB of the output QB of the latch module 120 low; the second inverter 122 inverts the voltage VQB of the output QB of the latch module 120, outputting the high level of the second power supply signal VGH, making the voltage VQ of the output Q of the second inverter 122 high; since the ninth transistor M9 is turned off, there is no connection between the output of the input module 110 and the output Q of the second inverter 122; the output module 130 inverts the voltage VQB of the output QB of the latch module 120, providing the high level of the second power supply signal VGH to the signal output GOUT, therefore, the gate drive signal OUT is high in this stage.

[0076] In the second stage T2: the first clock signal CK1 is low; the third transistor M3 is turned off, and the input signal IN cannot be transmitted to the output of the input module 110. Therefore, the level change of the input signal IN in this stage does not affect the output state of the gate drive circuit; the ninth transistor M9 is turned on, and the latch module 120 enters the latch state. Therefore, the voltage VQB of the output terminal QB of the latch module 120 remains low, and correspondingly, the voltage VQ of the output terminal Q of the second inverter 122 remains high, and the gate drive signal OUT remains high.

[0077] In the third stage T3, the first clock signal CK1 is low, and the input signal IN is low. The third transistor M3 is turned on, transmitting the low level of the input signal IN to the output of the input module 110. The first inverter 121 inverts the output level of the input module 110, outputting the high level of the second power supply signal VGH, making the voltage VQB of the output QB of the latch module 120 high. The second inverter 122 inverts the voltage VQB of the output QB of the latch module 120, outputting the low level of the first power supply signal VGL, making the voltage VQ of the output Q of the second inverter 122 low. Since the ninth transistor M9 is turned off, there is no connection between the output of the input module 110 and the output Q of the second inverter 122. The output module 130 inverts the voltage VQB of the output QB of the latch module 120, providing the low level of the third power supply signal VGL2 to the signal output GOUT. Therefore, the gate drive signal OUT is low in this stage.

[0078] In the fourth stage T4: the first clock signal CK1 is low; the third transistor M3 is turned off, and the input signal IN cannot be transmitted to the output of the input module 110; the ninth transistor M9 is turned on, and the latch module 120 enters the latching state. Therefore, the voltage VQB at the output terminal QB of the latch module 120 remains high, and correspondingly, the voltage VQ at the output terminal Q of the second inverter 122 remains low, and the gate drive signal OUT remains low.

[0079] The third stage T3 and the fourth stage T4 can be repeated until the input signal IN jumps to a high level again.

[0080] It should be noted that, Figure 5 The example provided illustrates a high-level pulse of the input signal IN overlapping a low-level pulse of the first clock signal CK1, but this is not intended to limit the invention. In other embodiments, see, for example, [link to relevant documentation]. Figure 6 When the high-level pulse of the input signal IN is wider, the gate drive circuit can repeat the first stage T1 and the second stage T2 until the input signal IN is low in the next low-level pulse of the first clock signal CK1, and then enter the third stage T3.

[0081] It should also be noted that, Figure 5 The example illustrates the process by which a gate drive circuit shifts and outputs a high-level pulse of the input signal IN, but this is not intended to limit the invention. In other embodiments, see, for example, [link to relevant documentation]. Figure 7 The gate drive circuit can also shift and output the low-level pulse of the input signal IN. Figure 7 The driving process shown is Figure 5 The results are basically the same, the difference being the level of the input signal IN compared to... Figure 5 Fully inverted, correspondingly, the voltage VQB at the output terminal QB of latch module 120, the voltage VQ at the output terminal Q of second inverter 122, and the gate drive signal OUT are compared to Figure 5 All are completely out of phase, and the specific driving process will not be described in detail.

[0082] Figure 8 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. See also... Figure 8 Based on the above embodiments, the input module 110 may optionally further include: a fourth transistor M4; the gate of the fourth transistor M4 is connected to the second clock signal CK1B, the first terminal of the fourth transistor M4 is connected to the signal input terminal GIN, and the second terminal of the fourth transistor M4 is connected to the output terminal of the input module 110. The third transistor M3 and the fourth transistor M4 have different channel types, and the second clock signal CK1B is the inverted signal of the first clock signal CK1. Figure 8 The driving timing of the gate drive circuit shown can be found in [reference]. Figure 9 It can be seen that the second clock signal CK1B and the first clock signal CK1 are inverted signals. Furthermore, since the third transistor M3 and the fourth transistor M4 have different channel types, the on and off states of the third transistor M3 and the fourth transistor M4 are essentially the same.

[0083] In this embodiment, by configuring the input module 110 as a transmission gate circuit, the input module 110 can transmit both high and low voltage levels without voltage drop loss. Specifically, P-type transistors experience voltage loss when transmitting low levels, and N-type transistors experience voltage loss when transmitting high levels. By using a transmission gate circuit composed of two transistors with opposite channel types, and connecting the gates of the two transistors to two inverted signals, the aforementioned level loss problem can be effectively solved, allowing both low and high voltage levels to pass without loss, thus ensuring the level transmission capability of the input module 110. For example, the third transistor M3 and the fourth transistor M4 are both MOS transistors; for instance, the third transistor M3 is a PMOS transistor, and the fourth transistor M4 is an NMOS transistor.

[0084] Based on the above embodiments, optionally, the latch control unit 123 further includes: a tenth transistor M10, the gate of which is connected to a second clock signal CK1B, the first terminal of which is connected to the output terminal of the input module 110, and the second terminal of which is connected to the output terminal Q of the second inverter 122; the ninth transistor M9 and the tenth transistor M10 have different channel types, and the second clock signal CK1B is the inverted signal of the first clock signal CK1. In this embodiment, by setting the latch control unit 123 as a transmission gate circuit, the latch control unit 123 can transmit high and low voltages without voltage drop loss. For example, the ninth transistor M9 and the tenth transistor M10 are both MOS transistors, for example, the ninth transistor M9 is an NMOS transistor and the tenth transistor M11 is a PMOS transistor.

[0085] In summary, the gate drive circuit can be a CMOS circuit composed of different types of MOS transistors. Specifically, the second transistor M2, the third transistor M3, the sixth transistor M6, the eighth transistor M8, and the tenth transistor M10 can all be PMOS transistors, while the first transistor M1, the fourth transistor M4, the fifth transistor M5, the seventh transistor M7, and the ninth transistor M9 can all be NMOS transistors.

[0086] See also Figure 3Based on the above embodiments, optionally, the gate driving circuit further includes a reset module 140; the reset module 140 is connected to the output terminal QB of the latch module 120, and is respectively connected to the reset control signal RST and the reset signal VR. The reset module 140 is used to transmit the reset signal VR to the output terminal QB of the latch module 120 when the reset control signal RST is turned on, so that the output module 130 outputs an inactive level of the gate driving signal, controlling the functional module in the pixel circuit that receives the gate driving signal to turn off. It can be understood that in the display panel, the gate driving signal is provided to the control terminal of the relevant functional module in the pixel circuit, specifically to the gate of the transistor in that functional module; the active level of the gate driving signal is the level that controls the module receiving the gate driving signal to turn on, and the inactive level is the level that controls the module receiving the gate driving signal to turn off. This embodiment provides a function for forced reset of the gate driving circuit by setting the reset module 140.

[0087] For example, the reset signal VR can be a DC signal with a fixed level; the level of the reset signal VR can be specifically set according to the effective level of the gate drive signal. For instance, the level of the reset signal VR can be close to or the same as the effective level of the gate drive signal, so that the output module 130 can obtain the ineffective level of the gate drive signal after inverting the reset signal.

[0088] Figure 10 This is a driving timing diagram of another gate driving circuit provided in an embodiment of the present invention. See also Figure 10 Taking a low conduction level for the reset module 140 as an example, optionally, the operation of the display panel where the gate driving circuit is located includes a power-on phase TS and a display phase TD. The reset control signal RST can be at the conduction level of the reset module 140 during the power-on phase TS and at the cutoff level of the reset module 140 during the display phase TD. Accordingly, the reset module 140 is used to conduct in response to the reset control signal RST during the power-on phase TS, transmitting the reset signal VR to the output terminal QB of the latch module 120, causing the gate driving circuit to output an inactive level of the gate driving signal; and to deactivate in response to the reset control signal RST during the display phase TD, stopping the transmission of the reset signal VR to the output terminal QB of the latch module 120, thereby not affecting the normal operation of the gate driving circuit during the display phase TD.

[0089] See Figure 8In one embodiment, optionally, the reset module 140 includes an eleventh transistor M11, the gate of which is connected to a reset control signal RST, the first terminal of which is connected to a reset signal VR, and the second terminal of which is connected to the output terminal QB of the latch module 120. This embodiment sets the reset module 140 to consist of a single transistor, making the structure of the reset module 140 simple and easy to implement. For example, the eleventh transistor M11 can be a MOS transistor, such as a PMOS transistor.

[0090] Based on the above embodiments, optionally, the power signal already present in the display panel can be multiplexed as a reset signal VR to simplify panel wiring. For details, see [link to documentation]. Figure 11 When the effective level of the gate drive signal is the same as the voltage of the second power supply signal VGH, the second power supply signal VGH can be multiplexed as a reset signal. Alternatively, see [link to relevant documentation]. Figure 12 When the effective level of the gate drive signal is the same as the voltage of the third power supply signal VGL2, the first power supply signal VGL can be multiplexed as a reset signal.

[0091] In summary, facing the trend of increasingly lower power consumption and narrower bezels in current screen products, and the increasing demand for gate driving circuits, this invention provides a new CMOS gate driving circuit with advantages such as fewer components, smaller layout space, lower power consumption, stepless output voltage, and stable, ripple-free output. Specifically, by using two inverters in conjunction with the latch control unit 123 to control whether the latch module 120 forms a latch structure, the voltage of the output terminal QB of the latch module 120 can be stabilized; adding another inverter forms the output module 130. Compared with the structure in related technologies where both upper and lower output transistors are P-type transistors, the CMOS structure can stably output the third power supply signal VGL2 without providing Super VGL to the gate of the first transistor M1, eliminating the need for capacitors in the circuit, and the setting of the third power supply signal VGL2 can effectively suppress the leakage current when the first transistor M1 is turned off. Furthermore, this circuit is suitable for shifting and outputting input signals with high-level pulses, low-level pulses, and arbitrary pulse widths. Based on the same circuit structure, only the pulse level and / or pulse width of the input signal need to be adjusted as required to meet the driving requirements of different functional modules in the pixel circuit. By selecting the input signal, this gate driving circuit can provide scanning signals for N-type transistors, P-type transistors, and light-emitting control transistors in the pixel circuit.

[0092] This invention also provides a gate driving module, which includes the gate driving circuit provided in any embodiment of this invention and has corresponding beneficial effects.

[0093] Figure 13 This is a schematic diagram of a gate driving module provided in an embodiment of the present invention. See also... Figure 13 In one embodiment, optionally, the gate driving module includes a plurality of cascaded gate driving circuits 100, and the gate driving module further includes a start signal line LS. The signal output terminal GOUT of each stage of the gate driving circuit 100 can be connected to at least one row of pixel circuits in the display panel.

[0094] In this circuit, the signal input terminal GIN of the first-stage gate drive circuit 100 is connected to the start signal line LS; that is, the start signal transmitted on the start signal line LS serves as the input signal of the first-stage gate drive circuit 100. The connection relationships between the various stages of the gate drive circuit 100 can be found in [reference needed]. Figure 13 Except for the first stage, the signal input terminal GIN of each subsequent gate drive circuit 100 is connected to the signal output terminal GOUT of the previous stage gate drive circuit 100. Alternatively, see also Figure 14 Based on the latch module of the gate drive circuit 100, which includes a first inverter, a second inverter, and a latch control unit, the signal input terminal GIN of each subsequent stage of the gate drive circuit 100, except for the first stage, can be connected to the output terminal Q of the second inverter in the previous stage of the gate drive circuit 100. (See also...) Figure 5-7 as well as Figure 9-10 As can be seen from the timing diagram, the waveform of the gate drive signal OUT is basically the same as the waveform of the voltage VQ at the output terminal Q of the second inverter. The only difference is the specific voltage of their low levels. The low level of the gate drive signal OUT is the voltage of the third power supply signal VGL2, and the low level of the voltage VQ at the output terminal Q of the second inverter is the voltage of the first power supply signal VGL. However, the low levels of both power supply signals are sufficient to control the PMOS transistor to turn on and the NMOS transistor to turn off. Therefore, the signal input terminal GIN of the subsequent gate drive circuit 100 can be connected to either the signal output terminal GOUT of the preceding gate drive circuit 100 or the output terminal Q of the second inverter. In practical applications, the connection can be set according to the requirements.

[0095] See also Figure 13 and Figure 14Based on the above embodiments, optionally, the gate driving circuit 100 receives the required first clock signal through its first clock terminal GCK1. The gate driving module also includes a first clock signal line LCK1 and a second clock signal line LCK2. The first clock signal line LCK1 can be used to connect to the first clock terminal GCK1 of the odd-level gate driving circuit, providing the required first clock signal to the odd-level gate driving circuit. The second clock signal line LCK2 can be used to connect to the first clock terminal GCK1 of the even-level gate driving circuit, providing the required first clock signal to the even-level gate driving circuit. The clock signals provided by the first clock signal line LCK1 and the second clock signal line LCK2 can be two clock signals with the same frequency and pulse width, and alternating low-level pulses.

[0096] Understandably, when the gate drive circuit 100 also needs to receive a second clock signal that is inverted by the first clock signal, a third clock signal line and a fourth clock signal line can be provided. The third clock signal line can transmit a set of inverted signals with the first clock signal line, and the fourth clock signal line can transmit a set of inverted signals with the second clock signal line. Therefore, the third clock signal line can be connected to odd-numbered gate drive circuits to transmit the required second clock signal to them; the fourth clock signal line can be connected to even-numbered gate drive circuits to transmit the required second clock signal to them.

[0097] Based on the above embodiments, optionally, the gate driving module may also include: a first power line, a second power line, and a third power line; all three power lines are connected to the gate driving circuits 100 at each stage; the first power line is used to provide a first power signal to the gate driving circuits 100 at each stage, the second power line is used to provide a second power signal to the gate driving circuits 100 at each stage, and the third power line is used to provide a third power signal to the gate driving circuits 100 at each stage.

[0098] This invention also provides a display panel, including the gate driving module provided in any embodiment of this invention, which has corresponding beneficial effects.

[0099] Figure 15 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. See also: Figure 15The display panel may include a display area AA and a non-display area NAA surrounding the display area AA. A gate driving module 1000 may be disposed in the non-display area NAA. Multiple sub-pixels 20 may be arrayed in the display area AA, and each sub-pixel 20 may include pixel circuitry and light-emitting devices. The gate driving module 1000 can connect each row of sub-pixels 20 via multiple gate lines LG, which provide gate driving signals to the connected sub-pixels 20. Furthermore, the display panel may also include multiple data lines LD, which are respectively connected to each column of sub-pixels 20. The data lines LD provide data voltages to the linked sub-pixels.

[0100] Based on the above embodiments, optionally, the display panel includes at least two gate driving modules 1000; each gate driving module 1000 is provided with a corresponding start signal line. The pulse widths and / or pulse levels of the start signals transmitted by the start signal lines in any two gate driving modules 1000 are different.

[0101] For example, when the gate driving module 1000 is connected to a P-type transistor (e.g., a data write transistor) in the pixel circuit other than the light-emitting control transistor, the starting signal transmitted by the starting signal line connected to the gate driving module 1000 may have a low-level pulse; when the gate driving module 1000 is connected to a P-type light-emitting control transistor or an N-type transistor (e.g., a threshold compensation transistor) in the pixel circuit other than the light-emitting control transistor, the starting signal transmitted by the starting signal line connected to the gate driving module 1000 may have a high-level pulse; wherein, the pulse width of the starting signal with the high-level pulse and the starting signal with the low-level pulse may be the same, or the pulse width of the starting signal with the high-level pulse may be wider, which can be set according to actual needs. For example, when one gate driving module 1000 is connected to the P-type light-emitting control transistor in the pixel circuit, and the other gate driving module 1000 is connected to the N-type transistor in the pixel circuit other than the light-emitting control transistor, the start signal transmitted by the start signal lines connected to both gate driving modules 1000 has a high-level pulse, but the pulse width of the high-level pulse of the start signal connected to the gate driving module 1000 connected to the P-type light-emitting control transistor can be wider.

[0102] It is understandable that when two or more gate drive modules 1000 are set in the display panel, the start signal lines required by each gate drive module 1000 are set independently; the clock signal lines and power lines required by each gate drive module 1000 can be set independently or shared, which can be determined according to actual needs, and is not limited here.

[0103] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0104] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, include: The input module is connected to the signal input terminal of the gate drive circuit and is connected to the first clock signal; The input module is used to control whether to output the signal connected to the signal input terminal according to the first clock signal; The latch module is connected to the output terminal of the input module and is respectively connected to the first clock signal, the first power signal, and the second power signal; The latch module is used to output the first power signal or the second power signal according to the level of the output terminal of the input module, and to control whether to latch the output state of the latch module according to the first clock signal; The voltage of the first power signal is lower than the voltage of the second power signal; The output module includes a first output unit and a second output unit; the second output unit is connected to the output terminal of the latch module and the signal output terminal of the gate drive circuit, and is connected to the second power supply signal; the first output unit includes a first transistor, the gate of the first transistor is connected to the output terminal of the latch module, the first terminal of the first transistor is connected to the third power supply signal, and the second terminal of the first transistor is connected to the signal output terminal; the first transistor is an N-type transistor, and the voltage of the third power supply signal is lower than the voltage of the first power supply signal.

2. The gate driving circuit according to claim 1, characterized in that, The second output unit includes: a second transistor; the gate of the second transistor is connected to the output terminal of the latch module, the first terminal of the second transistor is connected to the second power supply signal, and the second terminal of the second transistor is connected to the signal output terminal; the second transistor is a P-type transistor; Preferably, the first transistor is an NMOS transistor and the second transistor is a PMOS transistor.

3. The gate driving circuit according to claim 1, characterized in that, The input module includes: a third transistor; the gate of the third transistor is connected to the first clock signal, the first terminal of the third transistor is connected to the signal input terminal, and the second terminal of the third transistor is connected to the output terminal of the input module; Preferably, the input module further includes: a fourth transistor; the gate of the fourth transistor is connected to a second clock signal, the first terminal of the fourth transistor is connected to the signal input terminal, and the second terminal of the fourth transistor is connected to the output terminal of the input module; the third transistor has a different channel type from the fourth transistor, and the second clock signal is the inverted signal of the first clock signal; Preferably, the third transistor is a PMOS transistor and the fourth transistor is an NMOS transistor.

4. The gate driving circuit according to claim 1, characterized in that, The latch module includes: A first inverter, the control terminal of the first inverter is connected to the output terminal of the input module, the first input terminal of the first inverter is connected to the first power signal, the second input terminal of the first inverter is connected to the second power signal, and the output terminal of the first inverter is connected to the output terminal of the latch module. The second inverter has its control terminal connected to the output terminal of the first inverter, its first input terminal connected to the first power signal, and its second input terminal connected to the second power signal. A latch control unit is connected between the output terminal of the input module and the output terminal of the second inverter, and the control terminal of the latch control unit is connected to the first clock signal; the on / off states of the latch control unit and the input module are different.

5. The gate driving circuit according to claim 4, characterized in that, The first inverter includes a fifth transistor and a sixth transistor; the gates of the fifth transistor and the sixth transistor are both connected to the control terminal of the first inverter; the first terminal of the fifth transistor is connected to the first input terminal of the first inverter; the first terminal of the sixth transistor is connected to the second input terminal of the first inverter; the second terminals of the fifth transistor and the sixth transistor are both connected to the output terminal of the first inverter; the fifth transistor and the sixth transistor have different channel types. The second inverter includes a seventh transistor and an eighth transistor; the gates of the seventh transistor and the eighth transistor are both connected to the control terminal of the second inverter; the first terminal of the seventh transistor is connected to the first input terminal of the second inverter; the first terminal of the eighth transistor is connected to the second input terminal of the second inverter; the second terminals of the seventh transistor and the eighth transistor are both connected to the output terminal of the second inverter; the seventh transistor and the eighth transistor have different channel types. The latch control unit includes: a ninth transistor; the gate of the ninth transistor is connected to the first clock signal, the first terminal of the ninth transistor is connected to the output terminal of the input module, and the second terminal of the ninth transistor is connected to the output terminal of the second inverter; Preferably, the input module includes: a third transistor; the gate of the third transistor is connected to the first clock signal, the first terminal of the third transistor is connected to the signal input terminal, and the second terminal of the third transistor is connected to the output terminal of the input module; the third transistor has a different channel type than the ninth transistor; Preferably, the latch control unit further includes: a tenth transistor, the gate of the tenth transistor being connected to a second clock signal, the first terminal of the tenth transistor being connected to the output terminal of the input module, and the second terminal of the tenth transistor being connected to the output terminal of the second inverter; the ninth transistor and the tenth transistor have different channel types, and the second clock signal is the inverted signal of the first clock signal; Preferably, the third transistor, the sixth transistor, the eighth transistor, and the tenth transistor are all PMOS transistors, and the fifth transistor, the seventh transistor, and the ninth transistor are all NMOS transistors.

6. The gate driving circuit according to claim 1, characterized in that, Also includes: A reset module is connected to the output terminal of the latch module and is respectively connected to a reset control signal and a reset signal; Preferably, the operation of the display panel where the gate driving circuit is located includes a power-on stage and a display stage; the reset module is used to transmit the reset signal to the output terminal of the latch module in response to the reset control signal in the power-on stage, and to stop transmitting the reset signal to the output terminal of the latch module in response to the reset control signal in the display stage. Preferably, the effective level of the gate drive signal output by the signal output terminal is the same as the voltage of the third power supply signal, and the first power supply signal is multiplexed as the reset signal; or, the effective level of the gate drive signal output by the signal output terminal is the same as the voltage of the second power supply signal, and the second power supply signal is multiplexed as the reset signal; wherein, the effective level of the gate drive signal is the level at which the module connected to the gate drive signal is turned on.

7. The gate driving circuit according to claim 6, characterized in that, The reset module includes an eleventh transistor, the gate of which is connected to the reset control signal, the first terminal of which is connected to the reset signal, and the second terminal of which is connected to the output terminal of the latch module. Preferably, the eleventh transistor is a PMOS transistor.

8. A gate driving module, characterized in that, include: The gate drive circuit according to any one of claims 1-7.

9. The gate driving module according to claim 8, characterized in that, Also includes: Start signal line; Furthermore, the gate driving module includes multiple cascaded gate driving circuits; The signal input terminal of the first-stage gate driving circuit is connected to the starting signal line, and the signal input terminal of each subsequent stage of the gate driving circuit is connected to the signal output terminal of the previous stage of the gate driving circuit. Alternatively, the latch module of the gate driving circuit includes a first inverter, a second inverter, and a latch control unit, and the signal input terminal of each subsequent stage of the gate driving circuit is connected to the output terminal of the second inverter in the previous stage of the gate driving circuit.

10. A display panel, characterized in that, include: The gate driving module as described in claim 8 or 9; Preferably, the display panel includes at least two of the gate driving modules; Each of the gate driving modules is provided with a corresponding start signal line; The pulse widths and / or pulse levels of the start signals transmitted on the start signal lines in any two gate drive modules are different.

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