Shift register and driving method thereof, gate driving circuit and display device

Abstract

Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device. The shift register comprises: an input circuit configured to provide a signal of an input power terminal to a pull-up node under control of a signal input terminal; a first pull-down circuit configured to provide a signal of a third power terminal to a first pull-down node under control of the pull-up node; a first pull-down control circuit configured to provide a signal of the first power terminal to a first auxiliary node under control of the first power terminal; a suppression circuit configured to disconnect the first auxiliary node and the first pull-down node based on a signal of a control signal terminal when the signal of the pull-up node is an open signal; and a first output circuit configured to provide a signal of a clock signal terminal to a first output terminal under control of the open signal of the pull-up node. The shift register of the present disclosure can withstand high voltage.

Description

[0001] This application claims priority to the earlier Chinese application filed on April 25, 2025, with application number 202510535112.5 and titled "Shift Register and Driving Method Thereof, Gate Driving Circuit and Display Device". Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a shift register and its driving method, a gate driving circuit and a display device. Background Technology

[0003] With the rapid development of e-paper technology, users have placed higher demands on e-paper products, such as high-quality full-color e-paper. Full-color e-paper (ACeP) is composed of ink particles of four colors (usually including yellow, cyan, magenta, and white). Its working principle is to apply an electric field and use the principle of positive and negative attraction to push the corresponding pigment ink particles to the display side to mix and present a variety of colors (about 50,000 colors).

[0004] As the number of ink particles increases, the required driving voltage also rises. Related projects require electronic paper products to withstand higher voltages, such as ±38V; however, this is difficult to achieve with existing technology. Summary of the Invention

[0005] This disclosure provides a shift register and its driving method, a gate driving circuit, and a display device to solve or alleviate one or more technical problems in the prior art.

[0006] As a first aspect of the present disclosure, an embodiment of the present disclosure provides a shift register, including: The input circuit, which is coupled to the signal input terminal, the input power terminal and the pull-up node respectively, is configured to provide the signal from the input power terminal to the pull-up node under the signal control of the signal input terminal. The first pull-down circuit is coupled to the pull-up node, the third power supply terminal and the first pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the first pull-down node under the signal control of the pull-up node; The first pull-down control circuit is coupled to the first power supply terminal and the first auxiliary node respectively, and is configured to provide the first power supply terminal signal to the first auxiliary node under the signal control of the first power supply terminal; The suppression circuit, coupled to the control signal terminal, the first auxiliary node and the first pull-down node respectively, is configured to disconnect the first auxiliary node and the first pull-down node based on the signal at the control signal terminal when the signal of the pull-up node is an on signal. The first output circuit is coupled to the pull-up node, the clock signal terminal and the first output terminal respectively, and is configured to provide the clock signal terminal to the first output terminal under the control of the pull-up node enable signal; The first output pull-down circuit is coupled to the first pull-down node, the fourth power supply terminal, and the first output terminal, respectively, and is configured to provide the signal of the fourth power supply terminal to the first output terminal under the control of the first pull-down node.

[0007] In some embodiments, the suppression circuit is further configured to enable the first auxiliary node and the first pull-down node to conduct based on the signal at the control signal terminal when the signal of the pull-up node is a closed signal.

[0008] In some embodiments, the suppression circuit includes a nineteenth transistor, the gate of which is coupled to a control node, the control node being coupled to a control signal terminal, and the first and second terminals of the nineteenth transistor being coupled to a first auxiliary node and a first pull-down node, respectively.

[0009] In some embodiments, the suppression circuit further includes a state control sub-circuit, which is coupled to a control signal terminal, a first voltage signal, a second voltage signal and a control node, respectively. The state control sub-circuit is configured to, when the signal at the pull-up node is an on signal, provide a first voltage signal to the control node based on the signal at the control signal terminal, thereby disconnecting the first and second terminals of the nineteenth transistor; and / or, The state control sub-circuit is configured to provide a second voltage signal to the control node based on the signal at the control signal terminal when the signal at the pull-up node is a closed signal, so as to turn on the first and second terminals of the nineteenth transistor.

[0010] In some embodiments, the state control subcircuit satisfies at least one of the following: The state control sub-circuit includes a first control transistor, the gate of which is coupled to a control signal terminal, and the first and second terminals of which are coupled to a first voltage signal and a control node, respectively. When the signal of the pull-up node is an enable signal, the signal at the control signal terminal controls the first control transistor to conduct. The state control sub-circuit includes a second control transistor. The gate of the second control transistor is coupled to the control signal terminal. The first and second terminals of the second control transistor are coupled to the second voltage signal and the control node, respectively. When the signal of the pull-up node is a turn-off signal, the signal at the control signal terminal controls the second control transistor to turn on.

[0011] In some embodiments, the first control transistor includes an NMOS and the second control transistor includes a PMOS.

[0012] In some embodiments, The control signal terminal has the same voltage level as the pull-up node; The signals at the control signal terminal include a first preset signal and a second preset signal, and the level states of the first preset signal and the second preset signal are opposite.

[0013] In some embodiments, the control signal terminal is coupled to the pull-up node.

[0014] In some embodiments, the suppression circuit includes a nineteenth transistor, the gate of which is coupled to a control node, the control node being coupled to a control signal terminal and an auxiliary control signal terminal, and the first and second terminals of the nineteenth transistor being coupled to a first auxiliary node and a first pull-down node, respectively.

[0015] In some embodiments, the suppression circuit further includes a first state control subcircuit and a second state control subcircuit. The first state control subcircuit is coupled to a control signal terminal, a third voltage signal, and a control node, respectively. The second state control subcircuit is coupled to an auxiliary control signal terminal, a fourth voltage signal, and a control node, respectively. When the pull-up node signal is enabled, the first state control subcircuit is configured to provide a third voltage signal to the control node based on the signal at the control signal terminal, and the second state control subcircuit is configured to disable the supply of a fourth voltage signal to the control node based on the signal at the auxiliary control signal terminal, thereby disconnecting the first and second terminals of the nineteenth transistor; and / or, When the signal of the pull-up node is the off signal, the first state control sub-circuit is configured to disable the supply of the third voltage signal to the control node based on the signal of the control signal terminal, and the second state control sub-circuit is configured to supply the fourth voltage signal to the control node based on the signal of the auxiliary control signal terminal, so that the first and second terminals of the nineteenth transistor are turned on.

[0016] In some embodiments, the first state control sub-circuit includes a third control transistor, the gate of which is coupled to a control signal terminal, and the first and second terminals of which are coupled to a third voltage signal and a control node, respectively. When the signal at the pull-up node is an enable signal, the signal at the control signal terminal controls the third control transistor to turn on; when the signal at the pull-up node is a disable signal, the signal at the control signal terminal controls the third control transistor to turn off.

[0017] In some embodiments, the second state control sub-circuit includes a fourth control transistor, a fifth control transistor, a sixth control transistor, and a capacitor. The gate of the fourth control transistor is coupled to the first terminal of the fifth control transistor, the second terminal of the sixth control transistor, and the second terminal of the capacitor. The gate of the fifth control transistor is coupled to a control signal terminal, and the second terminal of the fifth control transistor is coupled to a third voltage signal. The gate of the sixth control transistor is coupled to an auxiliary control signal terminal, and the first terminal of the sixth control transistor is coupled to the fourth voltage signal. The first terminal of the capacitor is coupled to the third voltage signal. When the signal at the pull-up node is an enable signal, the signal at the control signal terminal controls the fifth control transistor to turn on, and the signal at the auxiliary control signal terminal controls the sixth control transistor to turn off, so as to output a third voltage signal to the gate of the fourth control transistor and control the fourth control transistor to turn off. When the signal at the pull-up node is the off signal, the signal at the control signal terminal controls the fifth control transistor to turn off, and the signal at the auxiliary control signal terminal controls the sixth control transistor to turn on, so as to output the fourth voltage signal to the gate of the fourth control transistor, control the fourth control transistor to turn on, and charge the capacitor. When the signal at the pull-up node is the off signal, the signal at the control signal terminal controls the fifth control transistor to turn off, the signal at the auxiliary control signal terminal controls the sixth control transistor to turn off, and the capacitor discharges to keep the fourth control transistor on.

[0018] In some embodiments, the third control transistor, the fourth control transistor, the fifth control transistor, and the sixth control transistor include NMOS.

[0019] In some embodiments, the signal at the control signal terminal is the same as the level state of the pull-up node; the signal at the control signal terminal includes a first preset signal and a second preset signal, and the level states of the first preset signal and the second preset signal are opposite. The auxiliary control signal terminal includes a third preset signal and a fourth preset signal. The level of the third preset signal is opposite to that of the first preset signal, and the level of the fourth preset signal is opposite to that of the third preset signal.

[0020] In some embodiments, the control signal terminal is coupled to the pull-up node.

[0021] In some embodiments, it also includes: The second pull-down circuit is coupled to the pull-up node, the third power supply terminal, and the second pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the second pull-down node under the signal control of the pull-up node; The second pull-down control circuit is coupled to the second power supply terminal and the second auxiliary node respectively, and is configured to provide the signal of the second power supply terminal to the second auxiliary node under the signal control of the second power supply terminal; The second output pull-down circuit is coupled to the second pull-down node, the fourth power supply terminal and the first output terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first output terminal under the control of the second pull-down node. The suppression circuit is also coupled to the second auxiliary node and the second pull-down node, and is also configured to disconnect the second auxiliary node and the second pull-down node based on the signal at the control signal terminal when the signal of the pull-up node is an on signal; and / or, the suppression circuit is also configured to turn on the second auxiliary node and the second pull-down node based on the signal at the control signal terminal when the signal of the pull-up node is a off signal.

[0022] In some embodiments, the suppression circuit includes a 29th transistor, the gate of which is coupled to a control node, the control node being connected to a control signal terminal, and the first and second terminals of the 29th transistor being coupled to a second auxiliary node and a second pull-down node, respectively.

[0023] In some embodiments, it also includes at least one of the following: The first auxiliary pull-down circuit is coupled to the signal input terminal, the third power supply terminal and the first pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the first pull-down node under the signal control of the signal input terminal; The first noise reduction circuit is coupled to the first pull-down node, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the signal control of the first pull-down node; The second auxiliary pull-down circuit is coupled to the signal input terminal, the third power supply terminal, and the second pull-down node, respectively, and is configured to provide the signal from the third power supply terminal to the second pull-down node under the signal control of the signal input terminal. The second noise reduction circuit is coupled to the second pull-down node, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the signal control of the second pull-down node; The horizontal reset circuit is coupled to the horizontal reset signal terminal, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the signal control of the horizontal reset signal terminal. The frame reset circuit is coupled to the frame reset signal terminal, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the signal control of the frame reset signal terminal. The output reset circuit is coupled to the horizontal reset signal terminal, the fourth power supply terminal and the first output terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first output terminal under the signal control of the horizontal reset signal terminal.

[0024] In some embodiments, the voltage levels of the first power supply terminal and the second power supply terminal are opposite.

[0025] In some embodiments, at least one of the following is satisfied: The input circuit includes a first transistor, the gate of which is coupled to the signal input terminal, and the first and second terminals of the first transistor are coupled to the input power supply terminal and the pull-up node, respectively. The first pull-down circuit includes a sixteenth transistor, the gate of which is coupled to a pull-up node, and the first and second terminals of the sixteenth transistor are coupled to a third power supply terminal and a first pull-down node, respectively. The first pull-down control circuit includes a fifteenth transistor, the gate and first terminal of which are coupled to the first power supply terminal, and the second terminal of which is coupled to the first auxiliary node. The first auxiliary pull-down circuit includes a seventeenth transistor, the gate of which is coupled to the signal input terminal, and the first and second terminals of the seventeenth transistor are coupled to the third power supply terminal and the first pull-down node, respectively. The first noise reduction circuit includes an eighteenth transistor, the gate of which is coupled to a first pull-down node, and the first and second terminals of the eighteenth transistor are coupled to a third power supply terminal and a pull-up node, respectively. The second pull-down circuit includes a twenty-sixth transistor, the gate of which is coupled to a pull-up node, and the first and second terminals of which are coupled to a third power supply terminal and a second pull-down node, respectively. The second pull-down control circuit includes a twenty-fifth transistor, the gate and first terminal of which are both coupled to the second power supply terminal, and the second terminal of which is coupled to the second auxiliary node. The second auxiliary pull-down circuit includes a twenty-seventh transistor, the gate of which is coupled to the signal input terminal, and the first and second terminals of which are coupled to the third power supply terminal and the second pull-down node, respectively. The second noise reduction circuit includes a twenty-eighth transistor, the gate of which is coupled to a second pull-down node, and the first and second terminals of which are coupled to a third power supply terminal and a pull-up node, respectively. The first output circuit includes a third transistor, the gate of which is coupled to a pull-up node, and the first and second terminals of the third transistor are coupled to a clock signal terminal and a first output terminal, respectively. The first output pull-down module includes an eleventh transistor, the gate of which is coupled to the first pull-down node, and the first and second terminals of the eleventh transistor are coupled to the fourth power supply terminal and the first output terminal, respectively. The second output pull-down module includes a twenty-first transistor, the gate of which is coupled to the second pull-down node, and the first and second terminals of the twenty-first transistor are coupled to the fourth power supply terminal and the first output terminal, respectively. The horizontal reset circuit includes a second transistor, the gate of which is coupled to the horizontal reset signal terminal, and the first and second terminals of the second transistor are coupled to the third power supply terminal and the pull-up node, respectively. The frame reset circuit includes a seventh transistor, the gate of which is coupled to the frame reset signal terminal, and the first and second terminals of the seventh transistor are coupled to the third power supply terminal and the pull-up node, respectively. The output reset circuit includes a fourth transistor, the gate of which is coupled to the horizontal reset signal terminal, and the first and second terminals of the fourth transistor are coupled to the fourth power supply terminal and the first output terminal, respectively.

[0026] As a second aspect of the present disclosure, an embodiment of the present disclosure provides a method for driving a shift register, applied to the shift register of any claim of the present disclosure, the method comprising: In the first stage, a valid level signal is provided to the signal input terminal. Under the control of the valid level signal at the signal input terminal, the input circuit provides the input power signal to the pull-up node. Under the signal control of the pull-up node, the first pull-down circuit provides the third power signal to the first pull-down node. A first preset signal is provided to the control signal terminal to disconnect the first auxiliary node and the first pull-down node. In the second stage, a valid level signal is provided to the horizontal reset signal terminal. Under the control of the valid level signal at the horizontal reset signal terminal, the horizontal reset circuit provides the signal of the third power supply terminal to the pull-up node. Under the control of the signal at the first power supply terminal, the first pull-down control circuit provides the signal of the first power supply terminal to the first auxiliary node. A second preset signal is provided to the control signal terminal, so that the first auxiliary node and the first pull-down node are turned on.

[0027] As a third aspect of the present disclosure, the present disclosure provides a method for driving a shift register, applied to the shift register of any of the present disclosures, the method comprising: In the first stage, a valid level signal is provided to the signal input terminal. Under the control of the valid level signal at the signal input terminal, the input circuit provides the input power terminal signal to the pull-up node. Under the signal control of the pull-up node, the first pull-down circuit provides the third power terminal signal to the first pull-down node. A first preset signal is provided to the control signal terminal, and a third preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are disconnected. In the second stage, a valid level signal is provided to the horizontal reset signal terminal. Under the control of the valid level signal at the horizontal reset signal terminal, the horizontal reset circuit provides the signal of the third power supply terminal to the pull-up node. Under the control of the signal at the first power supply terminal, the first pull-down control circuit provides the signal of the first power supply terminal to the first auxiliary node. A second preset signal is provided to the control signal terminal, and a fourth preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are turned on. In the third stage, a second preset signal is provided to the control signal terminal and a third preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are connected.

[0028] As a fourth aspect of the present disclosure, the present disclosure provides a gate driving circuit including a shift register according to any of the present disclosures.

[0029] As a fifth aspect of the present disclosure, the present disclosure provides a display device that includes a shift register of any one of the present disclosures or a gate driving circuit of the present disclosure.

[0030] In this disclosed technical solution, a suppression circuit is provided between the first auxiliary node and the first pull-down node. When the pull-up node is enabled, the suppression circuit, based on the signal at the control signal terminal, disconnects the first auxiliary node and the first pull-down node. That is, when the pull-up node signal is enabled, the first auxiliary node and the first pull-down node are disconnected. This cuts off the connection between the first pull-down control circuit and the first pull-down circuit, preventing a path from forming between the first power supply terminal and the third power supply terminal via the first pull-down control circuit and the first pull-down circuit. Therefore, in this disclosure, when the pull-up node is enabled, no static current flows through the first pull-down control circuit and the first pull-down circuit, preventing forward bias of the devices in the first pull-down control circuit and the first pull-down circuit, avoiding characteristic shift of the internal devices, and enabling the shift register to withstand high voltages such as ±38V.

[0031] The above overview is for illustrative purposes only and is not intended to be limiting in any way. Further aspects, embodiments, and features of this disclosure will become readily apparent from the accompanying drawings and the following detailed description, in addition to the illustrative aspects, embodiments, and features described above. Attached Figure Description In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments according to this disclosure and should not be construed as limiting the scope of this disclosure.

[0032] Figure 1 It is a type of shift register in related technologies; Figure 2 This is a circuit diagram of a shift register in one embodiment of the present disclosure; Figure 3 This is a circuit diagram of a shift register in another embodiment of the present disclosure; Figure 4 This is a circuit diagram of a shift register in another embodiment of the present disclosure; Figure 5This is a circuit diagram of a shift register in yet another embodiment of the present disclosure; Figure 6 This is a circuit diagram of a shift register in yet another embodiment of the present disclosure; Figure 7 This is a circuit diagram of a shift register in yet another embodiment of the present disclosure; Figure 8 for Figure 7 The diagram shows a timing diagram of the shift register. Figure 9 This is a circuit diagram of a shift register in yet another embodiment of the present disclosure; Figure 10 for Figure 9 The diagram shows a timing diagram of the shift register. Figure 11 This is a circuit diagram of a shift register in yet another embodiment of the present disclosure; Figure 12 This is a schematic diagram of a gate drive circuit in one embodiment of the present disclosure; Figure 13 This is a schematic diagram of a gate driving circuit in a display panel according to an embodiment of the present disclosure; Figure 14 for Figure 13 A timing diagram of the middle gate drive circuit. Detailed Implementation

[0033] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are to be considered exemplary in nature and not restrictive.

[0034] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in these embodiments are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In these embodiments, the source (source electrode) is referred to as the first electrode, and the drain (drain electrode) as the second electrode; alternatively, the drain can be referred to as the first electrode, and the source as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate (also called the gate electrode), the signal input terminal is the source, and the signal output terminal is the drain. The switching transistors used in these embodiments can be P-type transistors (PMOS) or N-type transistors (NMOS). P-type transistors conduct when the gate is low and are cut off when the gate is high; N-type transistors conduct when the gate is high and are cut off when the gate is low. Furthermore, multiple signals in each embodiment of this invention correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential states of the signal and do not imply that the first potential or the second potential has a specific numerical value throughout the text. In this embodiment of the invention, the first potential is used as an example for illustration.

[0035] The coupling can include direct physical contact between the two ends or indirect connection between the two ends (such as establishing a connection between the two ends through a signal line). This embodiment of the invention does not limit the coupling method between the two ends.

[0036] It is understandable that electronic paper is also driven by a gate drive circuit, which includes a shift register that provides row drive signals to the display area of ​​the electronic paper.

[0037] Figure 1 A type of shift register in related technologies, such as Figure 1 As shown, the thin-film transistor (TFT) can be an oxide transistor. However, even with adjustments to the thin-film transistor process, a shift register using a conventional oxide transistor cannot withstand a high voltage of ±38V.

[0038] The inventor discovered through research that Figure 1 In the shift register shown, when the pull-up node PU is high, transistor M16 is turned on under the control of the high level of the pull-up node PU, forming a path from the first power supply terminal VDD1 → transistor M5A → transistor M6A → the third power supply terminal VGL1, with a large quiescent current flowing through this path. This large quiescent current puts significant stress on transistors M15 and M16, causing a shift in their characteristics, making them unable to withstand the ±38V high voltage. Transistors M25 and M26 also exhibit the same problem.

[0039] To address the issue that shift registers cannot withstand high voltage, this disclosure provides an embodiment of a shift register.

[0040] Figure 2 This is a circuit diagram of a shift register in one embodiment of the present disclosure, as shown below. Figure 2 As shown, the shift register includes an input circuit 11, a first pull-down circuit 12, a first pull-down control circuit 13, a suppression circuit 14, a first output circuit 18, and a first output pull-down circuit 15.

[0041] Input circuit 11 is coupled to signal input terminal INPUT, input power terminal VDD0, and pull-up node PU, respectively, and is configured to provide the input power terminal VDD0 signal to pull-up node PU under the signal control of signal input terminal INPUT. For example, when signal input terminal INPUT is a valid level signal, input circuit 11 provides the input power terminal VDD0 signal to pull-up node PU under the control of the valid level signal of signal input terminal INPUT, charging pull-up node PU and pulling it high; when signal input terminal INPUT is an invalid level signal, input circuit 11 disconnects signal input terminal INPUT and pull-up node PU.

[0042] The first pull-down circuit 12 is coupled to the pull-up node PU, the third power supply terminal VGL1, and the first pull-down node PD1, and is configured to provide the signal of the third power supply terminal VGL1 to the first pull-down node PD1 under the signal control of the pull-up node PU. For example, when the pull-up node PU is a valid level signal, such as a high level signal, the first pull-down circuit 12, under the control of the high level signal of the pull-up node PU, connects the first pull-down node PD1 to the third power supply terminal VGL1 and provides the signal of the third power supply terminal VGL1 to the first pull-down node PD1; when the pull-up node PU is an invalid level signal, such as a low level signal, the first pull-down circuit 12 disconnects the third power supply terminal VGL1 from the first pull-down node PD1.

[0043] The first pull-down control circuit 13 is coupled to the first power supply terminal VDD1 and the first auxiliary node N1, respectively, and is configured to provide the first power supply terminal VDD1 signal to the first auxiliary node N1 under the signal control of the first power supply terminal VDD1. That is, under the signal control of the first power supply terminal VDD1, the first pull-down control circuit 13 enables the first auxiliary node N1 to be connected to the first power supply terminal VDD1, thereby providing the first power supply terminal VDD1 signal to the first auxiliary node N1.

[0044] The suppression circuit 14 is coupled to the control signal terminal S, the first auxiliary node N1, and the first pull-down node PD1, respectively. It is configured to disconnect the first auxiliary node N1 and the first pull-down node PD1 based on the signal of the control signal terminal S when the signal of the pull-up node PU is an enable signal. For a shift register using a TFT, the enable signal can be understood as an active level signal. When the pull-up node PU is connected to the gate of the TFT, the enable signal can be understood as a signal that can control the conduction of the first and second electrodes of the TFT.

[0045] The first output circuit 18 is coupled to the pull-up node PU, the clock signal terminal CLK, and the first output terminal Gout, respectively. It is configured to provide the clock signal terminal CLK to the first output terminal Gout under the control of the enable signal of the pull-up node PU. For example, when the pull-up node PU is an enable signal or a valid level signal such as a high-level signal, the first output circuit 18 provides the clock signal terminal CLK to the first output terminal Gout under the control of the high-level signal of the pull-up node PU, enabling the first output terminal Gout to output the clock signal terminal CLK. Therefore, the "enable signal" can also be understood as a signal that controls the first output circuit to make the clock signal terminal and the first output terminal conduct.

[0046] The first output pull-down circuit 15 is coupled to the first pull-down node PD1, the fourth power supply terminal VGL2, and the first output terminal Gout, respectively. It is configured to provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout under the control of the first pull-down node PD1. For example, when the first pull-down node PD1 is an active signal, the first output pull-down circuit 15 can provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout, so that the first output terminal Gout can output the signal of the fourth power supply terminal VGL2.

[0047] like Figure 2 As shown, when the pull-up node PU is enabled, the first pull-down circuit 12, under the control of the enable signal of the pull-up node PU, provides the signal of the third power supply terminal VGL1 to the first pull-down node PD1; and the first pull-down control circuit 13, under the control of the signal of the first power supply terminal VDD1, provides the signal of the first power supply terminal VDD1 to the first auxiliary node N1. If the first auxiliary node N1 is directly connected to the first pull-down node PD1, then the path of first power supply terminal VDD1 → first pull-down control circuit 13 → first auxiliary node N1 → first pull-down node PD1 → first pull-down circuit 12 → third power supply terminal VGL1 can be formed, and a large static current flows through this path.

[0048] In this technical solution, a suppression circuit 14 is provided between the first auxiliary node N1 and the first pull-down node PD1. When the pull-up node PU is enabled, the suppression circuit 14 disconnects the first auxiliary node N1 and the first pull-down node PD1 based on the signal of the control signal terminal S. That is, when the signal of the pull-up node PU is enabled, the first auxiliary node N1 and the first pull-down node PD1 are disconnected. This cuts off the connection between the first pull-down control circuit 13 and the first pull-down circuit 12, preventing the first power supply terminal VDD1 from forming a path to the third power supply terminal VGL1 through the first pull-down control circuit 13 and the first pull-down circuit 12. Therefore, in this disclosure, when the pull-up node PU is enabled, no static current flows through the first pull-down control circuit 13 and the first pull-down circuit 12, preventing the positive bias of the devices in the first pull-down control circuit 13 and the first pull-down circuit 12, avoiding the characteristic offset of the internal devices, and enabling the shift register to withstand high voltages such as ±38V.

[0049] Understandably, in a display panel, a shift register typically includes two timing phases: a first phase and a second phase. The first phase, also known as the operating phase, is characterized by the pull-up node PU being enabled. Under the control of the enabled signal of the pull-up node PU, the first output circuit 18 provides the clock signal CLK to the first output terminal Gout. The second phase, also known as the non-operating phase, is characterized by the pull-up node PU being disabled. Under the control of the disabled signal of the pull-up node PU, the first output circuit 18 stops providing the clock signal CLK to the first output terminal Gout. Instead, the first output pull-down circuit 15 provides the signal of the fourth power supply terminal VGL2 to the first output terminal Gout.

[0050] As the timing of the shift register changes, the signal of the pull-up node PU can change from an enable signal to a disable signal. Under the control of the disable signal of the pull-up node PU, the first output circuit 18 stops providing the clock signal CLK to the first output terminal Gout. To ensure that the first auxiliary node N1 and the first pull-down node PD1 are connected when the pull-up node PU is disabled, the suppression circuit 14 can also be configured to enable the first auxiliary node N1 and the first pull-down node PD1 to conduct based on the signal of the control signal terminal S when the signal of the pull-up node PU is disabled. When the pull-up node PU is disabled, the first pull-down circuit 12, under the control of the disable signal of the pull-up node PU, stops providing the signal of the third power supply terminal VGL1 to the first pull-down node PD1. Therefore, the signal of the first auxiliary node N1 can be transmitted to the first pull-down node PD1, thus providing the signal of the first power supply terminal VDD1 to the first pull-down node PD1.

[0051] Figure 3This is a circuit diagram of a shift register according to another embodiment of this disclosure. Figure 3 As shown, the suppression circuit 14 may include a nineteenth transistor M19. The gate of the nineteenth transistor M19 is coupled to the control node N3, and the control node N3 is coupled to the control signal terminal S. The first and second terminals of the nineteenth transistor M19 are coupled to the first auxiliary node N1 and the first pull-down node PD1, respectively.

[0052] The control signal terminal S includes a first preset signal and a second preset signal, which have opposite level states. When the first preset signal is a high-level signal, the second preset signal is a low-level signal; when the first preset signal is a low-level signal, the second preset signal is a high-level signal.

[0053] The control signal terminal S is coupled to the control node N3 and can provide a first preset signal and a second preset signal to the control node N3. When the pull-up node PU is on, the control signal terminal S provides the first preset signal to the control node N3. Under the control of the first preset signal, the nineteenth transistor M19 is turned off or shut down, causing the first and second terminals of the nineteenth transistor M19 to disconnect, thereby disconnecting the first auxiliary node N1 and the first pull-down node PD1.

[0054] When the pull-up node PU is off, the control signal terminal S provides a second preset signal to the control node N3. The nineteenth transistor M19 is turned on under the control of the second preset signal, so that the first and second terminals of the nineteenth transistor M19 are turned on, thereby coupling the first auxiliary node N1 and the first pull-down node PD1.

[0055] In one example, the nineteenth transistor M19 can be a PMOS, the first preset signal can be a high-level signal, and the nineteenth transistor M19 is turned off under the control of the high-level signal; the second preset signal is a low-level signal, and the nineteenth transistor M19 is turned on under the control of the low-level signal.

[0056] In another example, the nineteenth transistor M19 can be an NMOS, the first preset signal can be a low-level signal, and the nineteenth transistor M19 is turned off under the control of the high-level signal; the second preset signal is a high-level signal, and the nineteenth transistor M19 is turned on under the control of the high-level signal.

[0057] In one embodiment, the control signal terminal S and the pull-up node PU have the same level state. That is, when the pull-up node PU is a high-level signal, the first preset signal of the control signal terminal S is also a high-level signal; when the pull-up node PU is a low-level signal, the second preset signal of the control signal terminal S is also a low-level signal. The high-level signal of the pull-up node PU and the high-level signal of the control signal terminal S may or may not be equal; the low-level signal of the pull-up node PU and the low-level signal of the control signal terminal S may or may not be equal.

[0058] In one embodiment, the control signal terminal S is coupled to the pull-up node PU, so that the signal of the control signal terminal S is the same as the signal of the pull-up node PU. At this time, Figure 3 In this embodiment, the nineteenth transistor M19 is a PMOS.

[0059] Figure 4 This is a circuit diagram of a shift register in another embodiment of the present disclosure, as shown below. Figure 4 As shown, the suppression circuit 14 may further include a state control sub-circuit 141. The state control sub-circuit 141 is coupled to the control signal terminal S, the first voltage signal V1, the second voltage signal V2, and the control node N3, respectively.

[0060] The state control sub-circuit 141 is configured to provide a first voltage signal V1 to the control node N3 based on the signal at the control signal terminal S when the signal at the pull-up node PU is an on signal, thereby disconnecting the first and second terminals of the nineteenth transistor M19. The first voltage signal V1 is an inactive level signal relative to the nineteenth transistor M19, and the nineteenth transistor M19 is turned off under the control of the first voltage signal V1, thus disconnecting the first and second terminals of the nineteenth transistor M19, and consequently disconnecting the first auxiliary node N1 from the first pull-down node PD1.

[0061] The state control sub-circuit 141 is configured to provide a second voltage signal V2 to the control node N3 based on the signal at the control signal terminal S when the signal at the pull-up node PU is off, thereby turning on the first and second terminals of the nineteenth transistor M19. The second voltage signal V2 is an active level signal relative to the nineteenth transistor M19. Under the control of the second voltage signal V2, the nineteenth transistor M19 turns on, turning on its first and second terminals, which in turn turns on the first auxiliary node N1 and the first pull-down node PD1.

[0062] If the control signal terminal S is directly coupled to the control node N3, then the gate of the nineteenth transistor M19 needs to directly bear the voltage signal of the control signal terminal S, which may cause the gate of the nineteenth transistor M19 to bear an inappropriate voltage.

[0063] Figure 4 In this embodiment, by setting a state control sub-circuit 141, the state control sub-circuit 141 can selectively provide a first voltage signal V1 or a second voltage signal V2 to the control node N3 according to the signal from the control signal terminal S, so that the gate of the nineteenth transistor M19 bears the first voltage signal V1 or the second voltage signal V2. The first voltage signal V1 or the second voltage signal V2 can be set to a voltage value suitable for the use of the nineteenth transistor M19, avoiding the gate of the nineteenth transistor M19 directly bearing the voltage signal from the control signal terminal S, which helps to ensure the performance of the nineteenth transistor M19 and extend its service life.

[0064] like Figure 4 As shown, the state control sub-circuit 141 may include a first control transistor M5. The gate of the first control transistor M5 is coupled to the control signal terminal S. The first and second terminals of the first control transistor M5 are coupled to the first voltage signal V1 and the control node N3, respectively. When the signal of the pull-up node PU is an on signal, the signal at the control signal terminal S controls the first control transistor M5 to conduct. For example, when the signal of the pull-up node PU is an on signal, the signal at the control signal terminal S is a first preset signal, which can control the first control transistor M5 to conduct, providing the first voltage signal V1 to the control node N3.

[0065] The state control sub-circuit 141 may include a second control transistor M6. The gate of the second control transistor M6 is coupled to a control signal terminal S. The first and second terminals of the second control transistor M6 are coupled to a second voltage signal V2 and a control node N3, respectively. When the signal of the pull-up node PU is a closed signal, the signal at the control signal terminal S controls the second control transistor M6 to turn on. For example, when the signal of the pull-up node PU is a closed signal, the signal at the control signal terminal S is a second preset signal, which can control the second transistor M2 to turn on, providing the second voltage signal V2 to the control node N3.

[0066] To prevent the first control transistor M5 and the second control transistor M6 from being turned on simultaneously, the first voltage signal V1 can be an invalid level signal for the second control transistor M6, ensuring that the first control transistor M5 is turned on while the second control transistor M6 is turned off. Similarly, the second voltage signal V2 can be an invalid level signal for the first control transistor M5, ensuring that the second control transistor M6 is turned on while the first control transistor M5 is turned off.

[0067] For example, in order to achieve the opposite state of the first control transistor M5 and the second control transistor M6, one of the first control transistor M5 and the second control transistor M6 can be a PMOS and the other can be an NMOS.

[0068] When the control signal terminal S and the pull-up node PU have the same voltage level, for example, when the control signal terminal S is coupled to the pull-up node PU. The first control transistor M5 includes an NMOS, and the second control transistor M6 includes a PMOS.

[0069] The type of the nineteenth transistor M19 can be determined based on the first voltage signal V1 and the second voltage signal V2. For example, if the first voltage signal V1 is a low-level signal and the second voltage signal V2 is a high-level signal, then the nineteenth transistor M19 can be an NMOS; if the first voltage signal V1 is a high-level signal and the second voltage signal V2 is a low-level signal, then the nineteenth transistor M19 can be a PMOS.

[0070] In one example, the first level signal can be provided by the fifth power supply terminal VGL3, meaning that the fifth power supply terminal VGL3 provides the first level signal, which is a low-level signal. The second level signal can be provided by the sixth power supply terminal VDD3, and the second level signal is a high-level signal.

[0071] In one embodiment, considering that the first control transistor M5 and the second control transistor M6 in the suppression circuit 14 are of different transistor types (one is PMOS and the other is NMOS), their joint fabrication in a single circuit presents problems such as high process complexity, susceptibility to short-channel effects leading to transistor threshold voltage drift, and increased leakage current. Therefore, based on the suppression circuit 14 comprising transistors of the same type (both PMOS or both NMOS), another circuit structure for the suppression circuit 14 is provided.

[0072] Figure 5 This is a circuit diagram of a shift register according to another embodiment of this disclosure. Figure 5 As shown, the suppression circuit 14 may include a nineteenth transistor M19. The gate of the nineteenth transistor M19 is coupled to the control node N3. The control node N3 is coupled to the control signal terminal S and the auxiliary control signal terminal CB. The first and second terminals of the nineteenth transistor M19 are coupled to the first auxiliary node N1 and the first pull-down node PD1, respectively.

[0073] The control signal terminal S includes a first preset signal and a second preset signal, with opposite level states. When the first preset signal is high, the second preset signal is low; when the first preset signal is low, the second preset signal is high. The auxiliary control signal terminal CB includes a third preset signal and a fourth preset signal, with opposite level states. When the third preset signal is high, the fourth preset signal is low; when the third preset signal is low, the fourth preset signal is high.

[0074] The control signal terminal S is coupled to the control node N3 and can provide the control node N3 with a first preset signal and a second preset signal. The auxiliary control signal terminal CB is coupled to the control node N3 and can provide the control node N3 with a third preset signal and a fourth preset signal. When the pull-up node PU is enabled, the control signal terminal S provides the first preset signal to the control node N3, and the auxiliary control signal terminal CB provides the third preset signal to the control node N3. Under the control of the first preset signal and the auxiliary control of the third preset signal, the nineteenth transistor M19 is turned off or switched off, causing the first and second terminals of the nineteenth transistor M19 to disconnect, thereby disconnecting the first auxiliary node N1 and the first pull-down node PD1.

[0075] When the pull-up node PU is off, the control signal terminal S provides a second preset signal to the control node N3, and the auxiliary control signal terminal CB provides a fourth preset signal to the control node N3. The nineteenth transistor M19 is turned on under the control of the second preset signal and the auxiliary control of the fourth preset signal, so that the first and second terminals of the nineteenth transistor M19 are turned on, thereby coupling the first auxiliary node N1 and the first pull-down node PD1.

[0076] When the pull-up node PU maintains the off signal, the control signal terminal S provides a second preset signal to the control node N3, and the auxiliary control signal terminal CB provides a third preset signal to the control node N3. The nineteenth transistor M19 is turned on under the control of the second preset signal and the auxiliary control of the third preset signal, so that the first and second terminals of the nineteenth transistor M19 are turned on, thereby coupling the first auxiliary node N1 and the first pull-down node PD1.

[0077] In one example, the nineteenth transistor M19 can be an NMOS. The first preset signal can be a high-level signal, and the third preset signal can be a low-level signal, so the nineteenth transistor M19 is off. The second preset signal is a low-level signal, and the fourth preset signal is a high-level signal, so the nineteenth transistor M19 is on. If the second preset signal (low-level signal) is continuously provided, and the third preset signal (low-level signal) is also provided, the nineteenth transistor M19 remains on.

[0078] In another example, the nineteenth transistor M19 can be a PMOS. The first preset signal can be a low-level signal, and the third preset signal can be a high-level signal, so the nineteenth transistor M19 is off. The second preset signal is a high-level signal, and the fourth preset signal is a low-level signal, so the nineteenth transistor M19 is on. If the second preset signal (high-level signal) is continuously provided, and the third preset signal (high-level signal) is also provided, the nineteenth transistor M19 remains on. In one embodiment, the control signal terminal S and the pull-up node PU have the same level state. That is, when the pull-up node PU is a high-level signal, the first preset signal of the control signal terminal S is also a high-level signal; when the pull-up node PU is a low-level signal, the second preset signal of the control signal terminal S is also a low-level signal. The high-level signal of the pull-up node PU and the high-level signal of the control signal terminal S may or may not be equal; the low-level signal of the pull-up node PU and the low-level signal of the control signal terminal S may or may not be equal.

[0079] In one embodiment, the control signal terminal S is coupled to the pull-up node PU, so that the signal of the control signal terminal S is the same as the signal of the pull-up node PU. At this time, Figure 5 In this embodiment, the nineteenth transistor M19 is an NMOS.

[0080] Figure 6 This is a circuit diagram of a shift register in another embodiment of the present disclosure, as shown below. Figure 6 As shown, the suppression circuit 14 also includes a first state control sub-circuit 142 and a second state control sub-circuit 143. The first state control sub-circuit 142 is coupled to the control signal terminal S, the third voltage signal V3 and the control node N3, respectively. The second state control sub-circuit 143 is coupled to the auxiliary control signal terminal CB, the fourth voltage signal V4 and the control node N3, respectively.

[0081] When the signal of the pull-up node PU is an on signal, the first state control sub-circuit 142 is configured to provide a third voltage signal V3 to the control node N3 based on the signal of the control signal terminal S, and the second state control sub-circuit 143 is configured to disable the supply of a fourth voltage signal V4 to the control node N3 based on the signal of the auxiliary control signal terminal CB, so that the first and second terminals of the nineteenth transistor M19 are disconnected. Relative to the nineteenth transistor M19, the third voltage signal V3 is an invalid level signal. The nineteenth transistor M19 is turned off under the control of the third voltage signal V3, so that the first and second terminals of the nineteenth transistor M19 are disconnected, thereby disconnecting the first auxiliary node N1 from the first pull-down node PD1.

[0082] When the signal of the pull-up node PU is a closed signal, the first state control sub-circuit 142 is configured to disable the supply of the third voltage signal V3 to the control node N3 based on the signal of the control signal terminal S, and the second state control sub-circuit 143 is configured to supply the fourth voltage signal V4 to the control node N3 based on the signal of the auxiliary control signal terminal CB, so that the first and second terminals of the nineteenth transistor M19 are turned on. The fourth voltage signal V4 is an effective level signal relative to the nineteenth transistor M19. The nineteenth transistor M19 is turned on under the control of the fourth voltage signal V4, so that the first and second terminals of the nineteenth transistor M19 are turned on, thereby turning on the first auxiliary node N1 and the first pull-down node PD1.

[0083] If the control signal terminal S or the auxiliary control signal terminal CB is directly coupled to the control node N3, then the gate of the nineteenth transistor M19 needs to directly bear the voltage signal of the control signal terminal S or the voltage signal of the auxiliary control signal terminal CB, which may cause the gate of the nineteenth transistor M19 to bear an inappropriate voltage.

[0084] Figure 6 In this embodiment, by setting a first state control sub-circuit 142 and a second state control sub-circuit 143, the first state control sub-circuit 142 can selectively provide a third voltage signal V3 to the control node N3 according to the signal from the control signal terminal S; the second state control sub-circuit 143 can selectively provide a fourth voltage signal V4 to the control node N3 according to the signal from the auxiliary control signal terminal CB, so that the gate of the nineteenth transistor M19 bears the third voltage signal V3 or the fourth voltage signal V4. The third voltage signal V3 or the fourth voltage signal V4 can be set to a voltage value suitable for the use of the nineteenth transistor M19, avoiding the gate of the nineteenth transistor M19 directly bearing the voltage signal from the control signal terminal S, which helps to ensure the performance of the nineteenth transistor M19 and extend its service life.

[0085] Figure 7 This is a circuit diagram of a shift register in another embodiment of the present disclosure, as shown below. Figure 7As shown, the first state control sub-circuit 142 includes a third control transistor M8, the gate of which is coupled to the control signal terminal S. The first and second terminals of the third control transistor M8 are coupled to the third voltage signal V3 and the control node N3, respectively. The second state control sub-circuit 143 includes a fourth control transistor M9, a fifth control transistor M12, a sixth control transistor M14, and a capacitor C2. The gate of the fourth control transistor M9 is coupled to the first terminal of the fifth control transistor M12, the second terminal of the sixth control transistor M14, and the second terminal of the capacitor C2, respectively. The gate of the fifth control transistor M12 is coupled to the control signal terminal S, and the second terminal of the fifth control transistor M12 is coupled to the third voltage signal V3. The gate of the sixth control transistor M14 is coupled to the auxiliary control signal terminal CB, and the first terminal of the sixth control transistor M14 is coupled to the fourth voltage signal V4. The first terminal of the capacitor C2 is coupled to the third voltage signal V3.

[0086] Among them, the control signal terminal S can be coupled to the pull-up node PU.

[0087] When the signal at pull-up node PU is enabled and the signal at auxiliary control signal terminal CB is disabled (first stage T1), the signal at control signal terminal S controls the third control transistor M8 and the fifth control transistor M12 to conduct, thereby outputting the third voltage signal V3 to the gates of control node N3 and the fourth control transistor M9. While ensuring that control node N3 is connected to the third voltage signal V3, the signal at auxiliary control signal terminal CB controls the fourth control transistor M9 to turn off, preventing the fourth voltage signal V4 from affecting the voltage of control node N3. Simultaneously, the signal at auxiliary control signal terminal CB controls the sixth control transistor M14 to turn off, preventing the fourth voltage signal V4 from affecting the gate voltage of the fourth control transistor M9.

[0088] When the signal at pull-up node PU is off and the signal at auxiliary control signal terminal CB is on (first stage T2), the signal at control signal terminal S controls the third control transistor M8 and the fifth control transistor M12 to turn off, preventing the third voltage signal V3 from affecting the voltage of control node N3 and the gate voltage of the fourth control transistor M9; the signal at auxiliary control signal terminal CB controls the sixth control transistor M14 to turn on, outputting the fourth voltage signal V4 to the gate of the fourth control transistor M9, thereby controlling the fourth control transistor M9 to turn on and provide the fourth voltage signal V4 to control node N3. Simultaneously, the fourth voltage signal V4 charges capacitor C2.

[0089] When the signal at the pull-up node PU is a turn-off signal and the signal at the auxiliary control signal terminal CB is a turn-off signal (first stage T3), the third control transistor M8 and the fifth control transistor M12 remain in the off state; the signal at the auxiliary control signal terminal CB controls the sixth control transistor M14 to turn off. At this time, capacitor C2 discharges and outputs a high-level signal to the gate of the fourth control transistor M9 to maintain the conduction state of the fourth control transistor M9, so that the fourth voltage signal V4 is continuously output to the control node N3.

[0090] In one example, to achieve the transistor states controlled by the control signal terminal S and the auxiliary control signal terminal CB, the third control transistor M8, the fourth control transistor M9, the fifth control transistor M12, and the sixth control transistor M14 can all be NMOS. The nineteenth transistor M19 is of the same type as the third control transistor M8, the fourth control transistor M9, the fifth control transistor M12, and the sixth control transistor M14, and is also an NMOS.

[0091] In one example, the signal at the control signal terminal S is at the same level as the pull-up node PU; the signal at the control signal terminal S includes a first preset signal and a second preset signal, the levels of which are opposite; the signal at the auxiliary control signal terminal CB includes a third preset signal and a fourth preset signal, the level of which is opposite to that of the first preset signal, and the level of the fourth preset signal is opposite to that of the third preset signal. In this example: When the signal at the pull-up node PU is an enable signal, the signal at the control signal terminal S is the first preset signal, and the signal at the auxiliary control signal terminal CB can be the third preset signal (first stage T1). The first preset signal can control the third control transistor M8 to turn on, providing the third voltage signal V3 to the control node N3; the third preset signal can control the sixth control transistor M14 to turn off.

[0092] When the signal at the pull-up node PU is the off signal, the signal at the control signal terminal S is the second preset signal, and the signal at the auxiliary control signal terminal CB can be the fourth preset signal (first stage T2). The second preset signal controls the third control transistor M8 and the fifth control transistor M12 to turn off; the fourth preset signal can control the sixth control transistor M14 to turn on, outputting the fourth voltage signal V4 to the gate of the fourth control transistor M9, thereby controlling the fourth control transistor M9 to turn on and provide the fourth voltage signal V4 to the control node N3.

[0093] When the signal at the pull-up node PU is the off signal, the signal at the control signal terminal S is the second preset signal, and the signal at the auxiliary control signal terminal CB can be the third preset signal (first stage T3). The second preset signal controls the third control transistor M8 and the fifth control transistor M12 to turn off; the third preset signal can control the sixth control transistor M14 to turn off.

[0094] For example, the first preset signal and the fourth preset signal can be high-level signals, and the second preset signal and the third preset signal can be low-level signals. Figure 8 for Figure 7 The timing diagram corresponding to the suppression circuit 14 in the shift register shown.

[0095] In one embodiment, such as Figure 2 As shown, the shift register may also include a second pull-down circuit 22, a second pull-down control circuit 23, and a second output pull-down circuit 25.

[0096] The second pull-down circuit 22 is coupled to the pull-up node PU, the third power supply terminal VGL1, and the second pull-down node PD2, respectively. It is configured to provide the signal of the third power supply terminal VGL1 to the second pull-down node PD2 under the signal control of the pull-up node PU. For example, when the pull-up node PU is a valid level signal, such as a high level signal, the second pull-down circuit 22, under the control of the high level signal of the pull-up node PU, connects the second pull-down node PD2 to the third power supply terminal VGL1, providing the signal of the third power supply terminal VGL1 to the second pull-down node PD2; when the pull-up node PU is an invalid level signal, such as a low level signal, the second pull-down circuit 22 disconnects the third power supply terminal VGL1 from the second pull-down node PD2.

[0097] The second pull-down control circuit 23 is coupled to the second power supply terminal VDD2 and the second auxiliary node N2 respectively, and is configured to provide the signal of the second power supply terminal VDD2 to the second auxiliary node N2 under the signal control of the second power supply terminal VDD2.

[0098] The second output pull-down circuit 25 is coupled to the second pull-down node PD2, the fourth power supply terminal VGL2, and the first output terminal Gout, respectively. It is configured to provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout under the control of the second pull-down node PD2. For example, when the second pull-down node PD2 is an active level signal, the second output pull-down circuit 25 can provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout, so that the first output terminal Gout can output the signal of the fourth power supply terminal VGL2.

[0099] The suppression circuit 14 is also coupled to the second auxiliary node N2 and the second pull-down node PD2, and is also configured to disconnect the second auxiliary node N2 and the second pull-down node PD2 based on the signal of the control signal terminal S when the signal of the pull-up node PU is an on signal.

[0100] For example, the shift register may include a first module and a second module. The first module includes a first pull-down control circuit 13, a first pull-down circuit 12, and a first output pull-down circuit 15. The second module includes a second pull-down control circuit 23, a second pull-down circuit 22, and a second output pull-down circuit 25. The first module and the second module can be used alternately in the operation of the shift register, or one of the first module and the second module can be selected for use. The two modules have the same or similar functions.

[0101] Referring to the previous text, when the second pull-down control circuit 23 and the second pull-down circuit 22 are used, when the pull-up node PU is the on signal, no static current will flow through the second pull-down control circuit 23 and the second pull-down circuit 22, preventing the devices in the second pull-down control circuit 23 and the second pull-down circuit 22 from being positively biased, avoiding the characteristic offset of the internal devices, so that the shift register can withstand high voltages such as ±38V.

[0102] The suppression circuit 14 is also configured to turn on the second auxiliary node N2 and the second pull-down node PD2 based on the signal of the control signal terminal S when the signal of the pull-up node PU is a closed signal. When the pull-up node PU is a closed signal, the second pull-down circuit 22 stops providing the signal of the third power terminal VGL1 to the second pull-down node PD2 under the control of the closed signal of the pull-up node PU. Thus, the signal of the second auxiliary node N2 can be transmitted to the second pull-down node PD2, thereby providing the signal of the second power terminal VDD2 to the second pull-down node PD2.

[0103] Corresponding to the nineteenth transistor M19, such as Figures 3-7 As shown, the suppression circuit 14 may further include a twenty-ninth transistor M29. The gate of the twenty-ninth transistor M29 is coupled to the control node N3, and the control node N3 is connected to the control signal terminal S. The first and second terminals of the twenty-ninth transistor M29 are coupled to the second auxiliary node N2 and the second pull-down node PD2, respectively. The twenty-ninth transistor M29 has the same function as the nineteenth transistor M19 mentioned above, and will not be described again here.

[0104] like Figure 4As shown, the shift register may further include a first auxiliary pull-down circuit 16 and a first noise reduction circuit 17. The first auxiliary pull-down circuit 16 is coupled to the signal input terminal INPUT, the third power supply terminal VGL1, and the first pull-down node PD1, respectively, and is configured to provide the signal of the third power supply terminal VGL1 to the first pull-down node PD1 under the signal control of the signal input terminal INPUT.

[0105] The first noise reduction circuit 17 is coupled to the first pull-down node PD1, the third power supply terminal VGL1 and the pull-up node PU respectively, and is configured to provide the signal of the third power supply terminal VGL1 to the pull-up node PU under the signal control of the first pull-down node PD1.

[0106] The shift register may also include a second auxiliary pull-down circuit 26 and a second noise reduction circuit 27. The second auxiliary pull-down circuit 26 is coupled to the signal input terminal INPUT, the third power supply terminal VGL1, and the second pull-down node PD2, and is configured to provide the signal of the third power supply terminal VGL1 to the second pull-down node PD2 under the signal control of the signal input terminal INPUT.

[0107] The second noise reduction circuit 27 is coupled to the second pull-down node PD2, the third power supply terminal VGL1 and the pull-up node PU respectively, and is configured to provide the signal of the third power supply terminal VGL1 to the pull-up node PU under the signal control of the second pull-down node PD2.

[0108] like Figure 4 As shown, the shift register may also include a row reset circuit 19. The row reset circuit 19 is coupled to the row reset signal terminal RST, the third power supply terminal VGL1, and the pull-up node PU, and is configured to provide the third power supply terminal VGL1 signal to the pull-up node PU under the signal control of the row reset signal terminal RST. In the display panel, the row reset circuit 19 can provide the third power supply terminal VGL1 signal to the pull-up node PU after the corresponding row pixel is displayed, thereby resetting the row pixel.

[0109] like Figure 4 As shown, the shift register may also include a frame reset circuit 20. The frame reset circuit 20 is coupled to the frame reset signal terminal TRST, the third power supply terminal VGL1, and the pull-up node PU, and is configured to provide the third power supply terminal VGL1 signal to the pull-up node PU under the signal control of the frame reset signal terminal TRST. In the display panel, the frame reset circuit 20 can provide the third power supply terminal VGL1 signal to the pull-up nodes PU of all shift registers after a frame ends, thereby resetting the entire frame to display the next frame.

[0110] like Figure 4As shown, the shift register may also include an output reset circuit 21. The output reset circuit 21 is coupled to the row reset signal terminal RST, the fourth power supply terminal VGL2, and the first output terminal Gout, and is configured to provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout under the signal control of the row reset signal terminal RST. In the display panel, the output reset circuit 21 can provide the signal of the fourth power supply terminal VGL2 to the first output terminal Gout of the corresponding shift register after the corresponding row pixel is displayed, thereby resetting the row pixel.

[0111] For example, the first module may further include a first auxiliary pull-down circuit 16 and a first noise reduction circuit 17, and the second module may further include a second auxiliary pull-down circuit 26 and a second noise reduction circuit 27. To enable alternating use of the first and second modules, the voltage levels of the first power supply terminal VDD1 and the second power supply terminal VDD2 are opposite. For example, when the first module is used, the first power supply terminal VDD1 is a working level signal, and the second power supply terminal VDD2 can be a common voltage signal Vcom; when the second module is used, the second power supply terminal VDD2 is a working level signal, and the first power supply terminal VDD1 can be a common voltage signal Vcom.

[0112] Understandable. Figures 5-7 The shift register shown can also include Figure 4 The circuits shown include the first auxiliary pull-down circuit 16, the first noise reduction circuit 17, the second auxiliary pull-down circuit 26, the second noise reduction circuit 27, the frame reset circuit 20, and the output reset circuit 21. Their working principles are the same as those described in the above embodiments and will not be repeated here.

[0113] In one embodiment, the third power supply terminal VGL1 and the fourth power supply terminal VGL2 can be coupled. The following... Figure 4 The following explanation uses the structure of the suppression circuit 14 shown as an example: Figure 9 This is a circuit diagram of a shift register in yet another embodiment of the present disclosure, as shown below. Figure 9 As shown, the signal input terminal INPUT can be coupled to the input power terminal VDD0, and the third power terminal VGL1 can be coupled to the fourth power terminal VGL2.

[0114] In one embodiment, such as Figure 9As shown, the input circuit 11 may include a first transistor M1. The gate of the first transistor M1 is coupled to the signal input terminal INPUT. The first and second terminals of the first transistor M1 are coupled to the input power supply terminal VDD0 and the pull-up node PU, respectively. The signal input terminal INPUT may be coupled to the input power supply terminal VDD0. When the signal input terminal INPUT provides a valid level signal, the first transistor M1 is turned on, and the signal from the signal input terminal INPUT is provided to the pull-up node PU, pulling the pull-up node PU high. When the signal input terminal INPUT provides an invalid level signal, the first transistor M1 is turned off or turned off.

[0115] The first pull-down circuit 12 may include a sixteenth transistor M16. The gate of the sixteenth transistor M16 is coupled to the pull-up node PU. The first and second terminals of the sixteenth transistor M16 are coupled to the third power supply terminal VGL1 and the first pull-down node PD1, respectively. When the pull-up node PU is an active signal, the sixteenth transistor M16 is turned on, and the third power supply terminal VGL1 is connected to the first pull-down node PD1. When the pull-up node PU is an inactive signal, the sixteenth transistor M16 is turned off.

[0116] The first pull-down control circuit 13 may include a fifteenth transistor M15. The gate and first terminal of the fifteenth transistor M15 are both coupled to the first power supply terminal VDD1, and the second terminal of the fifteenth transistor M15 is coupled to the first auxiliary node N1. When the first power supply terminal VDD1 is a valid level signal, the fifteenth transistor M15 is turned on, providing the signal of the first power supply terminal VDD1 to the first auxiliary node N1. When the first module is not used, the first power supply terminal VDD1 is an invalid level signal, and the fifteenth transistor M15 is turned off.

[0117] The first auxiliary pull-down circuit 16 may include a seventeenth transistor M17. The gate of the seventeenth transistor M17 is coupled to the signal input terminal INPUT. The first and second terminals of the seventeenth transistor M17 are coupled to the third power supply terminal VGL1 and the first pull-down node PD1, respectively. When the signal input terminal INPUT is a valid signal, the pull-up node PU is pulled high. At this time, it is necessary to ensure that the pull-down node is pulled low. By setting the first auxiliary pull-down circuit 16, the seventeenth transistor M17 can provide the signal of the third power supply terminal VGL1 to the first pull-down node PD1, pulling the first pull-down node PD1 low, ensuring that the pull-up node PU is pulled high while the pull-down node is pulled low.

[0118] The first noise reduction circuit 17 includes an eighteenth transistor M18. The gate of the eighteenth transistor M18 is coupled to the first pull-down node PD1. The first and second terminals of the eighteenth transistor M18 are coupled to the third power supply terminal VGL1 and the pull-up node PU, respectively. In the second stage (non-operating stage) of the shift register, the first pull-down node PD1 is a high-level signal. To prevent the pull-up node PU from being high-level, the first noise reduction circuit 17 can provide a low-level signal of the third power supply terminal VGL1 to the pull-up node PU through the eighteenth transistor M18 when the first pull-down node PD1 is a high-level signal, thus preventing the pull-up node PU from being high-level.

[0119] The second pull-down circuit 22 includes a twenty-sixth transistor M26. The gate of the twenty-sixth transistor M26 is coupled to the pull-up node PU. The first and second terminals of the twenty-sixth transistor M26 are coupled to the third power supply terminal VGL1 and the second pull-down node PD2, respectively.

[0120] The second pull-down control circuit 23 includes a twenty-fifth transistor M25. The gate and first terminal of the twenty-fifth transistor M25 are both coupled to the second power supply terminal VDD2, and the second terminal of the twenty-fifth transistor M25 is coupled to the second auxiliary node N2.

[0121] The second auxiliary pull-down circuit 26 includes a twenty-seventh transistor M27. The gate of the twenty-seventh transistor M27 is coupled to the signal input terminal INPUT. The first and second terminals of the twenty-seventh transistor M27 are coupled to the third power supply terminal VGL1 and the second pull-down node PD2, respectively. The working principle of the second auxiliary pull-down circuit 26 is the same as or similar to that of the first auxiliary pull-down circuit 16, and will not be described again here.

[0122] The second noise reduction circuit 27 includes a twenty-eighth transistor M28. The gate of the twenty-eighth transistor M28 is coupled to the second pull-down node PD2. The first and second terminals of the twenty-eighth transistor M28 are coupled to the third power supply terminal VGL1 and the pull-up node PU, respectively. The working principle of the second noise reduction circuit 27 is the same as or similar to that of the first noise reduction circuit 17, and will not be described in detail here.

[0123] The first output circuit 18 includes a third transistor M3. The gate of the third transistor M3 is coupled to the pull-up node PU. The first and second terminals of the third transistor M3 are coupled to the clock signal terminal CLK and the first output terminal Gout, respectively. When the signal from the pull-up node PU is an enable signal, the third transistor M3 is turned on, providing the clock signal CLK to the first output terminal Gout. When the signal from the pull-up node PU is an disable signal, the third transistor M3 is turned off. The first output circuit 18 may also include a storage capacitor C. One end of the storage capacitor is coupled to the second terminal of the third transistor M3, and the other end is coupled to the pull-up node PU.

[0124] The first output pull-down module 15 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is coupled to the first pull-down node PD1. The first and second terminals of the eleventh transistor M11 are coupled to the fourth power supply terminal VGL2 and the first output terminal Gout, respectively. When the first pull-down node PD1 is an invalid level signal, the eleventh transistor M11 is turned off; when the first pull-down node PD1 is an active level signal, the eleventh transistor M11 is turned on, providing the signal of the fourth power supply terminal VGL2 to the first output terminal Gout.

[0125] The second output pull-down module 25 includes a twenty-first transistor M21. The gate of the twenty-first transistor M21 is coupled to the second pull-down node PD2. The first and second terminals of the twenty-first transistor M21 are coupled to the fourth power supply terminal VGL2 and the first output terminal Gout, respectively. When the second pull-down node PD2 is an invalid level signal, the twenty-first transistor M21 is turned off; when the second pull-down node PD2 is an active level signal, the twenty-first transistor M21 is turned on, providing the signal of the fourth power supply terminal VGL2 to the first output terminal Gout.

[0126] The horizontal reset circuit 19 includes a second transistor M2. The gate of the second transistor M2 is coupled to the horizontal reset signal terminal RST. The first and second terminals of the second transistor M2 are coupled to the third power supply terminal VGL1 and the pull-up node PU, respectively. When the horizontal reset signal terminal RST is an active level signal, the second transistor M2 is turned on, providing the signal from the third power supply terminal VGL1 to the pull-up node PU, thus resetting the pull-up node PU. When the horizontal reset signal terminal RST is an inactive level signal, the second transistor M2 is turned off.

[0127] The frame reset circuit 20 includes a seventh transistor M7. The gate of the seventh transistor M7 is coupled to the frame reset signal terminal TRST. The first and second terminals of the seventh transistor M7 are coupled to the third power supply terminal VGL1 and the pull-up node PU, respectively. When the frame reset signal terminal TRST is a valid level signal, the seventh transistor M7 is turned on, providing the signal to the third power supply terminal VGL1 to the pull-up node PU, thereby realizing frame reset. When the frame reset signal terminal TRST is an invalid level signal, the seventh transistor M7 is turned off.

[0128] The output reset circuit 21 includes a fourth transistor M4. The gate of the fourth transistor M4 is coupled to the horizontal reset signal terminal RST. The first and second terminals of the fourth transistor M4 are coupled to the fourth power supply terminal VGL2 and the first output terminal Gout, respectively. When the horizontal reset signal terminal RST is an active level signal, the fourth transistor M4 is turned on, providing the signal from the third power supply terminal VGL1 to the first output terminal Gout, thus resetting the first output terminal Gout. When the horizontal reset signal terminal RST is an inactive level signal, the fourth transistor M4 is turned off.

[0129] In one embodiment, such as Figure 9 As shown, the shift register may further include a thirteenth transistor M13, a tenth transistor M10, and a twentieth transistor M20. The gate of the thirteenth transistor M13 is coupled to the pull-up node PU, and its first and second terminals are coupled to the clock signal terminal CLK and the second output terminal Out_C, respectively. The gate of the tenth transistor M10 is coupled to the first pull-down node PD1, and its first and second terminals are coupled to the second output terminal Out_C and the fourth power supply terminal VGL2, respectively. The gate of the twentieth transistor M20 is coupled to the second pull-down node PD2, and its first and second terminals are coupled to the second output terminal Out_C and the fourth power supply terminal VGL2, respectively.

[0130] The first module may also include the tenth transistor M10, and the second module may also include the twentieth transistor M20.

[0131] In the gate drive circuit, the first output terminal Gout is connected to the signal input terminal INPUT of the next stage shift register, and the second output terminal Out_C is connected to the row reset signal terminal RST of the previous stage shift register.

[0132] exist Figure 9 In this embodiment, the first module includes the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18, and the second module includes the twenty-fifth transistor M25, the twenty-sixth transistor M26, the twenty-seventh transistor M27, and the twenty-eighth transistor M28. The first module and the second module are used alternately.

[0133] It should be noted that, Figure 9 The illustration shows exemplary structures of various circuit modules or sub-circuit modules. Those skilled in the art will understand that... Figure 9 The illustrated structures can be simplified versions of each module. Those skilled in the art, based on conventional techniques, can further elaborate on... Figure 9 The functions of each module are achieved by adding components to the structure of each module. For example, the state control subcircuit 141 can adopt a structure of two or more thin-film transistors connected in series, so that the state control subcircuit 141 can still achieve the same functionality even with structural changes. Figures 3-7 They serve the same function. Therefore, the circuit modules or sub-circuit modules in this disclosure are not limited to... Figures 3-7 Any structure shown can achieve its function.

[0134] in addition, Figure 9The types of transistors are illustrated exemplarily. For example, the first control transistor M5 is an NMOS, the second control transistor M6 is a PMOS, the nineteenth transistor M19 and the twenty-ninth transistor M29 are both NMOS, and the first transistor M1 is an NMOS. It is understood that the type of each transistor can be set according to actual settings and specific control signals, as long as the function of this disclosure can be achieved. In one example, the NMOS type transistor in the shift register of this disclosure can be an oxide transistor, that is, the active layer material includes oxide semiconductor materials, such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), and other oxide semiconductor materials.

[0135] Figure 10 for Figure 9 The diagram below shows a timing diagram of a shift register. Figure 9 and Figure 10 The working principle of the shift register in the embodiments of this disclosure is explained in detail below. The first module is selected and the second module is idle. That is, the signal of the first power supply terminal VDD1 is a high-level signal, the signal of the second power supply terminal VDD2 is Vcom, and the third power supply terminal VGL1 and the fourth power supply terminal VGL2 are both low-level signals. The effective level signal is a high-level signal.

[0136] In the first stage T1, a valid level signal is provided to the signal input terminal INPUT. The first transistor M1 turns on under the control of the valid level signal, providing a high-level signal to the pull-up node PU. The sixteenth transistor M16, under the control of the high-level signal from the pull-up node PU, provides the signal for the third power supply terminal VGL1 to the first pull-down node PD1. The fifteenth transistor M15, under the control of the high-level signal from the first power supply terminal VDD1, provides the high-level signal from the first power supply terminal VDD1 to the first auxiliary node N1. At this time, since the control signal terminal S is coupled to the pull-up node PU, the control signal terminal S is also a high-level signal, causing the first control transistor M5 to turn on, providing the first voltage signal V1 from the fifth power supply terminal VGL3 to the control node N3. The first voltage signal V1 controls the nineteenth transistor M19 to turn off, disconnecting the connection between the first auxiliary node N1 and the first pull-down node PD1. Therefore, in the first stage T1, no quiescent current flows through the fifteenth transistor M15 and the sixteenth transistor.

[0137] In the first stage T1, the third transistor M3 is turned on under the control of the high-level signal of the pull-up node PU, providing the clock signal CLK to the first output terminal Gout. When the clock signal CLK is a high-level signal, due to the coupling effect, the level of the pull-up node PU is further increased, causing the third transistor M3 to be fully turned on, providing the high-level signal of the clock signal CLK to the first output terminal Gout, which is used to drive the corresponding row pixel.

[0138] In the second stage T2, a valid level signal is provided to the row reset signal terminal RST, turning on the second transistor M2 and providing the third power supply terminal VGL1 signal to the pull-up node PU, causing the pull-up node PU to reset to a low level signal. The sixteenth transistor M16 is turned off under the control of the low level signal of the pull-up node PU. The fifteenth transistor M15 provides the first power supply terminal VDD1 high level signal to the first auxiliary node N1 under the control of the high level signal of the first power supply terminal VDD1. At this time, since the control signal terminal S is coupled to the pull-up node PU, the control signal terminal S is also a low level signal, causing the second control transistor M6 to turn on and providing the second voltage signal V2 of the sixth power supply terminal VDD3 to the control node N3. The second voltage signal V2 controls the nineteenth transistor M19 to turn on, making the first auxiliary node N1 and the first pull-down node PD1 connected, and the high level signal of the first auxiliary node N1 is transmitted to the first pull-down node PD1. Therefore, in the second stage T2, the first pull-down node PD1 is a high level signal.

[0139] The shift register may also include a third stage T0, which can be called the frame interval stage, i.e., the gap between two frames. In the third stage T0, the power supply voltage levels of the first power supply terminal VDD1 and the second power supply terminal VDD2 are exchanged. For example, the signal at the first power supply terminal VDD1 changes from a high level to Vcom, and the signal at the second power supply terminal VDD2 changes from Vcom to a high level. Therefore, in the next frame, the shift register uses the second module. Alternating between the first and second modules extends the lifespan of the shift register.

[0140] Understandable. Figures 5-7 The shift register shown, except for the suppression circuit 14, can also be structured as follows: Figure 9 As shown. That is, in Figure 7 Under the suppression circuit 14 structure shown, the shift register structure can be as follows: Figure 11 As shown in the figure. Here, RST can be OUT_C(n+1), and INPUT can be OUT_C(n-1).

[0141] This disclosure also provides a method for driving a shift register, applicable to the shift register in any embodiment of this disclosure, specifically applied to... Figures 3-4The shift register corresponding to the suppression circuit 14 structure shown. The driving method of the shift register includes a first stage and a second stage.

[0142] In the first stage, a valid level signal is provided to the signal input terminal INPUT. Under the control of the valid level signal of the signal input terminal INPUT, the input circuit 11 provides the input power supply terminal VDD0 signal to the pull-up node PU. Under the signal control of the pull-up node PU, the first pull-down circuit 12 provides the third power supply terminal VGL1 signal to the first pull-down node PD1. A first preset signal is provided to the control signal terminal S, so that the first auxiliary node N1 and the first pull-down node PD1 are disconnected.

[0143] In the second stage, a valid level signal is provided to the horizontal reset signal terminal RST. Under the control of the valid level signal of the horizontal reset signal terminal RST, the horizontal reset circuit 19 provides the signal of the third power supply terminal VGL1 to the pull-up node PU. Under the control of the signal of the first power supply terminal VDD1, the first pull-down control circuit 13 provides the signal of the first power supply terminal VDD1 to the first auxiliary node N1. A second preset signal is provided to the control signal terminal S, so that the first auxiliary node N1 and the first pull-down node PD1 are turned on.

[0144] This disclosure also provides a method for driving a shift register, applicable to the shift register in any embodiment of this disclosure, specifically applied to... Figures 5-7 The shift register corresponding to the suppression circuit 14 structure shown. The driving method of the shift register includes a first stage, a second stage, and a third stage.

[0145] In the first stage, a valid level signal is provided to the signal input terminal. Under the control of the valid level signal at the signal input terminal, the input circuit provides the input power terminal signal to the pull-up node. Under the signal control of the pull-up node, the first pull-down circuit provides the third power terminal signal to the first pull-down node. A first preset signal is provided to the control signal terminal, and a third preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are disconnected. In the second stage, a valid level signal is provided to the horizontal reset signal terminal. Under the control of the valid level signal at the horizontal reset signal terminal, the horizontal reset circuit provides the signal of the third power supply terminal to the pull-up node. Under the control of the signal at the first power supply terminal, the first pull-down control circuit provides the signal of the first power supply terminal to the first auxiliary node. A second preset signal is provided to the control signal terminal, and a fourth preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are turned on. In the third stage, a second preset signal is provided to the control signal terminal and a third preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are connected.

[0146] The detailed process of driving the shift register can be found in the working principle described above, and will not be repeated here.

[0147] It should be noted that, in this article, "effective level signal" refers to the effective level signal for the corresponding module circuit or device; the effective level signals for different module circuits or devices may be the same or different. "Ineffective level signal" refers to the ineffective level signal for the corresponding module circuit or device; the ineffective level signals for different module circuits or devices may be the same or different. For PMOS, the effective level signal is a low-level signal, and the ineffective level signal is a high-level signal; the effective low-level signals for different PMOS devices may be the same or different. For NMOS, the effective level signal is a high-level signal, and the ineffective level signal is a low-level signal; the effective high-level signals for different NMOS devices may be the same or different.

[0148] One embodiment of this disclosure also provides a gate driving circuit, which includes the shift register in any embodiment of this disclosure.

[0149] The display panel includes a display area, and the gate drive circuit is located in the bezel area outside the display area. Figure 12 This is a schematic diagram of a gate drive circuit in one embodiment of the present disclosure, as shown below. Figure 12 As shown, the gate drive circuit includes multiple cascaded shift registers. Figure 12 Six of the shift registers are shown. For example... Figure 12 As shown, the first output terminal Gout of each shift register provides a gate signal to the corresponding row pixel. The signal input terminal INPUT of shift register GOA1 is connected to the first initial signal STV1, and the first output terminal Gout of shift register GOA1 provides a gate signal G1 to the first row pixel. The second output terminal Out_C of shift register GOA1 is connected to the signal input terminal INPUT of shift register GOA3, and the row reset signal terminal RST of shift register GOA1 is connected to the second output terminal Out_C of shift register GOA3. The first output terminal Gout of shift register GOA3 provides a gate signal G3 to the third row pixel, and the second output terminal Out_C of shift register GOA3 is connected to the signal input terminal INPUT of shift register GOA5, and the row reset signal terminal RST of shift register GOA3 is connected to the second output terminal Out_C of shift register GOA5. The first output terminal Gout of shift register GOA5 provides a gate signal G5 to the fifth row pixel.

[0150] The signal input terminal INPUT of shift register GOA2 is connected to the second initial signal STV2. The first output terminal Gout of shift register GOA2 provides the gate signal G2 to the second row of pixels. The second output terminal Out_C of shift register GOA2 is connected to the signal input terminal INPUT of shift register GOA4. The row reset signal terminal RST of shift register GOA2 is connected to the second output terminal Out_C of shift register GOA4. The first output terminal Gout of shift register GOA4 provides the gate signal G4 to the fourth row of pixels. The second output terminal Out_C of shift register GOA4 is connected to the signal input terminal INPUT of shift register GOA6. The row reset signal terminal RST of shift register GOA4 is connected to the second output terminal Out_C of shift register GOA6. The first output terminal Gout of shift register GOA6 provides the gate signal G6 to the sixth row of pixels.

[0151] Figure 13 This is a schematic diagram of a gate driving circuit in a display panel according to one embodiment of the present disclosure. In another embodiment, such as... Figure 13 As shown, the display panel may include a first border area and a second border area located on both sides of the display area. The gate driving circuit located in the first border area provides gate signals to pixels in odd-numbered rows, and the gate driving circuit located in the second border area provides gate signals to pixels in even-numbered rows. The gate driving circuit located in the first border area includes shift registers GOA1, GOA3, GOA5, GOA7, ...; the gate driving circuit located in the second border area includes shift registers GOA2, GOA4, GOA6, GOA8, ...

[0152] Specifically, the input terminal INPUT of shift register GOA1 is connected to the first initial signal STV1, and the clock signal terminal CLK of shift register GOA1 is connected to the first clock signal GCLK1; the input terminal INPUT of shift register GOA2 is connected to the second initial signal STV2, and the clock signal terminal CLK of shift register GOA2 is connected to the second clock signal GCLK2; the input terminal INPUT of shift register GOA3 is connected to the third initial signal STV3, and the clock signal terminal CLK of shift register GOA3 is connected to the third clock signal GCLK3; the input terminal INPUT of shift register GOA4 is connected to the fourth initial signal STV4, and the clock signal terminal CLK of shift register GOA4 is connected to the fourth clock signal GCLK4. The timing diagrams for the four initial signals and four clock signals can be found in [reference needed]. Figure 14 , Figure 14 for Figure 13 A timing diagram of the middle gate drive circuit. Figure 14 The timing diagram for four initial signals and four clock signals is shown, from... Figure 14As can be seen, the timing of the first initial signal STV1, the second initial signal STV2, the third initial signal STV3, and the fourth initial signal STV4 is arranged sequentially, so the shift registers GOA1, GOA2, GOA3, and GOA4 output gate signals G1, G2, G3, and G4 in sequence.

[0153] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display device, which includes a shift register as described in any embodiment of this disclosure or a gate driving circuit as described in any embodiment of this disclosure. Exemplarily, the display device may include a display panel, and the shift register or gate driving circuit may be disposed in a border area outside the display area of ​​the display panel.

[0154] The display device can be any product or component with a display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable display device, etc.

[0155] In the description of this specification, it should be understood that the terms "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0156] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0157] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0158] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0159] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0160] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register, characterized in that, include: The input circuit, coupled to the signal input terminal, the input power terminal, and the pull-up node respectively, is configured to provide the signal from the input power terminal to the pull-up node under the signal control of the signal input terminal; The first pull-down circuit is coupled to the pull-up node, the third power supply terminal and the first pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the first pull-down node under the signal control of the pull-up node; The first pull-down control circuit is coupled to the first power supply terminal and the first auxiliary node respectively, and is configured to provide the signal of the first power supply terminal to the first auxiliary node under the signal control of the first power supply terminal; The suppression circuit, coupled to the control signal terminal, the first auxiliary node, and the first pull-down node respectively, is configured to disconnect the first auxiliary node and the first pull-down node based on the signal of the control signal terminal when the signal of the pull-up node is an on signal. The first output circuit is coupled to the pull-up node, the clock signal terminal and the first output terminal respectively, and is configured to provide the clock signal terminal to the first output terminal under the control of the enable signal of the pull-up node. The first output pull-down circuit is coupled to the first pull-down node, the fourth power supply terminal, and the first output terminal, respectively, and is configured to provide the signal of the fourth power supply terminal to the first output terminal under the control of the first pull-down node.

2. The shift register according to claim 1, characterized in that, The suppression circuit is further configured to enable the first auxiliary node and the first pull-down node to conduct based on the signal at the control signal terminal when the signal at the pull-up node is a closed signal.

3. The shift register according to claim 1, characterized in that, The suppression circuit includes a nineteenth transistor, the gate of which is coupled to a control node, the control node being coupled to a control signal terminal, and the first and second terminals of the nineteenth transistor being coupled to the first auxiliary node and the first pull-down node, respectively.

4. The shift register according to claim 3, characterized in that, The suppression circuit further includes a state control sub-circuit, which is coupled to the control signal terminal, the first voltage signal, the second voltage signal and the control node respectively. The state control subcircuit is configured to, when the signal at the pull-up node is an on signal, provide the first voltage signal to the control node based on the signal at the control signal terminal, so as to disconnect the first and second terminals of the nineteenth transistor; and / or, The state control subcircuit is configured to provide the second voltage signal to the control node based on the signal at the control signal terminal when the signal at the pull-up node is a closed signal, so as to turn on the first and second terminals of the nineteenth transistor.

5. The shift register according to claim 4, characterized in that, The state control sub-circuit satisfies at least one of the following: The state control sub-circuit includes a first control transistor, the gate of which is coupled to the control signal terminal, and the first and second terminals of which are coupled to the first voltage signal and the control node, respectively. When the signal of the pull-up node is an enable signal, the signal at the control signal terminal controls the first control transistor to conduct. The state control sub-circuit includes a second control transistor, the gate of which is coupled to the control signal terminal, and the first and second terminals of which are coupled to the second voltage signal and the control node, respectively. When the signal of the pull-up node is a turn-off signal, the signal at the control signal terminal controls the second control transistor to turn on.

6. The shift register according to claim 5, characterized in that, The first control transistor includes an NMOS, and the second control transistor includes a PMOS.

7. The shift register according to claim 1, characterized in that, The control signal terminal has the same level as the pull-up node; The signals at the control signal terminal include the first preset signal and the second preset signal, and the level states of the first preset signal and the second preset signal are opposite.

8. The shift register according to claim 7, characterized in that, The control signal terminal is coupled to the pull-up node.

9. The shift register according to claim 1, characterized in that, The suppression circuit includes a nineteenth transistor, the gate of which is coupled to a control node, the control node being coupled to a control signal terminal and an auxiliary control signal terminal, and the first and second terminals of the nineteenth transistor being coupled to the first auxiliary node and the first pull-down node, respectively.

10. The shift register according to claim 9, characterized in that, The suppression circuit further includes a first state control subcircuit and a second state control subcircuit. The first state control subcircuit is coupled to the control signal terminal, the third voltage signal, and the control node, respectively. The second state control subcircuit is coupled to the auxiliary control signal terminal, the fourth voltage signal, and the control node, respectively. When the signal of the pull-up node is an on signal, the first state control sub-circuit is configured to provide a third voltage signal to the control node based on the signal of the control signal terminal, and the second state control sub-circuit is configured to disable the supply of a fourth voltage signal to the control node based on the signal of the auxiliary control signal terminal, so that the first and second terminals of the nineteenth transistor are disconnected. And / or, When the signal of the pull-up node is a closed signal, the first state control sub-circuit is configured to disable the supply of a third voltage signal to the control node based on the signal of the control signal terminal, and the second state control sub-circuit is configured to supply a fourth voltage signal to the control node based on the signal of the auxiliary control signal terminal, so that the first and second terminals of the nineteenth transistor are turned on.

11. The shift register according to claim 10, characterized in that, The first state control sub-circuit includes a third control transistor, the gate of which is coupled to the control signal terminal, and the first and second terminals of which are coupled to the third voltage signal and the control node, respectively. When the signal at the pull-up node is an enable signal, the signal at the control signal terminal controls the third control transistor to turn on; when the signal at the pull-up node is a disable signal, the signal at the control signal terminal controls the third control transistor to turn off.

12. The shift register according to claim 11, characterized in that, The second state control sub-circuit includes a fourth control transistor, a fifth control transistor, a sixth control transistor, and a capacitor. The gate of the fourth control transistor is coupled to the first terminal of the fifth control transistor, the second terminal of the sixth control transistor, and the second terminal of the capacitor. The gate of the fifth control transistor is coupled to the control signal terminal, and the second terminal of the fifth control transistor is coupled to the third voltage signal. The gate of the sixth control transistor is coupled to the auxiliary control signal terminal, and the first terminal of the sixth control transistor is coupled to the fourth voltage signal. The first terminal of the capacitor is coupled to the third voltage signal. When the signal of the pull-up node is an enable signal, the signal at the control signal terminal controls the fifth control transistor to turn on, and the signal at the auxiliary control signal terminal controls the sixth control transistor to turn off, so as to output the third voltage signal to the gate of the fourth control transistor and control the fourth control transistor to turn off. When the signal of the pull-up node is a turn-off signal, the signal at the control signal terminal controls the fifth control transistor to turn off, and the signal at the auxiliary control signal terminal controls the sixth control transistor to turn on, so as to output the fourth voltage signal to the gate of the fourth control transistor, control the fourth control transistor to turn on, and charge the capacitor. When the signal at the pull-up node is a shutdown signal, the signal at the control signal terminal controls the fifth control transistor to turn off, the signal at the auxiliary control signal terminal controls the sixth control transistor to turn off, and the capacitor discharges to keep the fourth control transistor on.

13. The shift register according to claim 12, characterized in that, The third, fourth, fifth, and sixth control transistors include NMOS.

14. The shift register according to claim 12, characterized in that, The signal at the control signal terminal is the same as the level state of the pull-up node; the signal at the control signal terminal includes the first preset signal and the second preset signal, and the level states of the first preset signal and the second preset signal are opposite. The auxiliary control signal terminal includes a third preset signal and a fourth preset signal. The level of the third preset signal is opposite to that of the first preset signal, and the level of the fourth preset signal is opposite to that of the third preset signal.

15. The shift register according to claim 14, characterized in that, The control signal terminal is coupled to the pull-up node.

16. The shift register according to any one of claims 1-15, characterized in that, Also includes: The second pull-down circuit is coupled to the pull-up node, the third power supply terminal, and the second pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the second pull-down node under the signal control of the pull-up node; The second pull-down control circuit is coupled to the second power supply terminal and the second auxiliary node respectively, and is configured to provide the signal of the second power supply terminal to the second auxiliary node under the signal control of the second power supply terminal; The second output pull-down circuit is coupled to the second pull-down node, the fourth power supply terminal and the first output terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first output terminal under the control of the second pull-down node. The suppression circuit is also coupled to the second auxiliary node and the second pull-down node, and is further configured to disconnect the second auxiliary node and the second pull-down node based on the signal at the control signal terminal when the signal of the pull-up node is an on signal; and / or, the suppression circuit is further configured to turn on the second auxiliary node and the second pull-down node based on the signal at the control signal terminal when the signal of the pull-up node is a off signal.

17. The shift register according to claim 16, characterized in that, The suppression circuit includes a twenty-ninth transistor, the gate of which is coupled to a control node, and the first and second terminals of which are coupled to the second auxiliary node and the second pull-down node, respectively.

18. The shift register according to claim 16, characterized in that, It also includes at least one of the following: The first auxiliary pull-down circuit is coupled to the signal input terminal, the third power supply terminal and the first pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the first pull-down node under the signal control of the signal input terminal; A first noise reduction circuit is coupled to the first pull-down node, the third power supply terminal, and the pull-up node, respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the signal control of the first pull-down node. The second auxiliary pull-down circuit is coupled to the signal input terminal, the third power supply terminal and the second pull-down node respectively, and is configured to provide the signal of the third power supply terminal to the second pull-down node under the signal control of the signal input terminal; The second noise reduction circuit is coupled to the second pull-down node, the third power supply terminal and the pull-up node respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the signal control of the second pull-down node; A horizontal reset circuit is coupled to the horizontal reset signal terminal, the third power supply terminal, and the pull-up node, respectively, and is configured to provide the signal of the third power supply terminal to the pull-up node under the signal control of the horizontal reset signal terminal; A frame reset circuit, coupled to the frame reset signal terminal, the third power supply terminal, and the pull-up node, is configured to provide the signal from the third power supply terminal to the pull-up node under the signal control of the frame reset signal terminal. The output reset circuit is coupled to the row reset signal terminal, the fourth power supply terminal and the first output terminal respectively, and is configured to provide the signal of the fourth power supply terminal to the first output terminal under the signal control of the row reset signal terminal.

19. The shift register according to claim 16, characterized in that, The voltage levels of the first power supply terminal and the second power supply terminal are opposite.

20. The shift register according to claim 18, characterized in that, Meet at least one of the following: The input circuit includes a first transistor, the gate of which is coupled to the signal input terminal, and the first and second terminals of the first transistor are coupled to the input power supply terminal and the pull-up node, respectively. The first pull-down circuit includes a sixteenth transistor, the gate of which is coupled to the pull-up node, and the first and second terminals of the sixteenth transistor are coupled to the third power supply terminal and the first pull-down node, respectively. The first pull-down control circuit includes a fifteenth transistor, the gate and first terminal of the fifteenth transistor are both coupled to the first power supply terminal, and the second terminal of the fifteenth transistor is coupled to the first auxiliary node; The first auxiliary pull-down circuit includes a seventeenth transistor, the gate of which is coupled to the signal input terminal, and the first and second terminals of which are coupled to the third power supply terminal and the first pull-down node, respectively. The first noise reduction circuit includes an eighteenth transistor, the gate of which is coupled to the first pull-down node, and the first and second terminals of which are coupled to the third power supply terminal and the pull-up node, respectively. The second pull-down circuit includes a twenty-sixth transistor, the gate of which is coupled to the pull-up node, and the first and second terminals of which are coupled to the third power supply terminal and the second pull-down node, respectively. The second pull-down control circuit includes a twenty-fifth transistor, the gate and first terminal of the twenty-fifth transistor are both coupled to the second power supply terminal, and the second terminal of the twenty-fifth transistor is coupled to the second auxiliary node; The second auxiliary pull-down circuit includes a twenty-seventh transistor, the gate of which is coupled to the signal input terminal, and the first and second terminals of which are coupled to the third power supply terminal and the second pull-down node, respectively. The second noise reduction circuit includes a twenty-eighth transistor, the gate of which is coupled to the second pull-down node, and the first and second terminals of which are coupled to the third power supply terminal and the pull-up node, respectively. The first output circuit includes a third transistor, the gate of which is coupled to the pull-up node, and the first and second terminals of which are coupled to the clock signal terminal and the first output terminal, respectively. The first output pull-down module includes an eleventh transistor, the gate of which is coupled to the first pull-down node, and the first and second terminals of which are coupled to the fourth power supply terminal and the first output terminal, respectively. The second output pull-down module includes a twenty-first transistor, the gate of which is coupled to the second pull-down node, and the first and second terminals of which are coupled to the fourth power supply terminal and the first output terminal, respectively. The row reset circuit includes a second transistor, the gate of which is coupled to the row reset signal terminal, and the first and second terminals of the second transistor are coupled to the third power supply terminal and the pull-up node, respectively. The frame reset circuit includes a seventh transistor, the gate of which is coupled to the frame reset signal terminal, and the first and second terminals of which are coupled to the third power supply terminal and the pull-up node, respectively. The output reset circuit includes a fourth transistor, the gate of which is coupled to the row reset signal terminal, and the first and second terminals of which are coupled to the fourth power supply terminal and the first output terminal, respectively.

21. A method for driving a shift register, characterized in that, Applied to the shift register of any one of claims 1-20, the method comprises: In the first stage, a valid level signal is provided to the signal input terminal. Under the control of the valid level signal at the signal input terminal, the input circuit provides the input power terminal signal to the pull-up node. Under the control of the signal from the pull-up node, the first pull-down circuit provides the third power terminal signal to the first pull-down node. A first preset signal is provided to the control signal terminal to disconnect the first auxiliary node from the first pull-down node. In the second stage, a valid level signal is provided to the horizontal reset signal terminal. Under the control of the valid level signal at the horizontal reset signal terminal, the horizontal reset circuit provides the signal of the third power supply terminal to the pull-up node. Under the control of the signal at the first power supply terminal, the first pull-down control circuit provides the signal of the first power supply terminal to the first auxiliary node. A second preset signal is provided to the control signal terminal, so that the first auxiliary node and the first pull-down node are turned on.

22. A method for driving a shift register, characterized in that, Applied to the shift register of any one of claims 1-20, the method comprises: In the first stage, a valid level signal is provided to the signal input terminal. Under the control of the valid level signal at the signal input terminal, the input circuit provides the input power terminal signal to the pull-up node. Under the signal control of the pull-up node, the first pull-down circuit provides the third power terminal signal to the first pull-down node. A first preset signal is provided to the control signal terminal, and a third preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are disconnected. In the second stage, a valid level signal is provided to the horizontal reset signal terminal. Under the control of the valid level signal at the horizontal reset signal terminal, the horizontal reset circuit provides the signal of the third power supply terminal to the pull-up node. Under the control of the signal at the first power supply terminal, the first pull-down control circuit provides the signal of the first power supply terminal to the first auxiliary node. A second preset signal is provided to the control signal terminal, and a fourth preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are turned on. In the third stage, a second preset signal is provided to the control signal terminal and a third preset signal is provided to the auxiliary control signal terminal, so that the first auxiliary node and the first pull-down node are connected.

23. A gate driving circuit, characterized in that, Includes the shift register according to any one of claims 1-20.

24. A display device, characterized in that, It includes the shift register of any one of claims 1-20 or the gate drive circuit of claim 23.

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