Driving method of electronic paper display panel and display device

Abstract

The application provides a driving method of an electronic paper display panel and a display device, wherein in the driving method of the electronic paper display panel, a row scanning signal is first output to scan each pixel unit row by row and write a plurality of column data signals into the pixel unit, the pixel voltage of each row of pixel units in a current display frame target display area is sensed, the pixel voltage to be written into each row of pixel units in a next writing frame target display area is obtained, and voltage comparison is performed; when the voltage ratio of the pixel voltage of each pixel unit in the i-th row of the target display area in the next writing frame and the pixel voltage in the current display frame is within a preset voltage range, the row scanning signal to the i-th row of pixel units in the target display area is stopped from being output in the next writing frame, and a non-refresh row is skipped, so that the invalid writing operation of the electronic paper display panel is reduced, power consumption is reduced, and the requirements of high resolution, low power consumption and miniaturization of the electronic paper display panel are met.

Description

Technical Field

[0001] This invention belongs to the field of electronic paper display panel technology, and particularly relates to a driving method and display device for an electronic paper display panel. Background Technology

[0002] Electronic paper electrophoretic display technology belongs to the reflective bistable display technology. This technology relies on a thin-film transistor active array to drive the directional migration of charged black-and-white or colored electrophoretic particles inside microcapsules, thereby completing the image and color imaging on the screen. This display technology has unique bistable display characteristics. After the displayed image is formed, the power supply to the driving chip and display panel can be completely cut off, and the displayed image can still be maintained stably for a long time without the need for continuous power supply to maintain the display. Based on this characteristic, electronic paper display devices have many advantages, such as ultra-low power consumption, paper-like eye-friendly display effect, high-definition viewing in strong light environments, flexible and thin body, and bendable adaptation to various terminal forms.

[0003] The working frame mechanism of electronic paper display devices differs significantly from that of conventional electrically charged display devices. The display frame duration of electronic paper is much longer than the data write frame duration. Only when the microcapsules are subjected to a stable electric field will the internal color particles undergo directional migration to complete the image update; once the image stabilizes, no electric field is needed to maintain it. In the most mainstream application scenario of electronic paper—electronic shelf labels—the device's daily operation only requires modifying the price and category information of local products; the pixel colors of most areas of the screen do not need to be updated. However, traditional electronic paper driving solutions use a globally unified refresh mechanism, performing data write and refresh operations on all pixels of the screen regardless of whether pixel colors need updating, resulting in a large number of invalid write operations.

[0004] Frequent invalid write operations not only significantly increase the overall power consumption of the device, but also cause repeated fluctuations in pixel voltage, which can easily lead to static electricity buildup and device breakdown. Furthermore, continuous invalid charging and discharging accelerates the aging of screen components and reduces the device's lifespan. Meanwhile, to alleviate the screen fluctuations and voltage instability issues caused by traditional global refresh, existing high-resolution e-paper display panels require large-sized storage capacitors. However, large storage capacitors limit the panel's thinness and lightness design, and also restrict further improvements in e-paper resolution, making it impossible to simultaneously meet the requirements of high-resolution display and low power consumption / miniaturization. Summary of the Invention

[0005] The purpose of this invention is to provide a driving method for an electronic paper display panel, which aims to solve the problem that invalid write operations in traditional electronic paper display panels make it impossible to simultaneously meet the requirements of high-resolution display, low power consumption, and miniaturization.

[0006] A first aspect of this invention provides a driving method for an electronic paper display panel, the electronic paper display panel including pixel units arranged in an array, the driving method for the electronic paper display panel including: The output row scan signal scans and activates each pixel unit line by line, and writes multiple columns of data signals to the pixel unit. The pixel voltage of each row corresponding to the pixel unit in the target display area of ​​the current display frame is sensed, and the pixel voltage of each row of the pixel unit to be written in the target display area of ​​the next write frame is obtained and the voltage is compared. The target display area is the area to be updated in the electronic paper display panel. When the voltage ratio of the pixel voltage in the next write frame to the pixel voltage in the current display frame of each pixel unit in the i-th row of the target display area is within a preset voltage range, in the next write frame, the output row scan signal to the pixel unit in the i-th row of the target display area is cut off; When the voltage ratio of the pixel voltage in the next write frame to the pixel voltage in the current display frame of each pixel unit in the i-th row of the target display area is not within a preset voltage range, a row scan signal is output to the pixel unit in the i-th row of the target display area in the next write frame, where i is a positive integer.

[0007] Optionally, the driving method for the electronic paper display panel further includes: The number of non-refreshing rows in the target display area is counted, and the refresh row activation duration is determined based on the total number of rows in the target display area, the number of non-refreshing rows, and the refresh rate of the electronic paper display panel. In the non-refreshing behavior, the voltage ratio of the pixel voltage of the next write frame of each pixel unit to the pixel voltage of the current display frame is within the corresponding row of the preset voltage range; The refresh behavior is such that the voltage ratio of the pixel voltage in the next write frame to the pixel voltage in the current display frame for each pixel unit is not within the corresponding row of the preset voltage range.

[0008] Optionally, determining the refresh line activation duration based on the total number of rows in the target display area, the number of non-refresh lines, and the refresh rate of the electronic paper display panel includes: The first activation duration is determined based on the refresh rate and the total number of rows in the target display area; The number of refresh rows is determined based on the total number of rows and the number of non-refresh rows, and the second activation duration is determined based on the refresh rate and the number of refresh rows. The opening stretching duration of the refresh row is determined based on the time difference between the first opening duration and the second opening duration; The activation duration of the refresh row is determined based on the activation stretch duration and the time and value of the first activation duration.

[0009] Optionally, the driving method for the electronic paper display panel further includes: Based on the number of non-refreshing rows from the first row to the nth row, determine the start time of the refresh row in the nth row, where n is a positive integer.

[0010] Optionally, determining the start time of refreshing the nth row based on the number of non-refresh rows from the first row to the nth row includes: The number of refreshed rows in the first to nth rows is determined based on the number of non-refreshed rows in the first to nth rows, and the first total duration is determined based on the number of refreshed rows in the first to nth rows and the second activation duration; The second total duration is determined based on the nth row number and the first activation duration, and the activation time of the nth refresh row is determined based on the time difference between the first total duration and the second total duration.

[0011] A second aspect of the present invention provides a display device including an electronic paper display panel and a driving circuit for the electronic paper display panel. The driving circuit for the electronic paper display panel is used to execute the driving method for the electronic paper display panel as described above. The electronic paper display panel includes pixel units arranged in an array.

[0012] Optionally, the pixel unit includes a storage capacitor and a write switch, the write switch being used to input a corresponding row scan signal and a data signal; The pixel unit further includes a pixel sensing unit, which is used to sense the pixel voltage of the pixel unit and output the sensing result to the driving circuit of the electronic paper display panel. The driving circuit of the electronic paper display panel is used to determine the pixel voltage of the pixel unit based on the sensing result.

[0013] Optionally, the pixel sensing unit includes a sensing capacitor, a trigger switch, an output switch, and a driving transistor; The trigger switch is used to transmit the voltage of the pixel unit to the sensing capacitor; The control terminal of the driving transistor is connected to the sensing capacitor and is used to generate a sensing signal based on the voltage on the sensing capacitor. The output switch is used to output the sensing signal to the driving circuit of the electronic paper display panel.

[0014] Optionally, the pixel sensing unit further includes multiple reset transistors, each of which is connected to a different node of the sensing capacitor, for resetting each node before sensing, so that each node is reset to a preset voltage.

[0015] Optionally, the driving circuit of the electronic paper display panel is also used to control the pixel sensing unit to work sequentially in the reset phase, sensing phase and output phase at the end of the current display frame. During the reset phase, each node is controlled to reset to a preset voltage; During the sensing phase, the trigger switch is turned on to couple the voltage of the pixel unit to the sensing capacitor; During the output phase, the output switch is controlled to turn on to output the sensing signal.

[0016] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: In the above-mentioned driving method of electronic paper display panel, firstly, the row scanning signal is output to scan and open each pixel unit line by line and write multiple columns of data signals to the pixel unit. The pixel voltage of the corresponding pixel unit in each row of the target display area of ​​the current display frame is sensed, and the pixel voltage to be written in each row of the pixel unit in the target display area of ​​the next writing frame is obtained and the voltage is compared. When the voltage ratio of the pixel voltage of each pixel unit in the i-th row of the target display area in the next writing frame to the pixel voltage of the current display frame is within the preset voltage range, in the next writing frame, the row scanning signal to the i-th row of the target display area is stopped, the non-refresh row is skipped, the invalid writing operation of electronic paper display panel is reduced, the power consumption is reduced, and the requirements of high resolution, low power consumption and miniaturization of electronic paper display panel are met. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of the electronic paper display panel provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the first process of driving a digital paper display panel according to Embodiment 1 of the present invention. Figure 3 This is a schematic diagram of the first signal waveform of the driving method for the electronic paper display panel provided in Embodiment 1 of the present invention; Figure 4 This is a circuit diagram of a pixel unit provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of a second process for driving an electronic paper display panel according to Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of a third process for driving an electronic paper display panel according to Embodiment 1 of the present invention. Figure 7 This is a schematic diagram of a second signal waveform for the driving method of the electronic paper display panel provided in Embodiment 1 of the present invention; Figure 8 This is a schematic diagram of the first structure of the display device provided in Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of the first type of circuit for a pixel unit provided in Embodiment 2 of the present invention; Figure 10 This is a schematic diagram of a second type of circuit for a pixel unit provided in Embodiment 2 of the present invention; Figure 11 This is a waveform diagram of the reset signal provided in Embodiment 2 of the present invention; Figure 12 This is a schematic diagram of a second structure of the display device provided in Embodiment 2 of the present invention; Figure 13 This is a schematic diagram of the signal waveform of the display device provided in Embodiment 2 of the present invention.

[0018] The figures in the diagram are labeled as follows: 100. Electronic paper display panel; 200. Driving circuit of electronic paper display panel; 210. Gate driving circuit; 220. Source driving circuit; 230. Voltage detection circuit; 240. Timing controller; 110. Pixel unit; 111. Pixel sensing unit; G1, First scan line; G2, Second scan line; G3, Third scan line; GM-2, M-2nd scan line; GM-1, M-1st scan line; GM, Mth scan line; T1, Write switch; Cst, Storage capacitor; S1, First data line; S2, Second data line; SN, Nth data line; Vd, Pixel voltage; G, Scan line; S, Data line; Vdd, Power supply voltage; Tf1, Current display frame; Tw, Next write frame; Tf2, Next display frame; a, Stretch start duration; c, Displacement amount; h1, First start duration; h2, Second start duration; Vsen, Sensing signal; Q1, Global write master switch; Q2, Global sensing master switch; C1, Sensing capacitor; T2, Trigger switch; 101, Output switch; T3, Driver transistor; T4, First output switch; T5, Second output switch; A, First node; B, Second node; C, Third node; Vcom, Common Voltage; Vref1, Reference Voltage; rst1, First Reset Signal; rst2, Second Reset Signal; rst3, Third Reset Signal; rst4, Fourth Reset Signal; SW, Sensing Switch Signal; Ctr1, Total Write Switch Signal; Ctr2, Total Sensing Switch Signal; Tf11, Sensing Period; Tf12, Frame Matching Period; SW1, Sensing Switch Signal for the First Row; SW2, Sensing Switch Signal for the Second Row; SW3, Sensing Switch Signal for the Third Row; SWM-2, Sensing Switch Signal for the (M-2)th Row; SWM-1, Sensing Switch Signal for the (M-1)th Row; SWM, Sensing Switch Signal for the Mth Row; Vgh, Row On Signal; Vgl, Row Off Signal; G02, Second Scan Control Signal Line; Tr1, First Reset Transistor; Tr2, Second Reset Transistor; Tr3, Third Reset Transistor; Tr4, Fourth Reset Transistor. Detailed Implementation

[0019] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] Example 1 A first aspect of this invention provides a driving method for an electronic paper display panel 100, such as... Figure 1As shown, the electronic paper display panel 100 includes pixel units 110 arranged in an array, such as... Figure 1 As shown, the array is arranged in a multi-row, multi-column matrix. Each row of pixel units 110 corresponds to one scan line, and each column of pixel units 110 corresponds to one data line. Each pixel unit 110 independently responds to the row scan signal and the data signal to complete the display and update of the screen. The scan line G may include the first scan line G1, the second scan line G2, the Mth scan line GM, etc., and the data line S may include the first data line S1, the second data line S2, and the Nth data line SN.

[0022] like Figure 2 As shown, in this embodiment, the driving method for the electronic paper display panel 100 includes: S10, Output row scanning signal to scan and enable each pixel unit 110 line by line and write multiple columns of data signals to pixel unit 110; S20. Sensing the pixel voltage Vd of each row of corresponding pixel units 110 in the target display area of ​​the current display frame Tf1, and obtaining the pixel voltage Vd to be written in each row of pixel units 110 in the target display area of ​​the next write frame Tw, and performing voltage comparison. The target display area is the area to be updated in the electronic paper display panel 100.

[0023] In this embodiment, as Figure 3 As shown, the electronic paper display panel 100 operates sequentially in the write frame and the display frame. Tf1 represents the current display frame, Tw represents the next write frame, and Tf2 represents the next display frame. In the initial state, the electronic paper display panel 100 operates in the write frame and performs normal image writing. The driving circuit 200 of the electronic paper display panel outputs line scanning signals line by line through multiple scan lines. GM-1 represents the (M-1)th scan line, and GM represents the Mth scan line.

[0024] The electronic paper display panel 100 scans and turns on each pixel unit 110 in the target display area in a preset row scanning order. When each row of pixel units 110 is turned on, the corresponding data signal is written to all pixel units 110 in that row through multiple data lines to complete the full display of the current display frame Tf1.

[0025] Specifically, the driving circuit 200 of the electronic paper display panel sequentially outputs row enable signals Vgh to the first row, the second row, and so on up to the Mth row, turning on the corresponding row's write switch T1. Simultaneously, the driving circuit 200 outputs corresponding data voltages to each column's data lines. These data voltages are written into the storage capacitor Cst of the pixel unit 110 through the turned-on write switch T1, completing the voltage writing of that row's pixels. After one row is written, the driving circuit 200 turns off the row scan signal for that row and turns on the row scan signal for the next row, thus progressing row by row until all rows are written.

[0026] The display frame of electronic paper is much longer than the write frame. At the end of the current display frame Tf1, a pixel voltage Vd sensing operation is performed to sense the pixel voltage Vd of each row of corresponding pixel units 110 in the target display area of ​​the current frame. The target display area is the effective screen area of ​​the electronic paper display panel 100 that currently needs to participate in image display and updates; it can be fully covered or partially limited according to actual display requirements.

[0027] In an optional embodiment, the target display area can be dynamically set. For example, in electronic shelf label applications, only the area containing the price digits can be sensed and refreshed, while other areas remain displayed without being sensed, further reducing power consumption. The range of the target display area can be automatically determined by the timing controller 240 based on the changing area of ​​the image to be displayed, or it can be pre-specified by the upper-level system.

[0028] like Figure 4 As shown, the sensing operation can be completed by the pixel sensing unit 111, which is integrated with each pixel unit 110. The pixel sensing unit 111 converts the pixel voltage Vd of the pixel unit 110 into a sensing signal Vsen and outputs it to the driving circuit 200 of the electronic paper display panel. The driving circuit 200 of the electronic paper display panel reads the sensing signal Vsen through the voltage detection circuit 230, and after analog-to-digital conversion and arithmetic processing, obtains the actual pixel voltage Vd of each row and column of the pixel unit 110 in the current display frame Tf1.

[0029] Simultaneously, the preset pixel voltage Vd to be written for each row of pixel units 110 in the target display area of ​​the next write frame Tw is retrieved. The pixel voltage Vd to be written in the next frame is determined by the image data to be displayed. The timing controller 240 calculates the target voltage value to be written for each pixel unit 110 based on the image data of the next frame.

[0030] After obtaining the pixel voltage Vd of the current display frame Tf1 and the pixel voltage Vd to be written in the next write frame Tw, a frame matching algorithm is executed to compare the pixel voltage Vd of the current display frame Tf1 with the pixel voltage Vd to be written in the next write frame Tw for each pixel unit 110 in the same row. The voltage comparison is performed row by row. For the i-th row of the target display area, the voltage ratio of the pixel voltage Vd of the current display frame Tf1 to the pixel voltage Vd to be written in the next write frame Tw for each column of pixel units 110 in that row is compared one by one.

[0031] S30. When the voltage ratio of the pixel voltage Vd of each pixel unit 110 in the i-th row of the target display area in the next write frame Tw to the pixel voltage Vd of the current display frame Tf1 is within the preset voltage range, in the next write frame Tw, the output row scan signal to the pixel unit 110 in the i-th row of the target display area is cut off. S40. When the voltage ratio of the pixel voltage Vd of each pixel unit 110 in the i-th row of the target display area in the next write frame Tw to the pixel voltage Vd of the current display frame Tf1 is not within the preset voltage range, in the next write frame Tw, a row scan signal is output to the pixel unit 110 in the i-th row of the target display area, where i is a positive integer.

[0032] A preset voltage range is used to determine whether a row of pixels needs to be refreshed. The preset voltage range can be set according to requirements. In one specific implementation, the preset voltage range can be set to 90% to 110% of the pixel voltage Vd of the current display frame Tf1, that is, the ratio of the pixel voltage Vd to be written in the next write frame to the pixel voltage Vd of the current display frame is between 0.9 and 1.1. In other words, when the pixel voltage Vd to be written in the next write frame Tw satisfies the condition that 90% × the pixel voltage Vd of the current display frame Tf1 is less than the pixel voltage Vd to be written in the next write frame Tw, and the pixel voltage Vd to be written in the next write frame Tw is less than 110% × the pixel voltage Vd of the current display frame Tf1, the voltage change of the pixel is considered to be within an acceptable range and no refresh is required.

[0033] The reason for setting upper and lower limit coefficients is that when the same pixel is written with the same color, the voltage maintenance rate of the storage capacitor Cst can meet the display requirements, and no additional refresh is needed. The specific values ​​of the upper and lower limit coefficients are determined based on the leakage resistance of the process device and the display uniformity requirements. For the electronic paper display panel 100 with strong leakage resistance and charge maintenance capabilities, the voltage fluctuation range can be appropriately expanded to further reduce the number of invalid refresh lines and optimize power consumption. For the electronic paper display panel 100 with high-precision display and low grayscale deviation requirements, the voltage fluctuation range can be narrowed to ensure the ultimate image display accuracy.

[0034] Differential frame write control is performed based on voltage comparison results. For the i-th row of pixel units 110 in the target display area, where i is a positive integer, the refresh execution status of each row is determined. If the voltage ratio of the pixel voltage Vd of the next write frame Tw to the pixel voltage Vd of the current display frame Tf1 for all pixel units 110 in the i-th row falls within the system's preset voltage range, then the row is determined to be a row that does not need to be updated and is considered a row that does not require refresh. During the overall write operation of the next write frame Tw, the driving circuit 200 of the electronic paper display panel stops outputting the row scan signal to the i-th row of pixel units 110 in the target display area. The pixel units 110 in this row maintain the current display frame Tf1 state and do not perform any data writing or refresh actions. That is, the row is skipped and no write operation is performed. The skipped row is called a non-refresh row.

[0035] For example Figure 7 As shown, when the voltage ratio of the pixel voltage Vd of all pixel units 110 in the second row for the next write frame Tw to the pixel voltage Vd of the current display frame Tf1 falls within the system's preset voltage range, it is determined that the row does not need to be updated and is a row that does not need to be refreshed. During the overall write operation of the next write frame Tw, the driving circuit 200 of the electronic paper display panel cuts off the output of the row scan signal to the second row pixel units 110 in the target display area. The pixel units 110 in this row maintain the current display frame Tf1 state and do not perform any data writing or refresh operations. That is, the row is skipped and no write operation is performed. The skipped row is called a non-refresh row.

[0036] If the ratio of the pixel voltage Vd of the next write frame Tw to the pixel voltage Vd of the current display frame Tf1 in any one or more pixel units 110 of the i-th row of the target display area exceeds the system's preset voltage range, then it is determined that the row of the image has an update requirement and is a row that needs to be refreshed. During the overall write operation of the next write frame Tw, the driving circuit 200 of the electronic paper display panel normally outputs a row scan signal to the pixel units 110 of the i-th row of the target display area, and completes the data writing and image refresh operation of the pixel units 110 of that row in conjunction with the data line. Normal write operation is performed on that row. The row that needs to be written is called the refresh row.

[0037] Through the aforementioned selective refresh mechanism, the electronic paper display panel 100 only writes to rows whose display state actually needs to be changed during refresh, avoiding invalid writes to rows that do not require modification. This eliminates meaningless pixel charging and discharging actions at the source, effectively reducing refresh power consumption. In typical application scenarios such as electronic shelf labels, each refresh only involves a few rows containing price figures, while the display content of most rows remains unchanged. The driving method of the electronic paper display panel 100 can skip a large number of non-refreshing rows, significantly reducing refresh power consumption. At the same time, it reduces invalid charging and discharging of pixel units 110, improving the lifespan of the components in pixel units 110. Furthermore, it eliminates the need for large-sized storage capacitors Cst, further enabling the thinner and lighter design of the electronic paper display panel 100 and achieving high resolution.

[0038] During the pixel voltage Vd sensing process, the driving method of the electronic paper display panel 100 supports two precise detection modes: current-type monitoring mode and voltage-type monitoring mode, which can be flexibly selected according to the hardware configuration of the driving circuit 200 of the electronic paper display panel. The current-type monitoring mode detects the turn-on current of the transistor in the pixel sensing unit 111 under saturation operation, and calculates the pixel voltage Vd of the current display frame Tf1 using the transistor device formula. The turn-on current satisfies the formula: Ion = 1 / 2 × μ n ×Cox×W / L(VGS-Vth) 2 ; Where μ n To drive the channel mobility of the transistor, C ox Vth is the gate oxide capacitance per unit area, W and L are the channel width and length of the driving transistor, respectively, Vth is the threshold voltage of the driving transistor, VGS is equal to the difference between Vdd and the pixel voltage Vd, where Vdd is the power supply voltage. The pixel voltage Vd can be deduced by measuring the turn-on current Ion.

[0039] The voltage-type monitoring mode directly acquires the real-time voltage of pixel unit 110 through an external voltage divider capacitor and feedback sampling circuit. After subtracting the transistor threshold voltage, the accurate pixel voltage Vd value is obtained. Both detection modes can independently and accurately acquire the pixel voltage Vd. The acquired voltage data is transmitted in real time to the register of the timing controller 240 inside the driving circuit 200 of the electronic paper display panel for storage, providing accurate data support for subsequent frame matching algorithms and voltage comparison.

[0040] The frame matching algorithm employs a unified line-wide judgment mechanism. A line is considered skippable only if the voltage ratios of all pixel units 110 in a given line fall within a preset range. If even a single pixel in the line has a voltage Vd ratio exceeding the limit, the line is deemed to require a refresh. This mechanism maximizes display accuracy, preventing image distortion and ghosting caused by local pixel grayscale deviations, while balancing low power consumption with high display quality.

[0041] When skipping the corresponding non-refreshed rows, using the traditional fixed-duration refresh method would result in insufficient charging, uneven display, and wasted time. Therefore, to reduce wasted time, in an optional embodiment, the driving method for the electronic paper display panel 100 further includes: S50. Count the number of non-refresh lines in the target display area, and determine the refresh line activation duration based on the total number of lines in the target display area, the number of non-refresh lines, and the refresh rate of the electronic paper display panel 100. Among them, the voltage ratio of the pixel voltage Vd of the next write frame Tw of each pixel unit 110 in the non-refreshing behavior to the pixel voltage Vd of the current display frame Tf1 is within the corresponding row of the preset voltage range. The voltage ratio of the pixel voltage Vd of the next write frame Tw to the pixel voltage Vd of the current display frame Tf1 for each pixel unit 110 during refresh behavior is not within the preset voltage range for the corresponding row.

[0042] In this embodiment, after the frame matching algorithm determines whether each row needs to be refreshed, the driving circuit 200 of the electronic paper display panel counts the number of non-refreshed rows in the target display area. A non-refreshed row refers to a row where the voltage ratio of the pixel voltage Vd of the next write frame Tw of each pixel unit 110 to the pixel voltage Vd of the current display frame Tf1 is within a preset voltage range; that is, rows that are skipped and not written. A refreshed row refers to a row where the voltage ratio of the pixel voltage Vd of the next write frame Tw of each pixel unit 110 to the pixel voltage Vd of the current display frame Tf1 is not within a preset voltage range; that is, rows that need to be written normally.

[0043] Let M be the total number of rows in the target display area, and x be the number of non-refreshing rows. Then the number of refreshing rows is M minus x. The refresh rate of the electronic paper display panel 100 is f, which is the number of frames refreshed per second.

[0044] In the traditional line-by-line refresh scheme, the opening time of each line is determined by the refresh rate and the total number of lines, that is, the opening time of each line is 1 / (f×M). This is because the total time of one frame is 1 divided by f, and M lines need to be written line by line within one frame. Therefore, the average opening time allocated to each line is 1 divided by f and then divided by M.

[0045] In this embodiment, since row x is skipped and not written, only row Mx ​​needs to be written. If the total time of a frame is allocated to refresh rows, the on-time of each refresh row can be extended to 1 / (f×(Mx)). Extending the on-time means that the write switch T1 is on for a longer period of time, and the storage capacitor Cst can be charged to a value closer to the target voltage, which is beneficial to improving the fullness of charging and display uniformity.

[0046] Therefore, the activation duration of the refresh line is determined based on the total number of rows M in the target display area, the number of non-refresh lines x, and the refresh rate f of the electronic paper display panel 100. The activation duration of the refresh line is longer than the activation duration of each line in the traditional progressive refresh scheme; the extra time comes from the time saved by skipped lines.

[0047] Taking a specific value as an example, assuming an e-paper display panel has 200 lines and a refresh rate of 50Hz, the traditional solution's on-time for each line is 1 / (50×200) = 0.1ms. If a frame matching algorithm determines that there are 150 non-refreshing lines, then the number of refreshing lines is 50, and the on-time for each refresh line can be extended to 1 / (50×50) = 0.4ms, which is four times that of the traditional solution. The longer on-time allows for more complete charging of the storage capacitor Cst, achieving satisfactory charging even with a smaller Cst, thus contributing to improved panel resolution.

[0048] Specifically, the refresh rate of the e-paper display panel 100 is a fixed factory parameter, representing the number of frames that the device can refresh per second. The total refresh duration of a single frame is the reciprocal of the refresh rate and remains constant. In traditional driving mode, the total duration of a single frame is evenly distributed among all pixel rows of the screen, with each row having a fixed activation duration. This embodiment, by counting invalid rows and reallocating timing resources, allows valid refresh rows to have a longer working duration, completely resolving the display defect caused by insufficient charging time per pixel in high-resolution panels. Furthermore, it achieves optimized display effects and reduced power consumption at low cost without increasing the driving voltage or changing the hardware architecture.

[0049] The activation duration can be determined based on the number of non-refreshing rows and the refresh rate. In one optional embodiment, such as... Figure 5 As shown, S50 includes: S51. Determine the first opening duration based on the refresh rate and the total number of rows in the target display area; S52. Determine the number of refresh rows based on the total number of rows and the number of non-refresh rows, and determine the second activation duration based on the refresh rate and the number of refresh rows; S53. Determine the refresh row's opening stretching duration a based on the time difference between the first opening duration and the second opening duration; S54. Determine the refresh row's start duration based on the start stretch duration and the time and value of the first start duration.

[0050] In this embodiment, a precise method for quantifying and calculating the refresh row activation duration is provided. Through multi-level timing calculations, precise quantitative control of the refresh row activation duration is achieved, ensuring the rationality and accuracy of timing allocation. The specific steps are as follows: The first step is to determine the first opening duration h1 based on the refresh rate f and the total number of rows M in the target display area. The first opening duration h1 = 1 / (f × M). The first opening duration corresponds to the opening duration of each row in the traditional progressive refresh scheme and is the base time for calculation.

[0051] The second step is to determine the number of refresh rows based on the total number of rows M and the number of non-refresh rows x. The number of refresh rows is equal to Mx. The second activation duration h2 is then determined based on the refresh rate f and the number of refresh rows Mx. The second activation duration h2 = 1 / (f × (Mx)). The second activation duration corresponds to the maximum activation duration that each row can obtain when all the total time of a frame is allocated to the refresh rows.

[0052] The third step is to determine the refresh row's start-up stretching duration 'a' based on the time difference between the first start-up duration h1 and the second start-up duration h2. For example... Figure 7 As shown, the stretching duration 'a' is equal to h2 minus h1. The stretching duration 'a' represents the additional write time that can be gained per row refresh compared to the traditional method.

[0053] The fourth step is to determine the start duration of the refresh line based on the sum of the start stretch duration 'a' and the first start duration h1. The start duration of the refresh line is equal to h1 plus a, which equals h2. In other words, the final start duration of the refresh line is equal to the second start duration, which is the start duration of one frame divided by the number of refresh lines for each refresh line.

[0054] It should be noted that, since some areas may require several rows to be opened and closed consecutively, timing shift control is necessary to prevent incorrect filling. Therefore, the actual opening time of a refresh row needs to be adjusted based on the number of non-refresh rows preceding it, but the opening duration of each refresh row remains the calculated h2.

[0055] The above calculation process is completed by the timing controller 240. After obtaining the number of non-refresh lines x, the timing controller 240 calculates the first enable duration h1, the second enable duration h2, the enable stretch duration a, and the enable duration of the refresh line according to the above formula, and configures the calculation results into the registers of the gate drive circuit 210 and the source drive circuit 220 to control the timing of each row scan signal in the write operation of the next write frame Tw.

[0056] Because some areas require several rows to be opened and closed consecutively, timing shift control is needed to prevent incorrect filling. In an optional embodiment, the driving method of the electronic paper display panel 100 further includes: S60. Based on the number of non-refreshing rows from the first row to the nth row, determine the start time of the refresh row in the nth row, where n is a positive integer.

[0057] In this embodiment, in the traditional row-by-row refresh scheme, the start time of each row is evenly distributed, and the start time of the nth row is equal to n×h1. However, in the selective refresh scheme, since some rows are skipped, the start time of the refresh rows is no longer evenly distributed and needs to be adjusted according to the number of non-refresh rows in front.

[0058] For the nth row, if it is a refresh row, its opening time depends on the number of non-refresh rows from the first row to the nth row. Let m be the number of non-refresh rows from the first row to the nth row, then nm is the number of refresh rows from the first row to the nth row. Since the opening time of each refresh row is h2, the total opening time of all refresh rows in the first n rows is (nm) × h2.

[0059] In the traditional approach, the total time for the first n rows is n×h1. In the selective refresh scheme, since m rows are skipped, m×h1 time is saved, and this time is allocated to the refresh rows as the start stretching duration 'a'. Therefore, the start time of the nth refresh row needs to be shifted forward from the traditional approach, and the shift amount 'c' is related to the number of non-refresh rows preceding it.

[0060] The timing controller 240 calculates the start time of the refresh line of the nth row based on the number m of non-refresh lines from the first row to the nth row, and configures the time point to the gate drive circuit 210 to control the output timing of the row scan signal of the nth row.

[0061] The timing displacement c is positively correlated with the number of preceding non-refresh lines. The more preceding non-refresh lines are skipped, the larger the timing displacement c of the current refresh line will be. This can accurately adapt to different refresh line distribution scenarios and achieve adaptive timing control, ensuring the charging time of the refresh line while eliminating display defects caused by timing overlap and signal crosstalk.

[0062] In an alternative embodiment, such as Figure 6 As shown, S60 specifically includes: S61. Determine the number of refreshed rows from the first row to the nth row based on the number of non-refreshed rows from the first row to the nth row, and determine the first total duration based on the number of refreshed rows from the first row to the nth row and the second opening duration. S62. Determine the second total duration based on the nth row number and the first opening duration, and determine the opening time of the nth row refresh based on the time difference between the first total duration and the second total duration.

[0063] In this embodiment, the driving method of the electronic paper display panel 100 provides precise quantitative calculation logic for the refresh row start time, realizes standardized calculation of timing offset, and ensures the accuracy and stability of timing control. The specific steps are as follows: The first step is to determine the number of refreshed rows from row 1 to row n based on the number m of non-refreshed rows from row 1 to row n. The number of refreshed rows from row 1 to row n is equal to nm, since there are n rows from row 1 to row n in total, of which m are non-refreshed rows, so the number of refreshed rows is nm. The first total duration is determined based on the number of refreshed rows nm from row 1 to row n and the second activation duration h2. The first total duration is equal to (nm) × h2, which is the total time required for all refreshed rows from row 1 to row n to be activated sequentially according to the activation duration h2.

[0064] The second step is to determine the second total duration based on the row number n of the nth row and the first opening duration h1. The second total duration is equal to n × h1, which is the total time required when each of the first n rows has an opening duration of h1 according to the traditional row-by-row refresh scheme.

[0065] The third step is to determine the start time for refreshing the nth row based on the time difference between the first total duration and the second total duration. For example... Figure 7 As shown, the start time of the nth refresh row is equal to the first total duration minus the second total duration, which is equal to (nm)×h2-n×h1.

[0066] Substituting h2=1 / (f×(Mx)) and h1=1 / (f×M) into the above formula, we can obtain the maximum displacement c of the nth refresh row. This displacement c represents the time that the nth refresh row moves forward relative to the start time of the nth row in the traditional scheme.

[0067] Taking a specific numerical example, assuming the total number of rows M is 200, the refresh rate f is 50Hz, and the total number of non-refreshing rows x is 150, then h1 equals 100μs and h2 equals 400μs. For the 100th row, if there are 80 non-refreshing rows before it, i.e., m equals 80, then the first total duration is (100-80)×400 equals 8ms, the second total duration is 100×100 equals 10ms, and the shift c at the start time of the 100th refreshed row is 8000-10000 equals -2ms, which means it starts 2ms earlier than the traditional solution.

[0068] Through the above calculations, the timing controller 240 can accurately determine the start time of each refresh line, ensuring that the refresh lines are closely connected and do not overlap, while making full use of the time saved by skipping lines to extend the start time of the refresh lines. Refresh lines at different positions have differentiated timing offsets, completely solving the crosstalk and incorrect charging problems caused by local concentrated refreshes. Even if there are large areas of continuous refresh lines, each line can work independently in a time-sharing manner through timing offsets, ensuring that the charging voltage of each pixel unit 110 is accurately controllable, greatly improving the display uniformity of the entire screen, and reducing the probability of display defects such as afterimages, ghosting, and horizontal lines.

[0069] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0070] Example 2 A second aspect of the present invention provides a display device, such as... Figure 8 As shown, the display device includes an electronic paper display panel 100 and a driving circuit 200 for the electronic paper display panel. The driving circuit 200 for the electronic paper display panel is used to execute the driving method of the electronic paper display panel 100 as described above. The electronic paper display panel 100 includes pixel units 110 arranged in an array.

[0071] In this embodiment, the display device is an electronic paper display device employing the driving method of the electronic paper display panel 100 described above. It can be specifically applied to various low-power display scenarios such as e-readers, electronic shelf labels, outdoor smart signs, industrial low-power display terminals, and flexible wearable devices. The display device as a whole includes two core hardware structures: the electronic paper display panel 100 and the driving circuit 200 for the electronic paper display panel. The surface of the electronic paper display panel 100 is provided with a plurality of pixel units 110 arranged in an array to form a complete display screen.

[0072] The electronic paper display panel 100 includes an array of pixel units 110, each pixel unit 110 corresponding to a display pixel. The pixel units 110 are arranged in an M-row N-column matrix, with the row direction corresponding to the scanning direction and the column direction corresponding to the data direction. The electronic paper display panel 100 also includes multiple scan lines and multiple data lines. Each scan line connects to all pixel units 110 in a corresponding row, and each data line connects to all pixel units 110 in a corresponding column.

[0073] The driving circuit 200 of the electronic paper display panel includes a gate driving circuit 210, a source driving circuit 220, a timing controller 240, and a voltage detection circuit 230. The gate driving circuit 210 outputs a line scan signal to each pixel unit 110 via scan lines, and the source driving circuit 220 outputs a data signal to each pixel unit 110 via data lines. The timing controller 240 is connected to both the gate driving circuit 210 and the source driving circuit 220, and is used to provide timing control signals and execute a frame matching algorithm. The voltage detection circuit 230 is connected to the output terminal of the pixel sensing unit 111, and is used to read the sensing signal Vsen and convert it into a pixel voltage Vd value.

[0074] In one embodiment, the gate driving circuit 210 can be implemented using an integrated gate driving array, that is, the gate driving circuit is integrated on the substrate of the display panel 100, which helps to reduce costs and achieve a narrow bezel. In another embodiment, the gate driving circuit 210 can also be implemented using an external gate driving chip. The source driving circuit 220 can be an external data driving chip, or it can be integrated with the gate driving circuit 210 into a two-in-one integrated circuit, achieving cost reduction and a more refined bezel design.

[0075] The display device may also include multiple sensing signal lines, each connected to the output terminal of a corresponding column of pixel sensing units 111, for transmitting the sensing signal Vsen to the voltage detection circuit 230. The sensing signal lines are arranged in parallel with the data lines, transmitting the sensing signal Vsen during the sensing phase and not operating during the writing phase.

[0076] In this design, the peripheral signals of the driving circuit 200 for the electronic paper display panel adopt a time-division multiplexing architecture. The sensing signal lines and data lines corresponding to each column of pixels are connected to the signal channels of the same source driving circuit 220 through a master control switch. The driving chip and voltage detection circuit 230 in the source driving circuit 220 can be connected to the signal channels of the source driving circuit 220. By controlling the on / off states of the global write master switch Q1 and the global sensing master switch Q2 in a time-division manner, the two working modes of data writing and voltage sensing can be switched in a time-division manner. There is no need to configure a dedicated chip channel for the sensing signal Vsen, which greatly simplifies the peripheral circuit wiring, reduces hardware complexity and mass production costs. The voltage detection circuit 230 can be integrated into the source driving circuit 220, or the source driving circuit 220 can be multiplexed as the voltage detection circuit 230. The source driving circuit can respectively implement the data writing and pixel voltage Vd sensing functions.

[0077] Pixel unit 110 can be configured with corresponding switches and sensing units to realize data writing and data voltage sensing output. In an optional embodiment, such as... Figure 4As shown, the pixel unit 110 includes a storage capacitor Cst and a write switch T1, which is used to input the corresponding row scan signal and data signal. The pixel unit 110 also includes a pixel sensing unit 111, which is used to sense the pixel voltage Vd of the pixel unit 110 and output the sensing result to the driving circuit 200 of the electronic paper display panel. The driving circuit 200 of the electronic paper display panel is used to determine the pixel voltage Vd of the pixel unit 110 based on the sensing result.

[0078] In this embodiment, each pixel unit 110 in the array includes a storage capacitor Cst and a write switch T1. The write switch T1 is a thin-film transistor, with its gate connected to the scan line of the corresponding row, its source connected to the data line of the corresponding column, and its drain connected to the pixel voltage node. The storage capacitor Cst is connected between the pixel voltage node and the common voltage Vcom. When the row scan signal turns on the write switch T1, the data voltage on the data line is written to the pixel voltage node through the write switch T1 and stored in the storage capacitor Cst. When the row scan signal turns off the write switch T1, the storage capacitor Cst maintains the potential of the pixel voltage node, allowing the electronic paper microcapsule to maintain the corresponding display state.

[0079] Pixel unit 110 also includes pixel sensing unit 111. Pixel sensing unit 111 is connected to a pixel voltage node and is used to sense the pixel voltage Vd of pixel unit 110, and output the sensing result to the voltage detection circuit 230 of the driving circuit of display panel 100. Pixel sensing unit 111 operates during the sensing phase at the end of a display frame, converting the potential of the pixel voltage node into a sensing signal Vsen and outputting it. Voltage detection circuit 230 receives the sensing signal Vsen and determines the pixel voltage Vd of pixel unit 110 based on the sensing result.

[0080] The pixel sensing unit 111 is integrated with the write switch T1 and the storage capacitor Cst in the same pixel area, and one pixel sensing unit 111 is provided for each pixel unit 110. The introduction of the pixel sensing unit 111 increases the number of transistors in the pixel, but since the pixel size of electronic paper is relatively large, and the pixel sensing unit 111 only works briefly during the inter-frame sensing stage, it will not affect the pixel structure and operation during the normal display stage.

[0081] Compared to traditional electronic paper pixel circuits that only have data writing and voltage storage functions, this technology integrates an independent sensing architecture within each pixel to achieve precise voltage detection pixel by pixel and line by line. This solves the problem of insufficient accuracy in traditional global and regional detection, allowing the refresh control of each pixel to be determined independently, minimizing power consumption caused by invalid refreshes, while ensuring display accuracy.

[0082] The pixel sensing unit 111 can adopt a corresponding switch and output unit. In an optional embodiment, such as... Figure 9 As shown, the pixel sensing unit 111 includes a sensing capacitor C1, a trigger switch T2, an output switch 101, and a driving transistor T3; The trigger switch T2 is used to transfer the voltage of the pixel unit 110 to the sensing capacitor C1; The control terminal of the driving transistor T3 is connected to the sensing capacitor C1 to generate a sensing signal Vsen based on the voltage on the sensing capacitor C1. The output switch 101 is used to output the sensing signal Vsen to the drive circuit 200 of the electronic paper display panel.

[0083] In this embodiment, the pixel sensing unit 111 includes four core components: sensing capacitor C1, trigger switch T2, output switch 101, and driving transistor T3. These components work together to complete the coupling, conversion, and output of the pixel voltage Vd.

[0084] Trigger switch T2 is a thin-film transistor, with its gate connected to the second scan control signal line G02, its source connected to the pixel voltage node, and its drain connected to the first node A. The second scan control signal line G02 transmits a second scan control signal, used to control the on and off states of trigger switch T2. During the sensing phase, the second scan control signal sequentially activates the trigger switches T2 for each row, transferring the potential of the pixel voltage node to the first node A.

[0085] Sensing capacitor C1 is connected between the first node A and the second node B. When the trigger switch T2 is turned on, the potential change of the pixel voltage node is coupled to the second node B through sensing capacitor C1, causing the potential of the second node B to follow the pixel voltage Vd change. Sensing capacitor C1 serves both voltage coupling and charge storage functions.

[0086] The driving transistor T3 is a thin-film transistor. Its control terminal (gate) is connected to the second node B, its drain is connected to the power supply voltage Vdd, and its source is connected to the third node C. Driving transistor T3 generates a sensing signal Vsen based on the voltage at the second node B, i.e., the voltage across sensing capacitor C1. When the voltage at the second node B changes, the gate-source voltage of driving transistor T3 changes accordingly, and its conduction current changes accordingly, thus converting the voltage signal into a current signal output. When driving transistor T3 operates in the saturation region, its drain current is proportional to the square of the gate-source voltage minus the threshold voltage. Therefore, by measuring the conduction current of driving transistor T3, the voltage at the second node B can be deduced, and thus the pixel voltage Vd can be obtained.

[0087] Output switch 101 includes a first output switch T4 and a second output switch T5. The first output switch T4 is a thin-film transistor (TFT), with its gate connected to the sensing switch signal line, its source connected to the power supply voltage Vdd, and its drain connected to the drain of the driving transistor T3. The second output switch T5 is a TFT, with its source connected to the third node C, i.e., the source of the driving transistor T3, and its drain connected to the sensing signal line for outputting the sensing signal Vsen. The sensing switch signal line transmits a sensing switch signal SW, used to control the on / off state of the first output switch T4. During the output phase, the sensing switch signal SW turns on the first output switch T4, and the power supply voltage Vdd is applied to the drain of the driving transistor T3 through the first output switch T4. The sensing current generated by the driving transistor T3 is output to the sensing signal line through the second output switch T5. The gate of the second output switch T5 can be connected to a fixed turn-on voltage, keeping it always in the on state during the sensing phase, or it can be connected to the sensing switch signal line for synchronous control with the first output switch T4.

[0088] The power supply voltage Vdd is greater than the maximum value of the pixel voltage Vd, for example, greater than 15V. This ensures that the driving transistor T3 can operate in the saturation region during the output stage and generate a sensing current corresponding to the pixel voltage Vd.

[0089] To reduce residual charge that could lead to abnormal sensing data, in one alternative embodiment, such as Figure 10 As shown, the pixel sensing unit 111 also includes multiple reset transistors, each of which is connected to a different node of the sensing capacitor C1, and is used to reset each node before sensing, so that each node is reset to a preset voltage.

[0090] In this embodiment, each reset transistor is controlled by an independent global reset signal, including four types of reset control signals: rst1, rst2, rst3, and rst4. Before each pixel voltage Vd sensing operation begins, the driving circuit 200 of the electronic paper display panel outputs a reset control signal to control each reset transistor to turn on one by one, clearing and resetting the residual voltage of all circuit nodes of the sensing unit, and stabilizing all node voltages to a preset reference voltage.

[0091] Multiple reset transistors are designated as first reset transistor Tr1, second reset transistor Tr2, third reset transistor Tr3, and fourth reset transistor Tr4. Each reset transistor is connected to a different node of the sensing capacitor C1, and resets each node during the reset phase.

[0092] The first reset transistor Tr1 is a thin-film transistor. Its gate is connected to the first reset signal line, its source is connected to the common voltage Vcom, and its drain is connected to the first node A. The first reset signal line transmits the first reset signal rst1. During the reset phase, the first reset transistor Tr1 is turned on, resetting the first node A to the common voltage Vcom.

[0093] The second reset transistor Tr2 is a thin-film transistor. Its gate is connected to the second reset signal line, its source is connected to the reference voltage Vref1, and its drain is connected to the second node B. The second reset signal line transmits the second reset signal rst2. During the reset phase, the second reset transistor Tr2 is turned on, resetting the second node B to the reference voltage Vref1.

[0094] The third reset transistor Tr3 is a thin-film transistor. Its gate is connected to the third reset signal line, its source is connected to the second node B, and its drain is connected to the third node C. The third reset signal line transmits the third reset signal rst3. During the reset phase, the third reset transistor Tr3 is turned on, resetting the third node C to the reference voltage Vref1.

[0095] The fourth reset transistor Tr4 is a thin-film transistor. Its gate is connected to the fourth reset signal line, its source is connected to the common voltage Vcom, and its drain is connected to the second node B. The fourth reset signal line transmits the fourth reset signal rst4. During a specific period of the reset phase, the fourth reset transistor Tr4 is turned on, forming a diode connection with the driving transistor T3, and discharging the second node B until the voltage at the second node B reaches the critical point of the sum of the common voltage Vcom and the threshold voltage Vth, where Vth represents the threshold voltage of the driving transistor.

[0096] Each reset transistor operates sequentially during the reset phase, resetting each node of the sensing capacitor C1 to a preset voltage, preparing it for the subsequent sensing phase. The reset operation ensures that each pixel sensing unit 111 is in a consistent initial state before sensing, eliminating the influence of residual charge from the previous frame and improving sensing accuracy.

[0097] The pixel voltage Vd sensing operation can be performed at the end of each write frame or between adjacent write frames. In an optional embodiment, the driving circuit 200 of the electronic paper display panel is also used to control the pixel sensing unit 111 to work sequentially in the reset phase, sensing phase and output phase at the end of the current display frame Tf1. During the reset phase, each node is controlled to reset to the preset voltage; During the sensing phase, the control trigger switch T2 is turned on, coupling the voltage of the pixel unit 110 to the sensing capacitor C1; During the output phase, the output switch 101 is turned on to output the sensing signal Vsen.

[0098] In this embodiment, the driving timing of the pixel sensing unit 111 is divided into three stages: a reset stage, a sensing stage, and an output stage. These three stages are performed sequentially between two adjacent frames.

[0099] During the reset phase, the drive circuit controls each reset transistor to operate sequentially, resetting each node to a preset voltage. The timing sequence of the reset phase is as follows: Figure 11 As shown. Specifically, when the pixel sensing unit 111 starts working, the first reset signal rst1, the second reset signal rst2, and the third reset signal rst3 respectively turn on the first reset transistor Tr1, the second reset transistor Tr2, and the third reset transistor Tr3, resetting the first node A, the second node B, and the third node C. This resets the first node A to the common voltage Vcom, the second node B to the reference voltage Vref1, and the third node C to the reference voltage Vref1. Then, the second reset signal rst2 turns off the second reset transistor Tr2, and the fourth reset signal rst4 turns on the fourth reset transistor Tr4. At this time, the voltage of the second node B is equal to the voltage of the third node C, which is equal to the reference voltage Vref1. The driving transistor T3 and the fourth reset transistor Tr4 form a diode connection structure, discharging the second node B until the voltage of the second node B reaches the critical point of the sum of the common voltage Vcom and the threshold voltage Vth. Then, the fourth reset transistor Tr4 and the first reset transistor Tr1 are turned off. At this time, for the pixel sensing unit 111 of all row pixels, the voltage of the first node A is the common voltage Vcom, and the voltage of the second node B is Vcom + Vth. Vth is the threshold voltage of the driving transistor T3 in the pixel sensing unit 111.

[0100] The diode connection discharge operation during the reset phase serves as a threshold compensation mechanism. Due to process variations in the threshold voltage of the driving transistor T3 for different pixels, the diode connection resets the voltage at the second node B to Vcom+Vth, eliminating the impact of threshold voltage deviation on subsequent sensing results and improving sensing accuracy and panel display uniformity.

[0101] During the sensing phase, the driving circuit 200 of the electronic paper display panel controls the trigger switch T2 to turn on, coupling the voltage of the pixel unit 110 to the sensing capacitor C1. Specifically, the second scan control signal controls the trigger switch T2 to turn on row by row. At this time, the potential of the first node A jumps to the pixel voltage Vd. Since the voltage across the sensing capacitor C1 cannot change abruptly, the voltage of the second node B is coupled to Vd+Vth by the sensing capacitor C1. Through this action, the pixel voltage Vd of each row is extracted to the second node B of the pixel sensing unit 111. The second scan control signal turns on the trigger switch T2 of each row row by row, so that the pixel voltage Vd of each row is sequentially coupled to the second node B of the corresponding pixel sensing unit 111.

[0102] During the output phase, the driving circuit controls the output switch 101 to conduct in order to output the sensing signal Vsen. Specifically, the sensing switch signal SW turns on the first output switch T4 of each row of pixels row by row. At this time, the power supply voltage Vdd is greater than the voltage of the second node B, and the driving transistor T3 is in saturation operation. The sensing current corresponding to the pixel voltage Vd is sequentially input to the sensing line and sensed by the driving circuit 200 of the electronic paper display panel. The sensing switch signal SW turns on the first output switch T4 of each row row by row, so that the sensing signal Vsen of each row of pixels is sequentially output to the sensing signal line, which is read by the voltage detection circuit 230 and converted into the pixel voltage Vd value.

[0103] After the output stage is completed, the driving circuit 200 of the electronic paper display panel obtains the pixel voltage values ​​of all pixel units 110 of the current display frame Tf1, sends them to the timing controller 240 to execute the frame matching algorithm, compares them with the pixel voltage Vd to be written in the next write frame Tw, determines whether each row needs to be refreshed, and calculates the opening duration and opening time of the refresh row to prepare for the writing operation of the next write frame Tw.

[0104] Among them, such as Figure 12 As shown, the row scanning signal is provided by the gate driving circuit 210, and the sensing switch signal SW can also be provided by the gate driving circuit 210. The position of the gate driving circuit 210 only represents the circuit connection. In actual products, the gate driving integrated circuit can be placed on the left, right, or bottom side of the panel, or integrated with the source driving circuit 220 into a two-in-one integrated circuit to achieve cost reduction and a more streamlined bezel design.

[0105] like Figure 12 As shown, the data lines and sensing signal lines in each column of pixels are controlled by the global write switch master signal Ctr1 and the sensing switch master signal Ctr2, respectively. The data signal lines and sensing signal lines are connected to the same source driver circuit 220's channel signal lines via the common source drain of the global write master switch Q1 and the global sensing master switch Q2, respectively, thus time-division multiplexing the signal channels of the source driver circuit 220. Figure 13 As shown, during the sensing period Tf11, the write switch master signal Ctr1 is low to turn off the global write master switch Q1, thereby shutting down all data signal line channels. The sensing switch master signal Ctr2 is high to turn on the global sensing master switch Q2, thereby turning on all sensing signal channels. The voltage detection circuit 230 reads the voltage of each row of pixels line by line. In the next write frame Tw, the data signal channels are turned on, the sensing signal channels are turned off, and the target voltage for the next write frame Tw is input through the gate drive circuit 210 and the source drive circuit 220.

[0106] The overall driving timing of this embodiment is described below.

[0107] A complete frame cycle consists of three parts: the display frame, the frame matching period Tf12, and the write frame. For example... Figure 7 and Figure 13 As shown, Tf1 and Tf2 represent the previous and next display frames, respectively. Unlike conventional displays, electronic paper displays have very long frames. During a display frame, the pixels maintain their display state, and the driving circuit can be in a low-power or power-off state.

[0108] At the end of the previous display frame Tf1, the sensing period Tf11 begins. The sensing switch master signal Ctr2 goes high to open all sensing signal channels. Here, SW1 represents the sensing switch signal for the first row, SW2 for the second row, SW3 for the third row, SWM-2 for the (M-2)th row, SWM-1 for the (M-1)th row, and SWM for the Mth row. The master signal Ctr1 goes low to close all data signal line channels. Sensing switch signals SW provide turn-on signals row by row. The driving transistors T3 are all N-type thin-film transistors, providing a high-level row turn-on signal Vgh to turn on and a low-level row turn-off signal Vgl to turn off. Since the power supply voltage Vdd is set to a high voltage, typically greater than 15V, and Vdd is greater than the pixel voltage Vd, the sensing signal lines will generate corresponding voltage or current signals. Each pixel voltage Vd is identified by the external circuitry, and comparisons are made during the frame matching phase Tf12.

[0109] After reading and matching are complete, the timing controller 240 determines the timing values ​​of the start duration and start time point through an algorithm, opens the data signal channel, closes the sensing signal channel, and enters the next write frame Tw. In the next write frame Tw, the gate drive circuit 210 controls the write switch T1 of the row that needs to be opened, and the source drive circuit 220 controls the voltage of the row that needs to be written, realizing the operation of skipping unnecessary rows and writing necessary pixels.

[0110] After the next write frame Tw is completed, the next display frame Tf2 is entered, and the pixels maintain the new display state.

[0111] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A driving method for an electronic paper display panel, characterized in that, The electronic paper display panel includes pixel units arranged in an array, and the driving method of the electronic paper display panel includes: The output row scan signal scans and activates each pixel unit line by line, and writes multiple columns of data signals to the pixel unit. The pixel voltage of each row corresponding to the pixel unit in the target display area of ​​the current display frame is sensed, and the pixel voltage of each row of the pixel unit to be written in the target display area of ​​the next write frame is obtained and the voltage is compared. The target display area is the area to be updated in the electronic paper display panel. When the voltage ratio of the pixel voltage in the next write frame to the pixel voltage in the current display frame of each pixel unit in the i-th row of the target display area is within a preset voltage range, in the next write frame, the output row scan signal to the pixel unit in the i-th row of the target display area is cut off; When the voltage ratio of the pixel voltage in the next write frame to the pixel voltage in the current display frame of each pixel unit in the i-th row of the target display area is not within a preset voltage range, a row scan signal is output to the pixel unit in the i-th row of the target display area in the next write frame, where i is a positive integer.

2. The driving method for an electronic paper display panel as described in claim 1, characterized in that, The driving method for the electronic paper display panel further includes: The number of non-refreshing rows in the target display area is counted, and the refresh row activation duration is determined based on the total number of rows in the target display area, the number of non-refreshing rows, and the refresh rate of the electronic paper display panel. In the non-refreshing behavior, the voltage ratio of the pixel voltage of the next write frame of each pixel unit to the pixel voltage of the current display frame is within the corresponding row of the preset voltage range; The refresh behavior is such that the voltage ratio of the pixel voltage in the next write frame to the pixel voltage in the current display frame for each pixel unit is not within the corresponding row of the preset voltage range.

3. The driving method for an electronic paper display panel as described in claim 2, characterized in that, The method of determining the refresh row activation duration based on the total number of rows in the target display area, the number of non-refresh rows, and the refresh rate of the electronic paper display panel includes: The first activation duration is determined based on the refresh rate and the total number of rows in the target display area; The number of refresh rows is determined based on the total number of rows and the number of non-refresh rows, and the second activation duration is determined based on the refresh rate and the number of refresh rows. The opening stretching duration of the refresh row is determined based on the time difference between the first opening duration and the second opening duration; The activation duration of the refresh row is determined based on the activation stretch duration and the time and value of the first activation duration.

4. The driving method for an electronic paper display panel as described in claim 3, characterized in that, The driving method for the electronic paper display panel further includes: Based on the number of non-refreshing rows from the first row to the nth row, determine the start time of the refresh row in the nth row, where n is a positive integer.

5. The driving method for an electronic paper display panel as described in claim 4, characterized in that, Determining the start time of refreshing the nth row based on the number of non-refresh rows from the first row to the nth row includes: The number of refreshed rows in the first to nth rows is determined based on the number of non-refreshed rows in the first to nth rows, and the first total duration is determined based on the number of refreshed rows in the first to nth rows and the second activation duration; The second total duration is determined based on the nth row number and the first activation duration, and the activation time of the nth refresh row is determined based on the time difference between the first total duration and the second total duration.

6. A display device, characterized in that, The invention includes an electronic paper display panel and a driving circuit for the electronic paper display panel, wherein the driving circuit for the electronic paper display panel is used to perform the driving method for the electronic paper display panel as described in any one of claims 1 to 5, and the electronic paper display panel includes pixel units arranged in an array.

7. The display device as claimed in claim 6, characterized in that, The pixel unit includes a storage capacitor and a write switch, the write switch being used to input the corresponding row scan signal and data signal; The pixel unit further includes a pixel sensing unit, which is used to sense the pixel voltage of the pixel unit and output the sensing result to the driving circuit of the electronic paper display panel. The driving circuit of the electronic paper display panel is used to determine the pixel voltage of the pixel unit based on the sensing result.

8. The display device as claimed in claim 7, characterized in that, The pixel sensing unit includes a sensing capacitor, a trigger switch, an output switch, and a driving transistor; The trigger switch is used to transmit the voltage of the pixel unit to the sensing capacitor; The control terminal of the driving transistor is connected to the sensing capacitor and is used to generate a sensing signal based on the voltage on the sensing capacitor. The output switch is used to output the sensing signal to the driving circuit of the electronic paper display panel.

9. The display device as claimed in claim 8, characterized in that, The pixel sensing unit also includes multiple reset transistors, each of which is connected to a different node of the sensing capacitor to reset each node before sensing, so that each node is reset to a preset voltage.

10. The display device as claimed in claim 9, characterized in that, The driving circuit of the electronic paper display panel is also used to control the pixel sensing unit to work sequentially in the reset phase, sensing phase and output phase at the end of the current display frame. During the reset phase, each node is controlled to reset to a preset voltage; During the sensing phase, the trigger switch is turned on to couple the voltage of the pixel unit to the sensing capacitor; During the output phase, the output switch is controlled to turn on to output the sensing signal.

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