Gate driving circuit, display panel and display device

Abstract

The application provides a gate drive circuit, a display panel and a display device. The gate drive circuit comprises a plurality of drive units connected in cascade, each drive unit comprising: a pull-up module, a control end of the pull-up module being connected to a stage transmission signal of a corresponding stage, an input end of the pull-up module being coupled with a power supply signal, and an output end of the pull-up module being coupled with a pull-up node, the pull-up module being configured to charge the pull-up node; an output module, a control end of the output module being coupled with the pull-up node, and an input end of the output module being connected to a clock signal, the output module being configured to output the clock signal as the stage transmission signal and a scanning signal when the pull-up node is at a high potential; and an input module, the input module being configured to output a pull-up input signal after performing a logical OR operation on a first power supply voltage and a second power supply voltage. The input end of the pull-up module is electrically connected with the output end of the input module, so as to output the pull-up input signal under the control of the stage transmission signal. The power supply signal comprises the first power supply voltage and the second power supply voltage, which are complementary in phase and square waves. The gate drive circuit can improve the problem of voltage loss of the pull-up node caused by the cascade pull-up.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] In TFT-LCD gate driving technology, the quality of the gate scan signal directly depends on the potential stability and driving capability of the pull-up node (Q point). A pull-up node with strong driving capability can ensure that the output scan signal has a steep rising edge and sufficient amplitude, thereby ensuring pixel charging and avoiding problems such as uneven display brightness and crosstalk.

[0003] Currently, the cascaded pull-up drive method is commonly used to pull up the potential of the Q point in gate drive circuits. Specifically, the cascaded pull-up utilizes the cascaded transmission signal generated by the preceding drive unit to pull up the potential of the Q point in the current stage.

[0004] However, in the cascaded pull-up method, the transmission signal generated by the previous stage pulls up the Q-point potential of the current stage through the transistor connected by the diode. Due to the influence of the diode connection method, there will be a threshold voltage loss when transmitting the high level, and the fault is easy to propagate between stages. Summary of the Invention

[0005] This application provides a gate driving circuit, a display panel, and a display device, aiming to solve the problems in the prior art where the pull-up of the Q-point potential in the gate driving circuit is affected by the diode connection method, resulting in voltage loss and easy propagation of faults between stages.

[0006] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a gate driving circuit. This gate driving circuit includes multiple cascaded driving units, each driving unit comprising: The pull-up module has a control terminal connected to the corresponding stage transmission signal, an input terminal coupled to the power signal, and an output terminal coupled to the pull-up node. It is used to output a power signal under the control of the corresponding stage transmission signal to charge the pull-up node. The output module has a control terminal coupled to the pull-up node and an input terminal connected to a clock signal. When the pull-up node is at a high potential, the clock signal is used as the stage transmission signal and the scan signal to be output from the stage transmission output terminal and the scan output terminal, respectively. The power supply signal includes a first power supply voltage and a second power supply voltage, wherein the first power supply voltage and the second power supply voltage are square wave signals with complementary phases. The gate drive circuit also includes an input module, which is coupled to a first power supply voltage and a second power supply voltage. The input module is used to perform a logical OR operation on the first power supply voltage and the second power supply voltage to output the power supply signal as a pull-up input signal. The input terminal of the pull-up module is electrically connected to the output terminal of the input module to output a pull-up input signal under the control of the cascade signal.

[0007] In some embodiments, the input module includes a first switch and a second switch; The control terminal of the first switching transistor is connected to the second power supply voltage, and its input terminal is connected to the first power supply voltage; the control terminal of the second switching transistor is connected to the first power supply voltage, and its input terminal is connected to the second power supply voltage; the output terminals of the first and second switching transistors are electrically connected, and the connection node serves as the output terminal of the input module. When the first power supply voltage is high and the second power supply voltage is low, the first switch is turned on to output the first power supply voltage as a pull-up input signal. When the first power supply voltage is low and the second power supply voltage is high, the second switch is turned on to output the second power supply voltage as a pull-up input signal.

[0008] In some embodiments, the first switch and the second switch are both P-type thin-film transistors; the drain of the first switch and the gate of the second switch are connected to a first power supply voltage, the gate of the first switch and the drain of the second switch are connected to a second power supply voltage, and the source of the first switch and the source of the second switch are electrically connected as the output terminal of the input module.

[0009] In some embodiments, the pull-up module includes a pull-up transistor, the gate of which is connected to the stage transmission signal of the corresponding stage, the drain of which is electrically connected to the output terminal of the input module, and the source of which is electrically connected to the pull-up node. The output module includes a first transistor and a second transistor; the gates of the first transistor and the second transistor are electrically connected to the pull-up node; the drains of the first transistor and the second transistor are connected to the clock signal; the source of the first transistor serves as the stage transmission output terminal, and the source of the second transistor serves as the scan output terminal. When the pull-up node is at a high potential, the first transistor and the second transistor are turned on to output the clock signal as the stage transmission signal and the scan signal, respectively.

[0010] In some embodiments, each drive unit further includes a reset module, which includes a first reset submodule and a second reset module. The input terminal of the first reset submodule is connected to a first low-level signal, the output terminal is electrically connected to the pull-up node, and the control terminal is connected to a first reset signal, so that the first low-level signal is output to the pull-up node under the control of the first reset signal. The input terminal of the second reset submodule is connected to the first low-level signal, the output terminal is electrically connected to the pull-up node, and the control terminal is connected to the second reset signal so that the first low-level signal is output to the pull-up node under the control of the second reset signal. The control terminal of the first reset submodule of the Nth stage drive unit is electrically connected to the stage transmission output terminal of the (N+L)th stage drive unit, and the stage transmission signal of the (N+L)th stage drive unit is used as the first reset signal; L and N are positive integers, L is greater than or equal to 4 and less than N; The control terminal of the second reset submodule is electrically connected to the timing controller and is used to output a first low-level signal to the pull-up node when the frame reset signal output by the timing controller is received.

[0011] In some embodiments, each pair of adjacent drive units constitutes a drive group, and each drive group includes an input module; in each drive group, the input terminals of the pull-up modules in the two adjacent drive units are electrically connected to the output terminals of the input modules, respectively.

[0012] In some embodiments, each drive unit further includes a pull-down module and a pull-down sustaining module; The dropdown module includes: The first pull-down module includes a third transistor, a fourth transistor, and a fifth transistor. The gate of the third transistor is electrically connected to the first pull-down node, the drain is connected to a first low-level signal, and the source is electrically connected to the pull-up node. The gate of the fourth transistor is electrically connected to the first pull-down node, the drain is connected to the first low-level signal, and the source is electrically connected to the stage output terminal. The gate of the fifth transistor is electrically connected to the first pull-down node, the drain is connected to a second low-level signal, and the source is electrically connected to the scan output terminal. The first pull-down module is used to output the first low-level signal to the pull-up node and the stage output terminal, and output the second low-level signal to the scan output terminal, under the control of the signal from the first pull-down node. The second pull-down module includes a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the sixth transistor is electrically connected to the second pull-down node, its drain is connected to a first low-level signal, and its source is electrically connected to the pull-up node. The gate of the seventh transistor is electrically connected to the second pull-down node, its drain is connected to a first low-level signal, and its source is electrically connected to the stage transmission output terminal. The gate of the eighth transistor is electrically connected to the second pull-down node, its drain is connected to a second low-level signal, and its source is electrically connected to the scan output terminal. The second pull-down module is used to output the first low-level signal to the pull-up node and the stage transmission output terminal, and output the second low-level signal to the scan output terminal, under the control of the signal from the second pull-down node. In each drive group, the first pull-down node of the front stage is electrically connected to the second pull-down node of the rear stage, and the second pull-down node of the front stage is electrically connected to the first pull-down node of the rear stage. The pull-down sustaining module includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The gate and drain of the ninth transistor are connected to a first power supply voltage, and its source is electrically connected to a sustaining connection node. The gate of the tenth transistor is electrically connected to a pull-up node, its drain is connected to a first low-level signal, and its source is electrically connected to a sustaining connection node. The gate of the eleventh transistor is electrically connected to a sustaining connection node, its drain is connected to the first power supply voltage, and its source is electrically connected to a first pull-down node. The gate of the twelfth transistor is electrically connected to the pull-up node of a cascaded drive unit in the same drive group, its drain is connected to a first low-level signal, and its source is electrically connected to a sustaining connection node.

[0013] To address the aforementioned technical problems, the second technical solution provided in this application is: to provide a display panel. The display panel includes: The display area includes an array of sub-pixels used to display images; The non-display area includes a gate driving circuit as provided in the above embodiments. The gate driving circuit is electrically connected to the sub-pixel and is used to provide a scan signal to the sub-pixel.

[0014] To address the aforementioned technical problems, the third technical solution provided in this application is: to provide a display device. The display device includes: The display panel is as described above and is used to display images; The data drive circuit is electrically connected to the display panel and is used to provide data signals to the display panel.

[0015] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a gate driving circuit, a display panel, and a display device. The gate driving circuit includes multiple cascaded driving units, each driving unit including a pull-up module, an output module, and an input module. The pull-up module outputs a power signal under the control of a stage transmission signal to charge the pull-up node. The output module outputs a clock signal as a stage transmission signal and a scan signal from the stage transmission output terminal and scan output terminal respectively when the pull-up node is at a high potential, providing stage transmission signals to the corresponding stage driving unit and scan signals to the sub-pixels of the display area. This application sets the first power supply voltage and the second power supply voltage as complementary square wave signals and performs a logical OR operation between them using the input module. This allows charging during the pull-up node charging process to utilize the consistently high-level signal in the complementary signals, avoiding the threshold voltage loss caused by diodes connecting transistors in traditional cascaded pull-up methods, ensuring that the pull-up node potential fully reaches the power supply voltage level. Furthermore, by directly charging the pull-up node with the power supply voltage, fault propagation between stages is avoided. Meanwhile, through the coordinated operation of the input module and the pull-up module, the pull-up input signal can be transmitted to the pull-up node stably and efficiently, which further improves the amplitude and rise steepness of the gate drive circuit output signal, which is conducive to more complete pixel charging and avoids uneven display and crosstalk. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0017] Figure 1 This is a schematic diagram of the gate drive circuit provided in an implementation of the related technology; Figure 2 This is a schematic diagram of the gate driving circuit provided in the first embodiment of this application; Figure 3 This is a schematic diagram of the gate drive circuit provided in another embodiment of the related technology; Figure 4 This is a schematic diagram of the gate driving circuit provided in the second embodiment of this application; Figure 5 This is a schematic diagram of the operating timing of a gate drive circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0018] Figure label: 100-Display panel; 101-Display area; 10-Sub-pixel; 11-Scan line; 12-Data line; 102-Non-display area; 20-Gate drive circuit; 21-Drive group; 22-Drive unit; 221-Pull-up module; 222-Output module; 223-Input module; 224-Reset module; 2241-First reset submodule; 2242-Second reset submodule; 225-Pull-down module; 2251-First pull-down module; 2252-Second pull-down module; 226-Pull-down holding module; 227-Third pull-down module; 30-Data drive circuit; Q(N) / Q(N+1) - Pull-up node; T1 - First switch transistor; T2 - Second switch transistor; T3 - Pull-up transistor; T41 - First transistor; T42 - Second transistor; T43 - Third transistor; T44 - Fourth transistor; T45 - Fifth transistor; T46 - Sixth transistor; T47 - Seventh transistor; T48 - Eighth transistor; T49 - Ninth transistor; T410 - Tenth transistor; T411 - Eleventh transistor; T412 - Twelfth transistor; T413 - Thirteenth transistor; T414 - Fourteenth transistor; T51 - First reset transistor; T52 - Second reset transistor; Qb(N) - First pull-down node; Qb(N+1) - Second pull-down node; N1 - Maintain connection node; C(Nm) / C(N) / C(Nx) / C(N+L) - Stage transmission signal; LC1 - First power supply voltage; LC2 - Second power supply voltage; CLK(N) / CLK(N+1) - Clock signal; LC - Pull-up input signal; G(N) / G(N+1) - Scan signal; VSS1 - First low level signal; VSS2 - Second low level signal; RST - Frame reset signal. Detailed Implementation

[0019] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0020] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of the gate driving circuit provided in an embodiment of related technology. In this embodiment, a gate driving circuit 20 is provided, which includes a plurality of cascaded driving units 22. Each driving unit 22 includes: The pull-up module 221 has its control terminal and input terminal connected to the corresponding stage transmission signal C(Nm), and its output terminal coupled to the pull-up node Q(N). It is used to charge the pull-up node Q(N) through the stage transmission signal C(Nm) under the control of the corresponding stage, so as to pull the potential of the pull-up node Q(N) to the corresponding point. The output module 222 has its control terminal coupled to the pull-up node Q(N) and its input terminal connected to the corresponding clock signal CLK(N). When the pull-up node Q(N) is at a high potential, the clock signal CLK(N) is used as the stage transmission signal C(N) and the scan signal G(N) to be output from the stage transmission output terminal and the scan output terminal, respectively.

[0025] Specifically, taking the Nth-level drive unit 22 as an example, the control terminal and input terminal of the pull-up module 221 can be connected to the stage transmission signal C(Nm) output by the (Nm)th-level drive unit 22, where m is a positive integer and m is less than N. For example, the stage transmission signal C(N-4) output by the (N-4)th-level drive unit 22 is output to the Nth-level drive unit 22 to charge the pull-up node Q(N) of the Nth-level drive unit 22. When the stage transmission signal C(N-4) is high, the pull-up module 221 is turned on to charge the pull-up node Q(N), pulling the potential of the pull-up node Q(N) up to the high potential level of the stage transmission signal C(N-4); when the pull-up node Q(N) is high, the output module 222 is turned on, and the clock signal is output through the output module 222 to the stage transmission output terminal and the scan output terminal, so as to output the stage transmission signal C(N) at the stage transmission output terminal and the scan signal G(N) at the scan output terminal. Among them, the transmission signal C(N) is used as the trigger signal for the (N+4)th level driving unit 22, and the scanning signal G(N) is used to drive the Nth row sub-pixel 10.

[0026] Furthermore, the pull-up module 221 includes a pull-up transistor T3. The control terminal and input terminal of the pull-up transistor T3 are connected to the stage transmission signal C(Nm) of the first m stages, and the output terminal is electrically connected to the pull-up node Q(N). When the stage transmission signal C(Nm) is high, the pull-up transistor T3 is turned on, and the stage transmission signal C(Nm) is transmitted to the pull-up node Q(N) through the transistor, charging the pull-up node Q(N) and pulling up the potential of the pull-up node Q(N).

[0027] In this embodiment, the stage transmission signal C(N-4) generated by the first m stages is connected to the pull-up module 221 of the current stage drive unit 22. The pull-up node Q(N) is charged through the pull-up module 221. Due to the connection method of its pull-up switch, the voltage transmitted to the pull-up node Q(N) will have a threshold voltage loss, which makes it easy for the pull-up node Q(N) to be insufficiently charged, and this voltage loss is easy to be transmitted between stages.

[0028] This application provides a gate driving circuit, a display panel, and a display device. The gate driving circuit includes multiple cascaded driving units, each driving unit including a pull-up module, an output module, and an input module. The pull-up module outputs a power signal under the control of a cascade transmission signal to charge the pull-up node. The output module outputs a clock signal as a cascade transmission signal and a scan signal from the cascade output terminal and scan output terminal respectively when the pull-up node is at a high potential, providing a cascade transmission signal to the corresponding driving unit and a scan signal to the sub-pixels of the display area. This application sets the first power supply voltage and the second power supply voltage as complementary square wave signals, and performs a logical OR operation between them using the input module. This allows charging during the pull-up node charging process to utilize the consistently high-level signal in the complementary signals, avoiding the threshold voltage loss caused by diodes connecting transistors in traditional cascaded pull-up methods, ensuring the pull-up node potential fully reaches the power supply voltage level. Furthermore, by directly charging the pull-up node with the power supply voltage, fault propagation between stages is prevented. Meanwhile, through the coordinated operation of the input module and the pull-up module, the pull-up input signal can be transmitted to the pull-up node stably and efficiently, which further improves the amplitude and rise steepness of the gate drive circuit output signal, which is conducive to more complete pixel charging and avoids uneven display and crosstalk.

[0029] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] Please see Figure 2 , Figure 2 This is a schematic diagram of the gate driving circuit provided in the first embodiment of this application. This embodiment provides a gate driving circuit 20, which includes multiple cascaded driving units 22. Each driving unit 22 includes: Pull-up module 221 has a control terminal connected to the corresponding stage transmission signal C(Nm), an input terminal coupled to a power signal, and an output terminal coupled to the pull-up node Q(N). It is used to output a power signal under the control of the corresponding stage transmission signal C(Nm) to charge the pull-up node Q(N). The output module 222 has a control terminal coupled to the pull-up node Q(N) and an input terminal connected to the clock signal CLK(N). When the pull-up node Q(N) is at a high potential, the clock signal CLK(N) is used as the stage transmission signal C(N) and the scan signal G(N) to be output from the stage transmission output terminal and the scan output terminal respectively. The power supply signal includes a first power supply voltage LC1 and a second power supply voltage LC2, wherein the first power supply voltage LC1 and the second power supply voltage LC2 are square wave signals with complementary phases. The gate drive circuit 20 also includes an input module 223, which is coupled to the first power supply voltage LC1 and the second power supply voltage LC2 and is used to perform a logical OR operation on the first power supply voltage LC1 and the second power supply voltage LC2 to output the power supply signal as a pull-up input signal. The input terminal of the pull-up module 221 is electrically connected to the output terminal of the input module 223 to output a pull-up input signal under the control of the cascade signal.

[0031] Specifically, taking the Nth-level drive unit 22 as an example, where N is a positive integer, the control terminal of the pull-up module 221 is connected to the corresponding level transmission signal, such as the level transmission signal C(Nm) of the (Nm)th level, where m is a positive integer and m is less than N; that is, the level transmission signal C(Nm) generated by the (Nm)th-level drive unit 22 is transmitted to the control terminal of the pull-up module 221 of the Nth-level drive unit 22 as a trigger signal for the Nth-level drive unit 22 to charge the pull-up node Q(N) of the Nth-level drive unit 22. For example, m can be 1, 2, 3, 4, 5, etc.

[0032] When the (Nm)th stage transmission signal C(Nm) is high, the pull-up module 221 is turned on, and the power signal at the input terminal is output to the pull-up node Q(N) through the pull-up module 221 to charge the pull-up node Q(N) and pull its level high to the potential of the power signal. When the pull-up node Q(N) is high, the output module 222 is turned on, and the clock signal CLK(N) is output to the stage transmission output terminal and the scan output terminal through the output module 222. The Nth stage transmission signal C(N) is output at the stage transmission output terminal, and the Nth stage scan signal is output at the scan output terminal. Among them, the stage transmission signal C(N) is used as the trigger signal of the (N+4)th stage driving unit 22 to control the potential of the pull-up node Q(N) and charge the pull-up node Q(N); the scan signal G(N) is used to drive the Nth row sub-pixel 10.

[0033] Specifically, in this embodiment, the power supply signals include a first power supply voltage LC1 and a second power supply voltage LC2 that are complementary in phase. Complementary phase means that the first power supply voltage LC1 and the second power supply voltage LC2 have the same frequency but opposite phases; that is, when the first power supply voltage LC1 is high, the second power supply voltage LC2 is low, and vice versa. The input module 223 is coupled to the first power supply voltage LC1 and the second power supply voltage LC2 and is used to perform a logical OR operation to extract a high-level signal from the two complementary power supply signals as a pull-up input signal for output.

[0034] The input terminal of pull-up module 221 is electrically connected to the output terminal of input module 223 to receive the pull-up input signal output by input module 223. Under the control of the cascade signal C(Nm), it outputs a high-level pull-up input signal to charge pull-up node Q(N). Specifically, when the cascade signal is valid, pull-up module 221 is turned on. Since the first power supply voltage LC1 and the second power supply voltage LC2 are complementary, one voltage is always high. Input module 223 performs an OR operation on the first power supply voltage LC1 and the second power supply voltage LC2, ensuring that regardless of which power supply signal is high, its high level is transmitted to the output terminal without loss, i.e., the pull-up input signal. After receiving the pull-up input signal, pull-up module 221 charges pull-up node Q(N), causing the potential of pull-up node Q(N) to rapidly rise to the power supply voltage level, thereby controlling output module 222 to output a high-level cascade signal C(N) and a scan signal G(N).

[0035] In this embodiment, by setting the first power supply voltage LC1 and the second power supply voltage LC2 as complementary square wave signals, and cooperating with the input module 223 to perform a logical "OR" operation on the two, the high-level signal that is always present in the complementary signal can be used for charging during the charging process of the pull-up node Q(N). This avoids the threshold voltage loss caused by the switching diode connection method in the traditional cascaded pull-up method, allowing the potential of the pull-up node Q(N) to fully reach the power supply voltage level. Moreover, by using the power supply voltage to directly charge the pull-up node Q(N), the propagation of faults between stages is avoided. At the same time, through the coordinated work of the input module 223 and the pull-up module 221, the pull-up input signal can be stably and efficiently transmitted to the pull-up node Q(N), further improving the amplitude and rise edge steepness of the output signal of the gate drive circuit 20, which is conducive to more complete pixel charging and avoids uneven display and crosstalk.

[0036] Please see Figure 3 , Figure 3 This is a schematic diagram of a gate driving circuit provided in another embodiment of the related art. In this embodiment, a gate driving circuit 20 is provided, which includes a plurality of cascaded driving units 22, each driving unit 22 including: Pull-up module 221 has a control terminal connected to the corresponding stage transmission signal, an input terminal connected to a constant current power supply signal, and an output terminal coupled to pull-up node Q(N). It is used to output a constant current power supply signal under the control of the corresponding stage transmission signal to charge the pull-up node Q(N) so as to pull the potential of the pull-up node Q(N) up to the high potential of the constant current power supply signal. The output module 222 has its control terminal coupled to the pull-up node Q(N) and its input terminal connected to the corresponding clock signal CLK(N). When the pull-up node Q(N) is at a high potential, the clock signal CLK(N) is output as the stage transmission signal and the scan signal from the stage transmission output terminal and the scan output terminal, respectively.

[0037] In this embodiment, a DC pull-up method is used. By adding a dedicated signal line, the constant current power signal charges the pull-up node Q(N) through the pull-up module 221, enabling almost lossless transmission of a high level to the pull-up node Q(N). However, directly charging the pull-up node Q(N) through the pull-up module 221 using this DC pull-up method results in significant static power consumption. Furthermore, the constant current power signal continuously acts on the pull-up module 221, causing the electronic components within the pull-up module 221 to age under continuous voltage stress.

[0038] Please continue reading. Figure 2 To solve the above-mentioned technical problems, in some embodiments of this application, the input module 223 includes a first switch T1 and a second switch T2.

[0039] The control terminal of the first switch T1 is connected to the second power supply voltage LC2, and the input terminal is connected to the first power supply voltage LC1; the control terminal of the second switch T2 is connected to the first power supply voltage LC1, and the input terminal is connected to the second power supply voltage LC2; the output terminal of the first switch T1 and the output terminal of the second switch T2 are electrically connected, and the connection node serves as the output terminal of the input module 223.

[0040] When the first power supply voltage LC1 is high and the second power supply voltage LC2 is low, the first switch T1 is turned on so that the first power supply voltage LC1 is used as the pull-up input signal for output.

[0041] When the first power supply voltage LC1 is low and the second power supply voltage LC2 is high, the second switch T2 is turned on so that the second power supply voltage LC2 is used as the pull-up input signal for output.

[0042] The first switch T1 and the second switch T2 are connected by a cross-coupling structure. The first power supply voltage LC1 and the second power supply voltage LC2 alternately drive the first switch T1 and the second switch T2, allowing them to operate alternately. Each switch only undertakes the driving task when the corresponding phase high level arrives, remaining in the off state at other times. This avoids the device aging problem caused by long-term high voltage stress on the switches in DC pull-up circuits, thus improving circuit reliability and extending device lifespan. This structure utilizes the existing complementary clock signal CLK(N) for logic operations and level transmission, eliminating the need for additional DC power supply lines, resulting in a simpler circuit structure. It also reduces resistance losses in the conduction path, helping to lower the circuit's static power consumption.

[0043] In some embodiments, the first switch T1 and the second switch T2 are both P-type thin-film transistors; the drain of the first switch T1 and the gate of the second switch T2 are connected to the first power supply voltage LC1, the gate of the first switch T1 and the drain of the second switch T2 are connected to the second power supply voltage LC2, and the source of the first switch T1 and the source of the second switch T2 are electrically connected as the output terminal of the input module 223.

[0044] Specifically, the source of a P-type thin-film transistor is typically connected to a higher potential, the drain to a lower potential or a load, and the gate controls the on / off state. In this embodiment, the specific structure of the first switch T1 and the second switch T2 can be a P-type thin-film transistor made of amorphous silicon, low-temperature polycrystalline silicon, or oxide semiconductor material. The drain of the first switch T1 is connected to the input terminal of the first power supply voltage LC1, and its gate is connected to the input terminal of the second power supply voltage LC2; the drain of the second switch T2 is connected to the input terminal of the second power supply voltage LC2, and its gate is connected to the input terminal of the first power supply voltage LC1. The sources of the two transistors are interconnected to form a common output terminal. This connection method makes the two transistors cross-coupled. For example, the first power supply voltage LC1 and the second power supply voltage LC2 can be complementary clock signals. A P-type TFT with a channel length on the order of micrometers and a channel width on the order of tens of micrometers can be selected to achieve sufficient drive current. Alternatively, a P-type TFT with a multilayer insulating structure can be used to enhance stability. When LC1 is high, LC2 is low. At this time, the gate of the first switch T1 is low, and its source is high, so it is turned on. The high level of LC1 is output through its source. The gate of the second switch T2 is high, and its source is low, so it is turned off. The reverse is also true.

[0045] In this embodiment, by defining both the first switch T1 and the second switch T2 as P-type thin-film transistors, and employing a structure where the drain is cross-connected to the power supply voltage and the gate to the complementary power supply voltage, with the source providing a common output, the gate voltage of the P-type transistor is lower than the source voltage during high-level transmission. This satisfies the conduction condition and eliminates the threshold voltage drop, ensuring that the high-level amplitude of the pull-up input signal is completely equal to the power supply voltage. This eliminates the threshold voltage loss caused by diode connections, ensuring the integrity of the pull-up node Q(N) potential and a steep rising edge. By having the two P-type thin-film transistors alternately conduct, each transistor conducts only during the high-level phase of its corresponding complementary signal and is cut off at the other time. This avoids the long-term high-voltage stress on the switching transistors in the DC pull-up structure, reducing device aging rate and extending circuit lifespan. This structure utilizes the inherent level transmission characteristics of P-type TFTs, eliminating the need for additional DC bias circuitry, resulting in a simpler circuit topology. It also reduces static conduction paths, further reducing static power consumption.

[0046] Please see Figure 4 , Figure 4 This is a schematic diagram of the gate driving circuit provided in the second embodiment of this application. In this embodiment, the pull-up module 221 includes a pull-up transistor T3. The gate of the pull-up transistor T3 is connected to the stage transmission signal of the corresponding stage, the drain is electrically connected to the output terminal of the input module 223, and the source is electrically connected to the pull-up node Q(N) / Q(N+1). The output module 222 includes a first transistor T41 and a second transistor T42; the gates of the first transistor T41 and the second transistor T42 are electrically connected to the pull-up node Q(N) / Q(N+1); the drains of the first transistor T41 and the second transistor T42 are connected to the clock signal CLK(N) / CLK(N+1); the source of the first transistor T41 serves as the stage transmission output terminal, and the source of the second transistor T42 serves as the scan output terminal; When the pull-up node Q(N) / Q(N+1) is at a high potential, the first transistor T41 and the second transistor T42 are turned on, so that the clock signal CLK(N) / CLK(N+1) is used as the stage transfer signal C(N) / C(N+1) and the scan signal G(N) of this stage, respectively.

[0047] In a specific embodiment, the pull-up transistor T3 can be a thin-film transistor made of N-type or amorphous silicon, polycrystalline silicon, or oxide semiconductor materials. The first transistor T41 and the second transistor T42 can each use transistors with different aspect ratios to optimize drive capability, or they can use the same transistor structure to simplify the process. When the pull-up node Q(N) / Q(N+1) is high, the first transistor T41 and the second transistor T42 are turned on. When the clock signal CLK(N) / CLK(N+1) is high, the high level of the pull-up node Q(N) / Q(N+1) causes the gate potential of the two output transistors to be higher than the source potential, thereby transmitting the clock signal CLK(N) / CLK(N+1) to the output terminal without loss. This structure uses the potential state of the pull-up node Q(N) / Q(N+1) as an enable signal to control the path of the clock signal CLK(N) / CLK(N+1) to the stage transmission output terminal and the scan output terminal.

[0048] In this embodiment, by setting the gate of pull-up transistor T3 to the stage transmission signal, the drain to the output of input module 223, and the source to pull-up node Q(N) / Q(N+1), the stage transmission signal can precisely control the charging process of pull-up node Q(N) / Q(N+1). When pull-up transistor T3 is turned on, the lossless high level provided by input module 223 is transmitted to pull-up node Q(N) / Q(N+1), ensuring that the potential of pull-up node Q(N) / Q(N+1) reaches the power supply voltage level quickly and completely, thereby providing a stable control potential for subsequent signal output. By setting the gates of the first transistor T41 and the second transistor T42 in output module 222 to the pull-up node Q(N) / Q(N+1) and the drains of both to the clock signal CLK(N) / CLK(N+1), with the sources serving as the stage transmission output terminal and the scan output terminal respectively, the high potential of pull-up node Q(N) / Q(N+1) can simultaneously control the conduction of two output paths. When the clock signal CLK(N) / CLK(N+1) is high, the high level of the pull-up node Q(N) / Q(N+1) turns on the first transistor T41 and the second transistor T42, outputting the clock signal CLK(N) / CLK(N+1) as the stage transmission signal C(N) / C(N+1) and the scan signal G(N) / G(N+1) respectively. This realizes the simultaneous driving of stage transmission and scan output using the potential of a single pull-up node Q(N) / Q(N+1), simplifies the circuit structure, reduces the possibility of interference during signal transmission, and helps to improve the synchronization and stability of the drive signal output.

[0049] In some embodiments, each drive unit 22 further includes a reset module 224, which includes a first reset submodule 2241 and a second reset module 2242. The input terminal of the first reset submodule 2241 is connected to the first low-level signal VSS1, the output terminal is electrically connected to the pull-up node Q(N) / Q(N+1), and the control terminal is connected to the first reset signal, so that the first low-level signal VSS1 is output to the pull-up node Q(N) / Q(N+1) under the control of the first reset signal. The input terminal of the second reset submodule 2242 is connected to the first low-level signal VSS1, the output terminal is electrically connected to the pull-up node Q(N) / Q(N+1), and the control terminal is connected to the second reset signal, so that the first low-level signal VSS1 is output to the pull-up node Q(N) / Q(N+1) under the control of the second reset signal. The control terminal of the first reset submodule 2241 of the Nth stage drive unit 22 is electrically connected to the stage transmission output terminal of the (N+L)th stage drive unit 22, and the stage transmission signal C(N+L) of the (N+L)th stage drive unit 22 is used as the first reset signal; L and N are positive integers, L is greater than or equal to 4 and less than N; The control terminal of the second reset submodule 2242 is electrically connected to the timing controller and is used to output the first low-level signal VSS1 to the pull-up node Q(N) / Q(N+1) when the frame reset signal RST output by the timing controller is received.

[0050] Specifically, the function of the reset module 224 is to pull the potential of the pull-up nodes Q(N) / Q(N+1) down to the first low-level signal VSS1 (usually ground potential or negative power supply voltage) at a specific time to clear residual charge on the nodes and ensure the correct generation of the scan signal G(N) in the next cycle. The reset module 224 consists of a first reset submodule 2241 and a second reset submodule 2242 connected in parallel. Both transmit the first low-level signal VSS1 to the pull-up nodes Q(N) / Q(N+1), but the triggering timing is different. The control terminal of the first reset submodule 2241 receives the first reset signal, which originates from the stage transmission signal C(N+L) of the (N+L)th stage drive unit 22. Since L is greater than or equal to 4 and less than N, this means that the first reset signal does not come from the immediate preceding stage, but from a more distant preceding stage unit. This design utilizes the periodicity of the signal timing in the gate drive circuit, so that the stage transmission signal C(N+L) of the more distant subsequent stage can provide an effective low-level control signal when the current stage needs to be reset. The control terminal of the second reset submodule 2242 is directly connected to the timing controller and receives the frame reset signal RST. The frame reset signal RST is used to force the pull-up nodes Q(N) / Q(N+1) of all drive units 22 to reset at the beginning of each frame scan, so as to eliminate the charge interference left over from the previous frame.

[0051] In one embodiment, the first reset submodule 2241 includes a first reset transistor T51. The gate of the first reset transistor T51 is connected to the stage transmission signal C(N+L) of the (N+L)th stage, the source is electrically connected to the pull-up node Q(N) / Q(N+1), and the drain is connected to a first low-level signal VSS1. When the stage transmission signal C(N+L) is high, the first low-level signal VSS1 is output to the pull-up node Q(N) / Q(N+1) to reset the potential of the pull-up node Q(N) / Q(N+1). This can be understood as follows: the signal connected to the gate of the first reset transistor T51 of this stage is the stage transmission signal output by the driving unit 22 of the next L stages; that is, if this stage is the Nth stage driving unit 22, then the gate of the first reset transistor T51 of this stage is connected to the stage transmission signal C(N+L) of the (N+L)th stage; if this stage is the (N+1)th stage driving unit 22, then the gate of the first reset transistor T51 of this stage is connected to the stage transmission signal C(N+L+1) of the (N+L+1)th stage.

[0052] The second reset submodule 2242 includes a second reset transistor T52. The gate of the second reset transistor T52 is electrically connected to the timing controller, the source is electrically connected to the pull-up node Q(N), and the drain is connected to a first low-level signal VSS1. When the frame reset signal RST provided by the timing controller is high, the first low-level signal VSS1 is output to the pull-up node Q(N) to reset the potential of the pull-up node Q(N).

[0053] In a specific embodiment, both the first reset transistor T51 and the second reset transistor T52 can be constructed using N-type thin-film transistors (TFTs). Taking the first reset submodule 2241 as an example, its source is connected to a first low-level signal VSS1, its drain is connected to a pull-up node Q(N), and its gate is connected to the first reset signal as a control terminal. When the (N+L)th stage drive unit 22 outputs a high-level stage transmission signal C(N+L), this signal is inverted or directly coupled (depending on the specific circuit polarity; here, it is assumed that the low level is active or the signal polarity is matched) to turn on the first reset submodule 2241, thereby pulling the pull-up node Q(N) low. The first reset submodule 2241 and the second reset submodule 2242 can be configured to use the same N-type TFT structure, utilizing its pull-down characteristics when the gate is high-level and the source is low-level. The frame reset signal RST output by the timing controller can be a global control signal, distributed to the second reset submodule 2242 of each drive unit 22 through metal traces.

[0054] In this embodiment, by electrically connecting the control terminal of the first reset submodule 2241 to the stage transmission output terminal of the (N+L)th stage drive unit 22, and utilizing the interval relationship of L being greater than or equal to 4 and less than N, the first reset submodule 2241 can use the stage transmission signal C(N+L) from a more distant subsequent stage as the reset control signal. This non-adjacent stage reset signal multiplexing mechanism reduces the number of dedicated reset lines and simplifies the circuit wiring structure. By electrically connecting the control terminal of the second reset submodule 2242 to the timing controller to receive the frame reset signal RST, a global reset of the pull-up node Q(N) can be forcibly performed at the beginning of each frame scan, which helps to clear residual charge from the previous frame and prevent voltage drift and display abnormalities caused by charge accumulation. Through the coordinated cooperation of the first reset submodule 2241 and the second reset submodule 2242, dual protection of local automatic reset and global forced reset is achieved, enabling the potential of the pull-up node Q(N) to be pulled down to the first low level in a timely and stable manner, further improving the signal stability and reliability of the gate drive circuit 20 during continuous operation.

[0055] In some embodiments, each pair of adjacent drive units 22 constitutes a drive group 21, and each drive group 21 includes an input module 223; in each drive group 21, the input terminals of the pull-up modules 221 in the two adjacent drive units 22 are electrically connected to the output terminals of the input modules 223 respectively.

[0056] By adopting a structure where two adjacent drive units 22 share a single input module 223, both drive units 22 can simultaneously acquire lossless high-level pull-up signals generated by complementary square wave signals. This further avoids the threshold voltage accumulation loss caused by multi-stage cascaded pull-ups, ensuring the integrity of the Q(N) / Q(N+1) potential of the pull-up node in each drive unit 22. Sharing the input module 223 reduces the number of transistors and wiring complexity required for a separate input module 223 for each drive unit 22, thus reducing the overall circuit footprint and improving integration. By electrically connecting the input terminals of the pull-up modules 221 of adjacent drive units 22 to the output terminals of the input module 223, the pull-up process of these two drive units 22 is independent of the cascade signal state of the preceding drive unit 22. This helps to cut off the propagation path of faults between stages, improving the stability and reliability of the circuit operation.

[0057] In some embodiments, each drive unit 22 further includes a pull-down module 225 and a pull-down sustaining module 226; The dropdown module 225 includes: The first pull-down module 2251 includes a third transistor T43, a fourth transistor T44, and a fifth transistor T45. The gate of the third transistor T43 is electrically connected to the first pull-down node Qb1(N) / Qb1(N+1), its drain is connected to the first low-level signal VSS1, and its source is electrically connected to the pull-up node Q(N) / Q(N+1). The gate of the fourth transistor T44 is electrically connected to the first pull-down node Qb1(N) / Qb1(N+1), its drain is connected to the first low-level signal VSS1, and its source is electrically connected to the pull-up node Q(N) / Q(N+1). The gate of the fifth transistor T45 is electrically connected to the first pull-down node Qb1(N) / Qb1(N+1), the drain is connected to the second low-level signal VSS2, and the source is electrically connected to the scan output terminal. The first pull-down module 2251 is used to output the first low-level signal VSS1 to the pull-up node Q(N) / Q(N+1) and the stage transmission output terminal under the control of the signal of the first pull-down node Qb1(N) / Qb1(N+1), and output the second low-level signal VSS2 to the scan output terminal. The second pull-down module 2252 includes a sixth transistor T46, a seventh transistor T47, and an eighth transistor T48. The gate of the sixth transistor T46 is electrically connected to the second pull-down node Qb2(N) / Qb2(N+1), its drain is connected to the first low-level signal VSS1, and its source is electrically connected to the pull-up node Q(N) / Q(N+1). The gate of the seventh transistor T47 is electrically connected to the second pull-down node Qb2(N) / Qb2(N+1), its drain is connected to the first low-level signal VSS1, and its source is electrically connected to... The gate of the eighth transistor T48 is electrically connected to the second pull-down node Qb2(N) / Qb2(N+1), the drain is connected to the second low-level signal VSS2, and the source is electrically connected to the scan output terminal. The second pull-down module 2252 is used to output the first low-level signal VSS1 to the pull-up node Q(N) / Q(N+1) and the stage transmission output terminal under the control of the signal of the second pull-down node Qb2(N) / Qb2(N+1), and output the second low-level signal VSS2 to the scan output terminal. Among them, such as Figure 4 As shown, in each drive group 21, the first pull-down node Qb1(N) of the front stage is electrically connected to the second pull-down node Qb2(N+1) of the rear stage, and the second pull-down node Qb2(N) of the front stage is electrically connected to the first pull-down node Qb1(N+1) of the rear stage. The pull-down sustaining module 226 includes a ninth transistor T49, a tenth transistor T410, an eleventh transistor T411, and a twelfth transistor T412. The gate and drain of the ninth transistor T49 are connected to the first power supply voltage LC1, and the source is electrically connected to the sustaining connection node N1. The gate of the tenth transistor T410 is electrically connected to the pull-up node Q(N) / Q(N+1), the drain is connected to the first low-level signal VSS1, and the source is electrically connected to the sustaining connection node N1. The gate of the eleventh transistor T411 is electrically connected to the sustaining connection node N1, the drain is connected to the first power supply voltage LC1, and the source is electrically connected to the first pull-down node Qb1(N) / Qb1(N+1). The gate of the twelfth transistor T412 is electrically connected to the pull-up node Q(N) / Q(N+1) of the cascaded drive unit 22 in the same drive group 21, the drain is connected to the first low-level signal VSS1, and the source is electrically connected to the sustaining connection node N1.

[0058] Specifically, the aforementioned pull-down module 225 is used to pull down the potentials of the pull-up nodes Q(N) / Q(N+1), the stage transmission output terminal, and the scan output terminal at specific times to ensure the correct switching of signal potentials. The first pull-down module 2251 and the second pull-down module 2252 are connected in parallel and are controlled by different control signals, namely the potentials of the first pull-down node Qb1(N) and the second pull-down node Qb2(N). The gates of the third transistor T43, the fourth transistor T44, and the fifth transistor T45 in the first pull-down module 2251 are all connected to the first pull-down node Qb1(N). When the first pull-down node Qb1(N) is high, these transistors are turned on, applying a first low-level signal VSS1 to the pull-up nodes Q(N) / Q(N+1) and the stage transmission output terminal, and applying a second low-level signal VSS2 to the scan output terminal. Similarly, the gates of the sixth transistor T46, the seventh transistor T47, and the eighth transistor T48 in the second pull-down module 2252 are all connected to the second pull-down node Qb2(N) / Qb2(N+1) and controlled by the second pull-down node Qb2(N) / Qb2(N+1). When the second pull-down node Qb2(N) / Qb2(N+1) is high, these transistors are turned on, applying the first low-level signal VSS1 to the pull-up node Q(N) / Q(N+1) and the stage transmission output terminal, respectively, and applying the second low-level signal VSS2 to the scan output terminal.

[0059] This dual-path pull-down design provides redundancy and control flexibility. Within each drive group 21, the first pull-down node Qb1(N) of the pre-stage drive unit 22 is electrically connected to the second pull-down node Qb2(N+1) of the post-stage drive unit 22, and the second pull-down node Qb2(N) of the pre-stage drive unit 22 is electrically connected to the first pull-down node Qb1(N+1) of the post-stage drive unit 22. This cross-connection allows the pull-down actions of the upper and lower stage drive units 22 to be coordinated with each other, forming a complementary pull-down timing.

[0060] The pull-down sustaining module 226 is used to maintain the potential state of the first pull-down node Qb1(N) when a strong pull-down is not required, preventing false triggering due to floating. The ninth transistor T49 acts as a pull-up transistor, pulling the sustaining connection node N1 high to the first power supply voltage LC1. The tenth transistor T410 is controlled by the pull-up node Q(N) / Q(N+1). When the pull-up node Q(N) / Q(N+1) is low, it is turned on, pulling the sustaining connection node N1 low to the first low-level signal VSS1. The eleventh transistor T411 transmits the potential of the sustaining connection node N1 to the first pull-down node Qb1(N) / Qb1(N+1), thereby controlling the state of the first pull-down module 2251. The twelfth transistor T412 is controlled by the pull-up node Q(N) / Q(N+1) of the subsequent driving unit 22 in the same driving group 21. Its function is to feed back the state of the subsequent driving unit 22 to the sustaining connection node N1 of this stage, realizing inter-stage state linkage.

[0061] By setting up a first pull-down module 2251 and a second pull-down module 2252, and controlling them respectively by the first pull-down node Qb1(N) / Qb1(N+1) and the second pull-down node Qb2(N) / Qb2(N+1), the drive unit 22 has dual pull-down capability. This helps ensure that the pull-up node Q(N) / Q(N+1), the stage transmission output terminal, and the scan output terminal can be reliably pulled low under complex timing conditions, thus improving the stability of the signal output. In each drive group 21, the cross-connection method of electrically connecting the first pull-down node Qb1(N) of the previous stage with the second pull-down node Qb2(N+1) of the subsequent stage, and electrically connecting the second pull-down node Qb2(N) of the previous stage with the first pull-down node Qb1(N+1) of the subsequent stage, allows the pull-down control signals of adjacent drive units 22 to be interleaved. This facilitates a more refined pull-down timing coordination, enabling the pull-down action of each stage of drive unit 22 to accurately match the timing requirements of the scan signal and avoiding output glitches caused by timing misalignment. By setting up a pull-down sustaining module 226, and utilizing the sustaining circuit composed of the ninth transistor T49, the tenth transistor T410, the eleventh transistor T411, and the twelfth transistor T412, the first pull-down node Qb1(N) / Qb1(N+1) can be maintained at a defined low level when the first pull-down module 2251 is not working. This prevents the first pull-down node Qb1(N) / Qb1(N+1) from floating, which helps prevent false turn-on due to uncertain node potential, and improves the circuit's anti-interference capability and operational reliability. The twelfth transistor T412 introduces state feedback from the pull-up node Q(N) / Q(N+1) of the subsequent drive unit 22, enabling the current stage pull-down sustaining circuit to respond to state changes in the subsequent stage. This facilitates synchronization and coordination between stages, further improving the overall circuit's logic consistency.

[0062] In some embodiments, the drop-down module 225 further includes a third drop-down module 227; the third drop-down module 227 includes: The thirteenth transistor, T413, has its gate electrically connected to the pull-up node Q(N) / Q(N+1), its drain connected to the first low-level signal VSS1, and its source electrically connected to the first pull-down node Qb1(N) / / Qb1(N+1). The fourteenth transistor T414 has its gate connected to the corresponding stage transmission signal C(Nx), its drain connected to the first low-level signal VSS1, and its source electrically connected to the first pull-down node Qb1(N) / Qb1(N+1).

[0063] The aforementioned third pull-down module 227 includes a thirteenth transistor T413 and a fourteenth transistor T414, which are connected in parallel between the first pull-down node Qb1(N) / Qb1(N+1) and the first low-level signal VSS1. The gate of the thirteenth transistor T413 is directly electrically connected to the pull-up node Q(N) / Q(N+1). When the potential of the pull-up node Q(N) / Q(N+1) rises, the thirteenth transistor T413 is turned on, thereby pulling the first pull-down node Qb1(N) / Qb1(N+1) low to the first low-level signal VSS1. The gate of the fourteenth transistor T414 is connected to the stage transfer signal C(Nx) corresponding to the stage; where x is a positive integer and x is less than N; for example, x can be one of 1 to 8. When the stage transfer signal C(Nx) is valid, the fourteenth transistor T414 is turned on, which also pulls the first pull-down node Qb1(N) / Qb1(N+1) low to the first low-level signal VSS1. This design makes the potential of the first pull-down node Qb1(N) / Qb1(N+1) controlled by both the pull-up node Q(N) / Q(N+1) and the stage transfer signal C(Nx). Specifically, N-type thin-film transistors can be selected as the thirteenth transistor T413 and the fourteenth transistor T414. For example, in the operating timing of the gate drive circuit 20, when the previous stage drive unit 22 outputs the stage transfer signal C(N-1) and the pull-up node Q(N) / Q(N+1) of this stage is in a high-level state, the thirteenth transistor T413 and the fourteenth transistor T414 may both be in a conducting or pre-conducting state, quickly pulling the potential of the first pull-down node Qb1(N) / Qb1(N+1) low. This, in turn, through the linkage of the transistors in the pull-down maintenance module 226, ensures that the relevant transistors in the first pull-down module 2251 and the second pull-down module 2252 are reliably turned off or maintain a specific state, preventing node floating or malfunction. The stage transfer signal C(Nx) is usually provided by the output of the previous stage drive unit 22 for inter-stage timing transfer.

[0064] By setting up a third pull-down module 227 and using the thirteenth transistor T413 to connect the pull-up nodes Q(N) / Q(N+1) and the first pull-down nodes Qb1(N) / Qb1(N+1), the high level of the pull-up nodes Q(N) / Q(N+1) can directly and quickly control the potential of the first pull-down nodes Qb1(N) / Qb1(N+1). This facilitates close linkage between the pull-up action and the pull-down control logic, improving the synchronization of signal transmission within the circuit. By setting up a fourteenth transistor T414 to connect the stage transmission signal and the first pull-down nodes Qb1(N) / Qb1(N+1), the stage transmission signal C(Nx) can directly participate in the management of the pull-down control node of this stage. This allows the timing characteristics of the stage transmission signal C(Nx) to assist in adjusting the state of the first pull-down nodes Qb1(N) / Qb1(N+1), further enhancing the stability of the circuit during inter-stage switching. The parallel connection of the thirteenth transistor T413 and the fourteenth transistor T414 allows the first pull-down node Qb1(N) / Qb1(N+1) to be pulled low through two independent paths. This improves the redundancy and reliability of the pull-down control, ensuring that the circuit maintains the deterministic potential of the first pull-down node Qb1(N) / Qb1(N+1) under complex operating conditions, thus avoiding logic errors caused by the failure of a single control path.

[0065] Please refer to the following: Figure 4 and Figure 5 , Figure 5 This is a schematic diagram of the operating timing of a gate driving circuit according to an embodiment of this application. In this embodiment, taking the Nth stage driving unit as an example, the operating timing of the gate driving circuit 20 includes four stages. In each stage, the first power supply voltage LC1 and the second power supply voltage LC2 are ORed through the input module 223 to output a high-level pull-up input signal.

[0066] In the first stage, the corresponding stage transfer signal C(Nm) is low, the pull-up transistor T3 is cut off, and the pull-up node Q(N) is low.

[0067] In the second stage, the corresponding stage transmission signal C(Nm) is high, the pull-up transistor T3 is turned on, the pull-up node Q(N) is pulled high to the first high level, the first transistor T41 and the second transistor T42 in the output module 222 are turned on, and the corresponding clock signal CLK(N) is low, so there is no effective stage transmission signal C(N) and scan signal G(N) output.

[0068] In the third stage, the pull-up node Q(N) is coupled by the gate-source capacitance of the first transistor T41 and the second transistor T42 in the output module 222, and the potential rises again, being pulled up to the second high level; the first transistor T41 and the second transistor T42 remain in the conducting state, and the corresponding clock signal CLK(N) is at a high level. At this time, the valid stage transmission signal C(N) and the scan signal G(N) are output.

[0069] In the fourth stage, the clock signal CLK(N) is low, and the pull-up node Q(N) is pulled low.

[0070] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. In this embodiment, a display panel 100 is provided. The display panel 100 includes: Display area 101 includes arrayed sub-pixels 10 for displaying images; The non-display area 102 includes a gate driving circuit 20 as provided in any of the embodiments above. The gate driving circuit 20 is electrically connected to the sub-pixel 10 and is used to provide a scanning signal to the sub-pixel 10.

[0071] The display area 101 includes an array of sub-pixels 10 and multiple scan lines 11. The scan lines 11 extend along the row direction of the sub-pixels 10 and are arranged along the column direction of the sub-pixels 10. Specifically, there is a one-to-one correspondence between the rows of sub-pixels 10 and the scan lines 11, that is, each row of sub-pixels 10 corresponds to one scan line 11, and the sub-pixels 10 in the same row are connected to the same scan line 11.

[0072] The specific structure and function of the gate driving circuit 20 are the same as or similar to those of the gate driving circuit 20 provided in the above embodiments, and can achieve the same technical effects. For details, please refer to the above description; further details will not be repeated here. Specifically, the gate driving circuit 20 includes multiple cascaded driving units 22. Each driving unit 22 outputs a first-level scanning signal. The driving unit 22 corresponds one-to-one with and is electrically connected to the scan lines 11, thereby providing scanning signals to the sub-pixels 10 of the display area 101, so that the sub-pixels 10 open line by line according to the scanning signal timing sequence to display the corresponding image. Specifically, the display panel 100 can be a liquid crystal display or an electronic ink screen, etc.

[0073] In this embodiment, the gate driving circuit 20 sets the first power supply voltage LC1 and the second power supply voltage LC2 as complementary square wave signals, and performs a logical OR operation between them with the input module 223. This allows the high-level signal that is always present in the complementary signal to charge the pull-up nodes Q(N) / Q(N+1) during the charging process, avoiding the threshold voltage loss caused by the diode connecting the transistor in the traditional cascaded pull-up method. This ensures that the potential of the pull-up nodes Q(N) / Q(N+1) can fully reach the power supply voltage level. Moreover, by directly charging the pull-up nodes Q(N) / Q(N+1) with the power supply voltage, the propagation of faults between stages is avoided. At the same time, through the coordinated work of the input module 223 and the pull-up module 221, the pull-up input signal can be stably and efficiently transmitted to the pull-up nodes Q(N) / Q(N+1), further improving the amplitude and rise edge steepness of the output signal of the gate driving circuit 20. This is beneficial for more complete pixel charging and avoids uneven display and crosstalk. The first power supply voltage LC1 and the second power supply voltage LC2 alternately drive the first switch T1 and the second switch T2 in the input module 223, allowing the two switches to work alternately. Each switch only undertakes the driving task when the high level of its corresponding phase arrives, and remains in the off state at other times. This avoids the device aging problem caused by long-term high voltage stress on the switches in DC pull-up circuits, which is beneficial to improving circuit reliability and extending device lifespan. This structure utilizes existing phase-complementary clock signals for logic operations and level transmission without the need for additional DC power supply lines. At the same time, the phase-complementary first power supply voltage LC1 and the second power supply voltage LC2 can be reused to provide power to other modules in the gate drive circuit 20 (such as the pull-up sustaining module 226), making the circuit structure simpler and reducing the resistance loss of the conduction path, which helps to reduce the static power consumption of the circuit.

[0074] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. In this embodiment, a display device is provided, the display device comprising: The display panel 100 is the same as the display panel 100 provided in the above embodiment, and is used to display images; The data driving circuit 30 is electrically connected to the display panel 100 and is used to provide data signals to the display panel 100.

[0075] The specific structure and function of the display panel 100 are the same as or similar to those of the display panel 100 provided in the above embodiments, and can achieve the same technical effect. For details, please refer to the above description, which will not be repeated here.

[0076] The data driving circuit 30 provides data signals to the sub-pixels 10 of the display panel 100. Specifically, the display panel 100 also includes multiple data lines 12, which extend along the column direction of the sub-pixels 10 and are arranged along the row direction of the sub-pixels 10. Specifically, there is a one-to-one correspondence between the columns of sub-pixels 10 and the data lines 12, that is, each column of sub-pixels 10 corresponds to one data line 12, and sub-pixels 10 in the same column are connected to the same data line 12. When the scan signal turns on the sub-pixels 10 row by row, the data driving circuit 30 transmits data signals to the sub-pixels 10 row by row through the data lines 12, thereby displaying the corresponding image.

[0077] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A gate driving circuit, comprising a plurality of cascaded driving units, each stage of the driving unit comprising: The pull-up module has a control terminal connected to the corresponding stage transmission signal, an input terminal coupled to a power signal, and an output terminal coupled to the pull-up node. It is used to output the power signal under the control of the corresponding stage transmission signal to charge the pull-up node. The output module has a control terminal coupled to the pull-up node and an input terminal connected to a clock signal. When the pull-up node is at a high potential, the clock signal is used as a stage transmission signal and a scan signal to be output from the stage transmission output terminal and the scan output terminal, respectively. The power supply signal is characterized in that it includes a first power supply voltage and a second power supply voltage, wherein the first power supply voltage and the second power supply voltage are square wave signals with complementary phases. The gate drive circuit further includes an input module, which is coupled to the first power supply voltage and the second power supply voltage and is used to perform a logical OR operation on the first power supply voltage and the second power supply voltage to output the power supply signal as a pull-up input signal. The input terminal of the pull-up module is electrically connected to the output terminal of the input module to output the pull-up input signal under the control of the transmission signal.

2. The gate driving circuit according to claim 1, characterized in that, The input module includes a first switching transistor and a second switching transistor; The control terminal of the first switch is connected to the second power supply voltage, and its input terminal is connected to the first power supply voltage; the control terminal of the second switch is connected to the first power supply voltage, and its input terminal is connected to the second power supply voltage; the output terminals of the first switch and the second switch are electrically connected, and the connection node serves as the output terminal of the input module. When the first power supply voltage is high and the second power supply voltage is low, the first switch is turned on to output the first power supply voltage as a pull-up input signal. When the first power supply voltage is low and the second power supply voltage is high, the second switch is turned on so that the second power supply voltage is output as the pull-up input signal.

3. The gate driving circuit according to claim 2, characterized in that, Both the first and second switching transistors are P-type thin-film transistors; the drain of the first switching transistor and the gate of the second switching transistor are connected to the first power supply voltage, the gate of the first switching transistor and the drain of the second switching transistor are connected to the second power supply voltage, and the source of the first switching transistor and the source of the second switching transistor are electrically connected as the output terminal of the input module.

4. The gate driving circuit according to claim 1, characterized in that, The pull-up module includes a pull-up transistor, the gate of which is connected to the stage transmission signal of the corresponding stage, the drain of which is electrically connected to the output terminal of the input module, and the source of which is electrically connected to the pull-up node. The output module includes a first transistor and a second transistor; the gates of the first transistor and the second transistor are electrically connected to the pull-up node; the drains of the first transistor and the second transistor are connected to the clock signal; the source of the first transistor serves as the stage transmission output terminal, and the source of the second transistor serves as the scan output terminal. When the pull-up node is at a high potential, the first transistor and the second transistor are turned on to output the clock signal as the stage transmission signal and the scan signal, respectively.

5. The gate driving circuit according to claim 1, characterized in that, Each stage of the drive unit further includes a reset module, which includes a first reset submodule and a second reset module; The input terminal of the first reset submodule is connected to a first low-level signal, the output terminal is electrically connected to the pull-up node, and the control terminal is connected to a first reset signal, so that the first low-level signal is output to the pull-up node under the control of the first reset signal; The input terminal of the second reset submodule is connected to a first low-level signal, the output terminal is electrically connected to the pull-up node, and the control terminal is connected to a second reset signal, so that the first low-level signal is output to the pull-up node under the control of the second reset signal; Wherein, the control terminal of the first reset submodule of the Nth stage drive unit is electrically connected to the stage transmission output terminal of the (N+L)th stage drive unit, and the stage transmission signal of the (N+L)th stage drive unit is used as the first reset signal; L and N are positive integers, L is greater than or equal to 4 and less than N; The control terminal of the second reset submodule is electrically connected to the timing controller and is used to output the first low-level signal to the pull-up node when the frame reset signal output by the timing controller is received.

6. The gate driving circuit according to claim 1, characterized in that, Each pair of adjacent drive units forms a drive group, and each drive group includes one input module; in each drive group, the input terminals of the pull-up modules in the two adjacent drive units are electrically connected to the output terminals of the input modules, respectively.

7. The gate driving circuit according to claim 6, characterized in that, Each stage of the drive unit further includes a pull-down module and a pull-down maintenance module; The drop-down module includes: The first pull-down module includes a third transistor, a fourth transistor, and a fifth transistor. The gate of the third transistor is electrically connected to a first pull-down node, its drain is connected to a first low-level signal, and its source is electrically connected to the pull-up node. The gate of the fourth transistor is electrically connected to the first pull-down node, its drain is connected to the first low-level signal, and its source is electrically connected to the stage output terminal. The gate of the fifth transistor is electrically connected to the first pull-down node, its drain is connected to a second low-level signal, and its source is electrically connected to the scan output terminal. The first pull-down module is used to output the first low-level signal to the pull-up node and the stage output terminal, and output the second low-level signal to the scan output terminal, under the control of the signal from the first pull-down node. The second pull-down module includes a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the sixth transistor is electrically connected to the second pull-down node, its drain is connected to the first low-level signal, and its source is electrically connected to the pull-up node. The gate of the seventh transistor is electrically connected to the second pull-down node, its drain is connected to the first low-level signal, and its source is electrically connected to the stage output terminal. The gate of the eighth transistor is electrically connected to the second pull-down node, its drain is connected to the second low-level signal, and its source is electrically connected to the scan output terminal. The second pull-down module is used to output the first low-level signal to the pull-up node and the stage output terminal, and output the second low-level signal to the scan output terminal, under the control of the signal from the second pull-down node. In each of the drive groups, the first pull-down node of the front stage is electrically connected to the second pull-down node of the rear stage, and the second pull-down node of the front stage is electrically connected to the first pull-down node of the rear stage. The pull-down sustaining module includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the gate and drain of the ninth transistor are connected to the first power supply voltage, and the source is electrically connected to the sustaining connection node; the gate of the tenth transistor is electrically connected to the pull-up node, the drain is connected to the first low-level signal, and the source is electrically connected to the sustaining connection node; the gate of the eleventh transistor is electrically connected to the sustaining connection node, the drain is connected to the first power supply voltage, and the source is electrically connected to the first pull-down node; the gate of the twelfth transistor is electrically connected to the pull-up node of the cascaded driving unit in the same driving group, the drain is connected to the first low-level signal, and the source is electrically connected to the sustaining connection node.

8. The gate driving circuit according to claim 7, characterized in that, The dropdown module further includes a third dropdown module; the third dropdown module includes: The thirteenth transistor has its gate electrically connected to the pull-up node, its drain connected to the first low-level signal, and its source electrically connected to the first pull-down node. The fourteenth transistor has its gate connected to the corresponding stage transmission signal, its drain connected to the first low-level signal, and its source electrically connected to the first pull-down node.

9. A display panel, characterized in that, include: The display area includes an array of sub-pixels used to display images; The non-display area includes a gate driving circuit as described in any one of claims 1-8, the gate driving circuit being electrically connected to the sub-pixel and used to provide a scan signal to the sub-pixel.

10. A display device, characterized in that, include: The display panel is as described in claim 9, and is used to display images; A data driving circuit, electrically connected to the display panel, is used to provide data signals to the display panel.

Images