Physical layer circuit with improved read gate

Abstract

A physical layer circuit with improved read gating includes a delay circuit and an efficiency control circuit. In a first mode, corresponding to a first instruction, the efficiency control circuit generates a first reference edge in response to a first strobe edge from a memory, and the delay circuit generates a first internal edge. In a second mode, corresponding to a second instruction, the efficiency control circuit generates a second reference edge in response to a second strobe edge from the memory, and the delay circuit generates a second internal edge based on a first time difference between the first internal edge and the first reference edge, such that a second time difference between the second internal edge and the second reference edge is less than the first time difference, e.g., a multiple of the second time difference is less than the first time difference.

Description

Technical Field

[0001] This invention relates to a physical layer circuit with improved read gating, and more particularly to a physical layer circuit for accessing memory and capable of quickly locking the correct read gating timing in training mode. Background Technology

[0002] Memory is an indispensable component of modern electronic devices, and the physical layer circuitry used to access memory has become a key focus of modern electronic technology research and development. Summary of the Invention

[0003] One object of the present invention is to disclose a physical layer circuit (e.g., 10) with improved read gating. Figure 1 ), which can be coupled to a memory (e.g., 20, Figure 1 The physical layer circuit may include a delay circuit (e.g., 110, Figure 1 ), and a single-effect control circuit (e.g., 120, Figure 1 ) and a detection circuit (e.g., 130, Figure 1 The delay circuit can be coupled to a gating signal (e.g., DQS). Figure 1 The detection circuit can be coupled to the delay circuit and the effect control circuit. In a first mode (e.g., a training mode), the physical layer circuit can transmit a first instruction (e.g., cmd1) to the memory. Figure 4a This allows the memory to respond to the first instruction by sequentially forming multiple first strobe edges in the strobe signal (e.g., the edges where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tc1 and tcc1). Figure 4a ). Responding to the earliest of the multiple first gating edges (e.g., the gating edge at time tc1), Figure 4a This control circuit can be based on a reference signal (e.g., rdgt_ref). Figure 1 and Figure 4a A first reference is formed along (e.g., hr1) in the middle. Figure 4a Corresponding to the first instruction, the delay circuit can be set to an internal signal (e.g., rdgt_fbck). Figure 1 and Figure 4a A first internal edge is formed in (e.g., hn1, Figure 4a The detection circuit can detect a first time difference (e.g., dt1) between the first internal edge and the first reference edge. Figure 4a And make the corresponding detection results reflect a control signal (e.g., s_c, Figure 1 In this first mode, the physical layer circuitry can also transmit a second instruction (e.g., cmd2) to the memory. Figure 4bThis allows the memory to respond to the second instruction by sequentially forming multiple second strobe edges in the strobe signal (e.g., the edges where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tc2 and tcc2). Figure 4b ). Responding to the earliest of the multiple second gating edges (e.g., the gating edge at time tc2), Figure 4b The control circuit can also form a second reference edge (e.g., hr2) in the reference signal. Figure 4b Corresponding to the second instruction, the delay circuit can also form a second internal edge (e.g., hn2) in the internal signal according to the control signal. Figure 4b ), so that a second time difference (e.g., dt2) exists between the second inner edge and the second reference edge. Figure 4b It is less than the first time difference.

[0004] In one embodiment (e.g.) Figure 4a and Figure 4b When the delay circuit makes the second time difference less than the first time difference, the delay circuit can make the second time difference a multiple (integer multiple) less than the first time difference.

[0005] In one embodiment (e.g.) Figure 4a and Figure 4b The first time difference is greater than one interface clock cycle (e.g., T0). Figure 1 The delay circuit can be a multiple (integer multiple) of the first time difference; and when the delay circuit makes the second time difference less than the first time difference, the delay circuit can be a multiple (integer multiple) of the second time difference less than the interface clock period.

[0006] In one embodiment (e.g.) Figure 5 In a second mode (e.g., a normal mode), the physical layer circuitry can also transmit a third instruction (e.g., cmd[i]) to the memory. Figure 5 This allows the memory to respond to the third instruction by sequentially forming multiple third strobe edges in the strobe signal (e.g., the edges where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tz[i] and tzz[i]). Figure 5 ), and enable the memory to respond to the third instruction in a data signal (e.g., DQ, Figure 1 and Figure 5 Provide a third data string (e.g., u[i], ) Figure 5 Corresponding to this third instruction, the delay circuit can also be gated according to the control signal (e.g., rd_gt, ...). Figure 1 and Figure 5 A gating front is formed in the process (e.g., hp[i], Figure 5 ) and a gated trailing edge (e.g., hpp[i], Figure 5Based on the gating signal, the control circuit can further filter out those edges located between the leading and trailing edges of the gating from among the plurality of third gating edges, and reflect the filtering result in a gating signal (e.g., vDQS). Figure 1 and Figure 5 That is, the control circuit can select a subset from the plurality of third gating edges, and each gating edge in the subset occurs between the leading edge and the trailing edge of the gate. Furthermore, the physical layer circuit may also include a data circuit (e.g., 50, Figure 1 The data circuit can be coupled to the control circuit and the data signal, and can sample the data signal according to the timing of the gate selection signal to retrieve the third data string.

[0007] In one embodiment (e.g.) Figure 5 In response to the third instruction, the delay circuit can also form a third internal edge (e.g., hn[i]) in the internal signal according to the control signal. Figure 5 Based on the screening results, the control circuit can also form a third reference edge (e.g., hr[i]) in the reference signal. Figure 5 The detection circuit can also detect a third time difference (e.g., dt[i]) between the third internal edge and the third reference edge. Figure 5 This allows the corresponding detection results to be reflected in the control signal. The leading edge of the gate can be before the third inner edge, and the trailing edge can be after the third inner edge.

[0008] In one embodiment (e.g.) Figure 5 When the calibration circuit forms the third reference edge in the reference signal based on the screening result, the calibration circuit can be the earliest one of the multiple third gating edges that occurs after the gating front (e.g., the gating edge at time point tc[i]). Figure 5 The third reference edge is formed in the reference signal.

[0009] In one embodiment (e.g.) Figure 1 The physical layer circuit may also include a filter circuit (e.g., 140, Figure 1 The detection circuit is coupled between the detection circuit and the delay circuit. When the detection circuit detects the third time difference and reflects the corresponding detection result in the control signal, the detection circuit can reflect the corresponding detection result in a detection signal (e.g., s_d). Figure 1 The filtering circuit can then perform signal processing (e.g., filtering) on ​​the detected signal and reflect the result of the signal processing (filtering) in the control signal.

[0010] In one embodiment (e.g.) Figure 5When the delay circuit forms the third internal edge in the internal signal according to the control signal, the delay circuit can be at a third internal edge time point (e.g., tn[i]). Figure 5 This forms the third inner edge. The time point of this third inner edge can be a third reference time point (e.g., to[i]). Figure 5 After that, and the interval between the third reference time point and the third internal edge time point (e.g., dn[i], Figure 5 It may include a coarse adjustment period (e.g., Tn1, Figure 5 ) and a fine-tuning time period (e.g., Tn[i], Figure 5 The coarse adjustment period can be the interface clock cycle (e.g., T0). Figure 5 The fine-tuning period can be a multiple of the interface clock cycle, and the fine-tuning period can be less than the interface clock cycle.

[0011] In one embodiment (e.g.) Figure 5 The coarse adjustment period can be substantially equal to the first time difference minus the second time difference.

[0012] In one embodiment (e.g.) Figure 1 and Figure 5 This control signal may include a coarse adjustment signal (e.g., s_cr, Figure 1 ) and a fine-tuning signal (e.g., s_cf, Figure 1 When the delay circuit forms the third internal edge in the internal signal according to the control signal, the delay circuit may wait for the coarse adjustment period and the fine adjustment period according to the coarse adjustment signal and the fine adjustment signal respectively, and form the third internal edge at the time point when the waiting ends.

[0013] In one embodiment (e.g.) Figure 1 and Figure 5 The delay circuit may include a counter (e.g., 1101). Figure 1 This coarse adjustment signal can reflect a coarse adjustment number (e.g., Nk1, Figure 4a and Figure 4b When the delay circuit waits for the coarse adjustment period, it can count N interface clock cycles by the counter, where N is the number of coarse adjustments.

[0014] In one embodiment (e.g.) Figure 4a , Figure 4b and Figure 5 The number of coarse adjustments can be related to the first time difference.

[0015] In one embodiment (e.g.) Figure 1 The delay circuit may include a controlled delay line (e.g., 1102, Figure 1When the delay circuit waits for the fine-tuning period, the controlled delay line may wait for the fine-tuning period to pass; and the length of the fine-tuning period may be controlled by the fine-tuning signal.

[0016] In one embodiment (e.g.) Figure 5 When the detection circuit detects the third time difference between the third internal edge and the third reference edge, the operation of the detection circuit may include: comparing whether the third internal edge is earlier or later than the third reference edge.

[0017] In one embodiment (e.g.) Figure 4a When the detection circuit detects the first time difference between the first internal edge and the first reference edge and makes the corresponding detection result reflectable in the control signal, the operation of the detection circuit may include: counting the number of interface clock cycles covered by the first time difference and making the counting result reflectable in the control signal.

[0018] In one embodiment (e.g.) Figure 1 and Figure 6a In a second mode (e.g., a normal mode), the physical layer circuit also sequentially transmits a third instruction (e.g., cmd[i]) to the memory. Figure 6a ) and a fourth instruction (e.g., cmd[i+1], Figure 6a This causes the memory to also respond to the third and fourth instructions by sequentially forming multiple response strobe edges in the strobe signal (e.g., the edges where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tz[i] and tzz[i+1]). Figure 6a ), and cause the memory to also respond to the third and fourth instructions in a data signal (e.g., DQ, Figure 6a and Figure 6b Each of these provides a third data string (e.g., u[i], ...). Figure 6a ) and a fourth data string (e.g., u[i+1], Figure 6a If the interval between the third instruction and the fourth instruction is (e.g., Tcc[i], Figure 6a ) greater than a minimum time interval (e.g., T_min, Figure 6a The delay circuit can also be based on the control signal (e.g., s_c, Figure 1 And for a gating signal (e.g., rd_gt, Figure 1 and Figure 6a In the process, a third gating front edge, a third gating back edge, a fourth gating front edge, and a fourth gating back edge are formed (e.g., hp[i], hpp[i], hp[i+1], and hpp[i+1]). Figure 6aFurthermore, the control circuit can also select one or more third gated edges (e.g., the gated edge between time points tp[i] and tpp[i]) and one or more fourth gated edges (e.g., the gated edge between time points tp[i+1] and tpp[i+1]) from the plurality of response gated edges based on the gated signal. Each of the third gated edges can be one of the plurality of response gated edges and can be located between the leading edge and the trailing edge of the third gate; each of the fourth gated edges can be one of the plurality of response gated edges and can be located between the leading edge and the trailing edge of the fourth gate. The physical layer circuit may also include a data circuit (e.g., 50, Figure 1 The data circuit is coupled to the control circuit. The data circuit can sample the data signal according to one or more third gate selection edges to retrieve the third data string, and can sample the data signal according to one or more fourth gate selection edges to retrieve the fourth data string.

[0019] In one embodiment (e.g.) Figure 1 and Figure 6b In a second mode (e.g., a normal mode), the physical layer circuitry also sequentially transmits a third instruction (e.g., cmd[i]) to the memory. Figure 6b ) and a fourth instruction (cmd[i+1], Figure 6b This allows the memory to respond to the third and fourth instructions by sequentially forming multiple response strobe edges in the strobe signal (e.g., the edges where signals DQS_t and DQS_c change from level vq0 to level vq1 between time points tz[i] and tzz[i+1]). Figure 6b ), and enable the memory to also respond to the third and fourth instructions in a data signal (e.g., DQ, Figure 6b Each of these provides a third data string (e.g., u[i], ...). Figure 6b ) and a fourth data string (e.g., u[i+1], Figure 6b If the interval between the third instruction and the fourth instruction is (e.g., Tcc[i], Figure 6b The time interval is no greater than a minimum time interval (e.g., T_min). Figure 6b The delay circuit can also be gated by a control signal (e.g., rd_gt) based on the control signal. Figure 1 and Figure 6b In this context, an integrated gating front edge and an integrated gating back edge are formed (e.g., hp[i] and hpp[i+1]). Figure 6bThe control circuit can also select one or more gating edges from the plurality of response gating edges based on the gating signal (e.g., the gating edge between time points tp[i] and tpp[i+1]); wherein each gating edge is one of the plurality of response gating edges and is located between the leading edge and the trailing edge of the integrated gating. The physical layer circuit may also include a data circuit (e.g., 50, Figure 1 The data circuit is coupled to the control circuit; the data circuit can sample the data signal according to one or more gated strobe edges to retrieve the third data string and the fourth data string.

[0020] One object of the present invention is to disclose an improved physical layer circuit for read-gated access (e.g., 10, Figure 1 ), coupled to a memory (e.g., 20, Figure 1 The physical layer circuit may include a delay circuit (e.g., 110, Figure 1 ), and a single-effect control circuit (e.g., 120, Figure 1 ) and a detection circuit (e.g., 130, Figure 1 The control circuit can be coupled to the delay circuit and a gating signal (e.g., DQS_t). Figure 1 The detection circuit can be coupled to the delay circuit and the effect control circuit. The physical layer circuit can transmit an instruction (e.g., cmd1, cmd2, or cmd[i]) to the memory. Figure 4a , Figure 4b or Figure 5 This allows the memory to sequentially generate multiple strobe edges in the strobe signal in response to the instruction. Corresponding to this instruction, the delay circuit uses an internal signal (rdgt_fbck, Figure 1 An internal edge is formed within (e.g., hn1, hn2, or hn[i]). Figure 4a , Figure 4b or Figure 5 In a first mode (e.g., a training mode), Figure 4a or Figure 4b Under these conditions, the control circuit can respond to the earliest of the plurality of strobe edges to a reference signal (e.g., rdgt_ref). Figure 1 A reference is formed along (e.g., hr1 or hr2) in the middle. Figure 4a or Figure 4b In a second mode (e.g., a normal mode), the delay circuit can also be gated by a signal (e.g., rd_gt). Figure 1 and Figure 5 A gating front is formed in the process (e.g., hp[i], Figure 5 Furthermore, the control circuit can also respond to the nearest gating edge among the multiple gating edges (e.g., the gating edge at time point tc[i]). Figure 5The reference edge is formed in the reference signal. The gated edge precedes the inner edge. The detection circuit can detect the time difference (e.g., dt1, dt2, or dt[i]) between the inner edge and the reference edge. Figure 4a , Figure 4b or Figure 5 ), and reflect the corresponding detection results in a detection signal (e.g., s_d, Figure 1 ).

[0021] In one embodiment (e.g.) Figure 1 The physical layer circuit also includes a filter circuit (e.g., 140). Figure 1 The filter circuit is coupled between the detection circuit and the delay circuit. The filter circuit can filter the detection signal to provide a control signal (e.g., s_c). Figure 1 When the delay circuit forms the internal edge in the internal signal, the timing of the formation of the internal edge in the internal signal can be determined by the control signal.

[0022] In one embodiment (e.g.) Figure 5 When the delay circuit forms the internal edge in the internal signal, the delay circuit can be waiting for a coarse adjustment period (e.g., Tn1). Figure 5 ) and a fine-tuning time period (e.g., Tn[i], Figure 5 ) passes through, and within an internal time point (e.g., tn[i], after the waiting period ends, Figure 5 This internal edge is formed; wherein, the coarse adjustment period can be an interface clock cycle (e.g., T0, Figure 1 and Figure 5 The fine-tuning period can be an integer multiple of the clock cycle of the interface, and the fine-tuning period can be no greater than the clock cycle of the interface.

[0023] One object of the present invention is to disclose an improved read gating method, wherein the method can be implemented by a physical layer circuit (e.g., 10, Figure 1 A read gate circuit (e.g., 100) in ) Figure 1 This is implemented; the physical layer circuit can be coupled to a memory (e.g., 20, Figure 1 This method may include multiple steps. One of these steps could be: when the memory responds to a first instruction (e.g., cmd1, ...). Figure 4a And for a strobe signal (e.g., DQS, Figure 4a When multiple first strobe edges are formed in a signal, a reference signal (e.g., rdgt_ref) is referenced based on one of these first strobe edges (e.g., the earliest one). Figure 4a A first reference is formed along (e.g., hr1) in the middle. Figure 4a One of these steps could be: corresponding to the first instruction, to an internal signal (e.g., rdgt_fbck, Figure 1 and Figure 4a A first internal edge is formed in (e.g., hn1, Figure 4a One of these steps could be: detecting a first time difference (e.g., dt1) between the first inner edge and the first reference edge. Figure 4a And make the corresponding detection result reflect a control signal. One of these steps could be: when the memory responds to a second instruction (e.g., cmd2, ...), Figure 4b When multiple second gating edges are formed in the gating signal, a second reference edge (e.g., hr2) is formed in the reference signal based on one of these second gating edges (e.g., the earliest one). Figure 4b One of these steps could be: corresponding to the second instruction, forming a second internal edge (e.g., hn2) in the internal signal based on the control signal. Figure 4b ), so that a second time difference (e.g., dt2) exists between the second inner edge and the second reference edge. Figure 4b The second time difference is less than the first time difference, for example, a multiple (integer multiple) of the second time difference is less than the first time difference.

[0024] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0025] Figure 1 The illustration shows an electronic device according to an embodiment of the present invention, wherein the electronic device may include a physical layer circuit and a memory, and the physical layer circuit may include a read gate circuit, etc.

[0026] Figures 2a to 2d as well as Figures 3a to 3c Example Figure 1 An example of waveform timing of relevant signals when the physical layer circuit reads the memory in a normal mode.

[0027] Figures 4a to 4c Example Figure 1 An example of reading the waveform timing of relevant signals when the gated circuit is operating in a training mode.

[0028] Figure 5 , Figure 6a and Figure 6b Example Figure 1 An example of reading the waveform timing of relevant signals when the gated circuit is operating in this normal mode.

[0029] List of reference numerals

[0030] 10: Physical layer circuit

[0031] 12a to 12d: Lines

[0032] 20: Memory

[0033] 22: Storage Controller

[0034] 26: Bus

[0035] 30: Clock circuit

[0036] 40: Instruction Circuit

[0037] 50: Data Circuits

[0038] 60: Input / output circuit

[0039] 100: Read the gate circuit

[0040] 110: Delay circuit

[0041] 120: Effect control circuit

[0042] 130: Detection circuit

[0043] 140: Filtering circuit

[0044] 1000: Electronic devices

[0045] 1101: Counter

[0046] 1102: Controlled Delay Line

[0047] cmd, DQ, DQS, DQS_t, DQS_c, rdgt_ref, rdgt_fbck, rd_gt, s_c, s_cr, s_cf, s_d, s_dr, s_df, vDQS, vDQS_t, vDQS_c: signals

[0048] cmd1, cmd2, cmd#, cmd[i], cmd[i+1]: commands

[0049] CK_t, CK_c, ck0: Clock

[0050] d1, d2, d#, d[i], d[i+1], dd1, dd2, dd#, dd[i], dd[i+1], dn1, dn2, dn#, dn[i], dn[i+1], dt1, dt2, dt#, dt[i], dt[i+1], g0 , p0, RL0, Tcc[i], Tdq0, Tdqs0, TG0, T_min, T_mrg[i], Tn1, Tn[i], Tn[i+1], Tpre[i], Tpre[i+1], Tpst[i], Tpst[i+1]: Period

[0051] hn1, hn2, hn#, hn[i], hn[i+1], hr1, hr2, hr#, hr[i], hr[i+1]: main edge

[0052] hp[i], hp[i+1], hpp[i], hpp[i+1]: along

[0053] n1 to n11: Nodes

[0054] Nk1: Number

[0055] PU[1], PU[m], PU[M]: Processing units

[0056] s_cr[i-1], s_cf[i-1], s_cr[i], s_cf[i]: signal value

[0057] ta1, ta2, ta#, ta[i], ta[i+1], taa1, taa2, taa#, taa[i], taa[i+1], tb1, tb2, tb#, tb[i], tb[i+1], tbb1, tbb2, tbb#, tbb[i], tbb[i+1], tc1, tc2, tc#, tc[i], tc[i+1], tcc1, tcc2, tcc#, tcc[i], tcc[i+1], td1, td2, td#, td[i], td[i+1], tdd1, tdd2, tdd# , tdd[i], tdd[i+1], tn1, tn2, tn#, tn[i], tn[i+1], tnn1, tnn2, tnn#, tnn[i], tnn[i+1], to1, to2, to#, to[i], tp[i], tp[i+1] , tpp[i], tpp[i+1], tr1, tr2, tr#, tr[i], tr[i+1], trr1, trr2, trr#, trr[i], trr[i+1], tz[i], tz[i+1], tzz[i], tzz[i+1]: time point

[0058] T0: Period

[0059] u1, u2, u#, u[i], u[i+1]: data string

[0060] vc0, vc1, vg0, vg1, vk0, vk1, vn0, vn1, vp0, vp1, vq0, vq1, vr0, vr1: Level Detailed Implementation

[0061] Figure 1The illustration shows an electronic device 1000 according to an embodiment of the present invention, which may be a smartphone, tablet computer, laptop computer, desktop computer, smart home appliance, or smart office appliance, etc. The electronic device 1000 may include one or more processing units PU[1] to PU[M], a storage controller 22, a physical layer circuit 10, and a memory 20. In the electronic device 1000, the processing units PU[1] to PU[M] may be coupled to the storage controller 22 via a bus 26, and the physical layer circuit 10 may be coupled between the storage controller 22 and the memory 20.

[0062] In the electronic device 1000, each processing unit PU[m] (one of PU[1] to PU[M]) can be a central processing unit (or core unit), application processing unit, logic processing unit, arithmetic processing unit, signal processing unit, graphics processing unit, neural network processing unit, or peripheral unit, etc. When the memory 20 operates in a normal mode, the memory 20 can provide storage space for the processing units PU[1] to PU[M]. In one embodiment, the memory 20 can be a synchronous dynamic random-access memory (SDRAM), such as a double data rate (DDR) synchronous dynamic random-access memory. In one embodiment, the memory 20 may be a memory that conforms to an industry standard; for example, this industry standard may be a standard developed by the Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association, such as standards related to fourth-generation dual data rate (DDR4), fifth-generation dual data rate (DDR5), fourth-generation low-power dual data rate (LPDDR4, where LP stands for low power), and fifth-generation low-power dual data rate (LPDDR5).

[0063] The physical layer circuit 10 may include a clock circuit 30, an instruction circuit 40, a data circuit 50, and an input-output circuit 60. To implement this invention, the physical layer circuit 10 may also include a readgating circuit 100. In the physical layer circuit 10, the clock circuit 30 may include two input terminals, respectively coupled to nodes n7 and n8. The instruction circuit 40 may include an output terminal, coupled to node n9. The data circuit 50 may include an input terminal and two connection terminals, respectively coupled to nodes n6, n10, and n11. The input-output circuit 60 may be coupled to the memory 20 via lines 12a to 12d; the input-output circuit 60 may include two input terminals, two output terminals, and four connection terminals, respectively coupled to nodes n7 and n9, lines 12a and 12b, line 12c, line 12d, and nodes n10 and n11. The read gate circuit 100 may include an input terminal and an output terminal, which are coupled to nodes n11 and n6 respectively.

[0064] In physical layer circuit 10, clock circuit 30 can provide a pair of differential clocks CK_t and CK_c at node n7, and can provide another clock ck0 at node n8. For example... Figure 1 As shown, clocks CK_t and CK_c can oscillate between two levels vc1 and vc0, with equal oscillation periods and a 180-degree phase difference. In one embodiment, levels vc0 and vc1 can represent logic 0 and logic 1, respectively. The edge of clock CK_t changing from level vc0 to level vc1 can be considered a significant edge of clock CK_t, and the interval between two adjacent significant edges of clock CK_t can be one period T0 of clock CK_t; for example, period T0 can represent the industry-standard time measurement unit nCK. Clock ck0 can oscillate between two levels vk0 and vk1; in one embodiment, the oscillation period of clock ck0 can be half that of clock CK_t. In one embodiment, levels vk0 and vk1 can represent logic 0 and logic 1, respectively. The edge of clock ck0 changing from level vk0 to level vk1 can be considered a significant edge of clock ck0, and each significant edge of clock CK_t can be synchronized (e.g., aligned) with a corresponding significant edge of clock ck0. In one embodiment, the physical layer circuit 10 can operate under the trigger of clock ck0, and the input / output circuit 60 can drive the line 12a according to the timing of clocks CK_t and CK_c, so that the memory 20 can operate according to the timing of clocks CK_t and CK_c. In the physical layer circuit 10, clocks CK_t and CK_c can be regarded as interface clocks, period T0 can be regarded as an interface clock period, and clock ck0 can be regarded as an internal clock.

[0065] In the physical layer circuit 10, the instruction circuit 40 can provide a signal cmd at node n9, and the input / output circuit 60 can drive line 12b according to the signal cmd. When the processing unit PU[m] requests to store a write data into the memory 20, the memory controller 22 can control the physical layer circuit 10 according to this request. Under the control of the memory controller 22, the instruction circuit 40 in the physical layer circuit 10 can keep the memory 20 in a normal mode and can form a corresponding write instruction (not shown) in the signal cmd. The data circuit 50 can drive a signal DQ on node n10 according to the content of the write data, and can drive a signal DQS on node n11 according to the timing of the write data. According to the signal cmd, the input / output circuit 60 can drive line 12b to transmit the write instruction to the memory 20. The data circuit 50 drives node n10, causing the input / output circuit 60 to drive line 12c accordingly, and consequently, the memory 20 receives a write data signal (not shown). The data circuit 50 drives node n11, causing the input / output circuit 60 to drive line 12d accordingly, and consequently, the memory 20 learns the timing of the write data in the write data signal. Based on the timing of the write data, the memory 20 can sample the write data signal to retrieve the write data and store the write data according to the write instruction.

[0066] On the other hand, when the processing unit PU[m] requests to read memory 20, the memory controller 22 can control the physical layer circuit 10 according to this request. Under the control of the memory controller 22, the instruction circuit 40 in the physical layer circuit 10 can keep memory 20 in normal mode and can generate a corresponding read instruction (not shown) in the signal cmd. According to the signal cmd, the input / output circuit 60 can drive line 12b to transmit the read instruction to memory 20. In response to this read instruction, memory 20 can read a corresponding piece of stored data (not shown), can drive line 12c according to the content of the stored data, and can drive line 12d according to the timing of the stored data. The memory 20 drives line 12c, causing the input / output circuit 60 to correspondingly drive the signal DQ of node n10, and consequently, the data circuit 50 receives a stored data signal (not shown). The memory 20 drives line 12d, causing the input / output circuit 60 to correspondingly drive the signal DQS of node n11, and consequently, the read gate circuit 100 learns the timing of the stored data in the stored data signal. The read gate circuit 100 can reflect the timing of the stored data in a signal vDQS of node n6. Based on the signal vDQS, the data circuit 50 can sample the stored data signal to retrieve the stored data, and the storage controller 22 can then send the retrieved stored data back to the processing unit PU[m].

[0067] In the physical layer circuit 10, the signal cmd can be considered an instruction signal, the signal DQ can be considered a data signal, the signal DQS can be considered a strobe signal, and the signal vDQS can be considered a gated strobe signal. In one embodiment, the signal DQS may include a pair of differential signals DQS_t and DQS_c. In one embodiment, the signal vDQS may include a pair of differential signals vDQS_t and vDQS_c.

[0068] continue Figure 1 , Figures 2a to 2d An example illustrating the waveform timing of relevant signals when the physical layer circuit 10 reads the memory 20 in normal mode is given. Figure 2a As shown, when reading memory 20 in normal mode, instruction circuit 40 can form an instruction cmd[i] in signal cmd between two time points ta[i] and taa[i], such as a read instruction. In one embodiment, the interval between time points ta[i] and taa[i] can be equal to four cycles T0. Time points ta[i] and taa[i] can be located at two different dominant edges of clock CK_c (the edge where clock CK_c changes from level vc0 to level vc1). Input / output circuit 60 in physical layer circuit 10 can transmit instruction cmd[i] to memory 20 via line 12b. In response to this instruction cmd[i], memory 20 can read stored data (not shown), drive line 12c according to this stored data, and drive line 12d according to the timing of this stored data.

[0069] The driving of line 12d by memory 20 can make signals DQS_t and DQS_c present a clear waveform between two time points tz[i] and tzz[i], thereby sequentially forming multiple gating edges in signals DQS_t and DQS_c. Each gating edge in signal DQS_t can be an edge where signal DQS_t changes from one level vq0 to another level vq1, and each gating edge in signal DQS_c can be an edge where signal DQS_c changes from level vq0 to level vq1. In one embodiment, levels vq0 and vq1 can represent logic 0 and logic 1, respectively. Before and after memory 20 drives line 12d in response to instruction cmd[i], memory 20 does not drive line 12d; therefore, the waveforms of signals DQS_t and DQS_c before time point tz[i] and after time point tzz[i] are unclear. Figure 2a The middle part is represented by a diagonal shading.

[0070] The drive of line 12c by memory 20 enables signal DQ to exhibit a distinct waveform between two time points td[i] and tdd[i], thereby providing a data burst u[i] in signal DQ, which is the stored data read by memory 20. The data burst u[i] can have multiple string positions, and the number of these positions can be represented by a parameter BL (burst length, not shown) in industry standards; for example, parameter BL can be an even number. The data burst u[i] can extend for a time period Tdq0, that is, the interval between time points td[i] and tdd[i] can be equal to the time period Tdq0; in one embodiment, the length of time period Tdq0 can be equal to half of parameter BL multiplied by the period T0 (i.e., Tdq0 = (BL / 2)). T0). Before and after memory 20 responds to instruction cmd[i] and drives line 12c, memory 20 does not drive line 12c. Therefore, the waveform of signal DQ before time point td[i] and after time point tdd[i] is unclear. Figure 2a The middle part is represented by a diagonal shading.

[0071] Between two time points tc[i] and tcc[i], the gating edges of signals DQS_t and DQS_c can correspond to the timing of each bit in the data string u[i]. For example, the gating edge of signal DQS_t between time points tc[i] and tcc[i] can correspond to the odd-numbered positions (first, third, fifth, etc.) of the data string u[i], while the gating edge of signal DQS_c between time points tc[i] and tcc[i] can correspond to the even-numbered positions (second, fourth, sixth, etc.) of the data string u[i]. Time point tc[i] can be located at a gating edge of signal DQS_t, and time point tcc[i] can be located at a gating edge of signal DQS_c. The interval between time points tc[i] and tcc[i] can be equal to a time period Tdqs0, for example, the period T0 multiplied by a value (BL / 2-0.5). Between time points tc[i] and tcc[i], the number of gating edges in signal DQS_t can be equal to half of parameter BL, and the number of gating edges in signal DQS_c can be equal to half of parameter BL. Because the routing distributions of lines 12c and 12d may be different, time point tc[i] can be earlier than time point td[i], and the interval between the two can be equal to a time period dd[i]. The length of the time period dd[i] can represent a parameter tDQSQ (gating-to-data time difference (DQS-DQ skew), not shown) in the industry standard.

[0072] Since the transmission of instruction cmd[i] and the response of memory 20 require time, time point tc[i] can lag behind a time point tb[i] in instruction cmd[i]. Here, time point tb[i] can be the last major edge of clock CK_t before the end of instruction cmd[i] (at time point taa[i]). There can be another time point tbb[i] between time point tb[i] and time point tc[i]. The interval between time points tb[i] and tbb[i] can be equal to a time period RL0, and the interval between time points tbb[i] and tc[i] can be equal to a time period d[i]. Here, time period RL0 can be equal to the period T0 multiplied by a parameter RL (read latency, not shown) in the industry standard. Time period d[i] can represent another parameter tDQSCK (DQS output access time from CK_t / CK_c, not shown) in the industry standard.

[0073] like Figure 2a As shown, time point tz[i] can be earlier than time point tc[i], and can be separated from time point tc[i] by a time interval Tpre[i]. The time interval Tpre[i] is the preamble added by memory 20 to signals DQS_t and DQS_c; the length of the time interval Tpre[i] can represent a parameter tRPRE (read preamble, not shown) in the industry standard. Furthermore, as Figure 2a As shown, time point tcc[i] can be earlier than time point tzz[i], and can be separated from time point tzz[i] by a time interval Tpst[i]. The time interval Tpst[i] is the postamble added by memory 20 to signals DQS_t and DQS_c; the length of the time interval Tpst[i] can represent a parameter tRPST (read postamble, not shown) in the industry standard.

[0074] exist Figure 2a In the example, the preambles of signals DQS_t and DQS_c in the preamble period Tpre[i] are in the industry-standard toggle form, and the postambles in the postamble period Tpst[i] are in the industry-standard 0.5nCK form; that is, the period Tpst[i] can be equal to half a period T0. The preambles and postambles of signals DQS_t and DQS_c can also be in other forms, such as... Figures 2b to 2d As shown. In Figure 2bIn the example, the preamble of signals DQS_t and DQS_c in the preamble period Tpre[i] is in a switching form, while the postamble in the postamble period Tpst[i] is in the industry standard 1.5nCK form; that is, the period Tpst[i] can be equal to one and a half cycles T0, and the postamble period Tpst[i] of signals DQS_t and DQS_c will be extended by one cycle T0 more than half a cycle T0. Figure 2c In the example, the preambles of signals DQS_t and DQS_c in the preamble period Tpre[i] are in the industry standard static form, while the postamble in the postamble period Tpst[i] is in the 0.5nCK form. Figure 2d In the example, the preamble of signals DQS_t and DQS_c in the preamble period Tpre[i] is in static form, while the postamble in the postamble period Tpst[i] is in 1.5nCK form.

[0075] As mentioned earlier, the gating edges of signals DQS_t and DQS_c between time points tc[i] and tcc[i] correspond to the timing of each bit in the data string u[i]. Therefore, the gating edges of signals DQS_t and DQS_c between time points tc[i] and tcc[i] can be considered as valid gating edges; when physical layer circuit 10 ( Figure 1 When the data circuit 50 in the memory 20 needs to sample the signal DQ to retrieve the stored data sent back to the physical layer circuit 10, these valid gating edges can be used as the basis for sampling. Among the multiple valid gating edges of signals DQS_t and DQS_c between time points tc[i] and tcc[i], the gating edge occurring at time point tc[i] is the earliest valid gating edge. On the other hand, as Figures 2a to 2d As shown, signals DQS_t and / or DQS_c may also have gating edges in the preamble period Tpre[i] and / or the postamble period Tpst[i]. However, if the data circuit 50 in the physical layer circuit 10 incorrectly samples the signal DQ based on the gating edges in the preamble period Tpre[i] and / or the postamble period Tpst[i], it will sample areas with unclear waveforms in the signal DQ (shaded areas), making it impossible to correctly retrieve the stored data in the memory 20. Therefore, the gating edges of signals DQS_t and DQS_c in the preamble and postamble can be considered invalid gating edges. The read gate circuit 100 in the physical layer circuit 10 can remove the preamble and postamble from signals DQS_t and DQS_c, and reflect the removal result in signals vDQS_t and vDQS_c, so that the data circuit 50 can correctly sample the signal DQ based on signals vDQS_t and vDQS_c.

[0076] When processing units PU[1] to PU[M] frequently access memory 20, physical layer circuit 10 will also frequently transfer the corresponding instructions to memory 20, thus shortening the interval between two adjacent instructions. Figure 1 and Figures 2a to 2d , Figures 3a to 3c This example illustrates the waveform timing of relevant signals when physical layer circuit 10 accesses memory 20 in normal mode using two adjacent instructions cmd[i] and cmd[i+1]. Figure 3a As shown, in response to a certain access request (e.g., a read request) from processing units PU[1] to PU[M], the instruction circuit 40 can form an instruction cmd[i] (e.g., a read instruction) in the signal cmd between time points ta[i] and taa[i]. In response to the next access request (e.g., the next read request) from processing units PU[1] to PU[M], the instruction circuit 40 can form the next instruction cmd[i+1] (e.g., the next read instruction) in the signal cmd between time points ta[i+1] and taa[i+1] after time point taa[i].

[0077] like Figures 2a to 2d As described, in response to the instruction cmd[i], memory 20 can drive lines 12c and 12d; the driving of line 12d by memory 20 can cause signals DQS_t and DQS_c to form multiple gating edges with a defined waveform between time points tz[i] and tzz[i], and the driving of line 12c by memory 20 can provide the data string u[i] in signal DQ between time points td[i] and tdd[i]. Among them, time point tz[i] can be before time point tc[i] and separated from time point tc[i] by a preamble period Tpre[i]; time point tzz[i] can be after time point tcc[i] and separated from time point tcc[i] by a postamble period Tpst[i]; time point tcc[i] can be after time point tc[i] and separated from time point tc[i] by a period Tdqs0. Regarding signal DQS, time point tc[i] can be after another time point tbb[i], with an interval of time period d[i] between them; time point tbb[i] can be after time point tb[i], with an interval of time period RL0 between them; time point tb[i] can be the last major edge of clock CK_t before the end of instruction cmd[i] (time point taa[i]). Regarding signal DQ, time point td[i] can be after time point tc[i], with an interval of time period dd[i] between them; time point tdd[i] can be after time point td[i], with an interval of time period Tdq0 between them.

[0078] Similarly, in response to the instruction cmd[i+1], memory 20 can drive lines 12c and 12d; the driving of line 12d by memory 20 can cause signals DQS_t and DQS_c to form multiple gating edges with a defined waveform between two time points tz[i+1] and tzz[i+1], and the driving of line 12c by memory 20 can provide a data string u[i+1] in signal DQ between two other time points td[i+1] and tdd[i+1]. Regarding the signal DQS, time point tz[i+1] can be before time point tc[i+1], and separated from time point tc[i+1] by a preamble period Tpre[i+1]; time point tzz[i+1] can be after another time point tcc[i+1], and separated from time point tcc[i+1] by a postamble period Tpst[i+1]; time point tcc[i+1] can be after time point tc[i+1], and separated from time point tc[i+1] by a time interval Tpst[i+1]. The time interval is Tdqs0; time point tc[i+1] can be after time point tbb[i+1] and separated from time point tbb[i+1] by a time interval d[i+1]; time point tbb[i+1] can be after another time point tb[i+1] and separated from time point tb[i+1] by a time interval RL0; time point tb[i+1] can be the last major edge of clock CK_t before the end of instruction cmd[i+1] (time point taa[i+1]). Regarding signal DQ, time point td[i+1] can be after time point tc[i+1] and separated from time point tc[i+1] by a time interval dd[i+1]; time point tdd[i+1] can be after time point td[i+1] and separated from time point td[i+1] by a time interval Tdq0.

[0079] The timing of the subsequent instruction cmd[i+1] (tb[i+1]) can be separated from the timing of the previous instruction cmd[i] (tb[i]) by a time interval Tcc[i]. This time interval Tcc[i] represents a parameter tCCD (CAS-to-CAS delay, not shown) in the industry standard. The more frequent the read demand, the closer the timings tb[i] and tb[i+1] of adjacent instructions cmd[i] and cmd[i+1] will be, and the shorter the time interval Tcc[i] between tb[i] and tb[i+1]. Consequently, the timings tzz[i] (the end of the subsequent preamble time interval Tpst[i]) and tz[i+1] (the beginning of the preamble time interval Tpre[i+1]) of the related signals DQS_t and DQS_c will also be closer. Figure 3aIt can be seen that since time point tzz[i] can be equal to (tb[i] + RL0 + d[i] + Tdqs0 + Tpst[i]), and time point tz[i+1] can be equal to (tb[i+1] + RL0 + d[i+1] - Tpre[i+1]), the difference between time points tzz[i] and tz[i+1] (tz[i+1] – tzz[i]) can be equal to (tb[i+1] - tb[i] + d[i+1] - d[i] - Tpre[i+1] - Tdqs0 - Tpst[i]); furthermore, since (tb[i+1] – tb[i]) can be equal to Tcc[i], and the difference between time periods d[i+1] and d[i] is relatively small and can be regarded as zero, the difference between time points tz[i+1] and tzz[i] (tz[i+1] – tzz[i]) can be equal to (tz[i+1] – tcc[i]). –tzz[i]) can be further simplified to (Tcc[i] – Tdqs0 – Tpre[i+1] – Tpst[i]). Therefore, when time period Tcc[i] equals the sum of time periods Tpre[i+1], Tdqs0, and Tpst[i], time point tz[i+1] will coincide with tzz[i]. For ease of discussion, the sum of time periods Tpre[i+1], Tdqs0, and Tpst[i] is defined as a time period T_mrg[i], as follows... Figure 3a As shown.

[0080] exist Figure 3a In the example, the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is greater than the time interval T_mrg[i], which is sufficient to make time point tzz[i] lead time point tz[i+1]. However, when instructions cmd[i] and cmd[i+1] are closer, causing the time interval Tcc[i] to be less than the time interval T_mrg[i], memory 20 can combine (merge) the postcode corresponding to instruction cmd[i] with the precode corresponding to instruction cmd[i+1], such as... Figure 3b As shown. In Figure 3b In this context, memory 20 can continuously drive line 12d in response to instructions cmd[i] and cmd[i+1], so that signals DQS_t and DQS_c can continuously present a clear waveform between time point tcc[i] (the start point of the postcode corresponding to instruction cmd[i]) and time point tc[i+1] (the end point of the precode corresponding to instruction cmd[i+1]), in order to combine the postcode corresponding to instruction cmd[i] and the precode corresponding to instruction cmd[i+1]. In contrast, in Figure 3a In the example, signals DQS_t and DQS_c will not continuously exhibit a clear waveform between time points tcc[i] and tc[i+1]. Figure 3aIn the example, memory 20 does not combine the postcode corresponding to instruction cmd[i] with the precode corresponding to instruction cmd[i+1]. After responding to instruction cmd[i], memory 20 will not drive line 20d for a period of time. Therefore, signals DQS_t and DQS_c will not have a clear waveform between time points tzz[i] and tz[i+1] (i.e., the shaded area).

[0081] exist Figure 3b In the example, the waveforms of signals DQS_t and DQS_c at times tcc[i] and tc[i+1] due to the combination of preamble and postamble are related to factors such as the form of the preamble, the form of the postamble, and the length of the time period Tcc[i]. This has been described in industry standards and will not be repeated here. Figure 3b In the example, the explicit waveforms of signals DQS_t and DQS_c between time points tcc[i] and tc[i+1] may form one or more gating edges, but these or more gating edges are invalid gating edges.

[0082] Depend on Figure 3b It can be seen that since the end point tdd[i] of the data string u[i] can be equal to (tb[i] + RL0 + d[i] + dd[i] + Tdq0) and the start point td[i+1] of the data string u[i+1] can be equal to (tb[i+1] + RL0 + d[i+1] + dd[i+1]), the difference between the time points tdd[i] and td[i+1] (td[i+1] – tdd[i]) can be equal to (tb[i+1] – tb[i] + d[i+1] – d[i] + dd[i+1] – dd[i] – Tdq0). Since the difference between time periods dd[i+1] and dd[i] (dd[i+1] – dd[i]) is relatively small and can be considered zero, the difference between time points tdd[i] and td[i+1] (td[i+1] – tdd[i]) can be further simplified to (Tcc[i] - Tdq0). Therefore, when time period Tcc[i] equals time period Tdq0, time points tdd[i] and td[i+1] will coincide. For ease of discussion, time period Tdq0 is defined as a time period T_min; time period T_min can be considered as a minimum interval time period.

[0083] exist Figure 3bIn the example, the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is greater than the time interval T_min, which is sufficient to make the end point tdd[i] of data string u[i] precede the start point td[i+1] of data string u[i+1]. However, when instructions cmd[i] and cmd[i+1] are closer and the time interval Tcc[i] equals the time interval T_min, the time points tdd[i] and td[i+1] will coincide. Memory 20 can seamlessly connect the data string u[i] corresponding to instruction cmd[i] and the data string u[i+1] of instruction cmd[i+1] in the signal DQ, and can make the postcode corresponding to instruction cmd[i] and the precode corresponding to instruction cmd[i+1] disappear in the signals DQS_t and DQS_c, such as... Figure 3c As shown. In Figure 3c In this context, memory 20 can continuously and uninterruptedly drive line 12d in response to instructions cmd[i] and cmd[i+1], so that signals DQS_t and DQS_c can continuously present a clear waveform between time point tz[i] (the start point of the preamble corresponding to instruction cmd[i]) and time point tzz[i+1] (the end point of the postamble corresponding to instruction cmd[i+1]). Between time point tc[i] (the end point of the preamble corresponding to instruction cmd[i]) and time point tcc[i+1] (the start point of the postamble corresponding to instruction cmd[i+1]), each gating edge of signals DQS_t and DQS_c is a valid gating edge and can correspond to a bit in data string u[i] or u[i+1]; that is, the postamble corresponding to instruction cmd[i] and the preamble corresponding to instruction cmd[i+1] will disappear.

[0084] Regardless of whether the postcode and precode of the two instructions are combined ( Figure 3a ), combined ( Figure 3b ) or disappear ( Figure 3c The read gate circuit 100 of the present invention ( Figure 1 Both can remove invalid strobe edges from signals DQS_t and DQS_c, and reflect valid strobe edges from signals DQS_t and DQS_c in signals vDQS_t and vDQS_c. For example... Figure 1As shown, the read gate circuit 100 may include a delay circuit 110, a validation-control circuit 120, a detection circuit 130, and a filter circuit 140. The delay circuit 110 may include one input and two outputs, respectively coupled to nodes n4, n5, and n2. The validation-control circuit 120 may include two inputs and two outputs, respectively coupled to nodes n5, n11, and two other nodes n1 and n6. The detection circuit 130 may include two inputs and one output, respectively coupled to nodes n1, n2, and another node n3. The filter circuit 140 may include one input and one output, respectively coupled to nodes n3 and n4. The delay circuit 110 provides two signals, rd_gt and rdgt_fbck, at nodes n5 and n2 respectively. The control circuit 120 provides a signal rdgt_ref at node n1 and a signal vDQS (including signals vDQS_t and vDQS_c) at node n6. The detection circuit 130 provides a signal s_d at node n3, and the filter circuit 140 provides a signal s_c at node n4. Here, the signal rdgt_ref can be considered a reference signal, the signal rdgt_fbck can be considered an internal signal, the signal rd_gt can be considered a gating signal, and the signals s_d and s_c can be considered a detection signal and a control signal respectively.

[0085] To achieve this invention, before the memory 20 operates in normal mode, the physical layer circuitry 10 can first put the memory 20 into a training mode, such as the industry-standard read preamble training mode. (Continuing...) Figure 1 , Figures 4a to 4c This example illustrates a waveform timing embodiment for reading relevant signals when the gate circuit 100 is operating in training mode. After the memory 20 is put into training mode, the instruction circuit 40 in the physical layer circuit 10 can issue an instruction cmd1 to the memory 20 between two time points ta1 and taa1, such as... Figure 4a As shown. Before time point ta1, when memory 20 has entered training mode, memory 20 can drive line 12d to maintain signals DQS_t and DQS_c at levels vq0 and vq1 respectively, and can drive line 12c to maintain signal DQ at a fixed level. Afterwards, in response to the instruction cmd1 from time points ta1 to taa1, memory 20 can correspondingly change the driving of lines 12c and 12d; the driving of line 12d by memory 20 can sequentially form multiple gating edges (edges changing from level vq0 to level vq1) in signals DQS_t and DQS_c between two time points tc1 and tcc1, and the driving of line 12c by memory 20 can provide a data string u1 in signal DQ between two time points td1 and tdd1. Figure 4aAs shown, time point tcc1 can be after time point tc1, with an interval of time period Tdqs0; time point tc1 can be after another time point tbb1, with an interval of time period d1; time point tbb1 can be after yet another time point tb1, with an interval of time period RL0; time point tb1 can be the last major edge of clock CK_t before time point taa1. Time point td1 can be after time point tc1, with an interval of time period dd1; time point tdd1 can be after time point td1, with an interval of time period Tdq0.

[0086] like Figure 4a As shown, at the earliest gate edge in the corresponding signal DQS_t (i.e., the gate edge at time point tc1), the effect control circuit 120 can change the signal rdgt_ref from one level vr0 to another level vr1 at a time point tr1, so as to form a major edge hr1 in the signal rdgt_ref. In one embodiment, time point tr1 can coincide with or be very close to time point tc1, and levels vr0 and vr1 can represent logic 0 and logic 1, respectively. At another time point trr1 after time point tr1, the effect control circuit 120 can change the signal rdgt_ref from level vr1 back to level vr0, so as to form another reverse edge in the signal rdgt_ref. In one embodiment, the interval between time points trr1 and tr1 can be equal to a preset time period, such as period T0.

[0087] Corresponding to instruction cmd1, delay circuit 110 can change the signal rdgt_fbck from level vn0 to level vn1 at a time point tn1, thereby forming a major edge hn1 in the signal rdgt_fbck. In one embodiment, time point tn1 can be after time point to1, and separated from time point to1 by a time interval dn1; time point to1 can be earlier than time point tbb1, and separated from time point tbb1 by a time interval g0. In one embodiment, the length of time interval g0 can be equal to a preset number (e.g., 4) multiplied by period T0. In one embodiment, levels vn0 and vn1 can represent logic 0 and logic 1 levels, respectively. At another time point tnn1 after time point tn1, delay circuit 110 can change the signal rdgt_fbck from level vn1 back to level vn0, thereby forming another reverse edge in the signal rdgt_fbck. In one embodiment, the interval between time points tnn1 and tn1 can be equal to a preset time interval, such as period T0.

[0088] In some embodiments, the timing tn1 of the main edge hn1 can be timing tb1 plus one or more clock cycles (e.g., interface clock cycles or internal clock cycles). In some embodiments, the timing tn1 of the main edge hn1 can be located between timing tb1 and tc1. For example, the delay circuit 110 can determine the timing tn1 of the main edge hn1 based on the read delay (or time period RL0), where timing tn1 can be timing tbb1 minus one or more clock cycles (e.g., interface clock cycles or internal clock cycles), or timing tbb1 plus one or more clock cycles (e.g., interface clock cycles or internal clock cycles).

[0089] In the read-gated circuit 100, the detection circuit 130 can detect the time difference dt1 between the main edges hn1 and hr1 (that is, the interval between time points tn1 and tr1), and reflect the corresponding detection result in the signal s_d ( Figure 1 In one embodiment, when the detection circuit 130 detects the time difference dt1 and reflects the corresponding detection result in the signal s_d, the operation of the detection circuit 130 may include: counting the number of periods T0 covered in the time difference dt1 and reflecting the counting result in the signal s_d; Figure 4a The indicated number Nk1 represents the time difference dt1 counted by the detection circuit 130, which covers Nk1 periods T0. The filter circuit 140 (… Figure 1 The signal s_d can be processed (e.g., filtered), and the result of the signal processing is reflected in the signal s_c. In training mode, the memory 20 can continuously drive lines 12d and 12c after responding to instruction cmd1, maintaining signals DQS_t and DQS_c at levels vq0 and vq1 respectively, and maintaining signal DQ at a fixed level.

[0090] like Figure 4b As shown, when instruction cmd1 ends at time point taa1 and memory 20 is still operating in training mode, instruction circuit 40 in physical layer circuit 10 can issue another instruction cmd2 to memory 20 between two time points ta2 and taa2; wherein time point ta2 can be after time point taa1. In response to instruction cmd2 at time points ta2 to taa2, memory 20 can correspondingly change the drive of lines 12c and 12d; the drive of line 12d by memory 20 can sequentially form multiple gating edges in signals DQS_t and DQS_c between two time points tc2 and tcc2, and the drive of line 12c by memory 20 can provide a data string u2 in signal DQ between two time points td2 and tdd2. Figure 4bAs shown, time point tcc2 can be after time point tc2, with an interval of time period Tdqs0; time point tc2 can be after another time point tbb2, with an interval of time period d2; time point tbb2 can be after yet another time point tb2, with an interval of time period RL0; time point tb2 can be the last major edge of clock CK_t before time point taa2. Time point td2 can be after time point tc2, with an interval of time period dd2; time point tdd2 can be after time point td2, with an interval of time period Tdq0.

[0091] like Figure 4b As shown, at the earliest gate edge in the response signal DQS_t (i.e., the gate edge at time point tc2), the effect control circuit 120 can change the signal rdgt_ref from level vr0 to level vr1 at a time point tr2, so as to form a major edge hr2 in the signal rdgt_ref. In one embodiment, time point tr2 can coincide with or be very close to time point tc2. At another time point trr2 after time point tr2, the effect control circuit 120 can change the signal rdgt_ref from level vr1 back to level vr0. In one embodiment, the interval between time points trr2 and tr2 can be equal to the interval between time points trr1 and tr1.

[0092] Corresponding to instruction cmd2, delay circuit 110 can change the signal rdgt_fbck from level vn0 to level vn1 at a time point tn2, so as to form a main edge hn2 in the signal rdgt_fbck. In one embodiment, time point tn2 can be after another time point to2, and separated from time point to2 by a time interval dn2; time point to2 can be earlier than time point tbb2, and separated from time point tbb2 by a time interval g0. At another time point tnn2 after time point tn2, delay circuit 110 can change the signal rdgt_fbck from level vn1 back to level vn0, so as to form a reverse edge in the signal rdgt_fbck. In one embodiment, the interval between time points tnn2 and tn2 can be equal to the interval between time points tnn1 and tn1. Detection circuit 130 can detect the time difference dt2 between the main edge hn2 and hr2 (that is, the time difference between time points tn2 and tr2), and reflect the corresponding detection result in the signal s_d. The filter circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d and reflect the result of the signal processing on the signal s_c. In training mode, the memory 20 can continuously drive lines 12d and 12c after responding to the instruction cmd2, maintaining signals DQS_t and DQS_c at levels vq0 and vq1 respectively, and maintaining signal DQ at a fixed level.

[0093] exist Figure 4a and Figure 4bIn this context, time points to1 and to2 can be considered as origin time points; the interval between time points to2 and tb2 can be equal to the interval between time points to1 and tb1. That is to say, time points to1 and tb1 are similar and can both represent the timing of instruction cmd1; similarly, time points to2 and tb2 can both represent the timing of instruction cmd2. The main edges hr1 and hr2 formed by the control circuit 120 in the signal rdgt_ref can be considered as reference edges; the time points tr1 and tr2 of the main edges hr1 and hr2 can reflect the actual timing of the corresponding strobe edges of memory 20 when responding to instructions cmd1 and cmd2 (e.g., the time point when the earliest strobe edge actually occurs). On the other hand, the main edges hn1 and hn2 formed by the delay circuit 110 in the signal rdgt_fbck can be regarded as internal edges; the delay circuit 110 can estimate the expected timing of the strobe edge corresponding to the instruction cmd1 and cmd2 when the memory 20 responds to the instruction cmd1 and cmd2 (e.g., the time when the earliest strobe edge is expected to occur), and can reflect this expected timing in the time points tn1 and tn2 of the main edges hn1 and hn2. Therefore, for the instruction cmd1 ( Figure 4a The estimated expected timing of the gating edge, the time difference dt1 between time points tn1 and tr1 ( Figure 4a This can reflect the error between the expected timing of the strobe edge and the actual timing of the strobe edge; for the delay circuit 110, the instruction cmd2 ( Figure 4b The estimated expected timing of the gating edge, the time difference dt2 between time points tn2 and tr2 ( Figure 4b This can reflect the error between the expected timing of the gating edge and the actual timing of the gating edge.

[0094] exist Figure 4a In the middle, the delay circuit 110 can control the length of the time period dn1 to control how much the timing point tn1 of the main edge hn1 will be delayed compared to the timing point tb1 of the instruction cmd1; similarly, in Figure 4b In this circuit, the delay circuit 110 can also control the length of the time interval dn2 to control how much the timing point tn2 of the main edge hn2 will be delayed compared to the timing point tb2 of the instruction cmd2. Figure 4b In this process, the delay circuit 110 can control the length of the time period dn2 according to the signal s_c. As mentioned above, in one embodiment, the detection circuit 130 has previously... Figure 4a The count Nk1 is calculated and reflected in the signal s_d, and the filter circuit 140 has already made the signal s_d reflect the signal s_d; therefore, in Figure 4b In the process, when the delay circuit 110 controls the length of time interval dn2 according to the signal s_c, the delay circuit 110 can control the length of time interval dn2 according to the number Nk1, for example, making time interval dn2 equal to time interval dn1 plus Nk1 periods T0. Thus, the time difference dt2 between time point tn2 and time point tr2 ( Figure 4b The time difference dt1 can then be compared. Figure 4a () significantly reduced. Figure 4a The time difference dt1 can be greater than Nk1 periods T0, but when the delay circuit 110 adjusts the time interval dn2 according to the number Nk1, Figure 4b The time difference dt2 can be less than one period T0; that is, the delay circuit 110 can make the multiple of the time difference dt2 (e.g., the number Nk1) less than the time difference dt1. In other words, after only going through instructions cmd1 and cmd2, the expected timing of the strobe edge estimated by the delay circuit 110 for each instruction can quickly approach the actual timing of the strobe edge of the memory 20 when responding to the instruction.

[0095] like Figure 4c As shown, after instruction cmd2 ends, physical layer circuit 20 can continue to issue one or more subsequent instructions to memory 20 in training mode, such as instruction cmd# between two time points ta# and taa#; where time point ta# can be after time point taa2. In response to instruction cmd#, memory 20 can sequentially form multiple gating edges in signals DQS_t and DQS_c between two time points tc# and tcc#, and can provide a data string u# in signal DQ between two time points td# and tdd#. Wherein, time point tcc# can be after time point tc#, and separated from time point tc# by time period Tdqs0; time point tc# can be after another time point tbb#, and separated from time point tbb# by time period d#; time point tbb# can be after yet another time point tb#, and separated from time point tb# by time period RL0; time point tb# can be the last major edge of clock CK_t before time point taa#. Time point td# can be after time point tc#, and separated from time point tc# by a time interval dd#; time point tdd# can be after time point td#, and separated from time point td# by a time interval Tdq0.

[0096] The earliest gating edge of the response signal DQS at time point tc#, the control circuit 120 can form a main edge hr# (the edge from level vr0 to vr1) in the signal rdgt_ref at time point tr# to reflect the actual timing of the gating edge corresponding to the memory 20 when responding to the instruction cmd#. The delay circuit 110 can estimate the expected timing of the gating edge corresponding to the memory 20 when responding to the instruction cmd# based on the signal s_c (e.g., the time point at which the earliest gating edge is expected to occur), and can form a main edge hn# (the edge from level vn0 to level vn1) in the signal rdgt_fbck at time point tn# based on the expected timing. Among them, time point tn# can be after another time point to#, and is separated from time point to# by a time interval dn#; time point to# can be earlier than time point tbb#, and is separated from time point tbb# by a time interval g0. The detection circuit 130 can detect the time difference dt# between the main edge hn# and the main edge hr#, and reflect the corresponding detection result in the signal s_d. The filtering circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d, and reflect the result of the signal processing in the signal s_c. The signal s_c fed back to the delay circuit 110 by the detection circuit 130 and the filtering circuit 140 can be fine-tuned when the delay circuit 110 estimates its expected timing for the gate edge corresponding to other subsequent instructions (not shown) in training mode, so that the expected timing can be closer to the actual timing.

[0097] similar Figure 4a and Figure 4b , Figure 4c The intermediate time point to# can be regarded as a reference time point, and the main edges hr# and hn# can be regarded as a reference edge and an internal edge, respectively. When the delay circuit 110 estimates the expected timing of the corresponding strobe edge based on the signal s_c being the instruction cmd# and forms the main edge hn# based on the expected timing, the delay circuit 110 can determine the length of the time period dn# based on the signal s_c, which also determines the position of the time point tn# on the time axis. At the time point tnn# after the time point tn#, the delay circuit 120 can change the signal rdgt_fbck from level vn1 back to level vn0; at the time point trr# after the time point tr#, the control circuit 120 can change the signal rdgt_ref from level vr1 back to level vr0. The interval between the time points tr# and trr# can be equal to the interval between the time points tr1 and trr1, and the interval between the time points tn# and tnn# can be equal to the interval between the time points tn1 and tnn1. In training mode, memory 20 can continuously drive lines 12d and 12c after responding to the command cmd#, maintaining signals DQS_t and DQS_c at levels vq0 and vq1 respectively, and maintaining signal DQ at a fixed level. However, when memory 20 ends training mode (e.g., ...), Figures 4a to 4c And enter normal mode (e.g.) Figures 2a to 2d and Figures 3a to 3cAfter that, memory 20 will not continuously drive lines 12d and 12c, but will only drive lines 12d and 12c when responding to instructions to give signals DQS and DQ a clear waveform; Figures 2a to 2d and Figures 3a to 3c In the example, when memory 20 does not drive lines 12d and 12c, signals DQS and DQ will not have a clear waveform (as shown by the shading).

[0098] In one embodiment, the signal s_d may include two signals s_dr and s_df ( Figure 1 The signal s_dr can reflect how many cycles T0 are covered in the time difference dt# between the main edges hn# and hr#, while the signal s_df can reflect the leading or lagging relationship between the main edges hn# and hr#. For example, in one embodiment, the signal s_df can use a first logic value and a second logic value to reflect whether the main edge hn# in the signal rdgt_fbck is earlier or later than the main edge hr# in the signal rdgt_ref.

[0099] In one embodiment, the signal s_c provided by the filter circuit 140 may include two signals s_cr and s_cf ( Figure 1 The filter circuit 140 may also include two signal paths (not shown) to perform different signal processing on signals s_dr and s_df in signal s_d, thereby providing signals s_cr and s_cf. For example, when processing the signal s_df, the filter circuit 140 may accumulate the number of occurrences of the first logic value and the second logic value in signal s_df; if the number of occurrences of the first logic value is much greater than the number of occurrences of the second logic value (for example, the difference between the former and the latter is greater than a preset first threshold number), the filter circuit 140 may reflect an extension message (not shown) in signal s_cf; after the delay circuit 110 receives this extension message from signal s_c, when the delay circuit 110 needs to form the next internal main edge hn#' (not shown) in signal rdgt_fbck again for the next instruction cmd#' (not shown), the delay circuit 110 may extend the interval between the instruction cmd#' and the main edge hn#'. On the other hand, if the number of times the second logic value appears is much greater than the number of times the first logic value appears (for example, the difference between the former and the latter is greater than a preset second threshold number), the filter circuit 140 can reflect a shortening message (not shown) in the signal s_cf; after the delay circuit 110 receives this shortening message from the signal s_c, when the delay circuit 110 needs to form the next internal main edge hn#' in the signal rdgt_fbck in response to the instruction cmd#', the delay circuit 110 can shorten the interval between the instruction cmd#' and the main edge hn#'.

[0100] In training mode, when memory 20 responds to instructions cmd1, cmd2 or cmd#, memory 20 will not add preamble and postamble to signals DQS_t and DQS_c; that is, in training mode, the gating edges formed by memory 20 in signals DQS_t and DQS_c are all valid gating edges, which can reflect the timing of each bit in data strings u1, u2 and u# respectively.

[0101] After experiencing multiple instructions in training mode, the delay circuit 110 can lock the leading edge of the signal rdgt_fbck to the corresponding leading edge of the signal rdgt_ref, for example, making the leading edge of the signal rdgt_fbck substantially aligned with the corresponding leading edge of the signal rdgt_ref. Once locked, it means that the expected timing of the gating edge estimated by the read gate circuit 100 for each instruction is very close to the actual timing of the gating edge of each instruction. In one embodiment, after experiencing multiple instructions, if the number of occurrences of the first logic value and the second logic value in the signal s_df are approximately the same, and the signal value of the signal s_dr remains unchanged, the read gate circuit 100 can determine that locking has been achieved.

[0102] After the training mode is locked, the physical layer circuit 100 can enable the memory 20 to enter normal mode for access by memory cells PU[1] to PU[M]. (Continued) Figure 1 and Figures 2a to 2d , Figure 5 An example is provided illustrating the waveform timing of relevant signals when the gate circuit 100 is operating in normal mode. As previously described... Figures 2a to 2d As mentioned, in response to the instruction cmd[i], memory 20 can sequentially form multiple gating edges in signals DQS_t and DQS_c between time points tz[i] and tzz[i], and can provide the data string u[i] in signal DQ between time points td[i] and tdd[i]. Among them, the gating edge between time points tc[i] and tcc[i] is the valid gating edge.

[0103] like Figure 5As shown, corresponding to the instruction cmd[i], the delay circuit 110 in the gate circuit 100 can change the signal rdgt_fbck from level vn0 to level vn1 at one time point tn[i] to form a main edge hn[i], and can change the signal rdgt_fbck from level vn1 back to level vn0 at another time point tnn[i]. Furthermore, corresponding to the instruction cmd[i], the delay circuit 110 can also change the signal rd_gt from level vg0 to level vg1 at one time point tp[i] to form an edge hp[i], and change the signal rd_gt from level vg1 back to level vg0 at another time point tpp[i] to form another edge hpp[i]. Wherein, level vg0 and vg1 can represent logic 0 and logic 1 levels respectively; time point tn[i] can be after time point to[i], and separated from time point to[i] by a time interval dn[i]; time point to[i] can be before time point tbb[i], and separated from time point tbb[i] by a time interval g0. Time point tnn[i] can be after time point tn[i], and the interval between time points tn[i] and tnn[i] can be equal to the interval between time points tn1 and tnn1 ( Figure 4a Time point tp[i] can be before time point tn[i] and separated from time point n[i] by a time interval p0; time point tpp[i] can be after time point tp[i] and separated from time point tp[i] by a time interval TG0. In one embodiment, the time interval p0 can be equal to a preset value multiplied by the period T0, for example, a quarter of a period T0. In one embodiment, the time interval TG0 can be equal to the time interval Tdq0.

[0104] similar Figures 4a to 4c The time points to1, to2, and to# in the data are: Figure 5 The time point to[i] can be considered a reference time point; the interval between time points to[i] and tb[i] can be equal to the interval between time points to1 and tb1, therefore both time points to[i] and tb[i] can represent the timing of the instruction cmd[i]. Similarly... Figures 4a to 4c The main edges hn1, hn2 and hn# in the middle, Figure 5 The main edge hn[i] in the signal can be regarded as an internal edge. Furthermore, the edges hp[i] and hpp[i] formed by the delay circuit 110 in the signal rd_gt can be regarded as a gated leading edge and a gated trailing edge, respectively.

[0105] similar Figures 4a to 4c The training mode, in Figure 5In normal mode, when memory 20 responds to instruction cmd[i] and forms multiple gating edges in signals DQS_t and DQS_c, delay circuit 110 can estimate the expected timing of the valid gating edges among these gating edges based on signal s_c, and can reflect the expected timing in the timing point tn[i] of the main edge hn[i], the timing point tp[i] of the edge hp[i], and the timing point tpp[i] of the edge hpp[i]. For example, timing point tn[i] can reflect the timing point when the earliest expected valid gating edge occurs, timing point tp[i] is earlier than timing point tn[i], and can reflect a timing point between the earliest expected valid gating edge and the previous invalid gating edge; timing point tpp[i] is later than timing point tn[i], and can reflect a timing point between the latest expected valid gating edge and the next invalid gating edge.

[0106] Based on the edges hp[i] and hpp[i] of the signal rd_gt, the effect control circuit 120 can filter out one or more gated edges from the multiple gate edges of the signals DQS_t and DQS_c, and can reflect the filtering result in the signals vDQS_t and vDQS_c. For example, in one embodiment, the effect control circuit 120 can select the gated edge in the signals DQS_t and DQS_c between time points tp[i] and tpp[i] as the gated edge, and form a corresponding gate edge in the signals vDQS_t and vDQS_c in response to the selected gated edge (for example, changing the signals vDQS_t and vDQS_c from one level vp0 to another level vp1, where levels vp0 and vp1 can represent logic 0 and logic 1, respectively). The gated edges selected by the effect control circuit 120 from signals DQS_t and DQS_c can reflect the valid gated edges in signals DQS_t and DQS_c. That is, the effect control circuit 120 can remove invalid gated edges in the preamble and postamble by filtering based on signal rd_gt, and reflect the valid gated edges of signals DQS_t and DQS_c in signals vDQS_t and vDQS_c respectively. In this way, when the data circuit 50 in the physical layer circuit 10 samples the signal DQ according to the timing (gated edges) of signals vDQS_t and vDQS_c, it can correctly retrieve each bit in the data string u[i] and will not incorrectly sample the unclear parts of the waveform in signal DQ (shaded areas).

[0107] Furthermore, when the effect control circuit 120 selects the gate control edge from signals DQS_t and DQS_c based on the signal rd_gt, the effect control circuit 120 can also respond to the earliest gate control edge (that is, the earliest gate edge after edge hp[i], located at time point tc[i]) and change the signal rdgt_ref from level vr0 to level vr1 at a time point tr[i], so as to form a major edge hr[i] in the signal rdgt_ref. Similarly... Figures 4a to 4cThe main edges hr1, hr2 and hr# in the middle, Figure 5 The main edge hr[i] can be regarded as a reference edge, and the time when the main edge hr[i] occurs can reflect the actual time when the earliest effective gating edge actually occurs.

[0108] Similar to the previous Figures 4a to 4c The description, in Figure 5 In normal mode, detection circuit 130 can detect a time difference dt[i] between time points tn[i] and tr[i], and reflect the corresponding detection result in signal s_d; filtering circuit 140 can perform signal processing (e.g., filtering) on ​​signal s_d, and reflect the result of the signal processing in signal s_c. Similar to the previous... Figures 4a to 4c The description, in Figure 5 In normal mode, signal s_d can contain signals s_dr and s_df ( Figure 1 The signal s_c can contain the signals s_cr and s_cf. Figure 1 In one embodiment, after the detection circuit 130 detects the time difference dt[i] between time points tr[i] and tn[i], the detection circuit 130 can update the signal value of signal s_dr from a previous signal value s_dr[i-1] (not shown) to a current signal value s_dr[i] (not shown), and update the signal value of signal s_df from a previous signal value s_df[i-1] (not shown) to a current signal value s_df[i] (not shown), so as to reflect the detection result of time difference dt[i] in the signal values ​​s_dr[i] and s_df[i]. In one embodiment, when the detection circuit 130 detects the time difference dt[i], the detection circuit 130 can count how many periods T0 the time difference dt[i] covers, and compare whether the main edge hn[i] is earlier or later than the main edge hr[i]. When the detection circuit 130 reflects the detection result in the signal s_d, the detection circuit 130 can reflect how many periods T0 the time difference dt[i] covers in the signal value s_dr[i], and can reflect whether the main edge hn[i] is earlier or later than the main edge hr[i] in the signal value s_df[i]. In one embodiment, when the filter circuit 140 performs signal processing on the signal s_d after the signal value is updated and reflects the result of the signal processing on the signal s_c, the filter circuit 140 can update the signal value of the signal s_cr from a previous signal value s_cr[i-1] to a current signal value s_cr[i], and update the signal value of the signal s_cf from a previous signal value s_cr[i-1] to a current signal value s_cr[i], so that the result of the signal processing on the updated signal s_d is reflected in the signal values ​​s_cr[i] and s_cf[i].

[0109] In one embodiment, the operation of the detection circuit 130 and the filtering circuit 140 in training mode can be similar to their operation in normal mode. For example, in normal mode, the detection circuit 130 can reflect whether the main edge hn[i] is earlier or later than the main edge hr[i] in the signal value s_df[i] using a first logic value and a second logic value. If the signal value s_df[i] is the first logic value, the signal processing of the signal s_df by the filtering circuit 140 can increase the number of occurrences of the first logic value reflected by the signal value s_cf[i] by one compared to the number of occurrences of the first logic value reflected by the signal value s_cf[i-1]. If the signal value s_df[i] is the second logic value, the signal processing of the signal s_df by the filtering circuit 140 can increase the number of occurrences of the second logic value reflected by the signal value s_cf[i] by one compared to the number of occurrences of the second logic value reflected by the signal value s_cf[i-1].

[0110] The delay circuit 110 can control the length of the time interval dn[i] based on the signal s_c, thereby controlling the position of time point tn[i] (along with time points tp[i] and tpp[i]) on the time axis. For example... Figure 5 As shown, in one embodiment, the time period dn[i] may include two time periods Tn1 and Tn[i]. When the delay circuit 110 forms the main edge hn[i] in the signal rdgt_fbck, the delay circuit 110 may start from time point to[i] and wait for time period Tn1 based on the previous signal value s_cr[i-1] of the signal s_cr, and wait for time period Tn[i] based on the previous signal value s_cf[i-1] of the signal s_cf, and form the main edge hn[i] at time point tn[i] after the waiting ends. In one embodiment, the time period Tn1 may be equal to one or more periods T0, while the time period Tn[i] may be less than one period T0. In one embodiment, the time period Tn1 may be equal to Figure 4a Subtract the time difference dt1 in the middle Figure 4b The time difference dt2. In one embodiment, the signal value s_cr[i-1] of the signal s_cr can reflect the number Nk1 ( Figure 4a The delay circuit 110 may also include a counter 1101. Figure 1 When the delay circuit 110 waits for a period Tn1, the counter 1101 can count Nk1 cycles T0. (As previously stated...) Figure 4a As described, when the detection circuit 130 detects the time difference dt1, the detection circuit 130 can count how many cycles are in the time difference dt1 and reflect the counted number Nk1 in the signal s_cr. In other words, the signal s_cr in the normal mode can be the same as the signal s_cr obtained in the training mode.

[0111] In one embodiment, the delay circuit 110 may further include a controlled delay line 1102, controlled by the signal s_cf; when the delay circuit 110 waits for a period of time Tn[i], it may be through the controlled delay line 1102 waiting for the period of time Tn[i], and the length of the period of time Tn[i] may be controlled by the signal value s_cf[i-1]. In the read gate circuit 100, the signals s_cr and s_cf can be regarded as a coarse adjustment signal and a fine adjustment signal, respectively, the periods Tn1 and Tn[i] can be regarded as a coarse adjustment period and a fine adjustment period, respectively, and the number Nk1 can be regarded as a coarse adjustment number.

[0112] As previously described, when memory 20 is in Figure 4a , Figure 4b or Figure 4c In training mode, when responding to instructions cmd1, cmd2, or cmd#, memory 20 can generate multiple gating edges in the signal DQS between time points tc1 and tcc1, between time points tc2 and tcc2, or between time points tc# and tcc#, and these gating edges are all valid gating edges. On the other hand, when memory 20 is in Figure 5 In normal mode, when responding to the instruction cmd[i], the memory 20 can form multiple gating edges in the signal DQS between time points tz[i] and tzz[i]. However, among these multiple gating edges, only the gating edge between time points tc[i] and tcc[i] is a valid gating edge, and the other gating edges are invalid gating edges. That is, the gating edge between time points tz[i] and tc[i] and the gating edge between time points tcc[i] and tzz[i] are both invalid gating edges. Although memory 20 will form invalid strobe edges in the preamble and / or postamble of signal DQS in normal mode, the interval between time points tb# and tc# (and the interval between time points tb1 and tc1 and the interval between time points tb2 and tc2) in training mode can reflect the interval between time points tb[i] and tc[i] in normal mode; where time points tb1, tb2, tb# and tb[i] can represent the timing of instructions cmd1, cmd2, cmd# and cmd[i] respectively, and time points tc1, tc2, tc# and tc[i] can represent the timing of valid strobe edges respectively. That is to say, the interval between each instruction and its corresponding strobe edge in training mode (e.g., the interval between time points tb1 and tc1, tb2 and tc2 or tb# and tc#) can reflect the interval between each instruction and its corresponding valid strobe edge in normal mode (e.g., the interval between time points tb[i] and tc[i]).

[0113] When the delay circuit 110 is in training mode (such as...) Figures 4a to 4c In training mode, the delay circuit 110 can correctly estimate the interval between each instruction and its corresponding strobe edge. This means that the expected timing of each instruction's strobe edge can be locked to the actual timing in normal mode. Figure 5 When estimating the expected timing of the effective gate edges for each instruction, the delay circuit 110 can estimate the expected timing of the effective gate edges for each instruction based on the locking result previously achieved in the training mode (e.g., the signal s_cr after locking), and reflect this expected timing in the time period dn[i], the main edge hn[i], and the signal rd_gt. Based on the timing of the signal rd_gt, the gate control circuit 120 can filter the gate control gate edges from the signal DQS to reflect the effective gate edges between time points tc[i] and tcc[i], and reflect the filtering result in the signal vDQS and the main edge hr[i]. The detection circuit 130 can detect the time difference between the main edge hn[i] and hr[i]. Through the feedback from the detection circuit 130, the filtering circuit 140, and the delay circuit 110, the delay circuit 110 can be fine-tuned when estimating the expected timing of the effective gate edges for subsequent instructions, so that the expected timing of the effective gate edges can be continuously locked to the actual timing.

[0114] When memory 20 responds to instruction cmd[i] in normal mode, the actual timing of the effective gating edge will dynamically drift because the time interval d[i] between time point tbb[i] and time point tc[i] may change dynamically due to factors such as bias voltage and / or temperature drift. However, when memory 20 responds to multiple instructions sequentially in normal mode, the delay circuit 110 can continuously fine-tune its expected timing for the effective gating edge estimation through feedback from the detection circuit 130 and the filter circuit 140. Even if the actual timing of the effective gating edge drifts, the expected timing estimated by the delay circuit 110 for the effective gating edge can still be locked to the actual timing of the effective gating edge.

[0115] continue Figure 1 and Figure 3b and Figure 3c , Figure 6a and Figure 6b An example is provided illustrating a timing embodiment for reading the waveforms of relevant signals when the gate circuit 100 is operating in normal mode. As previously described... Figure 3b As described in Figure 6a In the context of memory 20 responding to instructions cmd[i] and cmd[i+1], since the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is less than the time interval T_mrg[i], memory 20 can combine the postcode corresponding to instruction cmd[i] with the precode corresponding to instruction cmd[i+1] in signals DQS_t and DQS_c, so that signals DQS_t and DQS_c can form multiple gating edges with a clear waveform between time points tz[i] and tzz[i+1]. On the other hand, since the time interval Tcc[i] is greater than the time interval T_min, the waveform of signal DQ between time points tdd[i] and td[i+1] will be ambiguous.

[0116] As previously Figure 5 As described, in Figure 6a In the corresponding instruction cmd[i], the delay circuit 110 can form the main edge hn[i] in the signal rdgt_fbck at time point tn[i], and can form edges hp[i] and hpp[i] in the signal rd_gt at time points tp[i] and tpp[i], respectively; wherein, the delay circuit 110 can determine the time points tp[i], tn[i], and tpp[i] according to the signal s_c. According to the signal rd_gt, the effect control circuit 120 can filter out the valid selection edges from the multiple selection edges of the signals DQS_t and DQS_c, and remove the invalid selection edges. Specifically, the effect control circuit 120 can respond to the gating edges of signals DQS_t and DQS_c between time points tp[i] and tpp[i] to form corresponding gating edges in signals vDQS_t and vDQS_c, and the gating edges in signals vDQS_t and vDQS_c represent the valid gating edges in signals DQS_t and DQS_c. Based on the gating edges in signals vDQS_t and vDQS_c, the data circuit 50 can sample the signal DQ to retrieve each bit of the data string u[i]. Furthermore, based on the earliest gating edge after time point tp[i] in the (response) signals DQS_t and DQS_c (that is, the earliest valid gating edge formed by memory 20 in signals DQS_t and DQS_c when responding to cmd[i]), the control circuit 120 can also form the main edge hr[i] in the signal rdgt_ref at time point tr[i]. The detection circuit 130 can detect the time difference dt[i] between the main edge hn[i] and hr[i], and reflect the corresponding detection result in the signal s_d; the filtering circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d, and reflect the result of the signal processing in the signal s_c.

[0117] Similarly, corresponding to the instruction cmd[i+1], the delay circuit 110 can change the signal rdgt_fbck from level vn0 to level vn1 at a time point tn[i+1], so as to form a major edge hn[i+1] in the signal rdgt_fbck; the delay circuit 110 can also change the signal rdgt_fbck from level vn1 back to level vn0 at another time point tnn[i+1]. Corresponding to the instruction cmd[i+1], the delay circuit 110 can also change the signal rd_gt from level vg0 to level vg1 at another time point tp[i+1], and can change the signal rd_gt from level vg1 back to level vg0 at yet another time point tpp[i+1], so as to form two edges hp[i+1] and hpp[i+1] in the signal rd_gt respectively. Specifically, time point tn[i+1] can be after another time point to[i+1], and separated from time point to[i+1] by a time interval dn[i+1]; time point to[i+1] can be before time point tbb[i+1], and separated from time point tbb[i+1] by a time interval g0; time point tp[i+1] can be before time point tn[i+1], and separated from time point tn[i+1] by a time interval p0; time point tpp[i+1] can be after time point tp[i+1], and separated from time point tp[i+1] by a time interval TG0. For the instruction cmd[i+1], time point to[i+1] can be regarded as a reference time point, which can reflect the timing of the instruction cmd[i+1]; the interval dn[i+1] is controlled by the signal s_c. In one embodiment, the interval dn[i+1] may include two time periods Tn1 and Tn[i+1], which are controlled by the signal values ​​s_cr[i] and s_cf[i] of the signal s_c, respectively.

[0118] Based on the signal rd_gt, when the memory 20 responds to the instruction cmd[i+1] and forms multiple gating edges in the signals DQS_t and DQS_c, the effect control circuit 120 can filter out the valid gating edges and remove the invalid gating edges from these multiple gating edges in the signals DQS_t and DQS_c. For example, the effect control circuit 120 can respond to the gating edge in the signals DQS_t and DQS_c located between time points tp[i+1] and tpp[i+1] and form corresponding gating edges in the signals vDQS_t and vDQS_c. Based on the gating edges in the signals vDQS_t and vDQS_c, the data circuit 50 can sample the signal DQ to retrieve each bit of the data string u[i+1]. Furthermore, based on the earliest gate edge after time point tp[i+1] in the (response) signals DQS_t and DQS_c, the control circuit 120 can also form a major edge hr[i+1] (the edge from level vr0 to vr1) in the signal rdgt_ref at a time point tr[i+1]. The detection circuit 130 can detect the time difference dt[i+1] between the major edge hn[i+1] and hr[i+1], and reflect the corresponding detection result in the signal s_d; the filtering circuit 140 can perform signal processing (e.g., filtering) on ​​the signal s_d, and reflect the result of the signal processing in the signal s_c.

[0119] like Figure 6aAs shown, the interval between time points to[i] and tb[i] can be equal to the interval between time points to[i+1] and tb[i+1], and the interval Tcc[i] between time points tb[i] and tb[i+1] is the interval between instructions cmd[i] and cmd[i+1]. Time points tc[i] and tc[i+1] can represent the actual timing of the effective strobe edges of memory 20 when responding to instructions cmd[i] and cmd[i+1], respectively, and the interval between time points tc[i] and tc[i+1] can be equal to the time interval (Tcc[i] + d[i+1] - d[i]). On the other hand, time points tn[i] and tn[i+1], time points tp[i] and tp[i+1], and time points tpp[i] and tpp[i+1] can represent the expected timing of the effective strobe edges corresponding to instructions cmd[i] and cmd[i+1]. The interval between time points tn[i] and tn[i+1], the interval between time points tp[i] and tp[i+1], and the interval between time points tpp[i] and tpp[i+1] can be equal to the time period (Tcc[i]+dn[i+1]-dn[i]). As described above, as the instruction cmd[i+1] gets closer to the instruction cmd[i] (the shorter the time interval Tcc[i]), the timing tc[i+1] related to memory 20 will get closer to the timing tc[i], and the timing tp[i+1], tn[i+1], and tpp[i+1] related to delay circuit 110 will also get closer to the timing tp[i], tn[i], and tpp[i], respectively. In other words, the expected timing of the effective gating edge of delay circuit 110 can follow the actual timing of the effective gating edge. Even if the time interval tcc[i] between adjacent instructions cmd[i] and cmd[i+1] changes, the control circuit 120 can still correctly filter the effective gating edge from signals DQS_t and DQS_c based on the signal rd_gt of delay circuit 110.

[0120] exist Figure 6a In the example, the time interval between instructions cmd[i] and cmd[i+1] is less than T_mrg[i]. Therefore, when the memory 20 responds to instructions cmd[i] and cmd[i+1], it combines the postcode corresponding to instruction cmd[i] and the precode corresponding to instruction cmd[i+1] in signals DQS_t and DQS_c between time points tcc[i] and tc[i+1]. This ensures that signals DQS_t and DQS_c have a clear waveform between time points tcc[i] and tc[i+1], and there is a possibility of invalid gating edges. However, just like... Figure 6a As shown, even if memory 20 will Figure 6aIn the example, combining the postcode corresponding to instruction cmd[i] and the precode corresponding to instruction cmd[i+1], the delay circuit 110 will still generate edges hpp[i] and hp[i+1] in the signal rd_gt; therefore, when the effect control circuit 120 operates according to the signal rd_gt, the effect control circuit 120 can eliminate invalid gating edges that may occur between time points tcc[i] and tc[i+1]. Figure 6a As shown, in one embodiment, the effect control circuit 120 can maintain signals vDQS_t and vDQS_c at levels vp0 and vp1 respectively between time points tpp[i] and tp[i+1] along hpp[i] and hp[i+1], so that signals vDQS_t and vDQS_c will not have a gating edge between time points tpp[i] and tp[i+1].

[0121] exist Figure 6b In the example, the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is equal to the time interval T_min. Therefore, when the memory 20 responds to instructions cmd[i] and cmd[i+1], it will seamlessly concatenate the data strings u[i] and u[i+1] in the signal DQ. It will also remove the postcodes corresponding to instructions cmd[i] and cmd[i+1] from signals DQS_t and DQS_c, so that there are no invalid gating edges between time points tc[i] and tcc[i+1] in signals DQS_t and DQS_c. However, as Figure 6b As shown, if the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is equal to T_min, the time point tpp[i] of the corresponding instruction cmd[i] and the time point tp[i+1] of the corresponding instruction cmd[i+1] can coincide (or, the time point tpp[i] can be after the time point tp[i+1]), so the delay circuit 110 can cancel the edge hpp[i] of the time point tpp[i] and the edge hp[i+1] of the time point tp[i+1] in the signal rd_gt, so that the signal rd_gt can be maintained at level vg1 between the time points tp[i] and tpp[i+1]. When the effect control circuit 120 operates according to the signal rd_gt, it filters out the gating edges between time points tp[i] and tpp[i+1] in signals DQS_t and DQS_c as valid gating edges, and reflects these filtered gating edges in signals vDQS_t and vDQS_c. Thus, when the data circuit 50 samples the signal DQ based on the gating edges in signals vDQS_t and vDQS_c, it can correctly retrieve the seamlessly concatenated data strings u[i] and u[i+1].

[0122] like Figure 3aAs shown, if the time interval Tcc[i] between instructions cmd[i] and cmd[i+1] is greater than the time interval T_mrg[i], the memory 20 will not combine the postcode of instruction cmd[i] and the precode of instruction cmd[i+1] when responding to instructions cmd[i] and cmd[i+1]. That is, the memory 20 will form complete precode and postcode in signals DQS_t and DQS_c when responding to instruction cmd[i], and will also form complete precode and postcode in signals DQS_t and DQS_c when responding to instruction cmd[i+1]. For Figure 3a For example, the operation of delay circuit 110 and effect control circuit 120 can be achieved by... Figure 5 and Figure 6a According to the relevant description, corresponding to cmd[i] and cmd[i+1], the delay circuit 110 will sequentially form along hp[i], hpp[i], hp[i+1] and hpp[i+1] in the signal rd_gt at times tp[i], tpp[i], tp[i+1] and tpp[i+1], where time point tpp[i] can be before time point tp[i+1], and the interval between time points tpp[i] and tpp[i+1] will reflect (e.g., be positively correlated with) the interval between time points tcc[i] and tc[i+1]. Therefore, when the effect control circuit 120 operates according to the signal rd_gt, the effect control circuit 120 can remove the postcode corresponding to the instruction cmd[i] (time points tcc[i] to tzz[i]) according to the edges hpp[i] and hp[i+1] of the signal rd_gt. Figure 3a The preamble corresponding to the instruction cmd[i+1] (from time point tz[i+1] to time point tc[i+1], Figure 3a For example, the effect control circuit 120 can maintain signals vDQS_t and vDQS_c at levels vp0 and vp1 respectively between time points tpp[i] and tp[i+1] along hpp[i] and hp[i+1], so that signals vDQS_t and vDQS_c will not have a gating edge between time points tpp[i] and tp[i+1].

[0123] In summary, the physical layer circuitry (e.g., 10) of this invention can access a memory (e.g., 20) and may include a read gating circuit (e.g., 100); this read gating circuitry can improve read gating operation when reading the memory. In one embodiment, the read gating circuitry of this invention may include a delay circuit (e.g., 110), an effect control circuit (e.g., 120), and a detection circuit (e.g., 130). When the memory is in a training mode (e.g., Figure 4aWhen a delay circuit responds to a first instruction (e.g., cmd1) and forms multiple first gating edges (e.g., the gating edge between time points tc1 and tcc1) in a gating signal (e.g., DQS_t and DQS_c), the delay circuit can reflect the expected timing between these first gating edges in a first internal time period (e.g., dn1), and can reflect this first internal time period in an internal signal (e.g., rdgt_fbck), for example, forming a first internal edge (e.g., hn1) in the internal signal based on the first internal time period; the control circuit can then reflect this... The actual timing of these first strobe edges is reflected in a reference signal (e.g., rdgt_ref), for example, a first reference edge (e.g., hr1) is formed in the reference signal based on (in response to) the earliest of these first strobe edges; the detection circuit can detect the timing difference between the internal signal and the reference signal, and make the detected timing difference reflected in a control signal (e.g., s_c), for example, detecting a first time difference (e.g., dt1) between the first internal edge and the first reference edge, and making the first time difference reflected in the control signal.

[0124] When the memory is in this training mode (e.g.) Figure 4b In response to a second instruction (e.g., cmd2), the delay circuit forms multiple second gating edges in the gating signal (e.g., gating edges between time points tc2 and tcc2). The delay circuit can determine a second internal time period (e.g., dn2) based on the control signal to reflect the expected timing of these second gating edges, and can reflect the second internal time period in the internal signal, for example, forming a second internal edge (e.g., hn2) in the internal signal based on the second internal time period. The control circuit can reflect the actual timing of these second gating edges in the reference signal, for example, forming a second reference edge (e.g., hr2) in the reference signal based on (responding to) the earliest of these second gating edges. The detection circuit can detect the timing difference between the internal signal and the reference signal, for example, detecting a second time difference (e.g., dt2) between the second internal edge and the second reference edge. In one embodiment, when detecting the first time difference, the detection circuit can count how many interface clock cycles (e.g., T0) are covered in the first time difference, and make a coarse adjustment number (e.g., Nk1) reflected in the control signal; when the delay circuit determines the second internal time period according to the control signal, the delay circuit can determine the length of the second internal time period according to the first internal time period and the coarse adjustment number, so that the second time difference can be much smaller than the first time difference, for example, making the multiple of the second time difference smaller than the first time difference. In other words, the present invention can quickly (e.g., through two instructions cmd1 and cmd2) lock the expected timing of the strobe edge to the actual timing of the strobe edge in training mode.

[0125] When the memory is in a normal mode (e.g.) Figure 5 When a delay circuit responds to a third instruction (e.g., cmd[i]) and forms multiple third gating edges (e.g., the gating edge between time points tz[i] and tzz[i]) in the gating signal (e.g., DQS_t and DQS_c) and provides a data string (e.g., u[i]) in a data signal (e.g., DQ), the delay circuit can determine a third internal time period (e.g., dn[i]) according to the control signal to reflect the expected timing of the effective gating edges among these third gating edges, and can reflect the third internal time period in the internal signal and a gating signal (e.g., rd_gt). For example, it can form a third internal edge (e.g., hn[i]) in the internal signal according to the third internal time period, and form a gating leading edge (e.g., hp[i]) and a gating trailing edge (e.g., hpp[i]) in the gating signal according to the third internal time period; the delay circuit can then... The timing of the gating signal is reflected in a gating strobe signal (e.g., vDQS_t and vDQS_c) and the reference signal. For example, the third strobe edge located between the gating leading edge and the gating trailing edge is reflected in the gating strobe signal, and a third reference edge (e.g., hr[i]) is formed in the reference signal according to the earliest third strobe edge located after the gating leading edge. A data circuit (e.g., 50) in the physical layer circuit can sample the data signal according to the gating strobe signal to retrieve each bit of the data string. The detection circuit can detect the timing difference between the internal signal and the reference signal and make the detected timing difference reflect the control signal. For example, a third time difference (e.g., dt[i]) between the third internal edge and the third reference edge is detected and the third time difference is reflected in the control signal. In one embodiment, the third internal time period may include a coarse adjustment period (e.g., Tn1) and a fine adjustment period (e.g., Tn[i]). The coarse adjustment period may be equal to the interface clock cycle multiplied by the number of coarse adjustments, and the fine adjustment period may be less than the interface clock cycle. In other words, based on the locking results in training mode, the present invention can continuously lock the timing of the valid strobe edge in normal mode in order to correctly retrieve each bit in the data string from the data signal.

[0126] When the memory is in normal mode (e.g.) Figure 6a and Figure 6bWhen a delay circuit responds to a third instruction (e.g., cmd[i]) and a fourth instruction (e.g., cmd[i+1]) in succession, and forms multiple response gating edges (e.g., gating edges between time points tz[i] and tzz[i+1]) in the gating signal (e.g., DQS_t and DQS_c) and provides two data strings (e.g., u[i] and u[i+1]) in the data signal, the delay circuit can determine a third internal time period (e.g., dn[i]) and a fourth internal time period (e.g., dn[i+1]) according to the control signal to reflect the expected timing of the effective gating edges among these response gating edges, and can reflect the third internal time period and the fourth internal time period in the internal signal, for example, forming a third internal edge (e.g., hn[i]) and a fourth internal edge (e.g., hn[i+1]) in the internal signal according to the third internal time period and the fourth internal time period. The delay circuit can also reflect the third and fourth internal time periods in the gating signal. For example, if the interval between the third and fourth instructions is greater than a minimum interval (e.g., T_min), Figure 6a The delay circuit can form a third gating leading edge (e.g., hp[i]) and a third gating trailing edge (e.g., hpp[i]) in the gating signal based on the third internal time period. Figure 6a ), and can form a fourth gating front edge (e.g., hp[i+1]) in the gating signal based on the fourth internal time period. Figure 6a The third instruction and the fourth instruction have a fourth gated trailing edge (e.g., hpp[i+1]); if the interval between the third instruction and the fourth instruction is not greater than (e.g., equal to) the minimum interval period, the delay circuit can form an integrated gated leading edge (e.g., hp[i]) in the gated signal based on the third internal period. Figure 6b ) and an integrated gated trailing edge (e.g., hpp[i+1], Figure 6bThe control circuit can reflect the timing of the gate signal in the gate strobe signal and the reference signal. For example, it can reflect the response strobe edges located between the leading edge and the trailing edge of the integrated gate in the gate strobe signal, and form a third reference edge (e.g., hr[i]) and a fourth reference edge (e.g., hr[i+1]) in the reference signal according to the earliest one of the response strobe edges located after the leading edge of the integrated gate. The data circuit (e.g., 50) can sample the data signal according to the gate strobe signal to retrieve each bit of the two data strings. The detection circuit can detect the timing difference between the internal signal and the reference signal, and make the detected timing difference reflect the control signal. For example, it can detect a third time difference (e.g., dt[i]) between the third internal edge and the third reference edge, detect a fourth time difference (e.g., dt[i+1]) between the fourth internal edge and the fourth reference edge, and make the third time difference and the fourth time difference reflect the control signal. In other words, regardless of whether the interval between two adjacent instructions is equal to the minimum interval period, the present invention can adaptably and correctly reflect the effective gating edge in the gating signal.

[0127] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A physical layer circuit with improved read gating, coupled to a memory, wherein: The physical layer circuit includes a delay circuit, an effect control circuit, and a detection circuit. The control circuit is coupled to the delay circuit and a gating signal; The detection circuit is coupled to the delay circuit and the effect control circuit; In a first mode, the physical layer circuit transmits a first instruction to the memory, causing the memory to respond to the first instruction by sequentially forming a plurality of first strobe edges in the strobe signal; In response to the earliest of the plurality of first strobe edges, the control circuit forms a first reference edge in a reference signal; In response to the first instruction, the delay circuit forms a first internal edge in an internal signal; The detection circuit detects a first time difference between the first internal edge and the first reference edge, and reflects the corresponding detection result in a control signal. In this first mode, the physical layer circuit also transmits a second instruction to the memory, causing the memory to respond to the second instruction by sequentially forming a plurality of second strobe edges in the strobe signal; In response to the earliest of the plurality of second strobe edges, the control circuit also forms a second reference edge in the reference signal; and In response to the second instruction, the delay circuit also forms a second internal edge in the internal signal according to the control signal, so that a second time difference between the second internal edge and the second reference edge is less than the first time difference.

2. The physical layer circuit as described in claim 1, wherein, The delay circuit makes the second time difference smaller than the first time difference by making the multiple of the second time difference smaller than the first time difference.

3. The physical layer circuit as described in claim 1, wherein: The first time difference is greater than a multiple of one interface clock cycle; and The delay circuit makes the second time difference smaller than the first time difference by making the second time difference smaller than the interface clock period.

4. The physical layer circuit as described in claim 1, wherein: In a second mode, the physical layer circuit also transmits a third instruction to the memory, causing the memory to respond to the third instruction by sequentially forming a plurality of third strobe edges in the strobe signal, and causing the memory to respond to the third instruction by providing a third data string in a data signal; In response to the third instruction, the delay circuit also forms a gating leading edge and a gating trailing edge in a gating signal based on the control signal; Based on the gating signal, the control circuit further filters out those located between the leading edge and the trailing edge of the gating from the plurality of third gating edges, and reflects the filtering result in a gating gating signal; The physical layer circuit also includes a data circuit; The data circuit is coupled to the effect control circuit; and The data circuit samples the data signal based on the gating signal to retrieve the third data string.

5. The physical layer circuit as described in claim 4, wherein: In response to the third instruction, the delay circuit also forms a third internal edge in the internal signal according to the control signal; Based on the screening result, the effect control circuit also forms a third reference edge in the reference signal; The detection circuit also detects a third time difference between the third internal edge and the third reference edge, and reflects the corresponding detection result in the control signal. The gating front edge precedes the third inner edge; and The gating trailing edge follows the third inner edge.

6. The physical layer circuit as described in claim 1, wherein: In a second mode, the physical layer circuit also transmits a third instruction to the memory, causing the memory to respond to the third instruction by sequentially forming a plurality of third strobe edges in the strobe signal; In response to the third instruction, the delay circuit also forms a third internal edge in the internal signal according to the control signal, and forms a gating leading edge in a gating signal according to the control signal. In response to the earliest of the plurality of third gating edges occurring after the gate leading edge, the control circuit also forms a third reference edge in the reference signal; and... The detection circuit also detects a third time difference between the third internal edge and the third reference edge, and reflects the corresponding detection result in the control signal.

7. The physical layer circuit as described in claim 6, wherein: The physical layer circuit also includes a filter circuit coupled between the detection circuit and the delay circuit; and When the detection circuit detects the third time difference and reflects the corresponding detection result in the control signal, the detection circuit reflects the corresponding detection result in a detection signal, and the filtering circuit filters the detection signal and reflects the result of the filtering process in the control signal.

8. The physical layer circuit as described in claim 6, wherein: The delay circuit is used to form the third inner edge at a third inner edge point; The third internal edge time point is after a third reference time point, and the interval between the third reference time point and the third internal edge time point includes a coarse adjustment period and a fine adjustment period; The coarse adjustment period is a multiple of one interface clock cycle; and The fine-tuning period is shorter than the interface clock cycle.

9. The physical layer circuit as described in claim 8, wherein: The coarse adjustment period is essentially equal to the first time difference minus the second time difference.

10. The physical layer circuit as described in claim 6, wherein: The control signal includes a coarse adjustment signal and a fine adjustment signal; The delay circuit is used to wait for a coarse adjustment period and a fine adjustment period according to the coarse adjustment signal and the fine adjustment signal respectively, and to form the third inner edge at a third inner edge point after the waiting ends.

11. The physical layer circuit of claim 10, wherein: The delay circuit includes a counter; This coarse adjustment signal reflects the number of coarse adjustments; as well as The delay circuit waits for the coarse adjustment period by counting N interface clock cycles using the counter, where N is the number of coarse adjustments.

12. The physical layer circuit as described in claim 11, wherein: The coarse adjustment number is related to the first time difference.

13. The physical layer circuit as described in claim 10, wherein: The delay circuit includes a controlled delay line; When the delay circuit waits for the fine-tuning period to pass through the controlled delay line, and... The length of this fine-tuning period is controlled by the fine-tuning signal.

14. The physical layer circuit as claimed in claim 6, wherein: When the detection circuit detects the third time difference between the third internal edge and the third reference edge, the operation of the detection circuit includes: comparing whether the third internal edge is earlier or later than the third reference edge.

15. The physical layer circuit as claimed in claim 1, wherein: When the detection circuit detects the first time difference between the first internal edge and the first reference edge and reflects the corresponding detection result in the control signal, the operation of the detection circuit includes: counting the number of interface clock cycles covered by the first time difference and reflecting the counting result in the control signal.

16. The physical layer circuit as claimed in claim 1, wherein: In a second mode, the physical layer circuit also sequentially transmits a third instruction and a fourth instruction to the memory, causing the memory to sequentially form multiple response strobe edges in the strobe signal in response to the third instruction and the fourth instruction, and causing the memory to provide a third data string and a fourth data string in a data signal in response to the third instruction and the fourth instruction, respectively. If the interval between the third instruction and the fourth instruction is greater than a minimum interval period, the delay circuit also forms a third gating leading edge, a third gating trailing edge, a fourth gating leading edge and a fourth gating trailing edge in a gating signal according to the control signal, and the control circuit also selects one or more third gating gating edges and one or more fourth gating gating edges from the plurality of response gating edges according to the gating signal; Each of the third gating edges is one of the plurality of response gating edges, and is located between the leading edge and the trailing edge of the third gating; Each of the fourth gating edges is one of the plurality of response gating edges, and is located between the leading edge and the trailing edge of the fourth gating; The physical layer circuitry also includes data circuitry coupled to the control circuitry; and The data circuit samples the data signal based on one or more third gated edges to retrieve the third data string, and samples the data signal based on one or more fourth gated edges to retrieve the fourth data string.

17. The physical layer circuit as claimed in claim 1, wherein: In a second mode, the physical layer circuit also sequentially transmits a third instruction and a fourth instruction to the memory, causing the memory to sequentially form multiple response strobe edges in the strobe signal in response to the third instruction and the fourth instruction, and causing the memory to provide a third data string and a fourth data string in a data signal in response to the third instruction and the fourth instruction, respectively. If the interval between the third instruction and the fourth instruction is not greater than a minimum interval period, the delay circuit also forms an integrated gating leading edge and an integrated gating trailing edge in a gating signal according to the control signal, and the control circuit also selects one or more gating gating edges from the plurality of response gating edges according to the gating signal. Each of these gating edges is one of the plurality of response gating edges, and is located between the leading edge and the trailing edge of the integrated gating; The physical layer circuitry also includes data circuitry coupled to the control circuitry; and The data circuit samples the data signal based on one or more gated edges to retrieve the third data string and the fourth data string.

18. An improved physical layer circuit for read gating, coupled to a memory, wherein: The physical layer circuit includes a delay circuit, an effect control circuit, and a detection circuit. The control circuit is coupled to the delay circuit and a gating signal; The detection circuit is coupled to the delay circuit and the effect control circuit; The physical layer circuit transmits an instruction to the memory, causing the memory to respond to the instruction by sequentially forming multiple strobe edges in the strobe signal; In response to the instruction, the delay circuit forms an internal edge in an internal signal; In a first mode, the control circuit responds to the earliest of the plurality of strobe edges to form a reference edge in a reference signal; In a second mode, the delay circuit also forms a gating leading edge in a gating signal, and the control circuit forms a reference edge in the reference signal in response to the nearest one of the plurality of gating edges after the gating leading edge, wherein the gating leading edge is earlier than the inner edge; as well as The detection circuit detects a time difference between the internal edge and the reference edge and reflects the corresponding detection result in a detection signal.

19. The physical layer circuit as described in claim 18, wherein: The physical layer circuit also includes a filter circuit coupled between the detection circuit and the delay circuit; The filtering circuit filters the detection signal to provide a control signal; as well as The delay circuit is used to determine the timing of the formation of the internal edge in the internal signal based on the control signal.

20. The physical layer circuit of claim 18, wherein: The delay circuit is used to wait for a coarse adjustment period and a fine adjustment period to pass, and to form the inner edge at an inner edge point after the waiting period ends; The coarse adjustment period is an integer multiple of one interface clock cycle; as well as The fine-tuning period should not exceed the clock cycle of the interface.

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