Storage arrays, memories, and electronic devices

Abstract

The application provides a storage array, a memory and an electronic device, relates to the technical field of semiconductors, and aims to optimize how to select a control signal line of the storage array. In the storage array, a plurality of storage layers are arranged in a stack along a first direction, a plurality of word lines are arranged in an array in a plane perpendicular to the first direction, the plurality of word lines are connected with storage units in the plurality of storage layers stacked along the first direction, each word line is simultaneously connected with a first transistor and a second transistor, and whether the word line is selected is realized by controlling the conduction and the shutdown of the first transistor and the second transistor. The storage array can reduce the number of control lines used for connecting the storage array and a control circuit for controlling reading and writing of the storage units in the storage array.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a memory array, memory, and electronic device. Background Technology

[0002] As semiconductor process nodes continue to shrink to below 10nm, the traditional planar dynamic random access memory (DRAM) architecture faces physical limits. Although the planar size of DRAM can be further reduced through cell structure optimization, its process complexity increases exponentially, with significant bottlenecks in areas such as photolithography alignment and parasitic capacitance control.

[0003] To overcome the limitations of planar miniaturization, three-dimensional (3D) dynamic random access memory (DRAM) employs vertical stacking technology, which significantly improves storage density by stacking multiple layers of storage cells. However, the increase in the number of storage cell layers leads to a sharp increase in the number of control signal lines such as word lines and bit lines, posing a significant challenge to reading and writing specific storage cells by selecting different control signal lines.

[0004] Therefore, how to select the control signal line to perform read and write operations on the memory cell is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a storage array, a memory, and an electronic device to optimize the problem of how to select control signal lines of the storage array.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a memory array, which may include: multiple memory layers, multiple word lines, multiple first transistors, multiple second transistors, multiple first control lines, multiple second control lines, multiple third control lines, and fixed voltage lines. The multiple memory layers are stacked along a first direction; each memory layer includes multiple memory cells arranged in an array; the multiple word lines are arranged in an array in a plane perpendicular to the first direction, and the multiple word lines are connected to the memory cells stacked along the first direction in the multiple memory layers; the multiple first transistors are arranged in multiple rows and columns, and the first electrodes of the multiple first transistors are connected to the multiple word lines one-to-one; the multiple second transistors are arranged in multiple rows and columns, and the second electrodes of the multiple second transistors are connected to the multiple word lines one-to-one; the multiple first control lines include: the gate of a first transistor in the same row is connected to a first control line; the gate of a second transistor in the same row is connected to a second control line; the second electrode of a first transistor in the same column is connected to a third control line; and the first electrodes of the multiple second transistors are connected to fixed voltage lines.

[0008] The memory array provided in this application includes multiple word lines arranged in an array. Each word line is connected to memory cells stacked along a first direction, forming a highly integrated three-dimensional memory array. The memory array also includes multiple first transistors and multiple second transistors. The multiple word lines are connected one-to-one to the first terminals of the multiple first transistors, and one-to-one to the second terminals of the multiple second transistors. Each first transistor is controlled by a first control line and a third control line coupled to its gate and second terminal. Each second transistor is controlled by a second control line coupled to its gate and first terminal, and a fixed voltage line. Therefore, the on / off state of the first and second transistors can be controlled through the first control line, the third control line, the second control line, and the fixed voltage line, thereby selecting one of the multiple word lines to control the memory cells coupled to the word line. Furthermore, since the gates of the first transistors in the same row are connected to a first control line, the gates of the second transistors in the same row are connected to a second control line, the second terminals of the first transistors in the same column are connected to a third control line, and the fixed voltage line connects to the first terminals of the multiple second transistors. Therefore, multiple first transistors and multiple second transistors can be controlled by using fixed voltage lines, a first control line equal to the number of rows of word lines, a second control line equal to the number of rows of word lines, and a third control line equal to the number of columns of word lines. This allows for the control of multiple word lines. Consequently, the number of control lines connected to word lines can be reduced from the same as the number of word lines to twice the number of rows plus the number of columns. For example, for a memory array with multiple word lines arranged in M ​​rows and N columns, the number of control lines connected to word lines can be reduced from M×N to 2M+N. Therefore, by reducing the number of control lines and their occupied area, the area efficiency of the memory array can be improved, thus increasing its storage capacity.

[0009] In one possible implementation of the first aspect, the first and second electrodes of the same first transistor are arranged along a first direction; and / or, the first and second electrodes of the same second transistor are arranged along the first direction. Thus, the arrangement direction of the first and second electrodes of the first transistor can be the same as the extension direction of the word line, thereby reducing the occupied area in a plane perpendicular to the extension direction of the word line and contributing to increased storage density. Similarly, the arrangement direction of the first and second electrodes of the second transistor can also be the same as the extension direction of the word line, which can also reduce the occupied area in a plane perpendicular to the extension direction of the word line and contribute to increased storage density.

[0010] In one possible implementation of the first aspect, the projection of the first transistor onto the memory layer overlaps with the projection of the word line onto the memory layer; and / or, the projection of the second transistor onto the memory layer overlaps with the projection of the word line onto the memory layer. This reduces the area occupied by the first transistor and word line in the plane perpendicular to the first direction, increasing the density of integrated memory cells per unit area. Similarly, it reduces the area occupied by the second transistor and word line in the plane perpendicular to the first direction, increasing the density of integrated memory cells per unit area.

[0011] In one possible implementation of the first aspect, a third control line is disposed on the side of the first transistor away from the word line along the first direction, and a fixed voltage line is disposed on the side of the second transistor away from the word line along the first direction. Thus, the third control line, the first transistor, and the word line can at least partially overlap in the first direction, that is, the projections of the third control line, the first transistor, and the word line onto a plane perpendicular to the first direction at least partially overlap. This reduces the area occupied by the third control line and the first transistor, improves area efficiency, and increases the storage density per unit area of ​​the memory array. Similarly, the fixed voltage line, the second transistor, and the word line can at least partially overlap in the first direction, that is, the projections of the fixed voltage line, the second transistor, and the word line onto a plane perpendicular to the first direction at least partially overlap. This reduces the area occupied by the fixed voltage line and the second transistor, improves area efficiency, and increases the storage density per unit area of ​​the memory array.

[0012] In one possible implementation of the first aspect, both the first and second control lines extend along a second direction, and both the third control line and the fixed voltage line extend along a third direction; the second and third directions intersect and are both perpendicular to the first direction. Thus, a first transistor can be positioned at the intersection of the extension directions of the first and third control lines, and a second transistor can be positioned at the intersection of the extension directions of the second control line and the fixed voltage line. This facilitates the arrangement of multiple first transistors in multiple rows and columns, and multiple second transistors in multiple rows and columns.

[0013] In one possible implementation of the first aspect, the first transistor and the second transistor are disposed at the same end of the word line. This allows the first transistor and the second transistor to be fabricated simultaneously in the same process step, simplifying the fabrication process.

[0014] In one possible implementation of the first aspect, the memory array includes multiple fixed voltage lines, which are arranged in the same layer as multiple third control lines. Thus, the multiple fixed voltage lines and multiple third control lines arranged in the same layer can be fabricated in the same process step, thereby reducing the number of processes and improving production efficiency.

[0015] In one possible implementation of the first aspect, a fixed voltage line is provided every two third control lines; adjacent columns of second transistors are connected to the same fixed voltage line. In this way, connecting adjacent columns of second transistors to the same fixed voltage line reduces the number of fixed voltage lines and increases the linewidth of each fixed voltage line, thereby reducing the resistance of the fixed voltage line and improving the performance of the memory array.

[0016] In one possible implementation of the first aspect, the first transistor and the second transistor are disposed at opposite ends of the word line. Thus, the first transistor, the second transistor, and the word line can all overlap in the extension direction of the word line. Therefore, this helps to reduce the area occupied by the corresponding first transistor, second transistor, and word line in a plane perpendicular to the word line, thereby improving the area efficiency of the memory array.

[0017] In one possible implementation of the first aspect, the fixed voltage line is a monolithically formed plate-like structure. Thus, the plate-like structure can be directly fabricated through simple process steps, such as by directly forming the plate-like structure with processes like deposition, which helps simplify the process.

[0018] Secondly, this application provides a memory including a control circuit and a memory array as described in any one of the first aspects; the control circuit is electrically connected to the memory array and is used to control the reading and writing of the memory array. Thus, by increasing the storage density of the memory array, the memory including the memory array also has a higher storage density.

[0019] In one possible implementation of the second aspect, the memory further includes a substrate, a control circuit disposed on the substrate, and a memory array disposed on the side of the control circuit away from the substrate; a first transistor and a second transistor of the memory array are disposed at the end of the word line of the memory array near the substrate. Thus, the first transistor and the second transistor can be disposed close to the control circuit, thereby reducing the length of the control line between the control circuit and the first and second transistors, facilitating the control circuit's control of the first and second transistors to select the word line.

[0020] In one possible implementation of the second aspect, the first transistor and the second transistor of the memory array are disposed at opposite ends of the word line of the memory array; the memory also includes a substrate, a control circuit is disposed on the substrate, and the memory array is disposed on the side of the control circuit away from the substrate; the first transistor is disposed at the end of the word line close to the substrate. Since multiple second transistors can all be connected to the same fixed voltage line, the electrical connection of the fixed voltage line is simple, while the first transistor needs to be connected to a first control line and a third control line, both of which need to be controlled by the control circuit. Therefore, when the first transistor is disposed at the end of the word line close to the substrate, the convenience of connecting the memory array to the control circuit can be improved.

[0021] Thirdly, this application provides an electronic device comprising a circuit board and a memory as described in any one of the second aspects, the memory being disposed on the circuit board. Because the memory included in this electronic device has a high storage density, the electronic device can also have good performance. Attached Figure Description

[0022] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this application;

[0023] Figure 2 A schematic diagram of a memory provided for an embodiment of this application;

[0024] Figure 3 This is a schematic diagram of a storage array structure provided in related technologies;

[0025] Figure 4 This is a schematic diagram of another storage array structure provided in related technologies;

[0026] Figure 5 An embodiment provided in this application Figure 4 A schematic diagram of the word lines and bit lines of the storage array shown.

[0027] Figure 6 This application provides a schematic diagram of the arrangement of a stepped region in a storage array.

[0028] Figure 7 This is a schematic diagram of the arrangement of the stepped area in another storage array provided in an embodiment of this application;

[0029] Figure 8 This application provides a top view of a storage layer in a storage array, as illustrated in an embodiment of the present application.

[0030] Figure 9 This is a top view of another storage layer in a storage array provided in an embodiment of this application;

[0031] Figure 10 This is a partial circuit diagram of a storage array provided in an embodiment of this application;

[0032] Figure 11 This is a partial structural diagram of a storage array provided in an embodiment of this application;

[0033] Figure 12 For along Figure 11 Schematic diagram of the cross-sectional structure of line A1-A2 in the middle;

[0034] Figure 13 For along Figure 11Schematic diagram of the cross-sectional structure of line B1-B2 in the middle;

[0035] Figure 14 A schematic diagram illustrating the arrangement of a fixed voltage line and a third control line according to an embodiment of this application;

[0036] Figure 15 A schematic diagram illustrating another arrangement of fixed voltage lines and third control lines provided in an embodiment of this application;

[0037] Figure 16 A schematic diagram of a memory array in which the first transistor and the second transistor are disposed at both ends of a word line, provided in an embodiment of this application;

[0038] Figure 17 This is a schematic diagram of another storage array provided in an embodiment of this application. Detailed Implementation

[0039] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by those skilled in the art. The terms "first," "second," "third," and similar words used in this application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of embodiments in this application, unless otherwise stated, "a plurality of" means two or more.

[0040] The directional terms such as “left,” “right,” “up,” and “down” are defined relative to the orientation of the device shown in the accompanying drawings. It should be understood that these directional terms are relative concepts and are used for relative description and clarification. They can change accordingly depending on the orientation of the chip or semiconductor package structure.

[0041] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0042] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0043] Please see Figure 1 , Figure 1 This is a schematic diagram of an electronic device 20 provided in an embodiment of this application. The electronic device 20 can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners), drones, radar, aerospace equipment, and vehicle-mounted equipment, among other different types of user equipment or terminal devices. The electronic device can also be a network device such as a base station. The embodiments of this application do not impose special limitations on the specific form of the electronic device.

[0044] Electronic device 20 may include a circuit board, a bus 25, and a system-on-chip (SoC) 21 connected to the bus 25. The bus 25 and the SoC 21 may be disposed on the circuit board. The SoC 21 may be used to process data, such as processing application data, image data, and caching temporary data. In one embodiment, the SoC 21 may include one or more processors, such as an application processor (AP) 26 for processing application data, and a graphics processing unit (GPU) 27 for processing image data. The SoC 21 may also include a first memory (random access memory, RAM) 28 for caching high-speed data. The first memory 28 may be electrically connected to the processor of the SoC 21, and the first memory 28 may be static random access memory (SRAM) or NAND flash memory, etc. Since the SoC 21 may include the first memory 28, the first memory 28 is also disposed on the circuit board.

[0045] The application processor 26, image processing unit 27 and first memory 28 can be integrated into a single die or disposed in multiple dies.

[0046] The electronic device 20 may also include a second memory 22 connected to the system-on-a-chip 21 via a bus 25. The second memory 22 may also be mounted on a circuit board. The second memory 22 may be dynamic random access memory (DRAM), in which case it can be used to store volatile data, such as temporary data generated by the system-on-a-chip 21. The storage capacity of the second memory 22 is typically larger than that of the first memory 28, but its read speed is typically slower. The second memory 22 may also be external memory, which may be NAND flash memory. Furthermore, the electronic device 20 may also include a communication chip 23 and a power management chip 24 connected to the system-on-a-chip 21 via a bus 25. The communication chip 23 may be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 24 may be used to supply power to other chips.

[0047] Figure 2 This is a schematic diagram of a memory 30 provided in an embodiment of this application. In some embodiments, the memory 30 may be as follows: Figure 1 The first memory 28 shown can also be the second memory 22.

[0048] The memory 30 may include a memory array 10 and a control circuit 300. The memory array 10 may be connected to the control circuit 300, which may be used to control the reading and writing of the memory array 10.

[0049] The storage array 10 may include multiple storage cells 100, which can be arranged in three dimensions; that is, the storage array 10 may be a three-dimensional storage array. Each storage cell 100 may include a floating-gate transistor. For example, the number of electrons in the floating gate of the floating-gate transistor can be controlled to erase and write data. The storage array 10 may also include signal lines such as word lines (WL) and bit lines (BL). Each storage cell 100 is electrically connected to a corresponding signal line. One or more signal lines can be used to receive control levels or transmit data signals. After selecting the storage cell 100 to be read or written in the storage array 10 through the signal line, read and write operations can be performed on the storage cell 100.

[0050] The control circuit 300 may include one or more of a decoder 320, a driver 330, a timing controller 340, a buffer 350, or an input / output driver 360. The decoder 320 is used to decode the address of the memory cell 100. The decoder 320 decodes the received address to determine the memory cell 100 that needs to be accessed. The driver 330 controls the level of the signal lines based on the decoding result generated by the decoder 320, thereby enabling access to the preset memory cell 100. The buffer 350 buffers the read data, for example, using a FIFO (first-in, first-out) buffer. The timing controller 340 controls the timing of the buffer 350 and controls the driver 330 to drive the signal lines in the memory array 10. The input / output driver 360 drives transmission signals, such as driving received data signals and data signals to be sent, enabling long-distance transmission of data signals. The aforementioned memory array 10, decoder 320, driver 330, timing controller 340, buffer 350 and input / output driver 360 can be integrated into one chip or integrated into different chips.

[0051] Please see Figure 3 and Figure 4 and combined Figure 2 , Figure 3 This is a schematic diagram of the structure of a storage array 10 provided in related technologies. Figure 4 This is a schematic diagram of another storage array 10 provided in related technologies. For ease of description, a structure is established as follows: Figure 3 or Figure 4 The coordinate system shown intersects the first direction X, the second direction Y, and the third direction Z. Exemplarily, the first direction X, the second direction Y, and the third direction Z may be perpendicular to each other. Figure 3 and Figure 4 As can be seen, the storage array 10 stacks multiple storage layers 11 in the vertical direction, and each storage layer 11 may include multiple storage cells 100, which can be arranged in multiple rows and columns. In this way, even if the size requirements in the plane perpendicular to the vertical direction are relaxed, the storage capacity per unit area of ​​the storage array 10 can be effectively increased.

[0052] Please continue reading Figure 3 and Figure 4The memory cell 100 may include transistors T and capacitors CAP. Transistors T and capacitors CAP are arranged along a second direction Y. Multiple transistors T may be repeatedly arranged in a first direction X, and multiple capacitors CAP may also be repeatedly arranged in the first direction X. A word line WL is connected to the gate of a plurality of transistors T arranged in the extension direction of word line WL, and a bit line BL is connected to the first electrode of a plurality of transistors T arranged in the extension direction of bit line BL. Understandably, the second electrode of transistor T is connected to capacitor CAP. The extension directions of word line WL and bit line BL may intersect. The extension direction of either word line WL or bit line BL may be along the thickness direction of the substrate. For example, a schematic diagram showing the extension direction of bit line BL along the thickness direction of the substrate if the thickness direction of the substrate is the first direction X is shown below. Figure 3 As shown in the diagram, the extension direction of the word line WL along the thickness direction of the substrate is illustrated in the figure below. Figure 4 As shown.

[0053] Because word lines WL and bit lines BL need to be selected for read and write operations on memory cells 100, the word lines WL or bit lines BL connected to each memory cell 100 are different. The higher the storage density of the memory array 10, the more word lines WL and bit lines BL there are. Therefore, controlling the huge number of word lines WL and bit lines BL through the control circuit 300 to select memory cells 100 in the memory array 10 for read and write operations presents a great challenge.

[0054] For ease of explanation, the following text will use the format "--" Figure 4 The following explanation uses storage array 10 as an example.

[0055] Please see Figure 5 and combined Figure 4 , Figure 5 An embodiment provided in this application Figure 4 This diagram illustrates the arrangement of word lines WL and bit lines BL in the memory array 10. The memory array 10 may include multiple memory layers 11, each of which may include multiple memory cells 100 arranged in multiple rows and columns. Each row of memory cells 100 may be arranged along a straight line, a curve, or a broken line; similarly, each column of memory cells 100 may be arranged along a straight line, a curve, or a broken line. Each column of memory cells 100 may be connected to the same bit line BL, and memory cells 100 stacked along a first direction X in the multiple memory layers 11 may be connected to the same word line WL.

[0056] Understandably, the bit line BL in each memory layer 11 needs to be connected to the control circuit 300 to enable read and write operations on the memory cell 100. Please refer to... Figure 6The bit lines BL in each memory layer 11 can be connected to the control circuit 300 by setting a step region. The step region may include multiple steps, such as steps SC1 to SCL, arranged in the column direction. Each step corresponds to one memory layer 11, that is, the bit lines BL in each memory layer 11 are connected to the control circuit 300 through the corresponding step. In this way, the bit lines BL in each memory layer 11 can be connected to the control circuit 300. However, this method of setting the step region results in a large area of ​​the step region, reducing the area efficiency of the memory array 10.

[0057] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating the arrangement of a stepped region in a memory array 10 according to an embodiment of this application. Multiple word lines BL in each memory layer 11 can be connected together and then connected to the control circuit 300 via a stepped section. This reduces the area of ​​each stepped section, thereby reducing the area of ​​the stepped region and improving the area efficiency of the memory array 10. For example, in... Figure 7 In the stepped region, the arrangement direction of multiple steps SC1 to SCL is the same as the arrangement direction of multiple potential lines BL. It can be seen that... Figure 7 The area occupied by the middle step area can be Figure 6 The area occupied by step SC1 in the step region of the memory. Understandably, in order to select a preset bit line BL in the same memory layer 11, each memory layer 11 may also include a multiplexer MUX, and each bit line BL is connected to the multiplexer MUX and then connected together. The control circuit 300 can select a preset bit line BL from multiple bit lines BL in the memory layer 11 through the multiplexer MUX.

[0058] Please see Figure 8 and combined Figure 4 , Figure 8 This is a top view of a storage layer 11 in the storage array 10, where multiple word lines WL are arranged in an array within the plane of the storage layer 11. Each word line WL can be connected to peripheral circuitry, allowing the control circuit 300 to select a preset word line WL. This, combined with the selected bit line BL, allows for the selection of a preset storage cell 100 for read / write operations. Understandably, for a storage array 10 with storage layer 11 comprising N rows and M columns of storage cells 100, the storage array 10 can include M multiplied by N word lines WL. Each time a read / write operation is performed on a storage cell 100, a word line WL needs to be selected; that is, M multiplied by N word lines WL need to be connected to the control circuit 300 to be selected.

[0059] Please see Figure 9 and combined Figure 4 and Figure 8M multiplied by N word lines WL are typically connected to the control circuit 300 via control lines DL, which are set in the same storage layer 11. Therefore, M control lines DL need to be set in the spacing between adjacent rows of storage cells 100. To lay out M control lines DL, the spacing between adjacent rows of storage cells 100 will increase, which is not conducive to providing storage density for the storage array 10.

[0060] Based on this, the present application provides a memory array that can reduce the number of control lines between word lines and control circuit 300, thereby increasing the memory array's storage density.

[0061] Please see Figure 10 and combined Figure 4 , Figure 10 This is a partial circuit diagram of a storage array 10 provided in an embodiment of this application.

[0062] As previously described, the storage array 10 may include multiple storage layers 11 and multiple word lines WL.

[0063] Multiple storage layers 11 can be stacked along a first direction X. Each storage layer 11 may include multiple storage cells 100. The multiple storage cells 100 can be arranged in an array, that is, the multiple storage cells 100 can be arranged in multiple rows and columns within the plane containing the storage layer 11. A row of storage cells 100 can be arranged along a straight line, a curve, or a broken line. The distance between two adjacent storage cells 100 in each row can be equal or unequal. Similarly, a column of storage cells 100 can be arranged along a straight line, a curve, or a broken line. The distance between two adjacent storage cells 100 in each column can be equal or unequal.

[0064] Understandably, although Figure 4 The memory cell 100 includes a transistor T and a capacitor CAP (1 transistor 1 capacitor, 1T 1C), but the memory cell 100 can also be other types of memory cells. For example, the memory cell 100 can also include two transistors and does not include a capacitor.

[0065] Each storage layer 11 may include multiple bit lines BL, and each bit line may connect to a row or column of storage cells 100. The multiple bit lines BL can be straight lines, polylines, or curves. For example... Figure 7 As shown, multiple bit lines BL can be connected to a multiplexer MUX and then connected to the same control line.

[0066] Multiple word lines (WL) can be arranged in an array in a plane perpendicular to the first direction X. These multiple word lines (WL) can be connected to memory cells 100 stacked along the first direction X in multiple memory layers 11. Therefore, the array arrangement of the multiple word lines (WL) can be adapted to the array arrangement of the multiple memory cells 100 in the memory layer 11. In other words, the array arrangement of the multiple word lines (WL) can be the same as the array arrangement of the multiple memory cells 100, thus facilitating the one-to-one connection of memory cells in a memory layer 11 to multiple word lines (WL).

[0067] The storage array 10 may also include a plurality of first transistors 110, a plurality of second transistors 120, a plurality of first control lines 101, a plurality of second control lines 102, a plurality of third control lines 103, and a fixed voltage line 104.

[0068] Multiple first transistors 110 can be arranged in multiple rows and columns. A row of first transistors 110 can be arranged along a straight line, a curve, or a broken line. The distance between any two adjacent first transistors 110 in each row can be equal or unequal. A column of first transistors 110 can also be arranged along a straight line, a curve, or a broken line. The distance between any two adjacent first transistors 110 in each column can be equal or unequal.

[0069] Similarly, multiple second transistors 120 can be arranged in multiple rows and columns. A row of second transistors 120 can be arranged along a straight line, a curve, or a broken line. The distance between any two adjacent second transistors 120 in each row can be equal or unequal. A column of second transistors 120 can also be arranged along a straight line, a curve, or a broken line. The distance between any two adjacent second transistors 120 in each column can be equal or unequal.

[0070] The memory array 10 can select a specific word line WL via a gating unit that includes a first transistor 110 and / or a second transistor 120. For example, the gating unit may include a first transistor 110 and a second transistor 120. Thus, the number of first transistors 110 may be equal to the number of second transistors 120.

[0071] The first terminals 111 of multiple first transistors 110 can be connected one-to-one with multiple word lines WL. Understandably, the first terminal 111 of a first transistor 110 can refer to either the source or drain of the first transistor 110, and the second terminal 112 of a first transistor 110 can refer to the other of the source or drain of the first transistor 110. The one-to-one connection means that one first transistor 110 is connected to one word line WL, and different first transistors 110 are connected to different word lines WL.

[0072] The gate of the first transistor 110 located in the same row is connected to a first control line 101. That is, multiple rows of first transistors 110 are connected to multiple first control lines 101 in a one-to-one correspondence. Understandably, the extension direction and extension form of the first control line 101 can correspond to the arrangement direction and arrangement form of a column of first control lines 101. For example, when a row of first transistors 110 is arranged in a straight line, the first control line 101 can be a straight line, and the straight line along which the row of first transistors 110 is arranged is parallel to the first control line 101.

[0073] The second electrode 112 of the first transistor 110 located in the same column is connected to a third control line 103. That is, multiple columns of first transistors 110 are connected to multiple third control lines 103 in a one-to-one correspondence. Understandably, the extension direction and extension form of the third control line 103 can correspond to the arrangement direction and arrangement form of a column of first transistors 110. For example, when a column of first transistors 110 is arranged in a straight line, the third control line 103 can be a straight line, and the straight line along which the column of first transistors 110 is arranged is parallel to the third control line 103.

[0074] The second terminals 122 of multiple second transistors 120 can be connected one-to-one with multiple word lines WL. Similarly, the first terminal 121 of the second transistor 120 can refer to either the source or the drain of the second transistor 120, and the second terminal 122 of the second transistor 120 can refer to either the source or the drain of the second transistor 120.

[0075] The gate of the second transistor 120 located in the same row is connected to a second control line 102. That is, multiple rows of second transistors 120 are connected to multiple second control lines 102 in a one-to-one correspondence. Understandably, the extension direction and extension form of the first control line 101 can correspond to the arrangement direction and arrangement form of a row of second transistors 120. For example, when a row of second transistors 120 is arranged in a straight line, the first control line 101 can be a straight line, and the straight line along which the row of second transistors 120 is arranged is parallel to the second control lines 102.

[0076] The first terminals 121 of the plurality of second transistors 120 can be connected to a fixed voltage line 104. That is, the first terminals 121 of the plurality of second transistors 120 are connected to the same fixed voltage. For example, this voltage can be a low voltage, and correspondingly, the third control line 103 can be connected to a high voltage.

[0077] The memory array 10 provided in this embodiment includes multiple word lines WL arranged in an array. Each word line WL is connected to memory cells 100 stacked along a first direction, forming a highly integrated three-dimensional memory array. The memory array 10 also includes multiple first transistors 110 and multiple second transistors 120. The multiple word lines WL are connected one-to-one with the first terminals 111 of the multiple first transistors 110, and the multiple word lines WL are connected one-to-one with the second terminals 122 of the multiple second transistors 120. Each first transistor 110 is controlled by a first control line 101 and a third control line 103 coupled to the gate and the second terminal 112. Each second transistor 120 is controlled by a second control line 102 coupled to the gate and the first terminal 121 and a fixed voltage line 104. Therefore, the first transistor 110 and the second transistor 120 can be switched on and off by the first control line 101, the third control line 103, the second control line 102 and the fixed voltage line 104, thereby selecting one of the multiple word lines WL to achieve control of the memory cell 100 coupled to the word line WL.

[0078] Based on this, since the gate of the first transistor 110 located in the same row is connected to a first control line 101; the gate of the second transistor 120 located in the same row is connected to a second control line 102; the second electrode 112 of the first transistor 110 located in the same column is connected to a third control line 103; and the fixed voltage line 104 connects to the first electrodes 121 of multiple second transistors 120, the control of multiple first transistors 110 and multiple second transistors 120 can be achieved through the first control line 101 (the same number of rows as the number of word lines WL in the array), the second control line 102 (the same number of rows as the number of word lines WL in the array), the third control line 103 (the same number of columns as the number of word lines WL in the array), and the fixed voltage line 104. Therefore, the order of magnitude of the number of control lines connected to the word lines WL can be reduced from the same as the number of word lines WL to twice the number of rows and columns of the word lines WL. For example, for a storage array 10 with multiple word lines WL arranged in M ​​rows and N columns, the number of control lines in the storage array 10 can be reduced from M×N to 2M+N. Therefore, by reducing the number of control lines and the area occupied by the control lines, the area efficiency of the storage array 10 can be improved, thereby increasing the storage capacity of the storage array.

[0079] Referring to Table 1, by setting the first control line 101 corresponding to the row containing the selected word line WL to a high voltage, setting the second control line 102 corresponding to the row containing the selected word line WL to a low voltage, and setting the third control line 103 corresponding to the column containing the selected word line WL to a high voltage, while the fixed voltage line 104 can also be connected to a low voltage, the first transistor 110 corresponding to the word line WL will be turned on and connected to the high voltage, while the second transistor 120 corresponding to the word line WL will be turned off. Thus, by setting the word line WL to a high voltage, the memory cell 100 connected to the word line WL can be selected. Combined with the bit line BL, a preset memory cell 100 can then be selected.

[0080] The other unselected word lines WL in the same row as the selected word line WL are connected to the same second control line 102. This means that the first transistors 110 corresponding to the other unselected word lines WL in the same row as the selected word line WL are all turned on, and the other unselected word lines WL are connected to their corresponding third control lines 103. Therefore, the third control lines 103 corresponding to the other unselected word lines WL in the same row as the selected word line WL are set to a low voltage. In this way, the other word lines WL in the same row as the selected word line WL are connected to a low voltage and thus are not selected.

[0081] For other unselected word lines WL located in the same row as the selected word line WL, the first control line 101 corresponding to the row of the unselected word line WL can be set to a low voltage, and the second control line 102 corresponding to the row of the unselected word line WL can be set to a high voltage. This causes the first transistor 110 corresponding to the word line WL to be turned off, and the second transistor 120 to be turned on, connecting to a fixed voltage line, i.e., connected to a low voltage. Thus, the other unselected word lines WL located in the same row as the selected word line WL are connected to a low voltage and are therefore not selected.

[0082] Table 1

[0083] Select the first control line corresponding to the line containing the text line. High voltage Select the second control line corresponding to the line containing the text line. low voltage The first control line corresponding to the line containing the unselected text line is not shown. low voltage The second control line corresponding to the line containing the unselected text line is not shown. High voltage Select the third control line corresponding to the column containing the text line. High voltage The third control line corresponding to the column containing the text line is not selected. low voltage Fixed voltage line Fixed voltage

[0084] Please see Figures 11-13 and combined Figure 4 , Figure 11 This is a partial structural diagram of a storage array 10 provided in an embodiment of this application. Figure 12 For along Figure 11 Schematic diagram of the cross-sectional structure of line A1-A2 in the middle. Figure 13 For along Figure 11 A schematic diagram of the cross-sectional structure of line B1-B2.

[0085] In some embodiments, the first electrode 111 and the second electrode 112 of the same first transistor 110 are arranged along a first direction X. In this way, the arrangement direction of the first electrode 111 and the second electrode 112 of the first transistor 110 can be the same as the extension direction of the word line WL, thereby reducing the occupied area in the plane perpendicular to the extension direction of the word line WL and helping to improve the storage density.

[0086] For example, since the first electrode 111 and the second electrode 112 of the same first transistor 110 are arranged along the first direction X, the first transistor 110 can be fabricated using a back-end process when the first direction X is the thickness direction of the substrate.

[0087] In some embodiments, the projection of the first transistor 110 onto the memory layer 11 may overlap with the projection of the word line WL onto the memory layer 11. That is, along the first direction X, the projection of the first transistor 110 onto the memory layer 11 may at least partially coincide with the word line WL. In this way, the area occupied by the first transistor 110 and the word line WL in the memory array 10 in the plane perpendicular to the first direction X can be reduced, thereby increasing the density of integrated memory cells 100 per unit area.

[0088] Similarly, in some embodiments, the first electrode 121 and the second electrode 122 of the same second transistor 120 are arranged along a first direction X. In this way, the arrangement direction of the first electrode 121 and the second electrode 122 of the second transistor 120 can be the same as the extension direction of the word line WL, reducing the occupied area in the plane perpendicular to the extension direction of the word line WL and helping to improve the storage density.

[0089] For example, since the first electrode 121 and the second electrode 112 of the same second transistor 120 are arranged along the first direction X, the second transistor 120 can also be fabricated using a back-end process when the first direction X is the thickness direction of the substrate.

[0090] In some embodiments, the projection of the second transistor 120 onto the memory layer 11 may overlap with the projection of the word line WL onto the memory layer 11. That is, along the first direction X, the projection of the second transistor 120 onto the memory layer 11 may at least partially coincide with the word line WL. In this way, the area occupied by the second transistor 120 and the word line WL in the memory array 10 in the plane perpendicular to the first direction X can be reduced, thereby increasing the density of integrated memory cells 100 per unit area.

[0091] In some embodiments, the first transistor 110 may be disposed between the third control line 103 and the word line WL along the first direction X. That is, the third control line 103 may be disposed on the side of the first transistor 110 away from the word line WL along the first direction X. Thus, the third control line 103, the first transistor 110, and the word line WL may at least partially overlap in the first direction X, meaning that the projections of the third control line 103, the first transistor 110, and the word line WL onto a plane perpendicular to the first direction X at least partially overlap. This reduces the area occupied by the third control line 103 and the first transistor 110, improves area efficiency, and increases the storage density per unit area of ​​the memory array 10.

[0092] In some embodiments, the second transistor 120 may be disposed between the fixed voltage line 104 and the word line WL along the first direction X. That is, the fixed voltage line 104 may be disposed on the side of the second transistor 120 away from the word line WL along the first direction X. Thus, the fixed voltage line 104, the second transistor 120, and the word line WL may at least partially overlap in the first direction X, i.e., their projections onto a plane perpendicular to the first direction X at least partially overlap. This reduces the area occupied by the fixed voltage line 104 and the second transistor 120, improves area efficiency, and increases the storage density per unit area of ​​the memory array 10.

[0093] In some embodiments, the first control line 101 and the second control line 102 may both extend along the second direction Y, and the third control line 103 and the fixed voltage line 104 may both extend along the third direction Z; the second direction Y and the third direction Z intersect and are both perpendicular to the first direction X. That is, the extension direction of the first control line 101 may intersect the extension direction of the third control line 103, so that the first transistor 110 can be placed at the position where the extension direction of the first control line 101 intersects the extension direction of the third control line 103. This facilitates the arrangement of multiple first transistors 110 into multiple rows and columns.

[0094] Similarly, the direction of the second control line 102 can intersect the direction of the fixed voltage line 104, thus allowing the second transistor 120 to be positioned at the intersection of the directions of the second control line 102 and the fixed voltage line 104. This facilitates the arrangement of multiple second transistors 120 into multiple rows and columns.

[0095] In some implementations, please refer to [link / reference]. Figures 11-13 The first transistor 110 and the second transistor 120 can be disposed at the same end of the word line WL. In this way, the first transistor 110 and the second transistor 120 can be fabricated simultaneously in the same process step, simplifying the fabrication process.

[0096] For example, the memory array 10 may include multiple fixed voltage lines 104, which are arranged on the same layer as multiple third control lines 103. Understandably, since the first transistor 110 and the second transistor 120 can be located at the same end of the word line WL, and the first transistor 110 is connected to the third control line 103 while the second transistor 120 is connected to the fixed voltage line 104, the multiple fixed voltage lines 104 and the multiple third control lines 103 can be arranged on the same layer. The multiple fixed voltage lines 104 and the multiple third control lines 103 arranged on the same layer can be fabricated in the same process step, thereby reducing the number of steps and improving production efficiency.

[0097] There are several ways to arrange multiple fixed voltage lines 104 and multiple third control lines 103 on the same layer.

[0098] For example, see Figure 14 and combined Figures 11-13 , Figure 14 This is a schematic diagram illustrating the arrangement of a fixed voltage line 104 and a third control line 103 according to an embodiment of this application. Figure 14 As shown in Figure (a), multiple fixed voltage lines 104 and multiple third control lines 103 can be arranged alternately, with the dashed box representing the projection of the word line WL. A first transistor 110 can be connected to the third control line 103 via a first connection structure 105, and a second transistor 120 can be connected to the fixed voltage line 104 via a second connection structure 106. Multiple first connection structures 105 can be arranged along a straight line extending in the second direction Y. Multiple second connection structures 106 can also be arranged along a straight line, which can also be arranged in the second direction Y.

[0099] Figure 14 Figure (b) illustrates a schematic diagram of the arrangement of a first transistor 110 and a second transistor 120 according to an embodiment of this application. The first transistor 110 may overlap with both the fixed voltage line 104 and the third control line 103. Similarly, the second transistor 120 may overlap with both the fixed voltage line 104 and the third control line 103. The first transistor 110 and the second transistor 120 connected to the same word line WL may be arranged in the third direction Z. Thus, the first transistor 110 and the second transistor 120 may also be arranged in the same layer, and therefore, the first transistor 110 and the second transistor 120 may be fabricated in the same process step. Simultaneously, the projections of the first transistor 110 and the second transistor 120 in a plane perpendicular to the first direction X may overlap with the projection of the word line WL in that plane. This facilitates the connection of the first transistor 110 to the word line WL and the second transistor 120 to the word line WL. The first transistor 110 and the second transistor 120 may be disposed within the projection of the word line WL in the plane perpendicular to the first direction X.

[0100] For example, please see Figure 15 and combined Figures 11-13 , Figure 15 This is a schematic diagram illustrating another arrangement of the fixed voltage line 104 and the third control line 103 provided in an embodiment of this application. Figure 15 As shown in Figure (a), a fixed voltage line 104 can be provided every two third control lines 103. In this way, two adjacent columns of second transistors 120 can be connected to the same fixed voltage line 104. This reduces the number of fixed voltage lines 104 and increases the linewidth of each fixed voltage line 104, thereby reducing the resistance of the fixed voltage line 104 and improving the performance of the memory array 10.

[0101] When a fixed voltage line 104 is provided every two third control lines 103, the arrangement of the first transistor 110 and the second transistor 120 along the third direction Y can also include various methods. For example, such as... Figure 15 As shown in Figure (a), along the third direction Y, the first transistor 110 and the second transistor 120 can be arranged alternately. For example, as... Figure 15 As shown in Figure (b), the two first transistors 110 and the two second transistors 120 arranged in sequence are repeatedly arranged along the third direction Y.

[0102] In some implementations, please refer to Figure 16 The first transistor 110 and the second transistor 120 can be disposed at opposite ends of the word line WL. Thus, the first transistor 110, the second transistor 120, and the word line WL can all overlap in the extension direction of the word line WL. Therefore, this helps to reduce the area occupied by the corresponding first transistor 110, second transistor 120, and word line WL in the plane perpendicular to the word line WL, thereby improving the area efficiency of the memory array 10.

[0103] For example, the fixed voltage line 104 can be a monolithically formed plate-like structure. That is, the fixed voltage line 104 can be a film layer structure disposed at one end of the word line WL and covering the memory layer. Understandably, all second transistors 120 can be connected to the same fixed voltage line 104. Thus, the plate-like structure can reduce the resistance of the fixed voltage line 104, which helps to improve the performance of the memory array 10. In addition, the plate-like structure can be monolithically formed, that is, the plate-like structure can be directly fabricated through simple process steps, such as being formed directly with processes such as deposition, which helps to simplify the process steps.

[0104] As mentioned above, the memory 30 provided in this application embodiment may include a control circuit 300 and any of the aforementioned memory arrays 10, such as... Figure 2 As shown.

[0105] In some implementations, please refer to Figure 17 and combined Figure 2 and Figures 10-16 The memory 30 may also include a substrate 40, and the control circuit 300 may be disposed on the substrate 40. The memory array 10 may be disposed on the side of the control circuit 300 away from the substrate 40. It can be understood that the control circuit 300 being disposed on the substrate 40 may mean that the source region and drain region of a transistor are formed in the substrate 40.

[0106] For example, when the first transistor 110 and the second transistor 120 of the memory array 10 are located at the same end of the word line WL, the first transistor 110 and the second transistor 120 can be located at the end of the word line WL closest to the substrate 40. In this way, the first transistor 110 and the second transistor 120 can be located close to the control circuit 300, thereby reducing the length of the control line between the control circuit 300 and the first transistor 110 and the second transistor 120, facilitating the control circuit 300 to control the first transistor 110 and the second transistor 120, thereby achieving the selection of the word line WL.

[0107] For example, when the first transistor 110 and the second transistor 120 are located at opposite ends of the word line WL, the first transistor 110 can be located at the end of the word line WL closest to the substrate 40. Since multiple second transistors 120 can all be connected to the same fixed voltage line 104, the electrical connection of the fixed voltage line 104 is simple. However, the first transistor 110 needs to be connected to the first control line 101 and the third control line 103, and both the first control line 101 and the third control line 103 need to be controlled by the control circuit 300. Therefore, when the first transistor 110 is located at the end of the word line WL closest to the substrate 40, the connection between the memory array 10 and the control circuit 300 can be facilitated.

[0108] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage array, characterized in that, include: Multiple storage layers are stacked along a first direction; each storage layer includes multiple storage cells arranged in an array. Multiple word lines are arranged in an array in a plane perpendicular to the first direction and connected to the memory cells stacked along the first direction in multiple memory layers; A plurality of first transistors are arranged in multiple rows and columns, and the first electrode of the plurality of first transistors is connected to the plurality of word lines in a one-to-one correspondence. Multiple second transistors are arranged in multiple rows and columns, and the second terminals of the multiple second transistors are connected to the multiple word lines in a one-to-one correspondence. Multiple first control lines, with the gate of the first transistor located in the same row connected to one of the first control lines; Multiple second control lines, with the gate of the second transistor located in the same row connected to one of the second control lines; Multiple third control lines are provided, with the second electrode of the first transistor located in the same column connected to one of the third control lines; A fixed voltage line is provided, and the first terminals of the plurality of first transistors are connected to the fixed voltage line.

2. The storage array as described in claim 1, characterized in that, The first and second electrodes of the same first transistor are arranged along the first direction; And / or, The first and second electrodes of the same second transistor are arranged along the first direction.

3. The storage array as described in claim 1 or 2, characterized in that, The projection of the first transistor onto the memory layer overlaps with the projection of the word line onto the memory layer. And / or, The projection of the second transistor onto the memory layer overlaps with the projection of the word line onto the memory layer.

4. The storage array as described in any one of claims 1 to 3, characterized in that, The third control line is disposed on the side of the first transistor away from the word line along the first direction, and the fixed voltage line is disposed on the side of the second transistor away from the word line along the first direction.

5. The storage array as described in any one of claims 1 to 4, characterized in that, The first control line and the second control line both extend along the second direction, and the third control line and the fixed voltage line both extend along the third direction; the second direction intersects with the third direction and is perpendicular to the first direction.

6. The storage array as described in any one of claims 1 to 5, characterized in that, The first transistor and the second transistor are located at the same end of the word line.

7. The storage array as described in claim 6, characterized in that, The storage array includes multiple fixed voltage lines, which are arranged on the same layer as the multiple third control lines.

8. The storage array as described in claim 7, characterized in that, A fixed voltage line is provided every two of the third control lines; The two adjacent columns of the second transistors are connected to the same fixed voltage line.

9. The storage array as described in any one of claims 1 to 5, characterized in that, The first transistor and the second transistor are disposed at opposite ends of the word line.

10. The storage array as claimed in claim 9, characterized in that... The fixed voltage line is a one-piece molded plate structure.

11. A memory, characterized in that, include: Storage array as described in any one of claims 1 to 10; A control circuit, which is electrically connected to the storage array, is used to control the reading and writing of the storage array.

12. The memory as claimed in claim 11, characterized in that, The memory also includes a substrate, the control circuit is disposed on the substrate, and the memory array is disposed on the side of the control circuit away from the substrate; The first transistor and the second transistor of the memory array are disposed at one end of the word line of the memory array near the substrate.

13. The memory as claimed in claim 11, characterized in that, The first transistor of the memory array is disposed at opposite ends of the word lines of the memory array; The memory also includes a substrate, the control circuit is disposed on the substrate, and the memory array is disposed on the side of the control circuit away from the substrate; The first transistor is disposed at one end of the word line near the substrate.

14. An electronic device, characterized in that, It includes a circuit board and a memory as described in any one of claims 11 to 13, the memory being disposed on the circuit board.

Images