Non-volatile memory devices and methods of operating the same

Abstract

The present invention provides a non-volatile memory device and an operating method thereof. The operating method of the non-volatile memory device includes performing a dynamic random access memory (DRAM) mode operation on the non-volatile memory device, performing a non-volatile memory mode storage operation on the non-volatile memory device, and periodically performing a storage operation to store a DRAM data to the non-volatile memory device before the non-volatile memory device is powered off.

Description

Technical Field

[0001] This invention relates to a non-volatile memory device and its operation method. Background Technology

[0002] A GCT (Gate-Controlled Thyristor) is an improved type of thyristor, characterized by stronger gate control capabilities, enabling faster switching and reduced power loss.

[0003] Non-volatile random access memory (NVRAM) is a type of memory that provides random access capabilities and retains data even after power is lost. It combines the fast access of RAM with the non-volatile storage characteristics (data is not lost when power is off), and is therefore widely used in devices that require fast data access but must also retain the data.

[0004] Types of NVRAM include non-volatile static random access memory (NVSRAM) and non-volatile dynamic random access memory (NVDRAM). However, NVSRAM has the disadvantages of large cell size and low memory density. NVDRAM, on the other hand, has the disadvantage of poor scalability.

[0005] Therefore, the industry needs a non-volatile memory device and its operation method to improve the shortcomings of existing non-volatile random access memory. Summary of the Invention

[0006] According to a first aspect of the present invention, a non-volatile memory device is provided, comprising: a substrate; a first gate structure, a second gate structure, and a third gate structure disposed on the substrate, separated from each other in a first direction and extending respectively along a second direction; and a plurality of channel bodies separated from each other in the second direction and a third direction, and respectively passing through the first gate structure, the second gate structure, and the third gate structure along the first direction. The first direction, the second direction, and the third direction are intersecting and perpendicular to each other, and an upper surface of the substrate is parallel to the first direction and the second direction, and the upper surface is perpendicular to the third direction. The material of the second gate structure includes oxide-nitride-oxide (ONO) or a ferroelectric thin film.

[0007] According to a second aspect of the present invention, a method for operating a non-volatile memory device is provided, comprising: performing a dynamic random access memory (DRAM) mode operation on the non-volatile memory device; performing a non-volatile memory mode storage operation on the non-volatile memory device; and periodically performing a storage operation to store DRAM data into the non-volatile memory device before the non-volatile memory device is powered off.

[0008] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0009] Figure 1 A perspective view of a non-volatile memory device according to an embodiment of the present invention is shown.

[0010] Figure 2 This shows a cross-sectional schematic diagram of the second gate structure of a non-volatile memory device according to an embodiment.

[0011] Figure 3 This diagram shows an equivalent circuit diagram of a non-volatile memory device according to an embodiment of the present invention.

[0012] Figure 4A This diagram shows an operation flowchart of a non-volatile memory device according to an embodiment of the present invention.

[0013] Figure 4B This diagram shows the current-voltage curve of a non-volatile memory device according to an embodiment of the present invention.

[0014] Figure 5A A schematic diagram showing the DRAM mode operation of a non-volatile memory device according to an embodiment of the present invention is displayed.

[0015] Figure 5B A schematic diagram showing a non-volatile memory device as an HRS or LRS.

[0016] Figure 6A This diagram illustrates a storage-to-NVM operation of a non-volatile memory device according to an embodiment of the present invention.

[0017] Figure 6B The diagram shows a simulation of the channel potential and a simulation of the coupling efficiency.

[0018] Figure 6C The electron density of the channels in the second gate structure G2 is shown in the cases of NVM “1” and NVM “0”.

[0019] Figure 7 This diagram shows a simulation of the NVM hold time of a non-volatile memory device according to an embodiment of the present invention.

[0020] Figure 8A This diagram shows the current-voltage curves of a non-volatile memory device according to an embodiment of the present invention.

[0021] Figure 8B The diagram shows the current-voltage curves and band-position diagram of a non-volatile memory device according to an embodiment of the present invention.

[0022] Figure 9 This illustrates a non-volatile memory device according to an embodiment of the present invention.

[0023] Figure 10 This graph shows the threshold voltage versus the absolute value of the bias voltage of G2 according to an embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10: Non-volatile memory devices

[0026] 100: Substrate

[0027] 112, 113, 114: Gate structure

[0028] 120: Channel Body

[0029] CP: Connecting pad

[0030] 140: First side plug

[0031] 150: Second side plug

[0032] D1~D3: direction

[0033] 1121~1123, 1131~1133, 1141~1143: Partial

[0034] 120a: First end

[0035] 120b: Second end

[0036] 118: Dielectric film

[0037] 201: Tunnel dielectric layer

[0038] 202: Charge trapping layer

[0039] 203: Barrier Dielectric Layer

[0040] CA~CD: Memory Units

[0041] TA1~TD3: Transistors

[0042] BL1, BL2: Bit lines

[0043] G1~G3: Gate structure Detailed Implementation

[0044] The technical terms used in this specification are based on common terminology in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment of the present invention has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0045] Figure 1 A perspective view of a non-volatile memory device 10 according to an embodiment of the present invention is shown. The non-volatile memory device 10 includes a substrate 100, a first gate structure 112 (also referred to as a first gate G1), a second gate structure 113 (also referred to as a second gate structure G2), a third gate structure 114 (also referred to as a third gate G3), a plurality of channel bodies (also referred to as "channels") 120, a plurality of pads CP, a first side connector 140, and a plurality of second side connectors 150. For the sake of simplicity, Figure 1 Some insulating materials are omitted from the drawing. For example, the insulating material between the substrate 100, the channel body 120, the first gate structure 112, the second gate structure 113 and the third gate structure 114 is omitted.

[0046] like Figure 1 As shown, the first gate structure 112, the second gate structure 113, and the third gate structure 114 are disposed on the substrate 100, separated from each other in the first direction D1 (e.g., the Y direction) and extending along the second direction D2 (e.g., the X direction). In other words, the non-volatile memory device 10 of this embodiment includes three gate structures, namely the first gate structure 112, the second gate structure 113, and the third gate structure 114, and the operation of the non-volatile memory device 10 is controlled by applying a bias voltage to the first gate structure 112, the second gate structure 113, and the third gate structure 114. The channel body 120 is separated from each other in the second direction D2 and the third direction D3 (e.g., the Z direction) and extends along the first direction D1 and passes through the first gate structure 112, the second gate structure 113, and the third gate structure 114. Figure 1 As shown, the first direction D1, the second direction D2, and the third direction D3 are intersected. The upper surface of the substrate 100 is parallel to the first direction D1 and the second direction D2, and the normal direction of the upper surface of the substrate 100 is parallel to the third direction D3. The first direction D1, the second direction D2, and the third direction D3 are substantially perpendicular to each other. The channel body 120 may be orthogonal to the first gate structure 112, the second gate structure 113, and the third gate structure 114.

[0047] exist Figure 1 In this invention, the first gate structure 112, the second gate structure 113, and the third gate structure 114 have, for example, asymmetrical widths (but the invention is not limited thereto), where the width is measured in a first direction D1. For example, in the first direction D1, a first width of the first gate structure 112, a second width of the second gate structure 113, and a third width of the third gate structure 114 are different from each other; for example, the first width is smaller than the second width, and the second width is smaller than the third width, but the invention is not limited thereto.

[0048] Furthermore, in this embodiment, the first gate structure 112 includes a plurality of portions 1121-1123, which have the same width in the first direction D1. Each portion 1121-1123 of the first gate structure 112 extends along the second direction D2, and these portions 1121-1123 are separated from each other along the third direction D3, for example, separated from each other by an insulating material (not shown) without direct contact. The lengths of these portions 1121-1123 of the first gate structure 112 in the second direction D2 are different from each other; for example, the lengths of portions 1121-1123 in the second direction D2 decrease along the second direction D2, that is, the length of portion 1121 in the second direction D2 is greater than the length of portion 1122 in the second direction D2, and the length of portion 1122 in the second direction D2 is greater than the length of portion 1123 in the second direction D2.

[0049] The second gate structure 113 includes a plurality of portions 1131-1133, which have the same width in the first direction D1. Each portion 1131-1133 of the second gate structure 113 extends along the second direction D2 and is separated from each other along the third direction D3, for example, by an insulating material (not shown) to separate them without direct contact. The lengths of the portions 1131-1133 of the second gate structure 113 in the second direction D2 are different from each other; for example, the lengths of the portions 1131-1133 in the second direction D2 decrease along the second direction D2, that is, the length of portion 1131 in the second direction D2 is greater than the length of portion 1132 in the second direction D2, and the length of portion 1132 in the second direction D2 is greater than the length of portion 1133 in the second direction D2.

[0050] The third gate structure 114 includes a plurality of portions 1141-1143, which have the same width in the first direction D1. Each portion 1141-1143 of the third gate structure 114 extends along the second direction D2 and is separated from each other along the third direction D3, for example, by means of an insulating material (not shown) that separates them from each other without direct contact. Similarly, the lengths of portions 1141-1143 in the second direction D2 are different from each other; for example, the lengths of portions 1141-1143 in the second direction D2 decrease along the second direction D2, that is, the length of portion 1141 in the second direction D2 is greater than the length of portion 1142 in the second direction D2, and the length of portion 1142 in the second direction D2 is greater than the length of portion 1143 in the second direction D2.

[0051] like Figure 1 As shown, the pads CP are stacked along the third direction D3 and separated from each other along the third direction D3. Each pad CP is connected to a corresponding first end 120a in the channel body 120. For example, each pad CP is connected to the three first ends 120a of the three channel bodies 120 that overlap each other in the second direction D2. The first side plug 140 extends along the third direction D3 and connects to all the pads CP. The second side plugs 150 extend along the third direction D3 and are separated from each other in the second direction D2. Each second side plug 150 is connected to a corresponding second end 120b in the channel body 120. For example, each second side plug 150 is connected to the three second ends 120b of the three channel bodies 120 that overlap each other in the third direction D3. The second end 120b is relative to the first end 120a, that is, the first end 120a and the second end 120b are the opposite ends of the channel body 120 extending in the first direction D1. The first gate structure 112 is closer to the first end 120a than the third gate structure 114, the third gate structure 114 is closer to the second end 120b than the first gate structure 112, and the second gate structure 113 is located between the third gate structure 114 and the first gate structure 112. According to one embodiment, the first end 120a includes a first conductivity type dopant, and the second end 120b includes a second conductivity type dopant. The second conductivity type dopant is different from the first conductivity type dopant; for example, the first conductivity type dopant is an N-type dopant, and the second conductivity type dopant is a P-type dopant. That is, the first end 120a includes a high concentration of N-type dopant (N+), and the second end 120b includes a high concentration of P-type dopant (P+).

[0052] Furthermore, each portion 1121-1123 of the first gate structure 112 may surround multiple channel bodies 120 and dielectric films 118, for example, three channel bodies 120 and dielectric films 118 of the same level, with portions 1121-1123 forming three gate-all-around (GAA) structures. Similarly, each portion 1131-1133 of the second gate structure 113 may surround multiple channel bodies 120 and dielectric films 118, for example, three channel bodies 120 and dielectric films 118 of the same level, with portions 1131-1133 forming three gate-all-around structures. Likewise, each portion 1141-1143 of the third gate structure 114 may surround multiple channel bodies 120 and dielectric films 118, for example, three channel bodies 120 and dielectric films 118 of the same level, with portions 1141-1143 forming three gate-all-around structures.

[0053] Parts 1121-1123 of the first gate structure 112, parts 1131-1133 of the second gate structure 113, and parts 1141-1143 of the third gate structure 114 can be biased independently, and the word line bias of different layers (pages) can be adjusted independently. Therefore, page erasure can be performed, and it is easier to adjust the disturbance and retention of unselected pages.

[0054] One embodiment of the non-volatile memory device 10 of the present invention is a 3D stacked GCTnvDRAM, which has the following device characteristics: (1) it uses P+ bit line (BL) and N+ source line (SL) to realize DRAM operation based on thyristor; (2) the gate dielectric layer of the second gate structure G2 includes an ONO (oxide-nitride-oxide) layer or a ferroelectric thin film to realize the non-volatile memory (NVM) function, wherein the ONO can also be designed using band-gap engineering, wherein the tunneling dielectric layer is composed of multiple layers of oxide and nitride; (3) the dielectric layers of the first gate G1 and the third gate G3 can be ONO, ferroelectric materials, or simple oxide; (4) it uses 3 word lines (wherein G1 and G3 are used as selectors) to enable the self-boosting principle during storage; (5) it supports recall-free operation mode. These details will be described below.

[0055] Figure 2 This shows a cross-sectional schematic diagram of the second gate structure 113 (also referred to as the second gate structure G2) of a non-volatile memory device 10 according to an embodiment. Figure 2As shown, the second gate structure 113 includes: a tunnel dielectric layer 201 (implemented by oxide), a charge trapping layer 202 (implemented by nitride), and a blocking dielectric layer 203 (implemented by oxide). Thus, the second gate structure 113 has an ONO (oxide-nitride-oxide) architecture. In other possible embodiments, the second gate structure 113 may be implemented using a ferroelectric thin film.

[0056] Figure 3 This diagram shows an equivalent circuit diagram of a non-volatile memory device 10 according to an embodiment of the present invention. Figure 3 As shown, according to one embodiment, the non-volatile memory device 10 further includes a plurality of memory cells (such as...). Figure 3 The memory cells CA~CD shown are formed by a corresponding channel body 120, a first gate structure 112, a second gate structure 113, and a third gate structure 114. Figure 3 The equivalent circuit diagram is shown below.

[0057] like Figure 3 As shown, for example, the channel body 120 forms transistors TA1, TA2, and TA3 at each intersection of portion 1121 of the first gate structure 112, portion 1131 of the second gate structure 113, and portion 1141 of the second gate structure 114, respectively. Figure 3 As shown, transistors TA1, TA2, and TA3 connected through the same channel body 120 form memory cell CA; transistors TB1, TB2, and TB3 connected through the same channel body 120 form memory cell CB; transistors TC1, TC2, and TC3 connected through the same channel body 120 form memory cell CC; and transistors TD1, TD2, and TD3 connected through the same channel body 120 form memory cell CD. The first end 120a of the channel body 120 is connected to the corresponding first side pad CP. The first side pads CP of different layers are electrically contacted with a first side plug 140 and electrically connected to the source line. Therefore, memory cells CA~CD are connected to a common source line CSL (i.e., at the same potential). The second end 120b of the channel body 120 is connected to the corresponding second side plug 150. That is, the channel bodies 120 that overlap each other on the third direction D3 are connected to the same second side plug 150. The second side plug 150 can be used as a bit line. For example, memory cells CA and CC are electrically connected to the first bit line BL1, and memory cells CB and CD are electrically connected to the second bit line BL2.

[0058] Please refer back to this. Figure 1According to this embodiment, the first gate structure 112, the second gate structure 113, and the third gate structure 114 can each serve as multiple word lines (WL). For example, each portion 1121-1123 of the first gate structure 112 can serve as one word line, meaning the first gate structure 112 can correspond to 3 word lines; each portion 1131-1133 of the second gate structure 113 can serve as one word line, meaning the second gate structure 113 can correspond to 3 word lines; and each portion 1141-1143 of the third gate structure 114 can serve as one word line, meaning the third gate structure 114 can correspond to 3 word lines. The first-side connector 140 can serve as a common source line (CSL). Each second-side connector 150 can serve as a bit line (BL).

[0059] In some embodiments, substrate 100 may comprise a semiconductor substrate, such as a bulk silicon substrate. In this embodiment, channel body 120 may be formed by a selective epitaxial growth process, and the material of channel body 120 may include single-crystal silicon. During operation (e.g., programming or erasing) of the non-volatile memory device 10, channel body 120 may be used to store carriers (e.g., electrons or holes). Dielectric film 118 does not need to have the function of storing carriers (e.g., electrons or holes), therefore dielectric film 118 does not include a charge storage structure, such as an oxide-nitride-oxide (ONO) structure. In one embodiment, the material of dielectric film 118 includes a dielectric material, such as an oxide, and dielectric film 118 may be a single-layer structure. In one embodiment, the material of dielectric film 118 may include a high dielectric constant material (high-k material). In one embodiment, the materials of the first side plug 140, the second side plug 150, the first gate structure 112, the second gate structure 113, and the third gate structure 114 may include semiconductor materials or metallic materials. It should be understood that the materials of the above-described elements of the present invention are not limited thereto.

[0060] Figure 4A This diagram shows the operation flowchart of a non-volatile memory device 10 according to an embodiment of the present invention. Figure 4B This displays a current-voltage graph of a non-volatile memory device 10 according to an embodiment of the present invention. Figure 4A The voltage values ​​shown are for illustrative purposes only, and the invention is not limited thereto.

[0061] like Figure 4AAs shown, during a DRAM write operation, the voltages VG1, VG2, and VG3 applied to the three gates G1, G2, and G3 are -2.5V, +4V, and -2.5V, respectively; the voltage VBL applied to the bit line is +3.5V (for writing "1") or 0V (for writing "0"); and the voltage VSL applied to the source line is 0V. Here, "DRAM write operation" refers to treating the non-volatile memory device 10 as DRAM and performing the write operation.

[0062] like Figure 4A As shown, during a DRAM read operation, the voltages VG1, VG2, and VG3 applied to the three gates G1, G2, and G3 are -2.5V, +4V, and -2.5V, respectively; the voltages VBL and VSL applied to the bit line and source line are +2V and 0V, respectively. Here, "DRAM read operation" refers to reading the non-volatile memory device 10 as DRAM. "DRAM write operation" and "DRAM read operation" can also be collectively referred to as "DRAM mode operation".

[0063] like Figure 4A As shown, during the NVM storage operation, the voltages VG1, VG2, and VG3 applied to the three gates G1, G2, and G3 are -2.5V, +15V, and +2.5V, respectively; the voltages VBL and VSL applied to the bit line and source line are +2V and 0V, respectively. Here, "NVM storage operation" means storing data as if the non-volatile memory device 10 were non-volatile memory. "NVM storage operation" can also be called "non-volatile memory mode storage operation".

[0064] like Figure 4A As shown, when the power is off, all voltages VG1, VG2 and VG3, VBL and VSL are of course 0V.

[0065] like Figure 4A As shown, during an NVM read operation, the voltages VG1, VG2, and VG3 applied to the three gates G1, G2, and G3 are -2.5V, +4V, and -2.5V, respectively; the voltages VBL and VSL applied to the bit line and source line are +2V and 0V, respectively. An "NVM read operation" refers to treating the non-volatile memory device 10 as non-volatile memory for reading. In an "NVM read operation," the NVM state (1 or 0) is read to confirm whether it is the same as the DRAM state (1 or 0). Here, the NVM state refers to the state stored in the non-volatile memory device 10 during the NVM write operation, while the DRAM state (or DRAM data) refers to the state (or data) written to the non-volatile memory device 10 during the DRAM write operation. Figure 4AAs shown in the source current ISL below, when the DRAM state is 1, reading the non-volatile memory device 10 will result in a high current, while when the DRAM state is 0, reading the non-volatile memory device 10 will result in a low current. A DRAM state of 1 corresponds to an NVM state of 1, and a DRAM state of 0 corresponds to an NVM state of 0. Therefore... Figure 4A As shown by the source current ISL below, when the NVM state is 1, reading the non-volatile memory device 10 will result in a high current, while when the NVM state is 0, reading the non-volatile memory device 10 will result in a low current. This demonstrates that, in one embodiment of the present invention, the NVM state is the same as the DRAM state.

[0066] In addition, in one embodiment of the present invention, the NVM read operation is a selective step because the NVM read operation is to verify whether the NVM state is the same as the DRAM state. Therefore, even if the NVM read operation is omitted, it will not affect the operation results of DRAM write, DRAM read, and storage to NVM operation of the non-volatile memory device 10 of the present invention.

[0067] It is important to note that Figure 4A The order of these operations (DRAM write, DRAM read, save to NVM, power off, and NVM read) is not intended to limit the operation of the non-volatile memory device 10 in this embodiment of the invention. That is, under normal circumstances, after multiple DRAM write and DRAM read operations, one or more "save to NVM operations" can be performed. In this way, even if a power off occurs, the data stored in the non-volatile memory device 10 can still exist and will not be lost.

[0068] At Figure 4B As can be seen from the diagram, when the non-volatile memory device 10 is written with a 1, the bit line current IBL has a high current (Ion), while when the non-volatile memory device 10 is written with a 0, the bit line current IBL has a low current (Ioff). The ratio of the high current (Ion) of the bit line current IBL to the low current (Ioff) of the bit line current IBL is approximately 1E7 (1×10⁻⁶). 7 Furthermore, VFB stands for Forward Break-over Voltage. VFB refers to the voltage at which a thyristor automatically turns on when the forward voltage rises to a certain value without an external gate trigger current. This is because the device automatically turns on when the applied gate voltage exceeds this value, without gate triggering.

[0069] Figure 5AA schematic diagram showing DRAM mode operation of a non-volatile memory device 10 according to an embodiment of the present invention is displayed. Figure 5A As shown, during DRAM mode operation of the non-volatile memory device 10, the voltages VG1, VG2, and VG3 applied to the three gates G1, G2, and G3 are -2.5V, +4V, and -2.5V, respectively. When writing a 1, the bit line voltage VBL applied to the bit line is higher than the forward breakdown voltage VFB to induce forward breakdown, locking the memory cell of the non-volatile memory device 10 to "1" (also known as the low resistance state (LRS)). On the other hand, when writing a "0", the bit line voltage VBL applied to the bit line is 0V, restoring the potential barrier. This locks the memory cell of the non-volatile memory device 10 to "0" (also known as the high resistance state (HRS)). During DRAM read operation, the bit line VBL is set between the holding voltage (approximately 0.4V) and VFB, and the bit line current IBL is read.

[0070] Figure 5B A schematic diagram showing the non-volatile memory device 10 as an HRS or LRS. (See diagram below.) Figure 5B As shown, a bit line voltage higher than VFB reduces the potential barrier (hole barrier or electron barrier), allowing the non-volatile memory device 10 to enter the LRS. A bit line voltage of 0V induces the potential barrier (hole barrier or electron barrier), allowing the non-volatile memory device 10 to enter the HRS.

[0071] Figure 6A This diagram illustrates the storage to NVM operation of a non-volatile memory device 10 according to an embodiment of the present invention. When DRAM "1" is stored to NVM "1" (GCT is on at this time, so electrons and holes can flow freely), the bias voltage of G2 is +15V. Since it is LRS at this time, the channel voltage of G2 is about half of the bit line voltage VBL (+2V) (+1V). The trans-voltage of G2 (from the bias voltage of G2 to the channel voltage of G2) is about 14V, which causes +FN tunneling (forward Fowler-Nordheim (FN) tunneling) to occur, which can store a large amount of charge in the channel of G2, which is NVM "1".

[0072] Conversely, when storing DRAM "0" to NVM "0" (GCT is off, so electrons and holes are prohibited from flowing), the bias voltage of G2 is +15V. Since this is HRS, the channel of G2 is in a floating state. Assuming a coupling efficiency of 0.8, the channel voltage of G2 is approximately 0.8 of the bias voltage of G2 (15V × 0.8 = 12V). The voltage across G2 (from the bias voltage of G2 to the channel voltage of G2) is approximately 15V - 12V = 3V, which prevents +FN tunneling (forward Fowler-Nordheim (FN) tunneling). Therefore, a large amount of charge will not be stored in the channel of G2, which is NVM "0".

[0073] Figure 6B The simulation plots show the channel potential and the coupling efficiency. Figure 6B As shown, during the "store to NVM operation", the channel surface potential exhibits a unique self-boosting characteristic of the DRAM "0" state. The significant difference between DRAM "1" and "0" thus satisfies the requirements of the "store to NVM operation".

[0074] from Figure 6B The simulation graph below shows that the peak surface potential of DRAM "0" as a function of the G2 bias voltage exhibits a coupling efficiency of 80%.

[0075] Figure 6C This shows the electron density of the G2 channel in the cases of NVM "1" and NVM "0". Therefore, from... Figure 6C It can be seen that the electrons trapped in the charge trapping layer only exist in the DRAM "1" (NVM "1") state, while the self-enhancing mechanism causes the electrons trapped in the charge trapping layer to disappear in the DRAM "0" (NVM "0") state.

[0076] In other words, in one embodiment of the present invention, writing DRAM "1" means enabling the memory cell (e.g., Figure 3 The memory cell CA…) is turned on (LRS), while writing to DRAM “0” means turning on the memory cell (such as…). Figure 3 The memory cell CA…) is turned off (HRS). In one embodiment of the present invention, storing DRAM “1” in NVM means trapping electrons in the second gate structure G2 of GCT, while storing DRAM “0” in NVM means eliminating the trapped electrons so that the electrons are not actually present in the second gate structure G2 of GCT.

[0077] Figure 7This diagram shows a simulation of the NVM hold time for a non-volatile memory device 10 according to an embodiment of the present invention. Here, +FN PGM represents programming, and -FN ERS represents erasing. Figure 7 As can be seen, in NVM mode, the memory cell of the non-volatile memory device 10 of an embodiment of the present invention has high temperature retention characteristics, showing that after baking at 85°C for 10 years, a voltage window of 1.1V can still be obtained.

[0078] Figure 8A This diagram shows the current-voltage curves of a non-volatile memory device 10 according to an embodiment of the present invention. Figure 8B The current-voltage curves and band-position diagrams of a non-volatile memory device 10 according to an embodiment of the present invention are shown.

[0079] like Figure 8A As shown, when electrons are captured in the ONO layer of the second gate structure G2 (i.e., NVM "1" state), a slight hysteresis effect occurs, and only LRS is observed, corresponding to the "1" state of DRAM. Conversely, if electrons are not captured in the ONO layer of the second gate structure G2 (i.e., NVM "0" state), typical hysteresis is exhibited. This means that as long as the bit line voltage VBL is less than the forward breakdown voltage VFB, the DRAM will remain in the "0" state. This function lays the foundation for the recall-free operation of the memory cell (nvDRAM) of the non-volatile memory device 10 of an embodiment of the present invention, because the NVM state (whether there are captured electrons in G2) can determine the DRAM state, thereby eliminating the need for an additional recall step (in the prior art, a recall step is required after power failure to save data from NVM back to DRAM).

[0080] like Figure 8B As shown, the curves of simulated source current ISL versus bit line voltage VBL and the energy band diagrams of the SONOS layer of G2 with different numbers of trapped electrons are presented. Because G2 modulates the hole barrier, as the number of trapped electrons increases, the hole barrier or electron barrier is effectively reduced, resulting in a decrease in the forward breakdown voltage VFB.

[0081] Figure 9 This diagram illustrates a simulation of a non-volatile memory device 10 in NVM erase operation according to an embodiment of the present invention. The simulation diagram shows the threshold voltage and absolute value of the bias voltage of G2 for the memory cells of the non-volatile memory device 10 in NVM mode for +FN write (+FN PGM) (for "storage") and -FN erase (for NVM "erase") (-FN ERS).

[0082] In addition, Figure 9The graph only shows the curves during forward sweeping. During +FN writing, the memory cell transitions from HRS to LRS as the number of trapped electrons increases. During -FN erasing, the threshold voltage Vth gradually increases due to hole tunneling.

[0083] When DRAM data is updated, NVM data should be erased. This erasure is achieved by injecting holes into the channels of the second gate structure G2 via a -FN erase operation to neutralize trapped electrons.

[0084] Figure 10 This invention presents a graph showing the threshold voltage versus the absolute value of the bias voltage of G2 according to an embodiment of the present invention. The graphs show the G2 dielectric layer using SONON material (referred to as SONOS cell) and the G2 dielectric layer using Fe (ferroelectric) material (referred to as FeFET cell), respectively. The graphs demonstrate the transient NVM write characteristics using either SONOS (measured) or FeFET (simulated) G2 structures. The FeFET architecture significantly reduces write voltage and latency.

[0085] The table below shows a performance comparison between one embodiment of the present invention and other existing embodiments.

[0086]

[0087] In the table above, a destructive read refers to an operation that alters or erases the original data when reading data from a memory cell, making the original data unrecoverable and requiring an additional reset (rewrite or refresh) operation to maintain data consistency.

[0088] As can be seen from the above description and the table above, the non-volatile memory device of this invention discloses a capacitor-free 3D nvDRAM based on GCT, one of its features being the ability to perform non-destructive reads without requiring a recall (even in the event of an unexpected power outage). Due to the absence of capacitors, the memory cells of the non-volatile memory device of this invention have a smaller size. These advantages enable the non-volatile memory device of this invention to achieve faster boot times and reduce power consumption during startup. The non-volatile memory device of this invention has the potential to achieve fast data backup and boot, making it a promising alternative to persistent memory.

[0089] While the invention may describe many specific details, these should not be construed as limiting the scope of the claimed invention, but rather as descriptions of the characteristics of particular embodiments. In this description, certain features described in the context of a single embodiment may also be implemented in combination in that single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, while features may initially be described as functioning in certain combinations, or even initially described as such combinations, in some cases one or more features may be removed from that combination, and the described combination may be for a sub-combination or a variation thereof. Similarly, while operations are depicted in the figures as being performed in a specific order, this should not be construed as requiring these operations to be performed in the specific order or sequence shown, or that all depicted operations must be performed to achieve the desired result.

[0090] Although the above embodiments of the present invention only disclose some examples and implementations, changes, modifications, and enhancements can be made to the examples, implementations, and other implementations based on the disclosed content.

[0091] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A non-volatile memory device, comprising: A substrate; A first gate structure, a second gate structure and a third gate structure are disposed on the substrate, separated from each other in a first direction and extending along a second direction respectively; as well as Multiple channel bodies are separated from each other in the second direction and a third direction, and respectively pass through the first gate structure, the second gate structure and the third gate structure along the first direction. The first direction, the second direction, and the third direction intersect each other and are perpendicular to each other. An upper surface of the substrate is parallel to the first direction and the second direction, and the upper surface is perpendicular to the third direction. The material of the second gate structure includes oxide-nitride-oxide (ONO) or ferroelectric thin film.

2. The non-volatile memory device according to claim 1, further comprising: Multiple pads are stacked along the third direction and separated from each other along the third direction, and each pad is connected to a corresponding first end in the channel body; A first-side plug extends along the third direction and connects to these pads; as well as Multiple second-side plugs extend along the third direction and are separated from each other in the second direction. Each second-side plug is connected to a corresponding second end in these channel bodies, the second end being relative to the first end, wherein the first gate structure is closer to the first end than the second gate structure.

3. The non-volatile memory device according to claim 1, wherein: The first gate structure includes multiple portions, which are respectively extended along the second direction and separated from each other along the third direction; The second gate structure includes multiple portions, which are respectively extended along the second direction and separated from each other along the third direction; as well as The third gate structure includes multiple portions, which are respectively extended along the second direction and separated from each other along the third direction.

4. The non-volatile memory device according to claim 3, wherein: The lengths of these portions of the first gate structure are different from each other in the second direction; The lengths of these portions of the second gate structure are different from each other in the second direction; as well as The lengths of these portions of the third gate structure are different from each other in the second direction.

5. The non-volatile memory device according to claim 2, wherein the first terminal includes a first conductivity type dopant, the second terminal includes a second conductivity type dopant, and the second conductivity type dopant is different from the first conductivity type dopant.

6. The non-volatile memory device according to claim 5, wherein, The first conductivity type dopant is an N-type dopant, and the second conductivity type dopant is a P-type dopant.

7. The non-volatile memory device according to claim 3, wherein, These portions of the first gate structure, these portions of the second gate structure, and these portions of the third gate structure are independently biased.

8. The non-volatile memory device according to claim 1, wherein, In this first direction, the first gate structure, the second gate structure, and the third gate structure have asymmetrical widths.

9. The non-volatile memory device according to claim 1, wherein, In the first direction, a first width of the first gate structure, a second width of the second gate structure, and a third width of the third gate structure are different from each other, with the first width being smaller than the second width and the second width being smaller than the third width.

10. A method of operating a non-volatile memory device, comprising: Perform a dynamic random access memory (DRAM) mode operation on the non-volatile memory device; Perform a non-volatile memory mode storage operation on the non-volatile memory device; as well as Before the non-volatile memory device is powered off, a storage operation is periodically performed to store DRAM data into the non-volatile memory device.

11. The method of operating the non-volatile memory device according to claim 10, wherein, This DRAM mode operation includes a DRAM write operation; When the non-volatile memory device is written with "1", the bit line voltage is higher than a forward breakdown voltage to induce forward breakdown and lock a memory cell of the non-volatile memory device to a first impedance state, and the bit line current is a first current. as well as When the non-volatile memory device is written with "0", the bit line voltage is 0V and the memory cell of the non-volatile memory device is locked to a second impedance state. The bit line current is a second current, and the first current is much higher than the second current.

12. The method of operating the non-volatile memory device according to claim 10, wherein, The DRAM mode operation includes: a DRAM read operation, in which a bit line voltage is set between a holding voltage and a forward breakdown voltage, and a bit line current is read.

13. The method of operating the non-volatile memory device according to claim 11, wherein, When performing this non-volatile memory mode storage operation, When DRAM "1" is stored in NVM "1", the memory cell of the non-volatile memory device is locked to the first impedance state, and the channel voltage of the second gate structure is related to the bit line voltage to store charge in the channel of the second gate structure. as well as When storing DRAM "0" to NVM "0", the memory cell of the non-volatile memory device is in the second impedance state to eliminate the charge trapped in the channel of the second gate structure.

14. The method of operating the non-volatile memory device according to claim 10, further comprising: An NVM read operation reads an NVM state to confirm whether it is the same as a DRAM state.

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