A method and system for dynamically adjusting the data refresh cycle of SLC NAND.

Abstract

This invention relates to the field of semiconductor memory data reliability management technology, and discloses a method and system for dynamically adjusting the data refresh cycle of SLC NAND. The method includes acquiring the operating status data of each data block of the SLC NAND, performing block-level timing correlation processing to obtain a block-level status sequence; evaluating data retention capability and degradation trend based on the block-level status sequence to obtain a retention margin sequence, a current retention margin, and a degradation rate; determining the safe retention duration and refresh cycle of each data block based on the current retention margin, the degradation rate, and the safe retention margin; generating a refresh task in conjunction with the SLC NAND operating load, and performing error correction writing processing on the valid data of the target data block to obtain a refreshed data block. This method can achieve block-level adjustment of the refresh cycle of each data block in SLC NAND.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor memory data reliability management, and particularly relates to a SLC NAND data refresh period dynamic adjustment method and system. BACKGROUND

[0002] At present, SLC NAND records data through threshold voltage states of storage units, and has the characteristics of long data retention time and high read-write reliability. In the long-term running process, the charge in the storage unit will gradually drain with the placement time, and the charge retention capability of different data blocks will also change due to wear and tear, temperature changes and cumulative read operations. The flash memory controller usually performs address mapping, error checking and background refresh scheduling through an application specific integrated circuit, and rewrites the data to an available data block when the data block reaches the refresh condition.

[0003] In one prior art, the refresh of each data block is usually performed according to a uniform refresh period, or the data blocks are divided into different levels according to the number of times of erasing and writing, and the same refresh period is configured for the data blocks of the same level. Since there are differences in the running state and data retention capability of different data blocks, it is difficult to reflect the actual changes of the retention capability of each data block by using a uniform period or a fixed grading method, which may cause the data blocks with low retention capability to fail to be refreshed in time, or the data blocks with high retention capability to be refreshed in advance.

[0004] There is a problem in the prior art that the refresh period of each data block of SLC NAND is difficult to accurately determine according to the data retention capability. SUMMARY

[0005] The present application provides a SLC NAND data refresh period dynamic adjustment method and system to solve the problem in the prior art that the refresh period of each data block of SLC NAND is difficult for accurate determination according to the data retention capability.

[0006] In a first aspect, to solve the above technical problem, the present application provides a SLC NAND data refresh period dynamic adjustment method, comprising: obtaining running state data of each data block of SLC NAND, performing block time sequence association processing on the running state data to obtain a block-level state sequence; performing data retention capability evaluation according to the block-level state sequence to obtain a retention margin sequence, and performing degradation trend evaluation according to the retention margin sequence to obtain a current retention margin and a degradation rate; performing remaining time evaluation according to the current retention margin, the degradation rate and a preset safe retention margin to obtain a safe retention time length of each data block, and performing refresh period determination processing on the safe retention time length of each data block respectively to obtain a refresh period of each data block. obtain a refresh task according to the refresh period of each data block and the SLC NAND running load; read valid data of a target data block according to the refresh task, perform error correction write processing on the valid data, and obtain a refresh data block.

[0007] In a second aspect, the present application provides a SLC NAND data refresh period dynamic adjustment system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method as described above when executing the program.

[0008] In a third aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein the program is executable by a processor to implement the method as described above.

[0009] Compared with the prior art, the present application has the following beneficial effects: (1) The present application obtains running state data of each data block of SLC NAND, performs block time sequence association processing on the running state data to obtain a block-level state sequence, performs data retention capability evaluation according to the block-level state sequence to obtain a retention margin sequence, so that the threshold voltage state and error correction state of each data block at different sampling time points can be uniformly represented, avoiding the judgment of data retention capability only according to the number of erasing and writing times or a single detection parameter, and providing a continuous and physically meaningful state basis for subsequent block-based determination of the refresh period.

[0010] (2) The present application obtains the current retention margin and the degradation rate by performing degradation trend evaluation according to the retention margin sequence, performs residual time evaluation according to the current retention margin, the degradation rate, and the safe retention margin to obtain the safe retention time length of each data block, and determines the refresh period of each data block according to the safe retention time length, so that the refresh period can be adjusted according to the change of the data retention capability of different data blocks, thereby avoiding the problems of refresh lag of data blocks with low retention capability and early refresh of data blocks with high retention capability caused by using a unified refresh period.

[0011] (3) The present application obtains a refresh task by performing refresh scheduling according to the refresh period of each data block and the SLC NAND running load, reads valid data of a target data block according to the refresh task, performs error correction write processing and read-back verification on the valid data, and obtains a refresh data block, so that the refresh operation can be executed in an orderly manner in combination with the running state of the storage medium, and correctable errors can be corrected and write results can be verified during data migration, thereby reducing data read abnormalities caused by continuous degradation of data blocks and improving the data retention reliability of SLC NAND during long-term operation. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a method for dynamically adjusting the data refresh cycle of SLC NAND provided in the first embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Reference Figure 1 The first embodiment of the present invention provides a method for dynamically adjusting the data refresh cycle of SLC NAND, comprising the following steps: S1, obtain the running status data of each data block of SLC NAND, and perform block-level time sequence association processing on the running status data to obtain the block-level status sequence; S2, perform data retention capability assessment based on the block-level state sequence to obtain a retention margin sequence, and perform degradation trend assessment based on the retention margin sequence to obtain the current retention margin and degradation rate; S3, based on the current holding margin, the degradation rate and the preset safe holding margin, the remaining time is evaluated to obtain the safe holding time of each data block, and the refresh cycle is determined according to the safe holding time of each data block to obtain the refresh cycle of each data block. S4, obtain the SLC NAND operating load, and perform refresh scheduling according to the refresh cycle of each data block and the SLC NAND operating load to obtain refresh tasks; S5: Read the valid data of the target data block according to the refresh task, perform error correction and writing processing on the valid data, and obtain the refresh data block.

[0015] In step S1, the running status data of each data block of the SLC NAND is obtained, and the running status data is processed by block-level time sequence association to obtain a block-level status sequence, including: Read the data block identifier, sampling time, most recent programming time, erase / write count, temperature record, cumulative read count, error correction count and threshold voltage status recorded by the SLC NAND controller to obtain the operating status data; The running status data is grouped according to the data block identifier to obtain block status data groups; The block state data set is time-sequentially arranged according to the sampling time, to obtain a block-level state sequence.

[0016] In an implementation, the data block identifier is a unique number assigned to a physical data block by an SLC NAND controller, and the SLC NAND controller generates the data block identifier according to a channel number, a chip selection number, a die number, a plane number and a block number, and writes the data block identifier into a block management table. For the same physical data block, the data block identifier remains unchanged before the physical data block enters a bad block table.

[0017] The sampling time is a system clock value read by the SLC NAND controller when forming a block state record, and the most recent programming time is a system clock value recorded when the corresponding data block last completed valid data writing. After the SLC NAND controller returns a success flag in a programming status register, the current system clock value is written into a most recent programming time field in the block management table. After data refresh of the data block, a time when refresh data writing is completed constitutes the most recent programming time of the corresponding refresh data block.

[0018] The erase-write count is a number of times of cumulative completion of erase operations of the corresponding data block, and the SLC NAND controller increases the erase-write count of the corresponding data block in the block management table once after returning a success flag in a data block erase status register. The erase-write count is not increased when erase fails, and the corresponding data block is written into a to-be-detected block list.

[0019] The cumulative read count is a number of page read commands received by the corresponding data block since the most recent programming time, and the SLC NAND controller increases the cumulative read count once after issuing a page read command to the corresponding data block. A multiple-page read command is cumulatively counted according to an actual number of read pages. After re-writing of the data block, the cumulative read count of the refresh data block is recorded from zero.

[0020] The temperature record is a sequence of temperature readings recorded by the SLC NAND controller between adjacent sampling times, and the temperature readings are output by an internal temperature detection unit of the SLC NAND chip. When the SLC NAND chip is not provided with the internal temperature detection unit, the temperature readings are output by a temperature detection unit close to the SLC NAND package. Each temperature reading contains a temperature value and a temperature collection time. The SLC NAND controller associates the data blocks in the same chip with the temperature readings in the same time interval to form the temperature record of the corresponding data block.

[0021] The temperature recording interval of this embodiment is set to 60 seconds, which is determined by an offline temperature playback test. The offline temperature playback test uses 30 seconds, 60 seconds and 120 seconds as candidate recording intervals respectively, and the equivalent time length formed by 1 second temperature record is taken as a control result. After playing back the temperature curve for 72 consecutive hours, the cumulative equivalent time length deviation corresponding to the 30-second candidate recording interval is 0.3%, the cumulative equivalent time length deviation corresponding to the 60-second candidate recording interval is 0.8%, and the cumulative equivalent time length deviation corresponding to the 120-second candidate recording interval is 2.1%. The longest candidate recording interval with a cumulative equivalent time length deviation of not more than 1% is selected, and the temperature recording interval of 60 seconds is obtained.

[0022] The error correction count is the maximum number of corrected bits reported by the error correction unit when the SLC NAND controller reads the corresponding data block in a sampling period. When reading the data block, the SLC NAND controller determines the valid pages according to the page validity flag in the logical-physical mapping table and reads all valid pages. For each error correction group in each valid page, the error correction unit outputs the corresponding number of corrected bits. The SLC NAND controller selects the maximum value from the number of corrected bits corresponding to all error correction groups in all valid pages, and writes the maximum value into the error correction count field corresponding to the sampling time. The page validity flag in the logical-physical mapping table represents that the corresponding physical page currently carries valid logical data.

[0023] The threshold voltage state is the threshold voltage distribution boundary state of the valid pages in the corresponding data block, which is indirectly represented by the read reference voltage. The SLC NAND controller calls the read retry instruction supported by the SLC NAND device, reads the valid pages in turn according to the read reference voltage level recorded by the device parameter page, and records the number of corrected bits corresponding to each read reference voltage level. For the same valid page, the read reference voltage corresponding to the minimum number of corrected bits is selected to obtain the page threshold voltage state; when there are multiple read reference voltages with the same number of corrected bits, the read reference voltage with the minimum distance from the nominal read reference voltage is selected. The SLC NAND controller selects the page threshold voltage state closest to the read reference boundary from the page threshold voltage states of all valid pages as the threshold voltage state of the corresponding data block.

[0024] It should be noted that this embodiment performs running state sampling on data blocks carrying valid data. The idle data blocks in the erase state do not form block state records; the data blocks that have been written into the bad block table do not enter the subsequent data retention capability evaluation process.

[0025] The sampling interval of the running state data is set to 12 hours in this embodiment, which is determined by an offline retention test of the same type of SLC NAND device. The offline retention test selects 30 SLC NAND chips, and four data blocks are selected from each chip, forming a total of 120 test data blocks. The 120 test data blocks are divided into three groups according to the erase count, i.e., 0 times, 1000 times, and 3000 times, with 40 test data blocks in each group. The 1-hour sampling result is used as the control data in the test process, and 6 hours, 12 hours, and 24 hours are used as candidate sampling intervals, respectively. The relative deviation between the degradation rate corresponding to each candidate sampling interval and the control degradation rate is calculated. The median relative deviation of the 6-hour candidate sampling interval is 2.3%, the median relative deviation of the 12-hour candidate sampling interval is 4.6%, and the median relative deviation of the 24-hour candidate sampling interval is 11.8%. The longest candidate sampling interval with a median relative deviation of not more than 5% is selected, and the sampling interval of 12 hours is obtained.

[0026] When forming the running state data, the SLC NAND controller establishes a block state data group according to the data block identifier, and writes the block state records with the same data block identifier into the same block state data group. Each block state record contains a sampling time and the latest programming time, erase count, temperature record, cumulative read count, error correction count, and threshold voltage state corresponding to the sampling time.

[0027] When performing timing arrangement, the block state records in the same block state data group are arranged from early to late according to the sampling time. If there are two block state records of the same data block at the same sampling time, the block state record with a complete field and a later generation time is retained. If a certain block state record lacks error correction count or threshold voltage state, the block state record is not written into the block-level state sequence, and the actual time difference between adjacent valid block state records constitutes the sampling interval in subsequent processing.

[0028] In step S2, the data retention capability is evaluated according to the block-level state sequence to obtain a retention margin sequence, and the degradation trend is evaluated according to the retention margin sequence to obtain the current retention margin and the degradation rate.

[0029] The data retention capability is evaluated according to the block-level state sequence to obtain a retention margin sequence, including: The threshold voltage state and the error correction count are extracted from the block-level state sequence; The read reference boundary and the rated voltage margin of the SLC NAND device are read, and the error correction safety threshold configured by the SLC NAND controller is read; The minimum distance between the threshold voltage state and the read reference boundary is calculated, and the minimum distance is proportionally converted according to the rated voltage margin to obtain a voltage margin ratio; calculating an error correction margin between the error correction safety threshold and the error correction count, scaling the error correction margin according to the error correction safety threshold to obtain an error correction margin ratio; selecting a smaller value from the voltage margin ratio and the error correction margin ratio corresponding to the same sampling time as a retention margin, and arranging the retention margin according to the sampling time to obtain a retention margin sequence.

[0030] In an implementation, the read reference boundary is a nominal read reference voltage used by SLC NAND devices to distinguish between erase states and program states. The SLC NAND controller reads the nominal read reference voltage in the device parameter page during the device initialization phase, and writes the nominal read reference voltage into the controller parameter area. The read reference boundary of the present embodiment corresponding to the SLC NAND device is 1.50 volts.

[0031] The rated voltage margin is a reference distance between the program state threshold voltage distribution boundary and the read reference boundary after the data block completes programming, and is determined through initial programming calibration tests of the same type of SLC NAND device. The initial programming calibration test selects 30 SLC NAND chips, and each chip selects four data blocks that have not experienced erase-write cycles, forming a total of 120 calibration data blocks. The same pseudo-random binary sequence is written into the 120 calibration data blocks, and after completing the writing, the threshold voltage state of each calibration data block is measured by using the threshold voltage state detection method described in step S1, and the distance between each threshold voltage state and the read reference boundary is calculated. All distances are arranged in ascending order of numerical value, and the 5th percentile is selected as the rated voltage margin. The rated voltage margin obtained in the present embodiment is 0.60 volts.

[0032] The error correction safety threshold is less than the maximum error correction amount of the SLC NAND controller. The error correction safety threshold is determined through an accelerated retention test. The accelerated retention test selects 30 SLC NAND chips of the same type, and respectively performs 0, 1000 and 3000 erase-write cycles on the test data blocks. After each test data block completes programming, it is continuously placed in an environment of 55 degrees Celsius, 70 degrees Celsius and 85 degrees Celsius, and the valid data is read once every 12 hours to record the error correction count and the moment when the uncorrectable error occurs. For each test data block, the error correction count at the sampling time before the first occurrence of uncorrectable error is extracted, all extraction results are arranged in ascending order of numerical value, and the 5th percentile is selected as the error correction safety threshold. The maximum error correction amount of the present embodiment is 60 bits per error correction group, and the 5th percentile is 42 bits per error correction group, so the error correction safety threshold is set to 42 bits.

[0033] The embodiment reads the block state records in the block level state sequence one by one, and calculates the minimum distance between the threshold voltage state and the read reference boundary for any sampling time. When the threshold voltage state is on the programming state side of the read reference boundary, the minimum distance is the difference between the threshold voltage state and the read reference boundary; when the threshold voltage state has crossed the read reference boundary, the minimum distance is recorded as zero.

[0034] When the minimum distance is proportionally converted according to the rated voltage margin, the voltage margin ratio is obtained by dividing the minimum distance by the rated voltage margin. When the voltage margin ratio is greater than 1, the voltage margin ratio is recorded as 1; when the voltage margin ratio is less than 0, the voltage margin ratio is recorded as 0. After the limiting processing, the voltage margin ratio is in the closed interval of 0 to 1.

[0035] When calculating the error correction margin ratio, the error correction margin is obtained by subtracting the error correction count from the error correction safety threshold, and then dividing the error correction margin by the error correction safety threshold. When the error correction margin ratio is greater than 1, the error correction margin ratio is recorded as 1; when the error correction margin ratio is less than 0, the error correction margin ratio is recorded as 0. After the limiting processing, the error correction margin ratio is in the closed interval of 0 to 1.

[0036] It should be noted that the voltage margin ratio represents the remaining proportion of the threshold voltage state relative to the rated voltage margin, and the error correction margin ratio represents the remaining proportion of the error correction count relative to the error correction safety threshold. Both margin ratios are dimensionless values and can be compared in the same value range.

[0037] The embodiment selects the smaller value from the voltage margin ratio and the error correction margin ratio corresponding to the same sampling time, and takes the smaller value as the retention margin corresponding to the sampling time. The processing writes the state that is closer to the safety boundary earlier in the threshold voltage state and the error correction state into the retention margin. Arranging a plurality of retention margins in order of sampling time from early to late obtains a retention margin sequence.

[0038] The degradation trend evaluation according to the retention margin sequence includes: Extracting the sampling interval between adjacent sampling times from the temperature record and the block level state sequence; Reading the reference temperature and temperature acceleration parameters configured for the SLC NAND device; According to the reference temperature and the temperature acceleration parameter, the equivalent time segment is obtained by equivalently converting the sampling interval corresponding to the temperature record; According to the sampling time, the equivalent time segments are accumulated to obtain an equivalent time sequence.

[0039] In one implementation, the reference temperature is the ambient temperature corresponding to the rated hold time of the SLC NAND device. In this embodiment, the rated hold conditions recorded on the device parameter page are read, and 25 degrees Celsius is set as the reference temperature. When performing temperature calculations, the Celsius temperature is increased by 273.15 to convert it to an absolute temperature.

[0040] The temperature acceleration parameter is an activation energy parameter characterizing the relationship between temperature change and retention degradation rate, determined through accelerated retention calibration experiments. The accelerated retention calibration experiment uses the same type of SLC NAND device, recording the placement time corresponding to the retention margin decreasing to 0.2 under three temperature conditions: 55°C, 70°C, and 85°C. In this embodiment, the placement times recorded under the above three temperature conditions are 6600 hours, 2300 hours, and 900 hours, respectively. It should be noted that the aforementioned 6600 hours, 2300 hours, and 900 hours are calibration times used for linear fitting in the temperature acceleration parameter calibration experiment, while the rated retention time mentioned later is determined using the 5th percentile of all test data at each calibration temperature. The two have different uses and statistical calibers. The natural logarithm of the placement time corresponding to the three temperature conditions is calculated, and the least squares method is used to fit the linear relationship between the natural logarithm and the reciprocal of the absolute temperature. The temperature acceleration parameter is determined based on the fitting slope and Boltzmann constant. The temperature acceleration parameter obtained in this embodiment is 0.68 electron volts, and 0.68 electron volts is written into the SLC NAND controller parameter area.

[0041] Regarding the temperature record of the first For each temperature reading, the corresponding equivalent time segment is calculated according to the following formula in this embodiment: ; in, Indicates the first The equivalent time segment corresponding to each temperature reading Indicates the first The actual duration corresponding to each temperature reading Indicates the temperature acceleration parameter, Represents the Boltzmann constant. This indicates the absolute temperature corresponding to the reference temperature. Indicates the first The absolute temperature corresponding to each temperature reading. The Boltzmann constant is taken as 8.617333262 times 10 to the power of -5 electron volts per Kelvin.

[0042] When the temperature record is formed at 60-second intervals, each temperature reading corresponds to an actual duration of 60 seconds. For all temperature readings between adjacent two running state data sampling time points, the equivalent time segments are calculated respectively, and then the equivalent time segments are accumulated according to the temperature collection time points to obtain the equivalent time segment corresponding to the adjacent sampling time points. If there is an end record with a duration shorter than 60 seconds in the temperature record, the actual duration of the end record is used for conversion.

[0043] When the equivalent time segments are accumulated according to the sampling time points, the equivalent duration corresponding to the latest programming time point is recorded as zero. The equivalent duration corresponding to the first sampling time point is the accumulation value of all equivalent time segments between the latest programming time point and the first sampling time point; the equivalent duration corresponding to the second sampling time point is the accumulation value of all equivalent time segments between the latest programming time point and the second sampling time point. The subsequent sampling time points are processed in the same way to obtain the equivalent duration sequence.

[0044] Exemplarily, the actual sampling interval between certain adjacent sampling time points is 12 hours, the temperature record remains 45 degrees Celsius within the 12 hours, the reference temperature is 25 degrees Celsius, and the temperature acceleration parameter is 0.68 electron volts. According to the foregoing temperature equivalent conversion process, the temperature acceleration multiple corresponding to the 12-hour actual sampling interval is 5.28, and the equivalent time segment is 63.36 hours. When the four consecutive sampling intervals have the same temperature record, the equivalent durations of the corresponding sampling time points are 63.36 hours, 126.72 hours, 190.08 hours and 253.44 hours in turn.

[0045] The degradation trend is evaluated according to the margin sequence to obtain the current margin and the degradation rate, including: The trend fitting is performed on the margin sequence and the equivalent duration sequence to obtain a fitting slope and an end fitting value; The end fitting value is determined as the current margin; When the fitting slope is less than zero, the amplitude conversion is performed on the fitting slope to obtain the degradation rate; When the fitting slope is not less than zero, the degradation rate is determined as zero.

[0046] In an implementation manner, the margin sequence and the equivalent duration sequence are aligned according to the sampling time points in the embodiment. Each sampling time point forms a fitting data pair, the horizontal coordinate of the fitting data pair is the equivalent duration of the corresponding sampling time point, and the vertical coordinate is the margin of the corresponding sampling time point. When there is a record with inconsistent sampling time points, only the sampling time points with equivalent duration and margin are retained.

[0047] The least square method is used for trend fitting in the embodiment. Let the first fitting data pair be (x1, y1), the second fitting data pair be (x2, y2), and the fitting function be y = ax + b. The fitting function is substituted into the first fitting data pair and the second fitting data pair to obtain two equations: x1a + b = y1 and x2a + b = y2. The two equations are solved to obtain the fitting slope a and the end fitting value b. The equivalent time length in a fitting data pair is , the margin is , the number of fitting data pairs is , the average of all equivalent time lengths is , the average of all margins is , the fitting slope is , and the fitting intercept is . The fitting slope and the fitting intercept are determined according to the following formula: ; Wherein, only represents the equivalent time length at the th sampling time, only represents the margin at the th sampling time, represents the number of sampling times participating in fitting, represents the fitting slope, represents the fitting intercept.

[0048] The end fitting value is obtained by substituting the end equivalent time length in the equivalent time length sequence into the fitting straight line. When the end fitting value is less than zero, the end fitting value is recorded as zero; when the end fitting value is greater than 1, the end fitting value is recorded as 1. The end fitting value after the limiting processing constitutes the current margin.

[0049] When the fitting slope is less than zero, the fitting straight line represents that the margin decreases with the equivalent time length. The absolute value of the fitting slope is determined as the degradation rate in this embodiment. The unit of the degradation rate is the decrease of the margin per equivalent hour.

[0050] When the fitting slope is not less than zero, the fitting straight line does not represent the decrease of the margin. The degradation rate is recorded as zero in this embodiment. The case that the fitting slope is not less than zero includes the short sampling period, the threshold voltage reading fluctuation and the short-time decrease of the error correction count. The subsequent remaining time evaluation is read according to the processing branch with the degradation rate of zero for the rated retention time.

[0051] It should be noted that the initial block state record is formed immediately after the data block is programmed, and the most recent programming time is taken as the initial sampling time, and the equivalent time length is recorded as 0. The newly programmed data block starts trend fitting after forming two block state records. When there is only one block state record, the margin in the block state record is determined as the current margin, and the degradation rate is recorded as zero. After forming a new block state record, trend fitting is performed again.

[0052] Exemplarily, the equivalent time length sequence corresponding to a certain data block is 0 hour, 63.36 hours, 126.72 hours, 190.08 hours and 253.44 hours, and the corresponding margin sequence is 0.82, 0.74, 0.67, 0.59 and 0.52. After trend fitting by using the ordinary least squares method, the fitting slope is about -0.00118, and the end fitting value is about 0.52. 0.52 is determined as the current margin, and the amplitude conversion is performed on -0.00118 to obtain the degradation rate of 0.00118 per equivalent hour.

[0053] In step S3, the remaining time is evaluated according to the current margin, the degradation rate and the preset safe margin, to obtain the safe retention time length of each data block, and the refresh cycle determination processing is performed according to the safe retention time length of each data block respectively, to obtain the refresh cycle of each data block.

[0054] In step S3, the remaining time is evaluated according to the current margin, the degradation rate and the preset safe margin, to obtain the safe retention time length of each data block, and the refresh cycle determination processing is performed on each data block according to the safe retention time length of each data block respectively, to obtain the refresh cycle of the data block. The margin difference value is obtained by evaluating the margin difference between the current margin and the preset safe margin; When the margin difference value is greater than zero and the degradation rate is greater than zero, the safe retention time length of the corresponding data block is obtained by time conversion according to the margin difference value and the degradation rate; When the margin difference value is greater than zero and the degradation rate is zero, the rated retention time length of the SLC NAND device and the current system time are read, the retention time length is evaluated according to the current system time and the latest programming time, to obtain the retained time length, and the greater value is selected from the difference between the rated retention time length and the retained time length and zero, to obtain the safe retention time length of the corresponding data block; When the margin difference value is not greater than zero, the safe retention time length of the corresponding data block is determined as zero.

[0055] In an implementation manner, the preset safe margin is a lower limit value triggering the refresh cycle contraction in the process of the margin decrease. The margin is in the closed interval of zero to one, the preset safe margin adopts the same dimensionless representation manner, and the preset safe margin is determined by the accelerated retention calibration test. 120 test data blocks are selected, and the 120 test data blocks are divided into four groups with 0 times, 1000 times, 2000 times and 3000 times of erase counts, and each group contains 30 test data blocks. Half of the test data blocks in each group are selected to perform 100000 times of page reading in advance. After the programming of each test data block is completed, the test data blocks are respectively placed in the environment of 55 degrees Celsius, 70 degrees Celsius and 85 degrees Celsius, and the margin is formed every 12 hours.

[0056] For each test data block, the embodiment records the retention margin corresponding to the time point one sample before the first occurrence of uncorrectable error, and obtains 120 critical retention margins. The 120 critical retention margins are arranged in ascending order of numerical value, and the 95th percentile is taken. The 95th percentile is 0.18, the retention margin storage precision of the SLC NAND controller is 0.05, the embodiment rounds up 0.18 to the adjacent storage position to obtain 0.20, and writes 0.20 into the controller parameter area as the preset safe retention margin.

[0057] When the margin difference is evaluated, the embodiment subtracts the preset safe retention margin from the current retention margin to obtain a margin difference value. When the margin difference value is greater than zero, the current retention margin has not yet decreased to the preset safe retention margin; when the margin difference value is equal to or less than zero, the current retention margin has reached or exceeded the preset safe retention margin.

[0058] When the margin difference value is greater than zero and the degradation rate is greater than zero, the embodiment divides the margin difference value by the degradation rate to obtain a remaining equivalent time length, and divides the remaining equivalent time length by the temperature acceleration multiple corresponding to the current temperature to obtain the safe retention time length of the corresponding data block. The unit of the safe retention time length is unified as actual hours.

[0059] It should be noted that the safe retention time length represents the remaining time length corresponding to the decrease of the current retention margin to the preset safe retention margin according to the current degradation trend. The degradation rate has been obtained through the temperature equivalent processing in step S2, and the degradation rate is not repeatedly corrected according to the erase count or the cumulative read count.

[0060] When the margin difference value is greater than zero and the degradation rate is zero, the embodiment reads the rated retention time length in the SLC NAND device configuration file. The SLC NAND device configuration file is generated in the device offline calibration stage, and the corresponding rated retention time length is recorded according to the temperature interval.

[0061] In constructing the SLC NAND device profile, four calibration temperatures of 25 degrees Celsius, 55 degrees Celsius, 70 degrees Celsius and 85 degrees Celsius are adopted in this embodiment. For each calibration temperature, the time length experienced by each test data block from completing programming to the margin of retention dropping to 0.20 is recorded, and all the time lengths corresponding to the same calibration temperature are arranged in ascending order of value, and the 5th percentile is taken as the rated retention time length corresponding to the calibration temperature. In this embodiment, the rated retention time length corresponding to 25 degrees Celsius is 87600 hours, the rated retention time length corresponding to 55 degrees Celsius is 7200 hours, the rated retention time length corresponding to 70 degrees Celsius is 1440 hours, and the rated retention time length corresponding to 85 degrees Celsius is 336 hours.

[0062] When reading the rated retention time length, this embodiment reads the temperature record corresponding to the end sampling time in the block-level state sequence, and selects the minimum calibration temperature not lower than the highest temperature in the temperature record from the four calibration temperatures. When the highest temperature in the temperature record is 60 degrees Celsius, 1440 hours corresponding to 70 degrees Celsius is selected as the rated retention time length; when the highest temperature in the temperature record exceeds 85 degrees Celsius, the rated retention time length is no longer selected, and the safe retention time length of the corresponding data block is directly determined as zero.

[0063] For the running scenario of continuous power supply of the storage system, the current system time is read from the monotonic clock counter of the SLC NAND controller. The monotonic clock counter continuously increments after the controller is powered on, and does not back up with external date calibration. The latest programming time has been written in the block-level state sequence in step S1. This embodiment calculates the time difference between the current system time and the latest programming time to obtain the retention time length, and then subtracts the retention time length from the rated retention time length. When the obtained difference value is greater than zero, the difference value is determined as the safe retention time length; when the obtained difference value is not greater than zero, zero is determined as the safe retention time length. When the margin difference value is not greater than zero, this embodiment no longer performs division operation, and directly determines the safe retention time length of the corresponding data block as zero.

[0064] Among them, according to the safe retention time length of each data block, the refresh cycle determination processing is performed to obtain the refresh cycle of each data block, including: Reading the safe reduction coefficient, the cycle upper limit table and the minimum refresh cycle configured by the SLC NAND controller; Extracting the erase-write count and the cumulative read count from the block-level state sequence, and performing interval mapping in the cycle upper limit table according to the erase-write count and the cumulative read count to obtain the maximum refresh cycle of each data block; Performing cycle reduction processing on the safe retention time length of each data block according to the safe reduction coefficient to obtain the candidate refresh cycle of each data block; The candidate refresh period of each data block is compared with the corresponding maximum refresh period, and the smaller value is selected as the initial refresh period of the corresponding data block; When the initial refresh period of the corresponding data block is greater than the minimum refresh period, the initial refresh period is determined as the refresh period of the corresponding data block; when the initial refresh period of the corresponding data block is not greater than the minimum refresh period, the minimum refresh period is determined as the refresh period of the corresponding data block.

[0065] In an implementation manner, the safety reduction coefficient is a proportional parameter used when converting the safety retention time length into the candidate refresh period. In this embodiment, the safety reduction coefficient is determined based on the accelerated retention data of the 120 test data blocks. For each test data block, the predicted safety retention time length is calculated according to the current retention margin and the degradation rate at each sampling time, and the predicted safety retention time length has been converted into an actual time length. The actual safety retention time length is divided by the predicted safety retention time length to obtain a time length ratio. After deleting the records with a predicted safety retention time length of zero, all the time length ratios are arranged in ascending order of numerical value, and the 5th percentile is taken. The 5th percentile is 0.83, the SLC NAND controller supports a coefficient configuration step of 0.05, 0.83 is rounded down to 0.80 in this embodiment, and 0.80 is written into the controller parameter area as the safety reduction coefficient.

[0066] The cycle upper limit table records the corresponding relationship among the erase-write count interval, the cumulative read count interval and the maximum refresh period. When constructing the cycle upper limit table, the rated erase-write count recorded in the SLC NAND device specification is read in this embodiment. The rated erase-write count of the corresponding device in this embodiment is 3000 times, 0 to 3000 times is divided into three erase-write count intervals according to one-third of the rated erase-write count, which are 0 to 999 times, 1000 to 1999 times and 2000 to 3000 times respectively, and the cumulative read count interval is determined through a read disturbance calibration test. The read disturbance calibration test continuously performs page reading on the test data block after completing programming, and each 10000 times of reading forms an error correction count record. The relationship between the error correction count and the cumulative read count is fitted by two linear segments, and the cumulative read count corresponding to the intersection point of the two fitted straight lines is determined as the read disturbance inflection point. The median of the read disturbance inflection points corresponding to the 120 test data blocks is 98000 times, and the controller takes 10000 times as one record interval, 98000 times is rounded to 100000 times in this embodiment, and the cumulative read count interval is divided into 0 to 99999 times and not less than 100000 times.

[0067] The embodiment forms six combined intervals according to three erase-write count intervals and two cumulative read count intervals. For each combined interval, data records belonging to the corresponding combined interval in the accelerated retention test are extracted, the actual safe retention time experienced from the sampling time to the retention margin dropping to 0.20 is counted, the 5th percentile is taken, and is rounded down to an integer hour to obtain the maximum refresh period of the corresponding combined interval.

[0068] In the cycle upper limit table of the embodiment, when the erase-write count is 0 to 999 times and the cumulative read count is 0 to 99999 times, the maximum refresh period is 720 hours; when the erase-write count is 0 to 999 times and the cumulative read count is not less than 100000 times, the maximum refresh period is 480 hours; when the erase-write count is 1000 to 1999 times and the cumulative read count is 0 to 99999 times, the maximum refresh period is 480 hours; when the erase-write count is 1000 to 1999 times and the cumulative read count is not less than 100000 times, the maximum refresh period is 336 hours; when the erase-write count is 2000 to 3000 times and the cumulative read count is 0 to 99999 times, the maximum refresh period is 336 hours; and when the erase-write count is 2000 to 3000 times and the cumulative read count is not less than 100000 times, the maximum refresh period is 168 hours.

[0069] The minimum refresh period is the shortest refresh time allowed to be configured for a single data block, which is recorded by 1000 single data block refresh tests from starting to read the target data block to completing the read-back check. 1000 execution times are arranged in ascending order of value, and the 99th percentile is 43 seconds. The controller supports three background scheduling gears of 30 seconds, 60 seconds and 120 seconds, and the minimum gear not less than 43 seconds is selected in the embodiment, and 60 seconds is written into the controller parameter area as the minimum refresh period. The minimum refresh period is also used as the minimum generation interval of adjacent background refresh tasks in the embodiment, so that the previous background refresh task has an execution window not less than the 99th percentile refresh execution time.

[0070] When performing cycle reduction processing, the safe retention time of each data block is multiplied by 0.80 in the embodiment to obtain a candidate refresh period. Then, the maximum refresh period is obtained by querying the cycle upper limit table according to the erase-write count and the cumulative read count of the corresponding data block, and the smaller value is selected from the candidate refresh period and the maximum refresh period to obtain an initial refresh period. When the initial refresh period is greater than 60 seconds, the initial refresh period is determined as the refresh period in the embodiment; when the initial refresh period is not greater than 60 seconds, 60 seconds is determined as the refresh period in the embodiment. When the safe retention time is zero, the candidate refresh period is also zero, and the final refresh period is 60 seconds.

[0071] In step S4, an SLC NAND running load is acquired, refresh scheduling is performed according to the refresh period of each data block and the SLC NAND running load, and a refresh task is obtained.

[0072] In an implementation manner, the SLC NAND running load is determined by a request queue occupation ratio and a channel busy ratio. The SLC NAND controller reads the number of pending requests in the host request queue, the maximum depth of the request queue, and the busy time length of each storage channel in the previous second every 1 second.

[0073] In the embodiment, the number of pending requests is divided by the maximum depth of the request queue to obtain the request queue occupation ratio. The busy time lengths of the storage channels in the previous second are added together and then divided by the product of the number of storage channels and 1 second to obtain the channel busy ratio. The greater value is selected from the request queue occupation ratio and the channel busy ratio to obtain the SLC NAND running load. The SLC NAND running load is in the closed interval of zero to one.

[0074] It should be noted that the 1 second is a fixed period for the SLC NAND controller to update the input / output statistical register. Each time the update is performed, the controller clears the busy time length of the channel in the previous statistical period and starts to record the next statistical period.

[0075] In the embodiment, the running load threshold is set to 0.60, which is determined by the input / output request records for seven consecutive days. For adjacent two 1-second statistical periods, the positive growth amounts of the request queue occupation ratio and the channel busy ratio are calculated, and the 99th percentiles of all positive growth amounts are counted respectively. The 99th percentile of the growth amount of the request queue occupation ratio is 0.36, and the 99th percentile of the growth amount of the channel busy ratio is 0.40. In the embodiment, 0.40 is subtracted from 1 to obtain 0.60, and 0.60 is written into the controller scheduling parameter area.

[0076] In the embodiment, the refresh due time is determined according to the refresh period of the corresponding data block. Specifically, the refresh due time is obtained by adding the refresh period determination time to the refresh period. Then, the current system time is read, and the time difference between the refresh due time and the current system time is calculated to obtain the refresh remaining time length. For all data blocks carrying valid data, the refresh candidate sequence is obtained by arranging the refresh remaining time lengths in ascending order. When the refresh remaining time lengths of two data blocks are the same, the data blocks are arranged in ascending order of data block identifiers.

[0077] When the remaining refresh time of any data block is not greater than zero, the embodiment generates an emergency refresh task for the any data block, and the emergency refresh task is not limited by the running load threshold. When the remaining refresh time of any data block is greater than zero and not greater than the minimum refresh period, the embodiment compares the SLC NAND running load with 0.60. When the SLC NAND running load is not greater than 0.60, a background refresh task is generated for the any data block; when the SLC NAND running load is greater than 0.60, no background refresh task is generated in the current statistical period, and the SLC NAND running load is read again in the next statistical period. When the remaining refresh time of any data block is greater than the minimum refresh period, the embodiment does not generate a refresh task for the any data block.

[0078] The refresh task includes a task identifier, a data block identifier of a target data block, a task generation time, a refresh expiration time, and a task type, and the task type includes an emergency refresh type and a background refresh type. The task identifier is generated by incrementing a task counter of the SLC NAND controller. The task generation time is read from the current system time. When there are multiple data blocks that meet the generation condition in the same statistical period, the embodiment generates refresh tasks in turn according to a refresh candidate sequence. Only one background refresh task is allowed to be generated in the current statistical period, and the generation time interval of the background refresh task and the last background refresh task is not less than the minimum refresh period; and the emergency refresh tasks are written into a refresh queue in the order of the remaining refresh time from small to large.

[0079] The configuration that only one background refresh task is allowed to be generated in the current statistical period is determined by continuously recording and playing back requests for seven days, and the number of background refresh tasks allowed to be generated in each statistical period is set to one, two, and three respectively, and the corresponding host request 95th percentile response time is counted. When one background refresh task is allowed to be generated, the 95th percentile response time is 3.8 milliseconds; when two background refresh tasks are allowed to be generated, the 95th percentile response time is 5.6 milliseconds; and when three background refresh tasks are allowed to be generated, the 95th percentile response time is 8.9 milliseconds. The embodiment selects the task configuration with the smallest response time.

[0080] In step S5, valid data of a target data block is read according to the refresh task, error correction write processing is performed on the valid data, and a refreshed data block is obtained, including: A target data block is determined according to the refresh task, and valid data in the target data block is read; Error correction processing is performed on the valid data to obtain error correction data; Idle block migration write processing is performed on the error correction data to obtain a data block to be verified; The write data in the to-be-verified data block is read back for verification, and when the read back verification passes, the to-be-verified data block is determined as a refresh data block.

[0081] In an implementation, a data block identifier of the target data block is read from the refresh task, and the target data block is located in the block management table according to the data block identifier. Each data block record in the block management table includes a data block identifier, a physical block location, a valid page bitmap, an erase state, and a block state flag. The valid page bitmap records the valid state of each physical page in the target data block in the order of the physical pages. When the bit value is one, the corresponding physical page carries valid data; and when the bit value is zero, the corresponding physical page does not carry valid data. In this embodiment, the physical pages with the bit value of one in the valid page bitmap are read in the order from small to large physical page number, to obtain the valid data in the target data block.

[0082] When any physical page is read, the data area and the redundancy area of the any physical page are read at the same time. The redundancy area records error correction verification information, a logical page number, and a page state flag. The logical page number records the page sequence number of the data carried by the any physical page in the logical address space, and the page state flag records whether the page programming is completed.

[0083] This embodiment adopts a BCH error correction code for error correction processing. The BCH error correction code divides an error correction group according to 1024 bytes, and the maximum error correction amount of each error correction group is 60 bits. The BCH error correction configuration is determined through a raw bit error rate calibration test. When the raw bit error rate calibration test is performed, 120 test data blocks are selected, each test data block is executed to the rated number of erase and write times, and is placed in an environment of 85 degrees Celsius until the retention margin decreases to 0.20. Subsequently, all the test data blocks are read according to the 1024-byte error correction group, and the number of error bits in each error correction group is counted. All the error bit numbers are arranged in the order from small to large, and the 99.9th percentile is 48 bits. The SLC NAND controller supports three BCH error correction gears of 40 bits, 60 bits, and 80 bits, and this embodiment selects the minimum gear not less than 48 bits, and determines 60 bits as the maximum error correction amount.

[0084] When performing the error correction processing, the embodiment inputs the valid data and the corresponding error correction check information into the BCH decoder. The BCH decoder calculates the error position according to the error correction check information, and performs an inversion operation on the bit corresponding to the error position to obtain the error correction data. When one physical page contains multiple error correction groups, the error correction processing is performed in sequence according to the order of the error correction groups in the physical page. When the BCH decoder reports that any error correction group is in the uncorrectable state, the embodiment performs read retry according to the read reference voltage level used when recording the threshold voltage state in step S1. For each read reference voltage level, the corresponding physical page is re-read and BCH decoding is performed, and the read result with the minimum error correction count and without reporting the uncorrectable state is selected to obtain the error correction data. When all read reference voltage levels report the uncorrectable state, the embodiment marks the refresh task as a read failure, and does not form a data block to be checked.

[0085] When performing the idle block migration write processing, the embodiment reads the SLC NAND idle block table. The SLC NAND idle block table records the data blocks that have completed erasing and do not carry valid data according to the channel, die and plane. Each idle block record contains a data block identifier, an erasing state and a write-erase count.

[0086] The embodiment first reads the first idle block record with a normal erasing state from the SLC NAND idle block table of the plane where the target data block is located; when there is no idle block record with a normal erasing state in the plane where the target data block is located, the first idle block record with a normal erasing state is read from other planes of the die where the target data block is located. When there is no idle block record with a normal erasing state in the die where the target data block is located, the embodiment performs the garbage collection process of the flash translation layer, and reselects after a new idle block record is written into the SLC NAND idle block table.

[0087] After selecting the erased idle data block, the embodiment arranges the error correction data according to the logical page number of the valid page in the target data block in ascending order. For each page of error correction data, the corresponding BCH error correction check information is regenerated, and the error correction data, the BCH error correction check information, the logical page number and the page state flag are written into the erased idle data block.

[0088] After each page is written, the embodiment reads the SLC NAND state register. When the state register reports a successful programming, the next page is written; when the state register reports a programming failure, the current erased idle data block is marked as an abnormal programming data block, the next idle block record with a normal erasing state is read from the SLC NAND idle block table, and the idle block migration write processing is re-executed.

[0089] When all valid data in the target data block is written and all page status registers report successful programming, the embodiment determines the corresponding erased free data block as the to-be-verified data block.

[0090] When performing the readback verification, the embodiment reads all written data in the to-be-verified data block in ascending order of logical page number and performs BCH decoding on the readback data. For the same logical page number, the embodiment compares the data read back and corrected with the error correction data before writing byte by byte. When the data corresponding to all logical page numbers are consistent and the BCH decoder does not report an uncorrectable state, it is determined that the readback verification is passed, and the to-be-verified data block is determined as the refreshed data block.

[0091] When the data corresponding to any logical page number is inconsistent, or the BCH decoder reports an uncorrectable state, the embodiment determines that the readback verification is failed, and marks the to-be-verified data block as a verification abnormal data block. Then, the next free block record with a normal erase state is read from the SLC NAND free block table, and the free block migration write processing and readback verification are re-executed. When there is no free block record with a normal erase state in the SLC NAND free block table, the embodiment marks the refresh task as a write failure.

[0092] It is worth noting that the target data block remains in the valid state before the to-be-verified data block passes the readback verification, and the valid data in the target data block is not subjected to erasing processing. After the to-be-verified data block passes the readback verification, the logical-physical mapping table is updated to point to the refreshed data block, the corresponding data in the target data block is marked as invalid, and the cumulative read count of the refreshed data block is cleared and the latest programming time is recorded.

[0093] For example, the target data block in a refresh task is identified as 1024, and the target data block contains 128 physical pages, of which 96 bits in the valid page bitmap are one. The data area of each physical page is 4096 bytes, corresponding to four BCH error correction groups of 1024 bytes. After reading 96 valid pages, the maximum number of error bits reported by the BCH decoder is 18 bits per error correction group, which does not exceed the maximum error correction amount of 60 bits. After the embodiment completes the error correction processing, an erased free data block with a data block identifier of 2048 is selected from the plane where the target data block is located, and the 96 pages of error correction data are written to the erased free data block to obtain a to-be-verified data block. During the readback verification process, the 96 pages of readback data are consistent with the corresponding error correction data byte by byte, and the BCH decoder does not report an uncorrectable state. The embodiment determines the to-be-verified data block with a data block identifier of 2048 as a refreshed data block.

[0094] To sum up, the application obtains the running state data of each data block of the SLC NAND, forms a block-level state sequence arranged according to data blocks and sampling time, determines a retention margin sequence, a current retention margin and a degradation rate according to the block-level state sequence, combines the safe retention margin to determine the safe retention time and the refresh cycle of each data block, generates a refresh task according to the refresh cycle and the running load of the SLC NAND, performs error correction, migration writing and read-back verification on the effective data of the target data block, and obtains a refreshed data block, so that the refresh cycle of each data block of the SLC NAND is adjusted respectively according to the data retention capability.

[0095] The second embodiment of the application provides a SLC NAND data refresh cycle dynamic adjustment system, which comprises a memory, a processor and a computer program stored in the memory and capable of running on the processor, and the processor implements the method as described above when executing the program.

[0096] It should be noted that the SLC NAND data refresh cycle dynamic adjustment system provided by the embodiments of the application is used to execute all process steps of the SLC NAND data refresh cycle dynamic adjustment method of the above embodiments, and the working principles and beneficial effects of the two are one-to-one corresponding, thus no longer being described in detail.

[0097] It should be noted that the system embodiments described above are only schematic, wherein the units described as separate components can or can not be physically separated, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. According to actual needs, part or all of the modules can be selected to achieve the purpose of the embodiments of the present application. Those skilled in the art can understand and implement without creative labor.

[0098] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the application. It should be understood that the above description is only for specific embodiments of the application and is not used to limit the protection scope of the application. It is particularly pointed out that any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principle of the application should be included in the protection scope of the application.

Claims

1. A method for dynamically adjusting the data refresh cycle of an SLC NAND flash memory, characterized in that, include: Obtain the running status data of each data block of SLC NAND, and perform block-level time sequence association processing on the running status data to obtain the block-level status sequence; The data retention capability is evaluated based on the block-level state sequence to obtain a retention margin sequence, and the degradation trend is evaluated based on the retention margin sequence to obtain the current retention margin and degradation rate. The remaining time is evaluated based on the current hold margin, the degradation rate, and the preset safety hold margin to obtain the safety hold duration of each data block. The refresh cycle is then determined based on the safety hold duration of each data block to obtain the refresh cycle of each data block. Obtain the SLC NAND operating load, and perform refresh scheduling based on the refresh cycle of each data block and the SLC NAND operating load to obtain refresh tasks; The refresh task reads the valid data of the target data block, performs error correction and write processing on the valid data, and obtains the refresh data block.

2. The method for dynamically adjusting the SLC NAND data refresh cycle according to claim 1, characterized in that, The process involves acquiring the operational status data of each data block in the SLC NAND, performing block-level time-series correlation processing on the operational status data to obtain a block-level status sequence, including: Read the data block identifier, sampling time, most recent programming time, erase / write count, temperature record, cumulative read count, error correction count and threshold voltage status recorded by the SLC NAND controller to obtain the operating status data; The running status data is grouped according to the data block identifier to obtain block status data groups; The block state data group is arranged in time sequence according to the sampling time to obtain the block-level state sequence.

3. The method for dynamically adjusting the SLC NAND data refresh cycle according to claim 2, characterized in that, The step of evaluating data retention capability based on the block-level state sequence to obtain a retention margin sequence includes: Extract the threshold voltage state and the error correction count from the block-level state sequence; Read the read reference boundary and rated voltage margin of the SLC NAND device, and read the error correction safety threshold configured by the SLC NAND controller; Calculate the minimum distance between the threshold voltage state and the reading reference boundary, and proportionally convert the minimum distance to the rated voltage margin to obtain the voltage margin ratio. Calculate the error correction margin between the error correction safety threshold and the error correction count, and perform a proportional conversion between the error correction margin and the error correction safety threshold to obtain the error correction margin ratio; The smaller value is selected from the voltage margin ratio and the error correction margin ratio corresponding to the same sampling time as the holding margin, and the holding margins are arranged according to the sampling time to obtain the holding margin sequence.

4. The method for dynamically adjusting the SLC NAND data refresh cycle according to claim 2, characterized in that, The degradation trend assessment based on the preservation margin sequence includes: Extract the temperature record and the sampling interval between adjacent sampling times from the block-level state sequence; Read the reference temperature and temperature acceleration parameters configured for the SLC NAND device; Based on the reference temperature and the temperature acceleration parameters, the sampling interval corresponding to the temperature record is equivalently converted to obtain an equivalent time segment. The equivalent time segments are accumulated according to the sampling time to obtain the equivalent duration sequence.

5. The method for dynamically adjusting the SLC NAND data refresh cycle according to claim 4, characterized in that, The step of evaluating the degradation trend based on the preservation margin sequence to obtain the current preservation margin and degradation rate includes: Trend fitting is performed on the maintenance margin sequence and the equivalent duration sequence to obtain the fitting slope and terminal fitting value; The end-fit value is determined as the current holding margin; When the fitted slope is less than zero, the fitted slope is converted to an amplitude to obtain the degradation rate. When the fitting slope is not less than zero, the degradation rate is determined to be zero.

6. The method for dynamically adjusting the SLC NAND data refresh cycle according to claim 2, characterized in that, The remaining time assessment based on the current hold margin, the degradation rate, and the preset safety hold margin to obtain the safety hold duration for each data block includes: The margin difference between the current holding margin and the preset safety holding margin is evaluated to obtain the margin difference value; When the margin difference is greater than zero and the degradation rate is greater than zero, time conversion is performed based on the margin difference and the degradation rate to obtain the safe retention time of the corresponding data block; When the margin difference is greater than zero and the degradation rate is zero, read the rated hold duration and the current system time of the SLC NAND device, perform a duration evaluation based on the current system time and the most recent programming time to obtain the held duration, and select the larger value from the difference between the rated hold duration and the held duration and zero to obtain the safe hold duration of the corresponding data block. When the margin difference is not greater than zero, the safe retention time of the corresponding data block is determined to be zero.

7. The method for dynamically adjusting the SLC NAND data refresh cycle according to claim 2, characterized in that, The process of determining the refresh cycle based on the security retention time of each data block to obtain the refresh cycle of each data block includes: Read the safety reduction factor, cycle limit table, and minimum refresh cycle configured in the SLC NAND controller; The erase / write count and the cumulative read count are extracted from the block-level state sequence. The erase / write count and the cumulative read count are then mapped to intervals in the cycle upper limit table to obtain the maximum refresh cycle for each data block. The security retention time of each data block is periodically reduced based on the security reduction factor to obtain the candidate refresh period for each data block; Compare the candidate refresh cycles of each data block with the corresponding maximum refresh cycle, and select the smaller value as the initial refresh cycle of the corresponding data block; When the initial refresh period of the corresponding data block is greater than the minimum refresh period, the initial refresh period is determined as the refresh period of the corresponding data block; when the initial refresh period of the corresponding data block is not greater than the minimum refresh period, the minimum refresh period is determined as the refresh period of the corresponding data block.

8. The method for dynamically adjusting the SLC NAND data refresh cycle according to claim 1, characterized in that, The step of reading valid data from the target data block according to the refresh task, performing error correction and writing processing on the valid data to obtain the refresh data block includes: The target data block is determined according to the refresh task, and the valid data in the target data block is read. The valid data is subjected to error correction processing to obtain error-corrected data; The error correction data is processed by free block migration and writing to obtain the data block to be verified; The written data in the data block to be verified is read back for verification. When the read back verification passes, the data block to be verified is determined as a refresh data block.

9. A dynamic adjustment system for SLC NAND data refresh cycle, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method described in any one of claims 1 to 8.

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