A one-time programmable read-write circuit, method and apparatus

Abstract

The application discloses a one-time programmable read-write circuit, method and device, which comprises a level conversion module, a clock module, a digital logic module and a fuse storage module; the input end of the level conversion module is connected with a VDD pin serving as a power voltage input and an encoding signal input; the output end of the level conversion module is connected with the data input end of the digital logic module; the clock module comprises a built-in clock and an external clock; the built-in clock comprises a relaxation oscillator, the enable end of the relaxation oscillator is connected with an EN pin serving as an enable control pin, the output end of the relaxation oscillator is connected with the clock input end of the digital logic module, the input end of the external clock is connected with an external clock pin, and the output end of the external clock is connected with the clock input end of the digital logic module; by introducing the relaxation oscillator circuit as a clock source, the difficulty of chip integration and power consumption are reduced.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a one-time programmable read / write circuit, method, and apparatus. Background Technology

[0002] One-time programmable memory (OTP) is widely used in programmable chips to store critical information such as calibration data, encryption information, firmware data, and license data. In the field of sensor chips, because the measured objects such as temperature, pressure, humidity, magnetic field, and current are easily affected by ambient temperature and wafer processing errors, the chip must integrate compensation circuits and storage modules to complete parameter calibration. Therefore, the low-cost, easy-to-operate, and small-area OTP read / write mechanism has become an important component of sensor chips.

[0003] However, technicians believe that the existing OTP read / write mechanism has the following shortcomings: the oscillation circuit used in the OTP read / write mechanism is difficult to integrate into the chip, and the oscillation circuit occupies a large chip area and consumes a lot of power, resulting in an increase in the overall chip power consumption. Summary of the Invention

[0004] This invention provides a one-time programmable read / write circuit, method, and apparatus. By introducing a relaxation oscillation circuit as a clock source, it overcomes the shortcomings of oscillation circuits in related technologies, such as high chip integration difficulty and high power consumption, thereby reducing chip integration difficulty and power consumption.

[0005] This invention provides a one-time programmable read / write circuit, including a level conversion module, a clock module, a digital logic module, and a fuse storage module; The input terminal of the level conversion module is connected to the VDD pin, which serves as both a power supply voltage input and an encoding signal input. The output terminal of the level conversion module is connected to the data input terminal of the digital logic module. The level conversion module is used to convert the voltage pulse signal input on the VDD pin into a digital encoding signal and output it to the digital logic module. The clock module includes a built-in clock for generating internal clock signals and outputting them to the digital logic module, and an external clock for receiving external clock signals and outputting them to the digital logic module. The built-in clock includes a relaxation oscillator. The enable terminal of the relaxation oscillator is connected to the EN pin, which serves as an enable control pin. The output terminal of the relaxation oscillator is connected to the clock input terminal of the digital logic module. The input terminal of the external clock is connected to an external clock pin, which serves as an external clock input pin. The output terminal of the external clock is connected to the clock input terminal of the digital logic module. The control output terminal of the digital logic module is connected to the control terminal of the fuse storage module, and outputs control signals to the fuse storage module according to the digital encoding signal, the internal clock signal and the external clock signal.

[0006] Optionally, the level conversion module includes a Zener diode, an NPN transistor, a Schmitt inverter, and a first current bias. The cathode of the Zener transistor is connected to the VDD pin, the anode of the Zener transistor is connected to the base of the NPN transistor and one end of the resistor R, and the other end of the resistor R and the emitter of the NPN transistor are grounded. The collector of the NPN transistor is connected to one end of the first current bias and the input of the Schmitt inverter, and the other end of the first current bias is connected to the power supply. The first current bias is used to provide bias current for the level conversion module. The output of the Schmitt inverter is the output of the level conversion module.

[0007] Optionally, the relaxor oscillator includes a second current bias for charging the oscillation capacitor with a constant current under the control of the EN pin, a first comparator, a first inverter, and a second inverter; The enable terminal of the second current bias is connected to EN, the output terminal of the second current bias is connected to the non-inverting input terminal of the first comparator, one end of the oscillation capacitor is connected to the non-inverting input terminal of the first comparator, and the other end of the oscillation capacitor is grounded. The output of the first comparator is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is the output of the relaxation oscillator.

[0008] Optionally, the relaxor oscillator further includes a first NMOS transistor and a second NMOS transistor; The first NMOS transistor is used to turn on when the second inverter outputs a high level to discharge the oscillation capacitor. The gate of the first NMOS transistor is connected to the output terminal of the second inverter, the drain of the first NMOS transistor is connected to the non-inverting input terminal of the first comparator, and the source of the first NMOS transistor is grounded. The second NMOS transistor is used to turn on when the first inverter outputs a high level, pulling the inverting input of the first comparator low to switch the comparison threshold. The gate of the second NMOS transistor is connected to the output of the first inverter, the drain of the second NMOS transistor is connected to the inverting input of the first comparator, and the source of the second NMOS transistor is grounded. The first inverter and the second inverter shape the level signal output by the first comparator and output an internal clock signal.

[0009] Optionally, the fuse storage module includes a data storage unit and a storage unit control circuit; The data storage unit includes a fuse bit group; The control terminal of the storage unit control circuit is connected to the control output terminal of the digital logic module. The storage unit control circuit is connected to the fuse bits in the fuse bit group. It is used to selectively allow a large current to flow through the corresponding fuse bit under the control of the control signal to perform programming operations, and to read the status of the fuse bit as configuration information output.

[0010] Optionally, the fuse bit group includes 20 data fuse bits and 1 lock fuse bit; The memory cell control circuit includes a second comparator corresponding to each fuse bit, a fuse programming switch, a first resistor, a second resistor, and a third current bias; One end of each fuse bit is connected to the VDD pin, and the other end is connected to the non-inverting input of the corresponding second comparator, one end of the corresponding first resistor, and one end of the corresponding fuse programming switch. The other end of the first resistor is connected to the inverting input terminal of the corresponding second comparator and one end of the corresponding second resistor, and the other end of the second resistor is grounded; The output of the second comparator is the data output of the fuse storage module, which is used to output the read fuse status as configuration information. The control terminal of the fuse programming switch is connected to the control output terminal of the digital logic module. The other terminal of the fuse programming switch is connected to one terminal of the corresponding third current bias, and the other terminal of the third current bias is grounded. The fuse programming switch is used to conduct under the control of the control signal, so that a large current flows through the corresponding fuse bit to perform the programming operation.

[0011] A one-time programmable read / write method includes the following steps: The voltage pulse signal input to the VDD pin is converted into a digitally encoded signal after level conversion; An internal clock signal is generated by the built-in clock, and an external clock signal is connected through the external clock pin. The digital coded signal is sampled and latched under the control of the internal clock signal and the external clock signal, and the working mode is switched according to the latched opcode; The control signal is output to the fuse storage module according to the working mode.

[0012] Optionally, after outputting a control signal to the fuse storage module according to the operating mode, the following steps are included: Control the fuse storage module to perform programming and reading; The fuse storage module outputs the read fuse status as configuration information.

[0013] Optional operating modes include pre-programming mode, programming mode, lock mode, and read mode; In pre-programming mode, the configuration data in the digitally encoded signal is stored in the internal latch without burning out the data fuse bits, supporting multiple writes and modifications; In programming mode, the corresponding data fuse bit is burned off according to the data in the internal latch; In locked mode, the lock fuse bit is burned, after which only read operations are allowed.

[0014] Compared with the prior art, the beneficial effects of the present invention are: This invention generates an internal clock signal by using a built-in clock including a relaxation oscillator. The relaxation oscillator has a simple structure, does not require an external crystal oscillator, and is easy to integrate into a chip, reducing the difficulty of chip integration and power consumption, and overcoming the shortcomings of existing oscillator circuits, which are difficult to integrate and have high power consumption. Attached Figure Description

[0015] Figure 1 This is a circuit block diagram of the first embodiment of the present invention.

[0016] Figure 2 This is a circuit diagram of the level conversion module according to the first embodiment of the present invention.

[0017] Figure 3 This is a clock circuit diagram of the relaxation oscillator according to the first embodiment of the present invention.

[0018] Figure 4 This is a fuse circuit diagram of the first embodiment of the present invention.

[0019] Figure 5 This is a schematic diagram of the digital programming process according to the first embodiment of the present invention.

[0020] Figure 6 This is a timing diagram of VDD signal latching for the unprogrammed state, pre-programmed state, programming state, and locked state in the first embodiment of the present invention.

[0021] Figure 7 This is a circuit layout of the second embodiment of the present invention.

[0022] Figure 8 This is a schematic diagram of the host computer read / write mechanism and experimental device according to the third embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] It should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Similarly, words such as "a" or "one" do not indicate a quantity limitation, but rather indicate the presence of at least one; "multiple" indicates two or more. Unless otherwise stated, words such as "before," "after," "below," and / or "above" are for illustrative purposes only and are not limited to a location or spatial orientation.

[0025] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0027] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0028] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical terms such as "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0029] One-Time Programmable Memory (OTP) is used in programmable chips to store critical information such as calibration data, encryption information, firmware data, and license data. The low-cost, easy-to-operate, and small-area OTP read / write mechanism is often used in sensor chips because the objects measured by sensor chips (such as temperature, pressure, humidity, magnetic field, and current) are easily affected by temperature and wafer fabrication errors, requiring embedded compensation circuits and storage modules for calibration. OTPs mainly include fuse-type, floating-gate type, and OTP ROM: floating-gate OTPs are more expensive and have the risk of leakage, suitable for high-density data storage scenarios; OTPs have extremely high data stability but the data cannot be rewritten after leaving the factory, suitable for fixed programs; fuse-type OTPs offer stable data and low cost, and can be programmed after leaving the factory, thus becoming the main storage unit of sensor chips.

[0030] A fuse-type OTP consists of a fuse unit, a programming module, a reading module, and control logic. The fuse unit is usually a thin wire made of chip metal layer (such as aluminum wire) or polysilicon. The cross-sectional area of ​​the fuse part is small, and it will break when a large current passes through it. The programming module is responsible for applying current to the fuse unit to "burn out" the fuse and realize the write operation. The reading module detects the status of the fuse unit (whether it is open) and converts the physical connection status into a digital logic signal (0 or 1) for other modules of the chip to read. The control logic manages the read and write operations of the fuse OTP and controls the process of address selection, execution of programming commands, and data output.

[0031] Mixed-signal design is a technique that integrates digital and analog circuits on a single wafer to achieve complex electronic functions with high performance and low power consumption. The design of a fuse-type OTP requires both digital logic for timing control of programming and reading, and analog circuitry for controlling the fuse's breaking current and detecting its status; therefore, a mixed-signal design is necessary.

[0032] To this end, this application designs and manufactures a mixed-signal memory circuit device based on a fuse-type OTP. In accordance with the mixed-signal design, the fuse-type OTP read module is developed based on the fabless model of BCD process. The OTP system is designed and simulated, focusing on the functional integrity and timing of its read and write operations. The simulation results, layout and experimental device are presented.

[0033] Fabless refers to a fabless model that only designs and sells chips and does not participate in manufacturing. BCD refers to a wafer foundry process that integrates three types of devices on a single wafer using a super-integrated gate process. OTP refers to one-time programmable memory.

[0034] First Embodiment Please refer to Figure 1 This embodiment provides a one-time programmable read / write circuit.

[0035] This invention provides a one-time programmable read / write circuit, including a level conversion module, a clock module, and a digital logic module (equivalent to...). Figure 1 (Digital logic section) and fuse storage module; The input terminal of the level conversion module is connected to the VDD pin, which serves as both the power supply voltage input and the encoding signal input. The output terminal of the level conversion module is connected to the data input terminal of the digital logic module. The level conversion module is used to convert the voltage pulse signal input on the VDD pin into a digital encoding signal and output it to the digital logic module. The advantage of this setup is that the VDD pin simultaneously serves as both power supply and encoding signal input, eliminating the need for a separate programming data input pin. This reduces the number of chip pins, simplifies the chip's peripheral interface circuitry, and lowers chip packaging costs and application complexity.

[0036] The clock module includes a built-in clock for generating internal clock signals and outputting them to the digital logic module, and an external clock for receiving external clock signals and outputting them to the digital logic module. For example, when the one-time programmable read / write circuit is in normal operating mode, the built-in clock is always oscillating, providing an internal clock signal for the digital logic module. In programming mode, coded data is transmitted to an external clock signal via an external clock pin, and the digital logic module simultaneously uses the internal clock signal for signal sampling. The built-in clock and the external clock are not mutually exclusive; they coexist and work together. Normal operating mode refers to the state where the chip performs regular functions after programming; programming mode refers to the state where the fuse bits are programmed and written.

[0037] The built-in clock includes a relaxation oscillator. The enable terminal of the relaxation oscillator is connected to the EN pin, which serves as the enable control pin. The output terminal of the relaxation oscillator is connected to the clock input terminal of the digital logic module. The input terminal of the external clock is connected to the external clock pin, which serves as the external clock input pin. The output terminal of the external clock is connected to the clock input terminal of the digital logic module. The control output terminal of the digital logic module is connected to the control terminal of the fuse storage module, and outputs control signals to the fuse storage module according to the digital encoding signal, the internal clock signal and the external clock signal.

[0038] Specifically, under the control of internal and external clock signals, the digital logic module samples and latches the digital encoded signal output by the level conversion module, then switches the operating mode according to the latched opcode, and outputs the corresponding control signal to the fuse storage module. Here, sampling refers to reading and holding the level of the digital encoded signal at a specific edge of the clock signal (such as the rising edge); latching refers to temporarily storing the sampled data in an internal latch until updated in the next sampling cycle; and the opcode refers to a specific bit sequence in the digital encoded signal used to indicate the operating mode.

[0039] For example, the input signal reuses the VDD power supply pin, which normally operates at 4.5V to 5.5V. Programming is achieved by inputting a signal higher than 6.2V. The module enable pin EN is activated by grounding the VREF pin; that is, when the VREF pin is grounded, the EN pin is active, and the one-time programmable read / write circuit enters the programming state. The external clock for the one-time programmable read / write circuit uses a 4MHz chip global clock. The chip global clock refers to the reference clock signal uniformly provided internally by the chip and used by all functional modules. An internally integrated gated clock provides asynchronous timing for the digital logic module. The gated clock refers to a clock signal whose on / off state is controlled by an enable signal, and the clock output is only turned on when needed to reduce power consumption. The fuse bit integrates a fuse unit, programming, and reading functions, supporting burn-out and read operations when the digital logic module is enabled. The fuse unit refers to the physical structure in the fuse bit that achieves data storage by burning out the fuse with a large current. The 1-bit lock fuse bit is a lock bit. When set to 1, the one-time programmable read / write circuit enters a locked state, allowing only read operations to prevent misprogramming. Setting it to 1 means burning out the fuse bit, resulting in a logic high level "1" for the read result. When the VDD pin voltage is between 4.5V and 5.5V, it is the normal power supply signal; when the VDD pin voltage is 6.2V, it is the input signal for communication programming. After the lock fuse bit is burned out, the PRGON_EN enable signal (equivalent to the control signal output by the digital logic module) is set to low, and other data fuse bits are locked, prohibiting programming operations. A high level refers to a voltage state above the logic threshold, corresponding to logic "1"; a low level refers to a voltage state below the logic threshold, corresponding to logic "0".

[0040] The advantages of this setup are that it enables single-pin power supply and data transmission through VDD pin multiplexing, meets the timing requirements of different modes through the coordinated operation of the built-in clock and the external clock, and achieves programming protection through the locking fuse bit. The overall circuit structure is simple, highly integrated, and has low power consumption, and effectively prevents misprogramming, thereby improving the security and reliability of data storage.

[0041] Please refer to Figure 2 In some implementations, the level shifting module includes a Zener diode, an NPN transistor, a Schmitt inverter, and a first current bias. The cathode of the Zener transistor is connected to the VDD pin, the anode of the Zener transistor is connected to the base of the NPN transistor and one end of the resistor R, and the other end of the resistor R is grounded to the emitter of the NPN transistor. The collector of the NPN transistor is connected to one end of the first current bias and the input of the Schmitt inverter, and the other end of the first current bias is connected to the power supply. The first current bias is used to provide bias current for the level conversion module. The output of the Schmitt inverter is the output of the level conversion module.

[0042] For example, the inputs of the level shifting module include VDD, ground, and a first current bias provided by the embedded power supply. The output signal is Y_otp (equivalent to a digitally encoded signal), which functions to output a high level "1" when the VDD voltage is higher than a threshold and a low level "0" when it is lower than the threshold. Select according to requirements... Figure 2 The level conversion circuit shown has a Zener diode with a forward voltage of 5.5V. A Zener diode is a diode that breaks down and conducts when the reverse voltage reaches a specific value; its forward voltage is its breakdown voltage. When VDD is greater than the sum of the Zener diode voltage and the base-emitter voltage threshold of the NPN transistor (V_Zener + V_th_NPN), the collector voltage of the NPN transistor is pulled low to ground. Conversely, when VDD is lower than this threshold, the collector voltage is pulled high by the first current bias. An NPN transistor is a bipolar transistor that conducts when its base voltage is higher than the emitter voltage by a threshold, resulting in a low-resistance state between the collector and emitter. To enhance signal stability, a Schmitt trigger inverter is connected after the NPN collector. A Schmitt trigger inverter is an inverter with hysteresis; its input threshold changes with the output level, filtering out noise and jitter in the input signal. This level conversion module is used for signal conversion of VDD.

[0043] Please refer to Figure 3 In some implementations, the relaxor oscillator includes a second current bias for charging the oscillation capacitor with a constant current under the control of the EN pin, a first comparator, a first inverter, and a second inverter. The enable terminal of the second current bias is connected to EN, the output terminal of the second current bias is connected to the non-inverting input terminal of the first comparator, one end of the oscillation capacitor is connected to the non-inverting input terminal of the first comparator, and the other end of the oscillation capacitor is grounded. The output of the first comparator is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is the output of the relaxation oscillator.

[0044] For example, a relaxor oscillator, used as a clock source, has the advantages of simple design, low resource consumption, low power consumption, and high stability, providing a 4MHz clock for a one-time programmable read / write circuit. The relaxor oscillator circuit shown in Figure 3 is selected. This module has a gating function, and the clock signal output can be controlled by controlling the bias current switch through an enable signal. Its circuit principle formula is as follows:

[0045] In the formula: The oscillation period; and These are the upper and lower comparison potentials, respectively; For oscillation; This is the bias current. The oscillator generates a stable oscillation signal by charging and discharging a capacitor at a constant rate and comparing the capacitor voltage with a reference voltage. The oscillation period refers to the time required for the oscillator to complete one full charge-discharge cycle; the comparison potential refers to the input voltage threshold corresponding to the flip of the first comparator.

[0046] The advantage of this setup is that the relaxor oscillator does not require an external crystal or resonant component. It can achieve a stable clock output simply through current bias, capacitors, and comparators. The circuit structure is simple, the chip integration is easy, and the power consumption is low. Furthermore, the clock can be flexibly controlled to turn on and off through the EN pin, which further reduces the system power consumption.

[0047] In some implementations, the relaxor oscillator further includes a first NMOS transistor (NMOS1) and a second NMOS transistor (NMOS2); The first NMOS transistor is used to turn on when the second inverter outputs a high level to discharge the oscillation capacitor. The gate of the first NMOS transistor is connected to the output terminal of the second inverter, the drain of the first NMOS transistor is connected to the non-inverting input terminal of the first comparator, and the source of the first NMOS transistor is grounded. The second NMOS transistor is used to turn on when the first inverter outputs a high level, pulling the inverting input of the first comparator low to switch the comparison threshold. The gate of the second NMOS transistor is connected to the output of the first inverter, the drain of the second NMOS transistor is connected to the inverting input of the first comparator, and the source of the second NMOS transistor is grounded. Specifically, when the second NMOS transistor is off, the inverting input of the first comparator is at a high level; when the second NMOS transistor is on, the inverting input of the first comparator is pulled low to ground, and the comparison threshold switches from high to low. An NMOS transistor is an N-channel metal-oxide-semiconductor field-effect transistor. It conducts when the gate voltage is higher than the source voltage by a threshold value, resulting in a low-resistance state between the drain and source. Off means the gate voltage is insufficient to turn the transistor on, resulting in a high-resistance state between the drain and source.

[0048] The first and second inverters shape the level signal output by the first comparator and output the internal clock signal.

[0049] For example, by alternately turning the first NMOS transistor and the second NMOS transistor on and off, the voltage of the oscillation capacitor is made to fluctuate between the high and low threshold values ​​of the first comparator, and the first comparator outputs a continuously toggling level signal accordingly. Alternating on and off means that the first NMOS transistor and the second NMOS transistor are in the on and off states at different times, and will not be on simultaneously.

[0050] The advantage of this setup is that the first NMOS transistor enables the rapid discharge of the oscillation capacitor, and the second NMOS transistor switches the comparison threshold, allowing the relaxor oscillator to generate a clock signal with a stable duty cycle and accurate frequency. Furthermore, the circuit structure is simple and requires no additional complex control logic, thus improving the stability and reliability of the clock output.

[0051] Please refer to Figure 4 In some implementations, the fuse storage module includes a data storage unit and a storage unit control circuit; The data storage unit includes a fuse bit group; The control terminal of the storage unit control circuit is connected to the control output terminal of the digital logic module. The storage unit control circuit is connected to the fuse bits in the fuse bit group. It is used to selectively make the corresponding fuse bit flow with a large current under the control of the control signal to perform programming operations, and read the status of the fuse bit as configuration information output.

[0052] For example, the fuse memory module (equivalent to an efuse unit) is the core memory unit of a one-time programmable read / write circuit, storing binary data through two states: the fuse bit is burned out and it is not burned out. The data storage unit stores the fuse bit group, and the memory unit control circuit selects a specific fuse bit for programming or reading operations based on the control signals output by the digital logic module. The configuration information refers to the data read from the fuse bit used for chip function configuration, including calibration parameters, encryption information, firmware configuration, etc.

[0053] In some implementations, the fuse bit group includes 20 data fuse bits and 1 lock fuse bit; The memory cell control circuit includes a second comparator corresponding to each fuse bit, a fuse programming switch, a first resistor (resistor R1), a second resistor (resistor R2), and a third current bias; One end of each fuse bit is connected to the VDD pin, and the other end is connected to the non-inverting input of the corresponding second comparator, one end of the corresponding first resistor, and one end of the corresponding fuse programming switch. The other end of the first resistor is connected to the inverting input terminal of the corresponding second comparator and one end of the corresponding second resistor, and the other end of the second resistor is grounded. The output of the second comparator is the data output of the fuse storage module, which is used to output the read fuse status as configuration information. The control terminal of the fuse programming switch is connected to the control output terminal of the digital logic module. The other terminal of the fuse programming switch is connected to one terminal of the corresponding third current bias, and the other terminal of the third current bias is grounded. The fuse programming switch is used to conduct under the control of the control signal, so that a large current flows through the corresponding fuse position to perform the programming operation.

[0054] For example, in read mode, an unburned fuse exhibits a low resistance of approximately tens of ohms, causing the comparator output to be "0"; a burned fuse has a resistance of approximately hundreds of thousands of ohms, causing the comparator output to be "1". By adjusting the resistance values ​​of the first resistor (resistor R1) and the second resistor (resistor R2), the fuse burning determination threshold can be optimized. The determination threshold refers to the voltage critical point at which the second comparator distinguishes between the burned and unburned states of the fuse. All fuses are in an unburned state at the factory, and the stored signal is initialized to 0; when a "1" signal needs to be written, an enable signal is input to the PROG_EN port (equivalent to the control signal output by the digital logic module), causing the fuse unit to burn under a large current. Read mode refers to the operating mode that only reads the fuse bit state without programming.

[0055] A one-time programmable read / write method includes the following steps: The voltage pulse signal input to the VDD pin is converted into a digitally encoded signal after level conversion; An internal clock signal is generated by the built-in clock, and an external clock signal is connected through the external clock pin. The system samples and latches digitally encoded signals under the control of internal and external clock signals, and switches the operating mode according to the latched opcode. The control signal is output to the fuse storage module according to the working mode.

[0056] For example, after the chip is powered on, the user can establish communication with the one-time programmable read / write circuit through a host computer, inputting programming instructions into the chip via voltage pulses on the VDD pin. The host computer refers to an external computer or debugging device used to control and configure the chip. Under the coordinated control of internal and external clock signals, the digital logic module samples and latches the digitally encoded signal converted from the voltage pulses bit by bit, parses the opcode to determine the current operating mode, and then outputs the corresponding control signals to the fuse storage module.

[0057] In some implementations, after outputting a control signal to the fuse storage module according to the operating mode, the steps include: Control the fuse storage module to perform programming and reading; The fuse storage module outputs the read fuse status as configuration information.

[0058] Please refer to Figure 5 In some implementations, the operating modes include pre-programming mode, programming mode, lock mode, and read mode; In pre-programming mode, the configuration data in the digitally encoded signal is stored in the internal latch without burning out the data fuse bits, supporting multiple writes and modifications; In programming mode, the corresponding data fuse bit is burned off according to the data in the internal latch; In locked mode, the lock fuse bit is burned, after which only read operations are allowed.

[0059] For example, users can establish communication with the one-time programmable read / write circuit via a host computer to write programming instructions into the chip's internal storage circuit. The one-time programmable read / write circuit provides a pre-programming function, supporting multiple signal storage and modification by the user. After signal storage is completed, parameters such as output zero point, output reference voltage, and magnetic sensitivity are tested and calibrated to meet specifications. Here, output zero point refers to the sensor's output voltage value at zero input; output reference voltage refers to the reference voltage used for signal comparison and calibration within the chip; and magnetic sensitivity refers to the change in output voltage corresponding to a unit change in the Hall sensor's magnetic field. After debugging, the chip enters programming mode, and the final signal is written by burning the fuse. After programming, the chip enters a locked mode, burning the internal locking fuse. From this point on, the chip can no longer enter pre-programming or programming states, ensuring the stored content is unchangeable.

[0060] Please refer to Figure 6 In one implementation, after the chip is powered on, the user sequentially writes a 25-bit control code into the chip via a host computer. This control code serves as the chip's control parameters, determining the chip's factory configuration. Among these, a 5-bit opcode is used to determine the operating mode of the efuse unit (equivalent to a fuse memory module), namely "01100" pre-programming mode, "00110" programming mode, and "10111" lock mode. When the chip receives an opcode other than these, the efuse unit will remain in read mode until a new valid opcode is received. The control code refers to a complete sequence of programming instructions containing the opcode and configuration data; a bit is the smallest unit of binary data, taking the value "0" or "1".

[0061] The internal logic circuit (equivalent to the digital logic module) only starts working after the VREF voltage is pulled low. The 25-bit control code sent by the host computer is shaped into a Y_otp signal (equivalent to a digital encoded signal) through the VDD voltage pulse. The digital signals "0" and "1" are represented by the duration and level of the level, respectively. The sampling clock CLK_smp is generated by the built-in clock (relaxation oscillator). The sampling clock CLK_smp is a clock signal generated by the internal oscillator to sample the input data. After the reset signal completes the initialization of the one-time programmable read / write circuit, CLK_smp will work in the form of a periodic cyclic pulse, sampling the Y_otp signal on the rising edge and storing it in 25 consecutive latches (Da_latch[24:0]) (equivalent to internal latches). Each sampling cycle stores 1 bit of signal. Among them, the reset signal is the control signal used to restore the circuit to the initial state; the rising edge is the moment when the clock signal jumps from low level to high level.

[0062] After the external input signal enters the circuit, it is latched, manifested as a single-pulse signal CLK_latch. CLK_latch is the latch trigger signal generated after the external input signal enters the circuit and is latched. This signal ensures that the internal storage circuit can completely save the operation code sent by the host computer. Using the rising edge of CLK_latch, the data in the 25 latches is latched to the data bus (Da_out[24:0]) (equivalent to the internal data bus) at once. After sampling, the VREF voltage is pulled high, the programming circuit stops working, and the programming process ends. Among them, the latch trigger signal is the pulse signal used to trigger the internal latches to output data to the data bus; the data bus is the common signal line used to transmit data between various functional modules.

[0063] In mixed-signal design, to reproduce the process of the 25-bit control code sent by the host computer being shaped into a Y_otp signal by the VDD voltage pulse and stored in Da_out[24:0], we established a joint simulation environment for digital and analog signals. The analog part includes level conversion, clock, fuse bits, bandgap reference power supply, and current bias, accurately simulating the transient voltage changes under actual power supply. The digital part uses timing logic to describe the level and duration of the Y_otp signal, realizing the encoding of "0" and "1" codes. Among them, mixed-signal design refers to a chip design method that includes both analog and digital circuits; bandgap reference power supply refers to a circuit that uses the bandgap voltage characteristics of semiconductor materials to generate a stable reference voltage that is independent of temperature; joint simulation refers to a method of co-verifying analog and digital circuits in the same simulation environment.

[0064] Second Embodiment Please refer to Figure 7 Unlike the first embodiment, this embodiment utilizes mature PDK components such as NMOS, PMOS, capacitors, resistors, NPN, and Zener to design a Poly Fuse cell. The layout is compact, with an overall area of ​​only 400μm × 200μm. The layout and routing are calculated using a foundry-specific algorithm, ultimately generating a photomask with over twenty layers for chip fabrication. Here, PDK stands for Process Design Kit, a set of design tools provided by the foundry that includes device models, design rules, and layout libraries; PMOS is a P-channel metal-oxide-semiconductor field-effect transistor; a Poly Fuse cell refers to a fuse memory cell made of polysilicon, which stores data by burning out the polysilicon fuse with a large current; layout and routing refers to the process of arranging and connecting components and interconnects in the circuit at the chip's physical layer according to design rules; a photomask is a mask used in chip lithography, containing graphic information of each circuit layer; and chip fabrication refers to the process of delivering the designed layout to the foundry for chip production.

[0065] Third Embodiment Please refer to Figure 7Unlike the first embodiment, this embodiment sets up a host computer read / write experimental device after chip packaging to test the OTP function and batch configure chip calibration data. During the programming process, the host computer inputs a preset format data waveform to the VDD port while simultaneously monitoring the output voltages of the VOUT and VREF ports in real time. An oscilloscope is used to observe the changes in the VDD waveform, and a current source applies a current of a specified amplitude to the module. Here, chip packaging refers to the process of wrapping the manufactured chip die with packaging material and leading out the pins; calibration data refers to the configuration data used to calibrate the chip's performance parameters; the VOUT port is the chip's voltage output port; the VREF port is the chip's reference voltage port; an oscilloscope is a measuring instrument used to observe the waveform of an electrical signal changing over time; and a current source is a power supply device capable of providing a stable output current.

[0066] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0067] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A one-time programmable read / write circuit, characterized in that, include: Level conversion module, clock module, digital logic module, and fuse storage module; The input terminal of the level conversion module is connected to the VDD pin, which serves as both a power supply voltage input and an encoding signal input, and the output terminal of the level conversion module is connected to the data input terminal of the digital logic module. The clock module includes a built-in clock and an external clock. The built-in clock includes a relaxation oscillator, the enable terminal of which is connected to the EN pin, which serves as an enable control pin, and the output terminal of which is connected to the clock input terminal of the digital logic module. The input terminal of the external clock is connected to an external clock pin, and the output terminal of the external clock is connected to the clock input terminal of the digital logic module. The control output terminal of the digital logic module is connected to the control terminal of the fuse storage module, and outputs control signals to the fuse storage module according to the digital encoding signal, the internal clock signal and the external clock signal.

2. The one-time programmable read / write circuit according to claim 1, characterized in that, The level conversion module includes a Zener diode, an NPN transistor, a Schmitt inverter, and a first current bias. The cathode of the Zener transistor is connected to the VDD pin, the anode of the Zener transistor is connected to the base of the NPN transistor and one end of the resistor R, and the other end of the resistor R and the emitter of the NPN transistor are grounded. The collector of the NPN transistor is connected to one end of the first current bias and the input of the Schmitt inverter, and the other end of the first current bias is connected to the power supply. The first current bias is used to provide bias current for the level conversion module. The output of the Schmitt inverter is the output of the level conversion module.

3. The one-time programmable read / write circuit according to claim 1, characterized in that, The relaxor oscillator includes a second current bias for charging the oscillation capacitor with a constant current under the control of the EN pin, a first comparator, a first inverter, and a second inverter. The enable terminal of the second current bias is connected to EN, the output terminal of the second current bias is connected to the non-inverting input terminal of the first comparator, one end of the oscillation capacitor is connected to the non-inverting input terminal of the first comparator, and the other end of the oscillation capacitor is grounded. The output of the first comparator is connected to the input of the first inverter, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is the output of the relaxation oscillator.

4. The one-time programmable read / write circuit according to claim 3, characterized in that, The relaxation oscillator also includes a first NMOS transistor and a second NMOS transistor; The first NMOS transistor is used to turn on when the second inverter outputs a high level to discharge the oscillation capacitor. The gate of the first NMOS transistor is connected to the output terminal of the second inverter, the drain of the first NMOS transistor is connected to the non-inverting input terminal of the first comparator, and the source of the first NMOS transistor is grounded. The second NMOS transistor is used to turn on when the first inverter outputs a high level, pulling the inverting input of the first comparator low to switch the comparison threshold. The gate of the second NMOS transistor is connected to the output of the first inverter, the drain of the second NMOS transistor is connected to the inverting input of the first comparator, and the source of the second NMOS transistor is grounded. The first inverter and the second inverter shape the level signal output by the first comparator and output an internal clock signal.

5. The one-time programmable read / write circuit according to claim 1, characterized in that, The fuse storage module includes a data storage unit and a storage unit control circuit; The data storage unit includes a fuse bit group; The control terminal of the storage unit control circuit is connected to the control output terminal of the digital logic module. The storage unit control circuit is connected to the fuse bits in the fuse bit group. It is used to selectively allow a large current to flow through the corresponding fuse bit under the control of the control signal to perform programming operations, and to read the status of the fuse bit as configuration information output.

6. The one-time programmable read / write circuit according to claim 5, characterized in that, The fuse bit group includes 20 data fuse bits and 1 lock fuse bit; The memory cell control circuit includes a second comparator corresponding to each fuse bit, a fuse programming switch, a first resistor, a second resistor, and a third current bias; One end of each fuse bit is connected to the VDD pin, and the other end is connected to the non-inverting input of the corresponding second comparator, one end of the corresponding first resistor, and one end of the corresponding fuse programming switch. The other end of the first resistor is connected to the inverting input terminal of the corresponding second comparator and one end of the corresponding second resistor, and the other end of the second resistor is grounded; The output of the second comparator is the data output of the fuse storage module, which is used to output the read fuse status as configuration information. The control terminal of the fuse programming switch is connected to the control output terminal of the digital logic module, and the other terminal of the fuse programming switch is connected to one terminal corresponding to the third current bias, and the other terminal of the third current bias is grounded.

7. A one-time programmable read / write method, characterized in that, An application of a one-time programmable read / write circuit according to any one of claims 1-6 includes the following steps: The voltage pulse signal input to the VDD pin is converted into a digitally encoded signal after level conversion; An internal clock signal is generated by the built-in clock, and an external clock signal is connected through the external clock pin. The digital coded signal is sampled and latched under the control of the internal clock signal and the external clock signal, and the working mode is switched according to the latched opcode; The control signal is output to the fuse storage module according to the working mode.

8. The one-time programmable read / write method according to claim 7, characterized in that, After outputting control signals to the fuse storage module according to the operating mode, the following steps are included: Control the fuse storage module to perform programming and reading; The fuse storage module outputs the read fuse status as configuration information.

9. A one-time programmable read / write method according to claim 7 or 8, characterized in that, The operating modes include pre-programming mode, programming mode, lock mode, and read mode; In pre-programming mode, the configuration data in the digitally encoded signal is stored in the internal latch without burning out the data fuse bits, supporting multiple writes and modifications; In programming mode, the corresponding data fuse bit is burned off according to the data in the internal latch; In locked mode, the lock fuse bit is burned, after which only read operations are allowed.

10. A one-time programmable read / write device, characterized in that, This includes a one-time programmable read / write method as described in claims 7-9.

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