Data processing method and memory

Abstract

The application discloses a data processing method and a memory. The memory comprises a plurality of memory rows, each memory row comprising a row of memory cells connected with a word line. The data processing method comprises the following steps: storing the same data in at least two memory rows, applying a turn-on voltage to at least one word line, and applying a reading voltage to a plurality of word lines. The data in the plurality of memory cells can be read synchronously by the same bit line. Even if some memory cells are defective, the bit line can still read the correct data in the memory cells without defects, so that the readout error of the data is reduced, and the robustness of the memory cells is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, specifically to a data processing method and a memory. Background Technology

[0002] Memory typically consists of a memory array, and as the area of ​​the memory array increases, the probability of defects also increases.

[0003] When information is stored in a defective location, it is prone to read errors, thereby reducing the robustness of the storage unit. Summary of the Invention

[0004] This application provides a data processing method and a memory to alleviate the technical problem of low robustness of memory cells.

[0005] In a first aspect, this application provides a data processing method for a memory, the memory including multiple storage rows, each storage row including a row of storage cells connected to a word line, the data processing method including: storing the same data into at least two storage rows; applying an on-state voltage to at least one word line; and applying a read-state voltage to the multiple word lines.

[0006] Secondly, this application provides a memory that performs the above-described data processing method.

[0007] The data processing method and memory provided in this application enable the same bit line to simultaneously read data from multiple memory cells by storing the same data in at least two memory lines, applying a conduction voltage to at least one word line, and applying a read voltage to multiple word lines. Even if some memory cells are defective, the bit line can still read the correct data from memory cells that are not defective, thereby reducing data read errors and improving the robustness of the memory cells. Attached Figure Description

[0008] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 This is a schematic diagram of the structure of a memory in related technologies.

[0010] Figure 2 This is a schematic diagram of the structure of a storage block in related technologies.

[0011] Figure 3 This is a schematic diagram of a first type of data processing method provided in an embodiment of this application.

[0012] Figure 4 This is a schematic diagram of the structure of the configuration data provided in the embodiments of this application.

[0013] Figure 5 This is a schematic diagram of a first structure for a read operation provided in an embodiment of this application.

[0014] Figure 6 This is a schematic diagram of a second structure for the read operation provided in an embodiment of this application.

[0015] Figure 7 This is a schematic diagram of a third structure for the read operation provided in an embodiment of this application.

[0016] Figure 8 This is a schematic diagram of the fourth structure for the read operation provided in the embodiments of this application.

[0017] Figure 9 This is a fifth structural diagram of the read operation provided in the embodiments of this application.

[0018] Figure 10 This is a second flowchart illustrating the data processing method provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features thus defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more unless otherwise explicitly specified.

[0021] Figure 1 This is a schematic diagram of the structure of a memory in the related art. The memory is exemplarily a NAND flash memory, which includes a storage array 10, a data buffer 20, and a configuration register 30. The storage array 10 is connected to the data buffer 20; the data buffer 20 is connected to the configuration register 30 to store data from the data buffer 20 into the configuration register 30; the data buffer 20 is connected to an input / output interface (IO) to enable data interaction with the outside world.

[0022] The storage array 10 includes one or more storage blocks, such as BLK0, BLK1...BLKn. For example, flash memory is erased in units of storage blocks (BLK). There are usually multiple word lines (WL) connected to the same storage block, such as 32, 64, 128... The number of bit lines (BL) corresponding to each word line is usually multiple. For example, the number of bit lines (BL) corresponding to each word line can be 2KB, 8KB, 16KB... etc., where 1KB equals 1024 lines.

[0023] The specific structure of the storage block is as follows: Figure 2 As shown, it includes multiple transistors connected to the string select line SSL and bit lines, multiple memory cells connected to word lines, and multiple transistors connected to the select line GSL and the common-source line CSL. Bit lines include, for example, BL0, BL1, BL2...BLm-2, BLm-1, and BLm. Word lines include, for example, WL0, WL1, WL2, WL3, WL4...WLk...WLn-2, ​​WLn-1, and WLn. In some embodiments, the select line GSL is grounded.

[0024] In some embodiments, the flash memory needs to be configured with configuration data such as bandgap reference (BG), charge pump (PUMP), X-repair, Y-repair, and bad blocks (BB), which are typically stored in configuration register 30.

[0025] Configuration register 30 loses its information upon power-down; therefore, the configuration data needs to be stored in a suitable location before shipment. Figure 1 The data in the flash memory storage cell shown (the data will not be lost after the cell is powered off) is read from the cell and stored in the configuration register 30 when the cell is powered on.

[0026] However, the storage array 10 has a very large area, which makes it prone to defects during manufacturing. When the configuration data is stored in a defective location, it will cause errors in reading the configuration data, reduce the robustness of the configuration data, and also reduce the yield.

[0027] Please see Figures 1 to 10 The memory may include multiple storage rows, each storage row including a row of storage cells connected to a word line, such as a row of storage cells connected to WL0, a row of storage cells connected to WL1, ... a row of storage cells connected to WLn.

[0028] This embodiment provides a data processing method for a memory, such as... Figure 3 As shown, the data processing method includes the following steps:

[0029] Step S10: Store the same data into at least two storage rows.

[0030] Step S20: Apply an on-state voltage to at least one word line and apply a read-state voltage to multiple word lines.

[0031] It is understood that the data processing method provided in this embodiment, by storing the same data in at least two storage lines, applying a conduction voltage to at least one word line, and applying a read voltage to multiple word lines, enables the same bit line to simultaneously read data from multiple storage cells. Even if some storage cells are defective, the bit line can still read the correct data from the storage cells that are not defective, thereby reducing data read errors and improving the robustness of the storage cells.

[0032] It should be noted that the on-state voltage is applied to the word line containing the unselected memory cell to ensure that the unselected memory cell is fully conductive, forming a current path so that the state of the selected memory cell can be accurately detected through the bit line. The read-state voltage is applied to the word line containing the selected memory cell to determine the state of the selected memory cell.

[0033] Figure 4 This is a schematic diagram of the configuration data provided in an embodiment of this application. The data is divided into a first data block A and a second data block B. A first marker code is set in the data header of the first data block A, and a first check code is set in the data tail of the first data block A. The first check code is obtained by encoding the first data block A, thereby forming a first data group A1. A second marker code is set in the data header of the second data block B, and a second check code is set in the data tail of the second data block B. The second check code is obtained by encoding the second data block B, thereby forming a second data group B1. The first marker code and the second marker code can be preset.

[0034] In some embodiments, the data divided into a first data block A and a second data block B is configuration data.

[0035] In some embodiments, word lines include first-type word lines and third-type word lines, and multiple storage rows include first-type storage rows for storing first-type data and third-type storage rows for storing third-type data. Each first-type storage row is connected to a first-type word line, and each third-type storage row is connected to a third-type word line. The data processing method further includes: applying an on-state voltage to the third-type word lines and applying a read-state voltage to the multiple first-type word lines.

[0036] It should be noted that, in this embodiment, the first type of storage line may store alternating first data group A1 and second data group B1, or it may store alternating second data group B1 and first data group A1. In some embodiments, the third type of storage line and the third type of word line are optional.

[0037] In some embodiments, word lines include first-type word lines and second-type word lines, and multiple memory rows include first-type memory rows and second-type memory rows, each first-type memory row being connected to a first-type word line, and each second-type memory row being connected to a second-type word line. The data processing method further includes: applying an on-state voltage to one of the first-type word lines and the second-type word lines, and applying a read-state voltage to the other of the multiple first-type word lines and the second-type word lines.

[0038] It should be noted that multiple Class 1 storage rows can be adjacent or non-contiguous. Multiple Class 2 storage rows can be adjacent or non-contiguous.

[0039] like Figure 4 As shown, each first type of storage row stores alternating first data group A1 and second data group B1, and each second type of storage row stores alternating second data group B1 and first data group A1. In some embodiments, if the first data group A1 and second data group B1 are configuration data, they need to be stored in storage array 10 before leaving the factory. In other embodiments, if the first data group A1 and second data group B1 are user data, there is no need to restrict when they are stored in storage array 10.

[0040] in, Figure 4 Each first checksum in the data block is not necessarily the same; it is calculated based on each data block. The same applies to the second checksum. Each first checksum can be equal, and each second checksum can be equal.

[0041] Figure 5 This is a schematic diagram of a first structure for a read operation provided in an embodiment of this application. The storage rows connected to WL0, WL2, WL4...WLn-2 and WLn can be exemplarily classified as first-type storage rows, each storing a first data group A1 and a second data group B1 that alternate sequentially. The storage rows connected to WL1, WL3, WLk...WLn-1 can be exemplarily classified as second-type storage rows, each storing a second data group B1 and a first data group A1 that alternate sequentially.

[0042] By applying a read voltage (Vread) to WL0 and applying a conduction voltage (Vpass) to other word lines such as WL1, WL2, WL3, WL4...WLk...WLn-2, ​​WLn-1 and WLn, the data in the memory line connected to WL0 can be read and stored in the data buffer 20 via the bit lines BL0, BL1, BL2...BLm-2, BLm-1 and BLm.

[0043] In some embodiments, the first type of storage row can be an even-numbered storage unit, and the second type of storage row can be an odd-numbered storage unit.

[0044] Figure 6 This is a schematic diagram of a second structural representation of a read operation provided in an embodiment of this application. Figure 5 The difference is that by applying a read voltage (Vread) to WL0, WL2, WL4...WLn-2 and WLn, and applying a conduction voltage (Vpass) to other word lines such as WL1, WL3, WLk...WLn-1, the data in each memory row connected to WL0, WL2, WL4...WLn-2 and WLn can be read and stored in the data buffer 20 via the bit lines BL0, BL1, BL2...BLm-2, BLm-1 and BLm.

[0045] from Figure 6 As can be seen, the data in multiple storage cells in the first column of storage cells from left to right, connected to WL0, WL2, WL4...WLn-2 and WLn, represents 1 bit of data read from BL0. This ensures the correctness of the read data even if some of these storage cells are defective, thus improving the robustness of the storage cells.

[0046] In related technologies, data is read from only one storage unit at a time. If this data changes, the current reading will change significantly, resulting in incorrect data being read.

[0047] In this embodiment, the storage cells in even-numbered rows of the first column store the same data. In this case, multiple identical data are read simultaneously from multiple series-connected storage cells. Even if some data changes due to the aforementioned defects, the change in read current is minimal because the data is series-connected, thus ensuring the accuracy of the read data.

[0048] The aforementioned defect refers to a situation where the data stored in the memory cell has changed, and the memory cell is turned on when an on-state voltage is applied, rather than turned off.

[0049] Figure 7 This is a schematic diagram of a third structure for a read operation provided in an embodiment of this application. Figure 6 The difference is that by applying a conduction voltage (Vpass) to WL0, WL2, WL4...WLn-2 and WLn, and applying a read voltage (Vread) to other word lines such as WL1, WL3, WLk...WLn-1, the data in each memory line connected to WL1, WL3, WLk...WLn-1 can be read and stored in the data buffer 20 via the bit lines BL0, BL1, BL2...BLm-2, BLm-1 and BLm.

[0050] from Figure 7 As can be seen, the data in multiple storage cells in the first column of storage cells from left to right, connected to WL1, WL3, WLk...WLn-1, represents 1 bit of data read from BL0. This ensures the correctness of the read data even if some of these storage cells are defective, thus improving the robustness of the storage cells.

[0051] Figure 8 This is a fourth structural diagram of the read operation provided in the embodiments of this application. The storage rows connected to WL0, WL1, and WL2 can be exemplary first-type storage rows, each storing a first data group A1 and a second data group B1 alternately. The storage rows connected to WLn-2, ​​WLn-1, and WLn can be exemplary second-type storage rows, each storing a second data group B1 and a first data group A1 alternately. The storage rows connected to third-type word lines, such as WL3, WL4...WLk, can be exemplary third-type storage rows, which can be used to store user data other than configuration data.

[0052] By applying a conduction voltage (Vpass) to WL0, WL1, WL2, WL3, WL4...WLk and a read voltage (Vread) to WLn-2, ​​WLn-1, and WLn, the data in each storage row connected to WLn-2, ​​WLn-1, and WLn can be read and stored in the data buffer 20 via bit lines (BL0, BL1, BL2...BLm-2, BLm-1, and BLm).

[0053] from Figure 8 As can be seen, the data in multiple storage cells in the first column of storage cells from left to right, connected to WLn-2, ​​WLn-1, and WLn, represents 1 bit of data read from BL0. This ensures the correctness of the read data even if some of these storage cells are defective, thus improving the robustness of the storage cells.

[0054] Figure 9 This is a schematic diagram of a fifth structure for a read operation provided in an embodiment of this application. Figure 8 The difference is that by applying a read voltage (Vread) to WL0, WL1, and WL2, and applying a conduction voltage (Vpass) to WL3, WL4...WLk...WLn-2, ​​WLn-1, and WLn, the data in each storage row connected to WL0, WL1, and WL2 can be read and stored in the data buffer 20 via bit lines (BL0, BL1, BL2...BLm-2, BLm-1, and BLm).

[0055] from Figure 9 As can be seen, the data in multiple storage cells in the first column of storage cells from left to right, connected to WL0, WL1, and WL2, represents 1 bit of data read from BL0. This ensures the correctness of the read data even if some of these storage cells are defective, thus improving the robustness of the storage cells.

[0056] In summary, the memory cell connected to the word line to which the on-state voltage (Vpass) is applied can act as a transmission tube. As the number of word lines to which the on-state voltage (Vpass) is applied increases, not only can the resistance on the corresponding bit line be reduced, but also the number of word lines to which the read voltage (Vread) is applied is reduced.

[0057] In some embodiments, the data processing method further includes: reading at least one first data group A1 and at least one second data group B1 to a data buffer 20; searching for the correct first data block A and a second data block B from the data buffer 20; and storing the correct first data block A and a second data block B to a configuration register 30.

[0058] It should be noted that as the number of first data groups A1 and second data groups B1 read increases, the correctness of the read data can be further ensured, thereby improving the robustness of the storage unit.

[0059] In some embodiments, searching for the correct first data block A and second data block B from the data buffer 20 includes the following steps:

[0060] like Figure 10 As shown, the system starts upon power-on, resetting the first status code (A_PASS=0) and the second status code (B_PASS=0).

[0061] The determination result of whether a read voltage is applied to multiple Class 1 word lines. That is, Figure 10 The determination of whether WL is even can be exemplified as follows: Figures 5 to 9 In the series WL0, WL2, WL4...WLn-2 and WLn, the odd WL can be exemplarily represented as: Figures 5 to 9 WL1, WL3, WLk...WLn-1.

[0062] Based on the judgment result, the first status code, and the second status code, the correct first data block A and the correct second data block B are searched. Due to potential defects, some first data blocks A and / or second data blocks B may have been read incorrectly from the storage array 10. Therefore, storing multiple first data blocks A and multiple second data blocks B in the data buffer 20 can increase the chance of finding the correct first data block A and the correct second data block B.

[0063] In some embodiments, searching for the correct first data block A and a second data block B based on the judgment result, the first status code, and the second status code includes: determining the first status code and the second status code based on the judgment result; and searching for the correct first data block A and a second data block B according to the first status code and the second status code.

[0064] It should be noted that in this embodiment, the correct first data block A and second data block B can be searched based on the judgment result, which simplifies the processing flow.

[0065] In some embodiments, determining a first status code and a second status code based on the judgment result includes: determining a first status code based on the judgment result and the verification result of the first data group A1; and determining a second status code based on the judgment result and the verification result of the second data group B1.

[0066] It should be noted that the verification results are used to determine whether the corresponding data group has been affected by the defect and an error has occurred.

[0067] In some embodiments, a first status code is determined based on the judgment result and the verification result of the first data group A1, such as... Figure 10 As shown, it includes the following steps:

[0068] If the judgment result indicates that multiple first-class word lines have been subjected to reading voltage, or if the second tag code is incorrect, or if the first status code is equal to the data "0", then the first tag code is read.

[0069] Determine if the first marker code is correct.

[0070] It should be noted that both the first and second marker codes are used to improve the speed of finding the correct first data block A and second data block B, thereby reducing search time. In other words, if either the first or second marker code is incorrect, the processing of the current data group will be abandoned, and processing will proceed to the next data group.

[0071] If the first tag code is correct, then the first data block A and the first check code are read, and the first calculated check code of the first data block A is calculated. The first calculated check code is obtained by encoding the first data block A stored in the data buffer 20.

[0072] Determine if the first calculated checksum is equal to the first checksum. This can be used to verify whether the first data block A has been corrupted due to a defect.

[0073] If the first calculated check code equals the first check code, then the first status code is determined to be data "1". The fact that the first calculated check code equals the first check code indicates that no error has occurred in the first data block A. At this point, the first marker code, the first data block A, and the first check code in the first data group A1 have all passed the verification, indicating that a correct first data block A has been found.

[0074] In some embodiments, based on a first status code and a second status code, the correct first data block A and a second data block B are searched, such as... Figure 10 As shown, it includes the following steps:

[0075] After determining that the first status code is data "1", or after the first calculated check code is not equal to the first check code, determine whether the second status code is equal to data "1".

[0076] If the second status code equals the data "1", then it is determined that the correct first data block A and second data block B have been found.

[0077] The second status code equals "1", indicating that the correct second data block B has been found. Since the search target has been completed, power-on can be terminated.

[0078] In some embodiments, a second status code is determined based on the judgment result and the verification result of the second data group B1, such as... Figure 10 As shown, it includes the following steps:

[0079] If the judgment result indicates that no reading voltage has been applied to multiple first-class word lines, or if the first tag code is incorrect, or if the second status code is equal to the data "0", then read the second tag code.

[0080] Determine if the second marker code is correct; if the second marker code is correct, read the second data block B and the second check code, and calculate the second calculated check code of the second data block B. The second calculated check code is obtained by encoding the second data block B stored in the data buffer 20.

[0081] Determine if the second calculated checksum is equal to the second checksum. This can be used to verify whether the second data block B has been corrupted due to a defect.

[0082] If the second calculated check code equals the second check code, then the second status code is determined to be data "1". The fact that the second calculated check code equals the second check code indicates that no error has occurred in the second data block B. At this point, the second marker code, the second data block B, and the second check code in the second data group B1 have all passed the verification, indicating that a correct second data block B has been found.

[0083] In some embodiments, based on a first status code and a second status code, the correct first data block A and a second data block B are searched, such as... Figure 10 As shown, it also includes the following steps:

[0084] After determining that the second status code is data "1", or after the second calculated check code is not equal to the second check code, determine whether the first status code is equal to data "1".

[0085] If the first status code equals "1", it indicates that the correct first data block A and second data block B have been found. A first status code of "1" means that the correct first data block A has been found. Since the search has been completed, power-on can be terminated.

[0086] In some embodiments, this embodiment also provides a memory that performs the data processing method described above.

[0087] It is understood that since the memory provided in this embodiment performs the above-described data processing method, it can also store the same data in at least two memory rows, apply a conduction voltage to at least one word line, and apply a read voltage to multiple word lines. This allows the same bit line to simultaneously read data from multiple memory cells. Even if some memory cells are defective, the bit line can still read the correct data from memory cells that are not defective, thereby reducing data read errors and improving the robustness of the memory cells.

[0088] It should be noted that the aforementioned memory may be, but is not limited to, NAND flash memory, or other memory chips applicable to this application, such as memory chips that do not have at least one of the serial select line SSL, select line GSL, and common source line CSL, and the transistors connected thereto.

[0089] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0090] The data processing method and memory provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data processing method for a memory, characterized in that, The memory includes multiple storage rows, each storage row including a row of storage units connected to a word line, and the data processing method includes: Store the same data into at least two of the storage rows; An on-state voltage is applied to at least one of the word lines, and a read-state voltage is applied to multiple of the word lines.

2. The data processing method according to claim 1, characterized in that, The word lines include first-type word lines and third-type word lines. The plurality of storage rows include first-type storage rows for storing first-type data and third-type storage rows for storing third-type data. Each first-type storage row is connected to a first-type word line, and each third-type storage row is connected to a third-type word line. The data processing method further includes: An on-state voltage is applied to the third type of word line, and a read-state voltage is applied to multiple first type of word lines.

3. The data processing method according to claim 1, characterized in that, The word lines include first-type word lines and second-type word lines; the plurality of storage rows include first-type storage rows and second-type storage rows; each first-type storage row is connected to a first-type word line; each second-type storage row is connected to a second-type word line; the data processing method further includes: An on-state voltage is applied to one of the first type word lines and the second type word lines, and a read-state voltage is applied to the other of the plurality of first type word lines and the second type word lines.

4. The data processing method according to claim 3, characterized in that, The data processing method further includes: Each of the first type of storage rows is configured to store alternating first and second data groups, and each of the second type of storage rows stores alternating second and first data groups.

5. The data processing method according to claim 4, characterized in that, The data processing method further includes: Each of the first data groups is configured to include a first marker code located in the data header, a first check code located in the data tail, and a first data block located between the data header and the data tail. Each of the second data groups is configured to include a second marker code located in the data header, a second check code located in the data tail, and a second data block located between the data header and the data tail.

6. The data processing method according to claim 5, characterized in that, The data processing method further includes: Read at least one of the first data groups and at least one of the second data groups into the data buffer; Search the data buffer for the correct first data block and the correct second data block; Store the correct first data block and second data block to the configuration register.

7. The data processing method according to claim 6, characterized in that, The step of searching for the correct first data block and second data block from the data buffer includes: In response to power-on, reset the first and second status codes; Determine the result of whether a read voltage is applied to multiple word lines of the first type; Based on the judgment result, the first status code, and the second status code, the correct first data block and the correct second data block are searched.

8. The data processing method according to claim 7, characterized in that, The step of searching for the correct first data block and second data block based on the judgment result, the first status code, and the second status code includes: Based on the judgment result, the first status code and the second status code are determined; Based on the first status code and the second status code, search for the correct first data block and the correct second data block.

9. The data processing method according to claim 8, characterized in that, The step of determining the first status code and the second status code based on the judgment result includes: Based on the judgment result and the verification result of the first data group, the first status code is determined; Based on the judgment result and the verification result of the second data group, the second status code is determined.

10. The data processing method according to claim 9, characterized in that, The determination of the first status code based on the judgment result and the verification result of the first data group includes: If the judgment result indicates that a reading voltage is applied to multiple first-class word lines, or if the second tag code is incorrect, or if the first status code is equal to the data "0", then the first tag code is read; Determine whether the first marker code is correct; If the first tag code is correct, then read the first data block and the first check code, and calculate the first calculated check code of the first data block; Determine whether the first calculated check code is equal to the first check code; If the first calculated check code is equal to the first check code, then the first status code is determined to be data "1".

11. The data processing method according to claim 10, characterized in that, The step of searching for the correct first data block and second data block based on the first status code and the second status code includes: After determining that the first status code is data "1", or after the first calculated check code is not equal to the first check code, determine whether the second status code is equal to data "1"; If the second status code equals the data "1", then it is determined that the correct first data block and second data block have been found.

12. The data processing method according to claim 11, characterized in that, The determination of the second status code based on the judgment result and the verification result of the second data group includes: If the judgment result indicates that no reading voltage has been applied to multiple first-class word lines, or if the first tag code is incorrect, or if the second status code is equal to the data "0", then the second tag code is read; Determine whether the second marker code is correct; If the second tag code is correct, then read the second data block and the second check code, and calculate the second calculated check code of the second data block; Determine whether the second calculated check code is equal to the second check code; If the second calculated check code is equal to the second check code, then the second status code is determined to be data "1".

13. The data processing method according to claim 12, characterized in that, The step of searching for the correct first data block and second data block based on the first status code and the second status code further includes: After determining that the second status code is data "1", or after the second calculated check code is not equal to the second check code, determine whether the first status code is equal to data "1"; If the first status code equals the data "1", then it is determined that the correct first data block and second data block have been found.

14. A memory, characterized in that, The memory performs the data processing method as described in any one of claims 1-13.

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