Method and device for reading and writing based on debugging communication channel and medium

Abstract

The application relates to the technical field of chip debugging, and provides a read-write acceleration method and device based on a debugging communication channel and a medium, wherein a special debugging data communication channel is constructed between a target CPU and an ET component by configuring a data reading register, a data writing register and a data control register, and configuring a debugging receiving signal and a debugging transmission signal; the data communication channel can enable the ET component and the target CPU to directly exchange data; the problem that only about 50 bytes of data can be transmitted between the ET component and the target CPU at a time is solved; and the data exchange adopts an interrupt response mechanism, so that the target CPU can reach a system rate when processing a data exchange request, thereby greatly improving the read-write speed of a storage body and improving the debugging efficiency of a tester on an application program.

Description

Technical Field

[0001] This invention belongs to the field of chip debugging technology, and relates to a read / write acceleration method, device and medium based on a debugging AC channel. Background Technology

[0002] With the continuous development of integrated circuit design technology and manufacturing processes, the performance of chips on the market is also getting better and better, and large applications require storage capacities of tens of gigabytes (GB). During chip debugging, the slow data transfer rate between the debugging host and the target CPU has long been a problem. As chip storage capacity continues to expand and application sizes continue to grow, solving the problem of slow data transfer rates between the debugging host and the target CPU has become urgent. Existing memory read / write methods are no longer sufficient to meet the needs of chip debugging; current memory read / write operations typically use the chip's core registers and specific instructions (such as Load and Store instructions) to read and write memory values.

[0003] The process of reading from memory is as follows: First, the starting address of the memory space is written to the kernel register via TDI (the data input pin in the JTAG interface). Then, the target CPU obtains the starting address via the Load instruction. Finally, the target CPU uses the Store instruction to store the data from the memory space into the kernel register. The final value of the kernel register is then fed back to TDO (the JTAG signal line) for the debugging host to access. The process of writing to memory is as follows: The starting address and data of the memory space are written together to the kernel register via TDI (the JTAG signal line). Then, the values ​​of these registers are written to the memory space via the Load instruction.

[0004] Since a chip typically has a dozen or so core registers, a single read / write operation can handle approximately 50 bytes of data (e.g., 13 (number of registers) × 4 (one register can store 4 bytes)). Compared to applications with large data volumes, this data volume results in slow memory read / write speeds and significant time consumption, severely hindering the debugging efficiency of chip applications. Current techniques combining core registers and instructions for reading and writing memory are no longer sufficient for chip debugging needs. The main reasons are: firstly, the target CPU typically has a dozen or so core registers, which can only hold 50 bytes of data at a time; secondly, the ET (Executable Transmission) component typically uses a debugging speed when reading and writing memory, which is far lower than the target CPU's system speed, further reducing the data exchange rate between the target CPU and the ET component. This, to some extent, reduces the efficiency of the target CPU's processing.

[0005] Therefore, existing technologies can only guarantee chip debugging efficiency when storage capacity is small and application applications are simple. Improving the read / write speed of the memory bank when chip storage capacity is expanded and application functions become more complex with large amounts of data being read and written has become one of the urgent technical problems to be solved. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention proposes a read / write acceleration method, device, and medium based on a debug AC channel, which can improve the read / write speed of the memory when the chip storage capacity is expanded, the application functions become more complex, and large amounts of data are read and written.

[0007] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a read / write acceleration method based on a debug communication channel is provided, including the following steps: The ET component of the chip is configured with a data read register, a data write register, and a data control register; the configured registers are used to establish a direct data exchange path between the target CPU and the ET component without going through the kernel registers and specific instructions; the specific instructions include the Load instruction and the Store instruction; Configure debug receive signal and debug transmit signal; the debug receive signal is associated with the first status bit of the data control register, and the debug transmit signal is associated with the second status bit of the data control register; The target CPU is triggered to enter the interrupt response routine by the change of the first or second status bit, and the bidirectional data communication initiated by the ET component is processed.

[0008] In one embodiment, the data read register is configured to store data sent by the ET component to the target CPU; The data write register is configured to store data sent by the target CPU to the ET component; The data control register is configured to enable synchronous handshaking between the target CPU and the asynchronous ET unit.

[0009] In one embodiment, both the data read register and the data write register are 32-bit registers, and all 32 bits are valid data. The data control register is a 32-bit register, with the lower 6 bits being valid and the register attribute being read-only.

[0010] In one embodiment, the lower 6 bits of the data control register are: bit 0 is the R bit, bit 1 is the W bit, and bits 2 to 5 include fixed values ​​representing the ET component version number; the first status bit is the R bit, and the second status bit is the W bit. Bits 6 through 31 of the data control register are reserved.

[0011] In one embodiment, the debug receive signal is configured as follows: When the R bit indicates that the data read register is not empty, the debug receive signal is pulled high to trigger the target CPU to retrieve data from the data read register; When the R bit indicates that the data read register is empty, the ET component is allowed to store data into the data read register.

[0012] In one embodiment, the debug transmission signal is configured as follows: When the W bit indicates that the data write register is empty, the debug transmission signal is pulled high to trigger the target CPU to write data to the data write register. When the W bit indicates that the data written to the register is not empty, it means that the ET component has not yet taken the data written to the register.

[0013] In one embodiment, data exchange between the target CPU and the ET component includes: In response to the debug transmission signal going high, the target CPU determines whether to enter the interrupt response routine based on the current interrupt priority. When the interrupt response routine is entered and the W bit is W=0, the target CPU writes the message to the data write register, and the ET unit sets the W bit to W=1 to indicate that the data write register contains the data to be retrieved. In response to the debug receive signal going high, the target CPU determines whether to enter the interrupt response routine based on the current interrupt priority. When the interrupt response routine is entered and the R bit is R=1, the target CPU reads the message from the data read register and the ET unit sets the R bit to R=0 to indicate that the data has been taken.

[0014] In one embodiment, data exchange between the ET component and the target CPU includes: The ET component reads bit R. When R=0, it writes the message to the data read register, sets bit R to R=1, and pulls the debug receive signal high to trigger the target CPU to retrieve the data. When R=1, the ET component enters polling and waits until bit R is restored to R=0. The ET component reads bit W. When W=1, it reads the message from the data write register, sets bit W to W=0, and pulls the debug transmission signal high to indicate that the data has been taken. When W=0, the ET component enters polling and waits until bit W=1.

[0015] On the other hand, a read / write acceleration device based on a debug communication channel is also provided, including an ET component, which includes a data read register, a data write register, and a data control register. The data read register is configured to store data sent by the ET component to the target CPU for the target CPU to read. The data write register is configured to store data sent from the target CPU to the ET unit, for the ET unit to read. The data control register is configured to implement a synchronous handshake between the target CPU and the asynchronous ET component; the data control register includes a first status bit and a second status bit, the first status bit representing the status of data read from the register, and the second status bit representing the status of data write to the register. The ET component is also equipped with a debug receive signal and a debug transmit signal. The debug receive signal is associated with a first status bit and is configured to go high to trigger the target CPU when the first status bit indicates that the data read register is not empty. The debug transmit signal is associated with a second status bit and is configured to go high to trigger the target CPU when the second status bit indicates that the data write register is empty.

[0016] On another front, a computer-readable storage medium is also provided, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the above-described read / write acceleration method based on a debug communication channel.

[0017] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned read / write acceleration method, device, and medium based on a debug communication channel establish a special debug data communication channel between the target CPU and the ET component by configuring data read registers, data write registers, and data control registers, as well as configuring debug receive signals and debug transmit signals. This data communication channel enables the ET component and the target CPU to exchange data directly, solving the previous problem of only being able to transfer about 50 bytes of data to the target CPU at a time. Furthermore, this data exchange adopts an interrupt response mechanism, enabling the target CPU to reach the system speed when processing data exchange requests, thereby significantly improving the read / write speed of the memory and enhancing the debugging efficiency of application programs for testers. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a read / write acceleration method based on a debug communication channel in one embodiment. Figure 2 Here is a block diagram of the debugging AC channel function in one embodiment; Figure 3This is a schematic diagram of the process by which the target CPU sends a message to the ET component in one embodiment; Figure 4 This is a schematic diagram of the process by which the target CPU receives messages from the ET component in one embodiment; Figure 5 This is a schematic diagram of the process by which the ET component sends a message to the target CPU in one embodiment; Figure 6 This is a schematic diagram of the process by which the ET component receives messages from the target CPU in one embodiment; Figure 7 This is a schematic diagram of the module architecture of a read / write acceleration device based on a debug communication channel in one embodiment. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0021] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0022] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] In one embodiment, a read / write acceleration method based on a debug communication channel is provided, such as... Figure 1 As shown, the above-mentioned read / write acceleration method based on the debugging communication channel may include the following processing steps S10 to S14: S10 configures a data read register, a data write register, and a data control register in the ET component of the chip; the configured registers are used to establish a direct data exchange path between the target CPU and the ET component without going through the kernel registers and specific instructions; the specific instructions include the Load instruction and the Store instruction.

[0024] Understandably, in existing technologies, every data exchange between the target CPU and the ET component must pass through the kernel register set. Since the kernel register set typically contains only a dozen or so registers, a single operation can transfer a maximum of about 50 bytes of data, creating a significant data transfer bottleneck. Furthermore, each data transfer requires the execution of Load and Store instructions, and the instruction execution itself consumes clock cycles, further reducing transfer efficiency.

[0025] In this step, by adding three registers at the hardware level of the ET component, a direct data exchange path independent of the traditional kernel register channel is established between the target CPU and the ET component. "Avoiding kernel registers and specific instructions" means that data transmission and reception completely bypass the original kernel register set and the data transport paths of Load and Store instructions within the chip. By configuring dedicated hardware registers directly in the ET component, the three registers for data reading, data writing, and data control form a bypass channel. This bypass channel allows the ET component and the target CPU to directly perform read and write operations on the physical addresses of the registers, eliminating the need for kernel registers as intermediate caches and the need for Load and Store instructions to transport data. Therefore, the data transmission path is greatly shortened, and the amount of data that can be transmitted in a single transaction is no longer limited by the number of kernel registers.

[0026] This design effectively overcomes the physical bottleneck of the number of kernel registers, laying the hardware foundation for subsequent high-volume and high-frequency data exchange. Specifically, the data read register stores data sent from the ET component to the target CPU, the data write register stores data sent from the target CPU to the ET component, and the data control register coordinates the read / write timing between the two, ensuring no data conflicts or loss occur between the two asynchronously operating entities. This three-register collaborative architecture fundamentally restructures the data exchange method between the target CPU and the ET component, providing the hardware foundation for accelerated read / write operations.

[0027] S12, configure debug receive signal and debug transmit signal; debug receive signal is associated with the first status bit of data control register, and debug transmit signal is associated with the second status bit of data control register.

[0028] It is understandable that even if a direct data exchange path is established in step S1, if the target CPU cannot detect in time when the ET component writes or retrieves data, the target CPU can only continuously check the register status by polling. This polling operation will continuously occupy the target CPU's computing resources, causing the target CPU to be unable to focus on executing other processes, which actually slows down the overall system's operating efficiency.

[0029] Therefore, this step further configures two interrupt signals in addition to the three hardware registers. The debug receive signal is used to notify the target CPU that there is data waiting to be read from the ET component, and its status is associated with the first status bit of the data control register; the debug transmit signal is used to notify the target CPU that data can be written to the ET component, and its status is associated with the second status bit of the data control register.

[0030] By associating changes in the status bits of the data control register with interrupt signals at the hardware level, the corresponding interrupt signal is automatically pulled high or low when the status bits of the data control register change, thereby triggering the interrupt response mechanism of the target CPU. This hardware-level signal binding ensures extremely low notification latency for status changes, enabling communication requests to be conveyed to the target CPU immediately and avoiding the latency and resource waste caused by software polling.

[0031] In this way, an event-driven data exchange and notification mechanism can be effectively formed. Changes in status bits are direct indicators of data exchange needs, while interrupt signals serve as the bridge to transmit this indicator to the target CPU via hardware interrupts. Working together, the target CPU can learn of communication needs without actively polling, allowing it to immediately return to normal processes after handling the interrupt service, significantly reducing unnecessary CPU time consumption. This interrupt-driven mechanism also enables the target CPU to respond at system speed when processing data exchanges, rather than passively waiting at debug speed.

[0032] S14, the target CPU is triggered to enter the interrupt response program by the state change of the first state bit or the second state bit, and the bidirectional data communication initiated by the ET component is processed.

[0033] It's understandable that in real-world debugging scenarios, the target CPU might be executing high-priority processes. If any debugging communication request unconditionally preempts the CPU, it could impact system stability and the execution of critical tasks. Therefore, it's necessary to ensure timely communication responses while also considering the target CPU's own task scheduling needs.

[0034] When the first status bit indicates that the data read register is not empty, or when the second status bit indicates that the data write register is empty, the corresponding interrupt signal will go high. The target CPU will determine whether to enter the interrupt response routine based on the interrupt priority in order to handle the data communication initiated by the ET component.

[0035] By incorporating interrupt signals into the target CPU's interrupt priority management system, the target CPU, upon receiving an interrupt signal, will determine its priority based on the current interrupt priority. Only if the priority condition is met will it enter the interrupt response routine. This ensures that debugging communication does not indiscriminately interrupt critical processes, while also guaranteeing timely responses to communication requests at appropriate times, ultimately achieving a balance between debugging communication and target CPU task scheduling. Specifically, status bits record data exchange needs, interrupt signals transmit notifications, and the interrupt priority management system determines the response timing. This multi-layered collaborative mechanism ensures that data exchange is both efficient and timely, without causing unnecessary interference to the normal operation of the target CPU.

[0036] In summary, the read / write acceleration method based on a debug communication channel provided in this embodiment is an advanced debugging method. Its debug communication channel is a special type of debug channel, built into the hardware mechanism of the ET component, used to establish an independent communication link between the target CPU and the ET component. It allows the ET component and the target CPU to exchange data directly without occupying conventional I / O (input / output) resources such as UART. The functional block diagram of the debug communication channel is shown below. Figure 2 As shown, Figure 2 Connection line 1 indicates that the target CPU obtains information from the debug host's data read register in the debug communication channel. Connection line 2 indicates that the target CPU writes information to the data write register in the debug communication channel. Connection line 3 indicates that the ET component obtains information from the debug host (which can be carried by the simulation debugging tool) from the JTAG interface and writes it to the data read register. Connection line 4 indicates that the ET component writes information obtained from the data write register to the JTAG interface. Connection line 5 indicates that the debug host writes messages to the JTAG signal line through the simulation debugging tool. Connection line 6 indicates that the simulation debugging tool transmits data on the JTAG signal line to the debug host.

[0037] The core technical concept of the above-mentioned read / write acceleration method based on the debug communication channel is to build a special debug data communication channel between the target CPU and the ET component. This data communication channel enables the ET component and the target CPU to exchange data directly, solving the problem that the traditional method can only transfer about 50 bytes of data with the target CPU at a time. Furthermore, this data exchange adopts an interrupt response mechanism, which enables the target CPU to reach the system speed when processing data exchange requests, thereby significantly improving the read / write speed of the memory and enhancing the debugging efficiency of the application for testers.

[0038] Specifically, this embodiment adds three hardware registers to the ET component design of the chip: a data read register, a data write register, and a data control register. The data read register stores data sent by the ET component to the target CPU for the target CPU to read; the data write register stores data sent by the target CPU to the ET component for the ET component to read; and the data control register, as the core of the debug data communication channel, uses two status bits to achieve synchronous handshake between the target CPU and the asynchronous ET component, thereby achieving synchronous communication.

[0039] In addition to the three hardware registers, two interrupt signals are added: a debug receive signal and a debug transmit signal. The purpose of these two interrupt signals is to enable the target CPU to enter the interrupt service routine to process the data sent by the ET unit. This design has two advantages in practical applications: first, it can promptly notify the target CPU to process the data sent by the ET unit; second, it allows the target CPU to exit the interrupt service routine after processing the ET unit's request and continue processing other processes, thus avoiding slowing down the target CPU's process processing efficiency. The ET unit, on the other hand, polls and waits for the data control register to determine if the target CPU has any new data to transmit.

[0040] In one embodiment, the data read register is configured to store data sent from the ET component to the target CPU. The data write register is configured to store data sent from the target CPU to the ET component. The data control register is configured to implement a synchronous handshake between the target CPU and the asynchronous ET component.

[0041] It is understandable that in the three-register architecture established above, it is crucial to clearly define the functional responsibilities of each register to ensure orderly and reliable bidirectional data exchange between the ET component and the target CPU. Unclear functional division of the registers may lead to conflicts between data writing and reading, or data errors may occur due to the ET component and the target CPU simultaneously operating on the same register.

[0042] This embodiment clearly defines the functional division of the three registers: the data read register is specifically responsible for unidirectional data storage from the ET component to the target CPU, the data write register is specifically responsible for unidirectional data storage from the target CPU to the ET component, and the data control register independently undertakes the control function of synchronous coordination between the two. This division of labor completely separates the read and write directions, and the data transmission in the two directions does not interfere with each other, thereby realizing full-duplex data exchange capability.

[0043] Because the read / write channels are physically separated into two independent registers, the operation of the ET component sending data to the target CPU and the operation of the target CPU sending data to the ET component can be performed concurrently without waiting for each other. The data control register, as an independent synchronization and coordination unit, monitors the empty / full status of the two data registers through status bits, ensuring that the ET component and the target CPU can accurately determine the availability of each other's registers at any time, thereby avoiding synchronization errors such as data overwriting and data loss.

[0044] In one embodiment, both the data read register and the data write register are 32-bit registers, with all 32 bits being valid data. The data control register is a 32-bit register, with the lower 6 bits being valid and the register attribute being read-only.

[0045] It is understandable that, after determining the functional division of registers, it is necessary to further select a more reasonable register bit width to achieve a better balance between hardware resource overhead and data transmission capability. If the bit width is set too small, the amount of data transmitted each time will still be limited, failing to fully realize the advantages of the direct switching channel; if the bit width is set too large, it will increase chip area and power consumption, resulting in unnecessary hardware costs. In addition, as a shared status register, the readability of the data control register is related to the read / write permission management between the ET component and the target CPU.

[0046] This embodiment configures both the data read register and the data write register to be 32 bits, with all 32 bits being valid data bits. This means that each data transfer operation can move 4 bytes of data. Combined with the system speed response of the target CPU in the interrupt-driven mechanism, it can transfer far more data than the existing technology's limit of approximately 50 bytes per unit time. The data control register is also 32 bits, but only the lower 6 bits are valid and are read-only. This means that the ET component and the target CPU can only read the contents of this register and cannot modify it through software.

[0047] A 32-bit register refers to a register with a width of 32 binary bits, meaning it can store 32 bits of data at a time. Converted to bytes, 32 bits equals 4 bytes. In this embodiment, all bits from the high to low of the data read register and data write register are valid data bits; there are no reserved bits. Therefore, each read / write operation can achieve 4 bytes of valid data transmission. The specific meanings of the data control registers are shown in Table 1. Table 1 Data Control Registers

[0048] This allows for a significant improvement in data transfer capabilities with more optimized hardware overhead. The 32-bit register width balances the versatility and cost-effectiveness of chip design, and is a widely adopted standard width in embedded chip design. The data control register uses a read-only attribute, ensuring consistent reading of status information by the ET component and the target CPU, while preventing either party from tampering with the status bits in software and causing synchronization errors. The consistent 32-bit width of the three registers also simplifies the internal bus interface design of the chip, reducing the complexity of hardware implementation. The lower 6 bits of the data control register are defined to accommodate necessary control and identification information such as the R bit, W bit, and version number without consuming additional storage units; the full-bit validity of the data register maximizes the data throughput per transmission cycle.

[0049] In one embodiment, in the lower 6 bits of the data control register, bit 0 is the R bit, bit 1 is the W bit, and bits 2 through 5 include fixed values ​​representing the ET component version number. The first status bit is the R bit, and the second status bit is the W bit. Bits 6 through 31 of the data control register are reserved bits.

[0050] It's understandable that, given the lower 6 bits of the data control register are valid, the challenge lies in how to rationally allocate the functional definitions of these 6 valid bits to ensure that control information is expressed concisely and clearly, while also considering scalability and version compatibility. If the bit definitions are unclear or ambiguous, it could lead to inconsistencies in the ET component's and the target CPU's understanding of the status bits, potentially causing errors at the communication protocol level.

[0051] In this embodiment, bit 0 is designated as the R bit to characterize the state of the data read register; bit 1 is designated as the W bit to characterize the state of the data write register; bits 2 to 5 are used to store the version number of the ET component, which is a fixed value. Bits 6 to 31 are reserved bits for future function expansion. The definitions of the R and W bits are concise and clear: the R bit corresponds to the Read direction (from the ET component to the target CPU), and the W bit corresponds to the Write direction (from the target CPU to the ET component). This naming and bit order arrangement allows developers to intuitively understand the correspondence between bits and data flow.

[0052] In this way, clear functional division and version management capabilities can be achieved within the smallest effective bit space. Specifically, the R and W bits are located in the lowest two bits, facilitating rapid extraction of status information via bit manipulation instructions; the version number bit is adjacent to the status bits, allowing version information to be obtained simultaneously during status reading, facilitating compatibility with debugging tools; reserved bits provide ample address space for potential future functional expansions, ensuring backward compatibility of the architecture. This bit definition scheme allows the data control register to become a self-describing control unit, requiring only the reading of the lower 6 bits of the register to obtain complete communication status and version information.

[0053] In one embodiment, the debug receive signal is configured such that when the R bit indicates the data read register is not empty, the debug receive signal goes high to trigger the target CPU to retrieve data from the data read register. When the R bit indicates the data read register is empty, the ET component is allowed to store data into the data read register.

[0054] It's understandable that after clarifying the relationship between the R bit and the debug receive signal, it's necessary to define more precisely the corresponding logic between the level state of the debug receive signal and the value of the R bit, as well as the behavior definition of the signal in different states. If the signal logic is not precise enough, it may cause the target CPU to be mistakenly interrupted when the data read register is empty, or the ET component to erroneously overwrite existing data when the data read register is not empty.

[0055] This embodiment establishes a strict correspondence between the R bit and the debug receive signal, such that when R equals 1, it indicates that the data read register is not empty, and the debug receive signal is pulled high to send an interrupt notification to the target CPU; when R equals 0, it indicates that the data read register is empty, and the debug receive signal is low, allowing the ET component to store new data into the data read register.

[0056] This mechanism achieves mutual exclusion protection between ET component write operations and target CPU read operations. The R bit records the empty / full state of the data read register. The debug receiver signal drives the target CPU's behavior based on the value of the R bit, while the target CPU's read operations and the ET component's write operations, in turn, change the value of the R bit and the state of the data read register. This closed-loop coordination mechanism ensures that the data read register will never be overwritten, better guaranteeing the consistency and integrity of data transmission from the ET component to the target CPU.

[0057] In one embodiment, the debug transfer signal is configured such that when the W bit indicating the data write register is empty, the debug transfer signal goes high to trigger the target CPU to write data to the data write register. When the W bit indicating the data write register is not empty, it indicates that the ET component has not yet removed data from the data write register.

[0058] As is understandable in the previous embodiment, a more precise definition of the logic corresponding to the level state of the debug transmission signal and the value of the W bit is needed to better achieve timing coordination between the target CPU's write operation and the ET component's read operation. If the logic definition of the W bit and the debug transmission signal is improper, it may cause the target CPU to erroneously write new data when the data write register is not empty, thus overwriting old data that has not yet been retrieved by the ET component.

[0059] This embodiment establishes a strict correspondence between the W bit and the debug transmission signal. When W equals 0, it indicates that the data write register is empty. At this time, the debug transmission signal is pulled high to notify the target CPU that it can write data to the data write register. When W equals 1, it indicates that the data write register is not empty, that is, the ET component has not yet taken the data from the register. At this time, the debug transmission signal is low, and the target CPU cannot write new data.

[0060] In this way, mutual exclusion protection can be achieved between the target CPU's write operations and the ET component's read operations. The W bit records the empty / full state of the data write register. The debug transmission signal drives the target CPU's behavior based on the value of the W bit, while the target CPU's write operations and the ET component's read operations, in turn, change the value of the W bit and the state of the data write register. The debug receive signal logic described above and the debug transmission signal logic of this embodiment form a symmetrical bidirectional protection mechanism, jointly ensuring the atomicity and consistency of data transmission in both directions of the data exchange channel. Together, they enable more reliable bidirectional asynchronous communication between the target CPU and the ET component.

[0061] In one embodiment, data exchange between the target CPU and the ET component may include the following process: like Figure 3 As shown, the process of the target CPU sending a message to the ET component is as follows: In response to the debug transmission signal going high, the target CPU determines whether to enter the interrupt response routine based on the current interrupt priority; when entering the interrupt response routine and the W bit is W=0, after the target CPU writes the message to the data write register, the ET component sets the W bit to W=1 to indicate that the data write register contains the data to be retrieved.

[0062] like Figure 4 As shown, the process of the target CPU receiving messages from the ET component is as follows: In response to the debug receive signal going high, the target CPU determines whether to enter the interrupt response routine based on the current interrupt priority; when entering the interrupt response routine and the R bit is R=1, the target CPU reads the message from the data read register, and the ET component sets the R bit to R=0 to indicate that the data has been taken.

[0063] Understandably, assuming the hardware registers and interrupt signals are already configured, it's still necessary to further clarify the complete timing and flow of the target CPU's operations in both the receiving and transmitting directions, especially the specific steps after the interrupt response. Without a clear definition of the operation flow, the target CPU might execute incorrect data operation sequences after the interrupt response, leading to data loss or communication failure.

[0064] This embodiment clearly designs the complete operation sequence for both directions. In the transmitting direction, the target CPU first determines the interrupt priority, then checks if the W-bit acknowledgment register is writable, then writes the data, and finally the ET component updates the W-bit status. In the receiving direction, the target CPU similarly first determines the interrupt priority, then checks if the R-bit acknowledgment register is ready, then reads the data, and finally the ET component updates the R-bit status. In both directions, the target CPU is the data initiator, while the ET component is responsible for updating and maintaining the status bits.

[0065] Thus, by introducing an interrupt priority judgment mechanism, the target CPU can participate in data exchange while ensuring the priority of critical tasks. Interrupt signals trigger notifications, interrupt priority management controls the response timing, R bits or W bits provide confirmation of data readiness, the target CPU performs specific data read and write operations, and the ET component updates the status bits to complete the handshake. This multi-factor collaboration ensures the reliability and real-time performance of the data exchange process, while minimizing the impact on the normal process processing of the target CPU.

[0066] In one embodiment, data exchange between the ET component and the target CPU may include the following processing: like Figure 5 As shown, the process of the ET component sending a message to the target CPU is as follows: The ET component reads the R bit, writes the message to the data read register when R=0, sets the R bit to R=1 and pulls the debug receive signal high to trigger the target CPU to retrieve the data; when R=1, the ET component enters polling wait until the R bit is restored to R=0.

[0067] like Figure 6 As shown, the process of the ET component receiving the target CPU message is as follows: The ET component reads the W bit, reads the message from the data write register when W=1, sets the W bit to W=0 and pulls the debug transmission signal high to indicate that the data has been taken; when W=0, the ET component enters polling wait until the W bit is set to W=1.

[0068] It is understood that this embodiment is symmetrical to the previous embodiment, and further design is needed to complete the timing and flow of the ET component's operation in both the transmitting and receiving directions. The ET component typically operates asynchronously in the system; its operating clock is not synchronized with the target CPU's system clock. Therefore, the ET component cannot respond to interrupts like the target CPU, and can only determine whether communication conditions are met by polling the status bits of the data control register. If the polling logic is poorly designed, it may cause the ET component to enter an infinite loop or miss the opportunity when data is ready.

[0069] This embodiment designs the operation sequence of the ET component in two directions. The ET component adopts a hybrid strategy of active polling and passive waiting: when the condition is not met (R=1 or W=0), the ET component enters polling waiting; when the condition is met, the ET component performs data operations and updates the status bit and interrupt signal. After the ET component completes the data operation, the interrupt signal notification will trigger an interrupt response from the target CPU, thus forming a complete round of data exchange.

[0070] In this way, reliable data exchange synchronization is achieved between asynchronous clock domains. The target CPU uses interrupt-driven operation to avoid invalid polling consuming CPU time; the ET component uses polling and waiting to adapt to its asynchronous operation characteristics and hardware limitations of lacking interrupt response capability. The R bit, W bit, debug receive signal, debug transmit signal, the polling operation of the ET component, and the interrupt response of the target CPU form a complete data exchange closed loop, ensuring that data exchange between the two asynchronous working entities is both efficient and reliable. The target CPU process of the previous embodiment and the ET component process of this embodiment together constitute the optimal implementation scheme for bidirectional data exchange in the debug communication channel.

[0071] Compared with existing technologies, the present invention has low design overhead and low hardware requirements, and achieves bidirectional communication and a simple handshake mechanism through a data control register. Traditional debugging methods require pausing the target CPU to complete input / output operations, while the present invention, through interrupt signals and a data control register, allows the target CPU to perform bidirectional data communication at full speed without interrupting program execution, significantly improving the data exchange rate. Only three hardware registers and two interrupt signals are needed to establish an independent communication link between the target CPU and the ET component, allowing the ET component to directly exchange data with the target CPU without occupying conventional I / O resources such as UART. When the status bits of the data control register change, a communication interrupt can even be generated to drive a more efficient data transmission and reception process, thereby achieving efficient data transfer.

[0072] It should be understood that, although Figure 1The steps are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Figure 1 At least some of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0073] In one embodiment, such as Figure 7 As shown, a read / write acceleration device 100 based on a debug communication channel is also provided, which may include an ET component. The ET component includes a data read register, a data write register, and a data control register. The data read register is configured to store data sent by the ET component to the target CPU for the target CPU to read. The data write register is configured to store data sent by the target CPU to the ET component for the ET component to read. The data control register is configured to implement synchronous handshaking between the target CPU and the asynchronous ET component. The data control register includes a first status bit and a second status bit, where the first status bit represents the status of the data read register, and the second status bit represents the status of the data write register.

[0074] The ET component is also equipped with a debug receive signal and a debug transmit signal. The debug receive signal is associated with a first status bit and is configured to go high to trigger the target CPU when the first status bit indicates that the data read register is not empty. The debug transmit signal is associated with a second status bit and is configured to go high to trigger the target CPU when the second status bit indicates that the data write register is empty.

[0075] It can be understood that the data read register, data write register, and data control register can serve as three hardware units within the ET component, collectively forming the physical carrier of the debug communication channel. The debug receive signal and debug transmit signal serve as interrupt signal lines output by the ET component, transmitting changes in the status bits in the data control register to the interrupt controller of the target CPU in real time. The complete device technical solution constituted by the connection relationships and signal transmission paths between the various hardware units can realize the data exchange function described in any of the aforementioned method embodiments. For specific limitations on the features of the aforementioned read / write acceleration device 100 based on the debug communication channel, please refer to the explanations of the corresponding features in the various embodiments of the read / write acceleration method based on the debug communication channel above; further details will not be repeated here.

[0076] The aforementioned read / write acceleration device 100 based on the debug communication channel establishes a special debug data communication channel between the target CPU and the ET component by configuring data read registers, data write registers, and data control registers, as well as configuring debug receive signals and debug transmit signals. This data communication channel enables the ET component and the target CPU to exchange data directly, solving the previous problem that only about 50 bytes of data could be transferred to the target CPU at a time. Furthermore, the data exchange adopts an interrupt response mechanism, enabling the target CPU to reach the system speed when processing data exchange requests, thereby significantly improving the read / write speed of the memory and enhancing the debugging efficiency of the application for testers.

[0077] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described read / write acceleration method based on a debug communication channel.

[0078] Computer-readable storage media may be read-only memory (ROM), random access memory (RAM), flash memory, hard disk storage media, optical disk storage media, or any other tangible medium capable of storing computer instructions.

[0079] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM). By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), memory bus type dynamic random access memory (Rambus DRAM, or RDRAM for short), and direct Rambus DRAM (DRDRAM), etc.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A read / write acceleration method based on a debug communication channel, characterized in that, Including the following steps: The ET component of the chip is configured with a data read register, a data write register, and a data control register; the configured registers are used to establish a direct data exchange path between the target CPU and the ET component without going through the kernel registers and specific instructions; the specific instructions include the Load instruction and the Store instruction; Configure debug receive signal and debug transmit signal; the debug receive signal is associated with the first status bit of the data control register, and the debug transmit signal is associated with the second status bit of the data control register; The target CPU is triggered to enter the interrupt response routine by the change of the first or second status bit, and the bidirectional data communication initiated by the ET component is processed.

2. The read / write acceleration method based on a debugging communication channel according to claim 1, characterized in that, The data read register is configured to store data sent by the ET component to the target CPU; The data write register is configured to store data sent by the target CPU to the ET component; The data control register is configured to enable synchronous handshaking between the target CPU and the asynchronous ET unit.

3. The read / write acceleration method based on a debugging communication channel according to claim 2, characterized in that, Both the data read register and the data write register are 32-bit registers, and all 32 bits are valid data. The data control register is a 32-bit register, with the lower 6 bits being valid and the register attribute being read-only.

4. The read / write acceleration method based on a debugging communication channel according to claim 3, characterized in that, In the lower 6 bits of the data control register, bit 0 is the R bit, bit 1 is the W bit, and bits 2 to 5 include fixed values ​​representing the ET component version number; the first status bit is the R bit, and the second status bit is the W bit; Bits 6 through 31 of the data control register are reserved.

5. The read / write acceleration method based on a debugging communication channel according to claim 4, characterized in that, The debug receive signal is configured as follows: When the R bit indicates that the data read register is not empty, the debug receive signal is pulled high to trigger the target CPU to retrieve data from the data read register; When the R bit indicates that the data read register is empty, the ET component is allowed to store data into the data read register.

6. The read / write acceleration method based on a debugging communication channel according to claim 4, characterized in that, The debug transmission signal is configured as follows: When the W bit indicates that the data write register is empty, the debug transmission signal is pulled high to trigger the target CPU to write data to the data write register. When the W bit indicates that the data written to the register is not empty, it means that the ET component has not yet taken the data written to the register.

7. The read / write acceleration method based on a debugging communication channel according to claim 4, characterized in that, Data exchange between the target CPU and the ET component includes: In response to the debug transmission signal going high, the target CPU determines whether to enter the interrupt response routine based on the current interrupt priority. When the interrupt response routine is entered and the W bit is W=0, the target CPU writes the message to the data write register, and the ET unit sets the W bit to W=1 to indicate that the data write register contains the data to be retrieved. In response to the debug receive signal going high, the target CPU determines whether to enter the interrupt response routine based on the current interrupt priority. When the interrupt response routine is entered and the R bit is R=1, the target CPU reads the message from the data read register and the ET unit sets the R bit to R=0 to indicate that the data has been taken.

8. The read / write acceleration method based on a debugging communication channel according to claim 4, characterized in that, Data exchange between the ET component and the target CPU includes: The ET component reads bit R. When R=0, it writes the message to the data read register, sets bit R to R=1, and pulls the debug receive signal high to trigger the target CPU to retrieve the data. When R=1, the ET component enters polling and waits until bit R is restored to R=0. The ET component reads bit W. When W=1, it reads the message from the data write register, sets bit W to W=0, and pulls the debug transmission signal high to indicate that the data has been taken. When W=0, the ET component enters polling and waits until bit W=1.

9. A read / write acceleration device based on a debugging communication channel, characterized in that, It includes the ET component, which comprises a data read register, a data write register, and a data control register; The data read register is configured to store data sent by the ET component to the target CPU for the target CPU to read. The data write register is configured to store data sent from the target CPU to the ET unit, for the ET unit to read. The data control register is configured to implement a synchronous handshake between the target CPU and the asynchronous ET component; the data control register includes a first status bit and a second status bit, the first status bit representing the status of data read from the register, and the second status bit representing the status of data write to the register. The ET component is also equipped with a debug receive signal and a debug transmit signal. The debug receive signal is associated with a first status bit and is configured to go high to trigger the target CPU when the first status bit indicates that the data read register is not empty. The debug transmit signal is associated with a second status bit and is configured to go high to trigger the target CPU when the second status bit indicates that the data write register is empty.

10. A computer-readable storage medium storing a computer program thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the read / write acceleration method based on the debug communication channel as described in any one of claims 1 to 8.

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