A memory chip-oriented high-frequency noise compensation test method, device and medium

Abstract

The application discloses a kind of high-frequency noise compensation test methods, equipment and medium for memory chip, it is related to memory test technical field, comprising: acquisition function test configuration data, select the same data output line grouping main test address and accompanying test address, in continuous readout bit sequence Complementary readout position and same value interval bit are determined, write main test data and mixed relationship accompanying test data, form same line mixed relationship address group;Two addresses are continuously read, and main test readout word and accompanying test readout word are obtained, and main test difference state, accompanying test difference state, same line mixed retention value and same value retention state are generated;When two addresses all exist readout difference, same line mixed retention value reaches permission limit and same value interval bit keeps same bit value, it is determined that same line high-frequency common influence and compensation passes;When same value interval bit does not keep same bit value, increase readout preparation interval and re-read main test address, to generate function test conclusion.The application reduces test false-positive rate and improves test stability.

Description

Technical Field

[0001] This invention relates to the field of storage testing technology, and in particular to a high-frequency noise compensation testing method, equipment and medium for storage chips. Background Technology

[0002] During mass production, memory chips typically require high-speed functional testing using ATE (Automatic Test Equipment). The test program writes all-zero, all-one, checkerboard, or address-dependent patterns to a specified memory address and reads the data at a predetermined test rate, comparing each bit with the written data. For DRAM, NAND, and embedded memory chips, functional testing also incorporates data output line grouping, read burst length, and read command intervals to assess read / write correctness, data retention capabilities, and high-speed output stability.

[0003] Under high-frequency readout conditions, adjacent readout processes on the same data output line may be affected by the same high frequency. Based solely on the difference in readout from the main test address, the common impact can easily be interpreted as a memory cell failure. At the same time, local misalignment or skipped-time anomalies in the consecutive readout bit sequence are similar to actual functional anomalies in ordinary comparisons, and conventional judgment is difficult to distinguish them with a small amount of read / write data. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a high-frequency noise compensation testing method for memory chips to solve the problems of insufficient differentiation between the common influence of high frequencies on the same line and the actual functional abnormalities, as well as insufficient granularity in the processing of bit-order sensitive readout differences in the existing technology.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a high-frequency noise compensation test method for memory chips, comprising: acquiring functional test configuration data of the memory chip under test, selecting a main test address and a co-test address grouped using the same data output line, determining the same-value interval bit and complementary read position in the continuous read bit sequence, writing main test data to the main test address, and writing co-test data to the co-test address that is bit-inverse of the main test data at the complementary read position and the same at the same-value interval bit, forming a mixed address group with the same line;

[0008] The same value interval position refers to the readout position in which the auxiliary test data and the main test data maintain the same bit value in the continuous readout sequence;

[0009] The complementary readout position refers to the readout position in the continuous readout sequence where the test data and the main test data have opposite bit values.

[0010] The so-called co-line mixed relationship address group refers to the address group formed by the main test address, the auxiliary test address and the corresponding written data according to the bit value relationship of the same value interval and complementary read position;

[0011] Continuously read the main test address and the companion test address, obtain the main test read words and the companion test read words, and compare them with the main test data and the companion test data to obtain the main test difference data and the companion test difference data;

[0012] The main test difference state refers to the state of no difference or the state of difference formed by comparing the main test readout character with the main test data bit by bit; the companion test difference state refers to the state of no difference or the state of difference formed by comparing the companion test readout character with the companion data bit by bit.

[0013] The co-line mixed holding value is calculated based on the number of positions that maintain opposite bit values ​​in the complementary readout positions and the total number of complementary readout positions, and the same value holding state is obtained based on the bit value relationship of the same value interval positions;

[0014] The co-line hybrid hold value refers to the ratio of the number of complementary readout positions that hold opposite bit values ​​to the total number of complementary readout positions;

[0015] If the main test difference status and the co-test difference status are different, the co-line mixed retention value reaches the co-line mixed permission limit, and the same value retention status is to maintain the same bit value, it is determined that the main test address is affected by the high frequency of the same line and compensation is passed; if the same value retention status is not to maintain the same bit value, the main test address is reread after increasing the read preparation interval; the functional test conclusion is generated by the main test read word after rereading and the difference retention status of the main test address at the same read position.

[0016] As a preferred embodiment of the high-frequency noise compensation test method for memory chips described in this invention, the functional test configuration data includes: an address mapping table, a data output line grouping table, a read burst length, memory row groups, memory page groups, memory block groups, test rate levels, functional test items, a basic read preparation interval, an interval increment step, and a maximum read preparation interval.

[0017] As a preferred embodiment of the high-frequency noise compensation testing method for memory chips described in this invention, the selection of the main test address and the co-test address using the same data output line grouping includes: determining the address for which read / write functionality needs to be determined in the current functional test project as the main test address; selecting addresses from the address mapping table that use the same data output line grouping as the main test address but are different from the memory row, memory page, and memory block where the main test address is located as co-test address candidates; when there are multiple co-test address candidates, selecting co-test addresses in descending order of physical memory block distance from the main test address; when there are no co-test address candidates, transferring the main test address to the normal functional test path.

[0018] As a preferred embodiment of the high-frequency noise compensation testing method for memory chips described in this invention, the step of determining the same-value skip position and complementary read position in the continuous read bit sequence includes: sequentially numbering the continuous output bits in a single read burst according to the read burst length to obtain the continuous read bit sequence; when the read burst length is odd, determining the middle read position of the continuous read bit sequence as the same-value skip position; when the read burst length is even, determining the read position near the middle of the continuous read bit sequence that is not at the first or last position as the same-value skip position; and determining the read positions other than the same-value skip positions as complementary read positions.

[0019] As a preferred embodiment of the high-frequency noise compensation testing method for memory chips described in this invention, the step of forming a co-line mixed address group includes: reading the bit values ​​of the main test data at each consecutive readout position; at the complementary readout position, setting the bit value of the auxiliary test data to the opposite bit value of the corresponding bit value of the main test data; at the same-value interval position, setting the bit value of the auxiliary test data to the same bit value as the corresponding bit value of the main test data; and forming a co-line mixed address group by the main test address, auxiliary test address, main test data, auxiliary data, complementary readout position, and same-value interval position.

[0020] As a preferred embodiment of the high-frequency noise compensation testing method for memory chips described in this invention, the main test difference data includes: main test difference state and main test difference position; the co-test difference data includes co-test difference state and co-test difference position; the main test readout word and the main test data are compared bit by bit in a continuous readout order; if the bit value of any readout position is different, the main test difference state is recorded as having a difference, and the readout positions corresponding to the different bit values ​​are recorded as the main test difference position; the co-test readout word and the co-test data are compared bit by bit in a continuous readout order; if the bit value of any readout position is different, the co-test difference state is recorded as having a difference, and the readout positions corresponding to the different bit values ​​are recorded as the co-test difference position.

[0021] As a preferred embodiment of the high-frequency noise compensation test method for memory chips described in this invention, the co-line mixed hold value includes: comparing the bit values ​​of the main test read word and the co-test read word at each complementary read position; counting the number of positions where the main test read word and the co-test read word maintain opposite bit values ​​at complementary read positions; taking the ratio of the number of positions maintaining opposite bit values ​​to the total number of complementary read positions as the co-line mixed hold value; comparing the bit values ​​of the main test read word and the co-test read word at the same value interval position, if they are the same, then the same value hold state is recorded as maintaining the same bit value, if they are different, then the same value hold state is recorded as not maintaining the same bit value.

[0022] As a preferred embodiment of the high-frequency noise compensation testing method for memory chips described in this invention, the generation of functional test conclusions includes: when the main test address is determined to be affected by high frequencies on the same line and compensation is passed, outputting a line-mixed relationship compensation pass conclusion; when the main test read word reread after increasing the read preparation interval is consistent with the main test data, outputting a high-frequency recovery pass conclusion; when the main test read word reread after increasing the read preparation interval still differs from the main test data at the same read position of the main test address, outputting a functional test failure conclusion; writing the line-mixed relationship address group, main test difference data, co-test difference data, line-mixed retention value, line-mixed permission limit, same value retention status, and functional test conclusions into the mass production test record; the high-frequency recovery pass conclusion includes a high-frequency occasional pass conclusion and a high-frequency bit-order sensitive pass conclusion.

[0023] In a second aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements any step of the high-frequency noise compensation test method for memory chips as described in the first aspect of the present invention.

[0024] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any step of the high-frequency noise compensation test method for memory chips as described in the first aspect of the present invention.

[0025] The beneficial effects of this invention are as follows: by setting up address groups for co-line mixed relationships and interval bits with the same value, it is possible to identify the common high-frequency influences of the same line without additional high-frequency waveform acquisition; by jointly judging the co-line mixed hold value, co-line mixed permission limit, and same value hold status, it is possible to distinguish between high-frequency misjudgment, bit sequence sensitivity, and actual functional abnormality; by selecting compensation pass, increasing the readout preparation interval, or reselecting the co-test address according to different judgment states, it is possible to reduce the false kill rate of high-frequency function testing of memory chips and improve test stability. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a flowchart of a high-frequency noise compensation test method for memory chips.

[0028] Figure 2 A schematic diagram for establishing a mixed address group on the same line.

[0029] Figure 3 This is a schematic diagram illustrating the determination of the continuous reading and maintenance state of mixed relationships on the same line.

[0030] Figure 4 A schematic diagram showing the selection of compensation processing methods and the generation of functional test conclusions.

[0031] Figure 5 A comparative data chart showing the residual anomaly detection rate under the compensation interpretation strategy.

[0032] Figure 6 This is a comparative data chart showing the false positive rate under high-frequency disturbances on the same line. Detailed Implementation

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0035] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0036] Reference Figures 1-6 This is one embodiment of the present invention, which provides a high-frequency noise compensation testing method for memory chips, including the following steps:

[0037] S1. Collect the functional test configuration data of the memory chip under test, select the main test address and the co-test address grouped using the same data output line, determine the same value interval bit and complementary read position in the continuous read bit sequence, write the main test data to the main test address, and write the co-test data to the co-test address that is bit-inverse of the main test data at the complementary read position and the same value interval bit, forming a mixed relationship address group on the same line.

[0038] The memory chip under test is connected to the test fixture of the ATE test equipment, and the ATE test equipment reads the functional test configuration data of the memory chip under test.

[0039] The functional test configuration data includes an address mapping table, a data output line grouping table, read burst length, storage row grouping, storage page grouping, storage block grouping, test rate level, functional test items, basic read preparation interval, interval increment step, and maximum read preparation interval.

[0040] It should be noted that the address mapping table is read from the address decoding configuration file in the mass production test program of the memory chip under test; the address mapping table is used to represent the mapping relationship between logical addresses and physical memory rows, physical memory pages, and physical memory blocks.

[0041] It should be noted that the data output line grouping table is jointly generated by the package pin table of the memory chip under test, the data bus connection table, and the ATE test channel configuration table. The generation process includes reading the pin number of each data pin in the package pin table, reading the data output line number connected to each data pin in the data bus connection table, and reading the interpretation channel number connected to each data output line in the ATE test channel configuration table. Data output lines connected to the same interpretation channel and continuously outputting in the same readout burst are grouped into the same data output line group to form the data output line grouping table.

[0042] It should be noted that the read burst length is read from the read command length in the current functional test item of the memory chip under test; the read burst length is used to represent the number of bits continuously output in a group on the same data output line during a continuous read; the test rate range is read from the clock frequency range of the current functional test item of the ATE test equipment; the basic read preparation interval is read from the read command interval parameter in the functional test item; and the maximum read preparation interval is read from the maximum read command interval allowed by the timing specification of the memory chip under test.

[0043] It should be noted that the interval increment step is obtained from the minimum stable interval increment required for a qualified sample of the same model to complete read recovery at the same test rate setting. The process includes selecting a qualified sample of the same model, and increasing the read preparation interval from the basic read preparation interval in increments according to the minimum interval adjustment unit supported by the ATE test equipment. Each time the read preparation interval is increased, the main test address read is performed continuously. When the data is consistent with the written data for a fixed number of consecutive reads, the difference between the current read preparation interval and the basic read preparation interval is taken as the minimum stable interval increment, and the minimum stable interval increment is taken as the interval increment step. The fixed number of reads ranges from three to five times, preferably three times, to eliminate the influence of occasional correct reads on the interval increment step.

[0044] Among them, the same value interval position refers to the reading position in which the auxiliary test data and the main test data maintain the same bit value in the continuous reading bit sequence;

[0045] Complementary readout position refers to the readout position in a continuous readout sequence where the test data and the main test data have opposite bit values.

[0046] The address group with the same line mixed relationship refers to the address group formed by the main test address, the auxiliary test address and the corresponding written data according to the bit value relationship of the same value interval and complementary read position;

[0047] The main test difference state refers to the state of no difference or the state of difference formed by comparing the main test readout character with the main test data bit by bit. The accompanying test difference state refers to the state of no difference or the state of difference formed by comparing the accompanying test readout character with the accompanying data bit by bit.

[0048] The co-line mixed hold value refers to the ratio of the number of complementary readout positions that hold opposite bit values ​​to the total number of complementary readout positions.

[0049] In a preferred embodiment, the interval increases by a step size that is an integer multiple of the readout burst clock cycle.

[0050] Furthermore, select the main test address from the functional test projects.

[0051] The main test address is the address where read / write functionality needs to be determined in the current functional test project.

[0052] Filter candidate test addresses from the address mapping table.

[0053] Among them, the candidate test addresses must simultaneously meet the following three conditions A1-A3:

[0054] A1: The candidate test addresses and the main test addresses are grouped using the same data output line;

[0055] A2: The candidate test address does not belong to the same storage row as the primary test address;

[0056] A3: The candidate test address does not belong to the same storage page and storage block as the primary test address.

[0057] It should be noted that the candidate test address and the primary test address use the same data output line group, so that the primary test address and the candidate test address pass through the same data output line group and the same judgment channel when read continuously; the candidate test address does not belong to the same storage row, the same storage page, and the same storage block as the primary test address, so that the candidate test address does not share the same local storage array area with the primary test address, thus avoiding the local storage array defects from affecting both the primary test address and the candidate test address at the same time.

[0058] When the number of candidate test addresses is greater than one, the candidate test addresses are arranged in descending order of their physical storage block distance from the primary test address, and the candidate test address ranked first is selected as the primary test address.

[0059] It should be noted that the physical storage block distance is the absolute value of the difference between the storage block number corresponding to the primary test address and the storage block number corresponding to the candidate test address. When the storage chip under test adopts a multi-level address mapping of storage surface, storage block, storage page and storage row, the physical storage block distance is determined first by the difference in storage block number. If the differences in storage block number are the same, they are then sorted by the difference in storage page number and the difference in storage row number in turn.

[0060] When two candidate test addresses are equidistant from the main test address in terms of physical storage block distance, the number of test exceptions for the two candidate test addresses in the historical mass production test records is read, and the candidate test address with the fewest test exceptions is selected as the test address.

[0061] When the number of abnormal tests is the same, the candidate test address with the smaller logical address number is selected as the test address.

[0062] When there are no suitable candidate test addresses, the ATE test equipment skips the process of establishing a mixed-relationship address group on the same line and transfers the main test address to the normal functional test path.

[0063] It should be noted that the normal functional test path is a test path that performs main test data writing, main test address reading, and main test read word comparison with main test data bit by bit according to the functional test items.

[0064] Furthermore, the sequential readout order is determined based on the readout burst length.

[0065] The sequential read bit sequence starts numbering from the first output bit of a read burst and ends at the last output bit of a read burst.

[0066] When the burst length is odd, the middle read position of the consecutive read position is selected as the same value interval position.

[0067] When the burst length is even, select a read position that is close to the middle of the continuous read sequence and is not the first or last position as the same value interval position.

[0068] In a preferred embodiment, when the readout burst length is even, the readout position before the middle segment is selected as the same value interval position.

[0069] The preceding and following read positions of the same value interval are both considered complementary read positions, and all read positions other than the same value interval are considered complementary read positions.

[0070] Furthermore, write the main test data to the main test address.

[0071] The main test data is generated from the test graphs in the functional test project. The test graphs include all-zero graphs, all-one graphs, checkerboard graphs, address-dependent graphs, and high-flip burst graphs.

[0072] Write the test data to the test address.

[0073] The process of generating the auxiliary test data includes reading the bit value of the main test data at each consecutive readout position; at the complementary readout position, setting the bit value of the auxiliary test data to the opposite bit value of the corresponding bit value of the main test data; and at the same value interval position, setting the bit value of the auxiliary test data to the same bit value as the corresponding bit value of the main test data.

[0074] The address group with the same line is formed by the main test address, the auxiliary test address, the main test data, the auxiliary test data, the complementary readout position, and the same value interval position.

[0075] S2. Continuously read the main test address and the auxiliary test address to obtain the main test read word and the auxiliary test read word, and compare them with the main test data and the auxiliary test data to obtain the main test difference data and the auxiliary test difference data. Calculate the co-line mixed holding value based on the number of positions that maintain opposite bit values ​​in the complementary read positions and the total number of complementary read positions, and obtain the same value holding status based on the bit value relationship of the same value interval positions.

[0076] The ATE test equipment first sends a read command to the master test address, receives the continuous output bits of the master test address on the same data output line group according to the read burst length, and arranges the continuous output bits according to the continuous read bit order to form the master test read word.

[0077] Furthermore, after the main test address read command is completed, the ATE test equipment does not insert erase / write, refresh, calibration, frequency reduction or other functional test items, but directly sends a read command to the auxiliary test address. It receives the continuous output bits of the auxiliary test address on the same data output line group according to the same read burst length, and arranges the continuous output bits according to the same continuous read bit order to form the auxiliary test read word.

[0078] It should be noted that no other functional test items are inserted between the main test address and the auxiliary test address in order to ensure that the main test read words and the auxiliary test read words pass through the same data output line group, the same judgment channel and adjacent read time periods, so as to avoid the intermediate operation changing the performance of the high frequency of the data output line.

[0079] Furthermore, the ATE test equipment compares the main test readout word with the main test data bit by bit according to the sequential readout bit order.

[0080] When the bit values ​​of the main test readout word are the same as the main test data at all consecutive readout positions, the main test difference state is recorded as no difference; when the bit value of the main test readout word at any consecutive readout position is different from the main test data, the main test difference state is recorded as a difference exists, and the main test difference position column is recorded, which includes the readout position number where the main test readout word is different from the main test data.

[0081] Furthermore, the ATE test equipment compares the read-out words with the read-out data bit by bit in the sequential read-out order.

[0082] When the bit value of the test word at all consecutive read positions is the same as the test data, the test difference state is recorded as no difference; when the bit value of the test word at any consecutive read position is different from the test data, the test difference state is recorded as a difference exists, and the test difference position column is recorded, which includes the read position number where the test word is different from the test data.

[0083] Furthermore, the ATE test equipment reads the complementary readout positions and compares the bit values ​​of the main test readout word and the co-test readout word at each complementary readout position.

[0084] When the primary test read value at a complementary read position is opposite to the secondary test read value, the ATE test equipment counts this complementary read position in the number of opposite hold positions; when the primary test read value at a complementary read position is the same as the secondary test read value, the ATE test equipment does not count this complementary read position in the number of opposite hold positions.

[0085] The number of complementary readout positions in which the primary readout word and the secondary readout word maintain opposite position values ​​is counted. The ratio of the number of complementary readout positions in which the primary readout word and the secondary readout word maintain opposite position values ​​to the total number of complementary readout positions is taken as the co-line mixed holding value.

[0086] Furthermore, the ATE test equipment reads the same-value interval bits and compares the bit value of the main test read word on the same-value interval bit with the bit value of the auxiliary test read word on the same-value interval bit.

[0087] When the position value of the main test readout word at the same interval position is the same as the position value of the auxiliary test readout word at the same interval position, the same value holding state is recorded as holding the same position value; when the position value of the main test readout word at the same interval position is different from the position value of the auxiliary test readout word at the same interval position, the same value holding state is recorded as not holding the same position value.

[0088] It should be noted that the same-value interval position is located in the middle of the continuous readout sequence. The same-value interval position is used together with the complementary readout position to distinguish two cases: when the complementary readout position maintains the opposite bit value relationship and the same-value interval position maintains the same bit value, the mixed relationship between the main test readout word and the co-test readout word still holds; when the complementary readout position maintains the opposite bit value relationship but the same-value interval position does not maintain the same bit value, the main test address is more likely to be sensitive to the high-frequency readout sequence.

[0089] When the co-line mixing hold value is not less than the co-line mixing permissible limit, the ATE test equipment records the co-line mixing hold status as having reached the permissible limit; when the co-line mixing hold value is less than the co-line mixing permissible limit, the ATE test equipment records the co-line mixing hold status as having not reached the permissible limit.

[0090] It should be noted that the permissible limit for co-line mixing is obtained by performing co-line mixing relationship readings on qualified samples of the same model at the same test rate level, the same data output line grouping, and the same readout burst length, calculating the co-line mixing hold value for each time, sorting it from smallest to largest, and reading the value at the first quartile position. The value range is from 0.80 to 1.00.

[0091] S3. If the main test difference status and the auxiliary test difference status are different, the co-line mixed maintenance value reaches the co-line mixed permissible limit, and the same value maintenance status is maintaining the same bit value, it is determined that the main test address is affected by the high frequency of the same line and compensation is passed. If the same value maintenance status is not maintaining the same bit value, the main test address is reread after increasing the read preparation interval.

[0092] Furthermore, the ATE testing equipment first determines the main test difference status.

[0093] When the main test difference status is no difference, it means that the bit values ​​of the main test read words and the main test data are consistent in all continuous read positions. The ATE test equipment records the main test address as the functional test pass address and further judges the difference status of the auxiliary test.

[0094] When the main test difference status is "no difference" and the companion test difference status is "difference exists", the ATE test equipment will not continue to use the companion test address as a candidate companion test address for the subsequent main test address, and will record the companion test address in the companion test address abnormal candidate table.

[0095] It should be noted that the main test address has been read correctly. The difference in the reading of the companion test address does not affect the functional test judgment of the main test address. However, the companion test address will no longer participate in the subsequent companion test judgment to avoid the companion test address's own abnormality from affecting the subsequent judgment of the mixed relationship of the same line.

[0096] When the main test difference status is "difference exists" and the co-test difference status is "no difference", it indicates that a single address read difference has occurred in the main test address. The ATE test equipment keeps the main test address, main test data, test rate level and basic read preparation interval unchanged, and performs a fixed number of repeated reads (e.g., three times) on the main test address to obtain the main test read words after repeated reads.

[0097] It should be noted that the fixed number of reads is three to eliminate occasional flips during a single high-frequency read, and to avoid excessive repeated reads that would increase mass production test time. When only one read is performed, a single read recovery can easily be mistaken for a stable main test address. When the number of reads exceeds three, the mass production test cycle time increases significantly.

[0098] If the main test read word after repeated reading is still different from the main test data at the same read position in the main test difference column, the ATE test equipment will list the main test address as a function abnormal address and record the processing method of the main test address as a function abnormality.

[0099] When the main test read word after repeated reading matches the main test data, the ATE test equipment classifies the main test address as a high-frequency, intermittent address, and determines the increased read preparation interval based on the basic read preparation interval, the interval increment step, and the maximum read preparation interval. The expression is:

[0100] ;

[0101] in, This indicates the increased read preparation interval. Indicates the basic readout preparation interval. This indicates that the interval increases by a step size. This indicates the maximum read-out preparation interval.

[0102] It should be noted that the increased read preparation interval is executed only once and does not increase cyclically according to the interval increment step; when the interval increment step is zero, the increased read preparation interval is equal to the basic read preparation interval; when the basic read preparation interval is greater than or equal to the maximum read preparation interval, the increased read preparation interval is equal to the maximum read preparation interval.

[0103] The ATE test equipment reads the main test address again according to the increased read preparation interval, obtains the main test read word after the increased interval, and records the processing method of the main test address as high-frequency intermittent pending processing.

[0104] When both the main test difference status and the auxiliary test difference status show differences, the ATE test equipment further reads the same-line mixed hold status and same-value hold status.

[0105] When the same line mixed holding state reaches the permissible limit and the same value holding state maintains the same bit value, it means that although the main test read word and the auxiliary test read word are different from the written data, the main test read word and the auxiliary test read word still maintain the opposite bit value relationship at the complementary read position, and still maintain the same bit value relationship at the same value interval position.

[0106] The ATE test equipment determines the difference in reading of the main test address as an abnormality caused by the combined influence of high frequency on the same data output line. It does not list the main test address as a function failure address, and records the processing method of the main test address as a compensation pass for the mixed relationship of the same line.

[0107] It should be noted that passing the mixed-relationship compensation test does not mean directly ignoring read differences. Instead, when the main test difference state, the auxiliary test difference state, the mixed-retention state of the same line, and the same-value retention state all meet the limiting relationship, the mixed bit value relationship retained by the main test read word and the auxiliary test read word in the same data output line group is used to eliminate misjudgments caused by the common influence of the same high frequency of the same data output line. Passing the mixed-relationship compensation test is not the same as passing the normal function test. The ATE test equipment marks the main test address as the compensation pass address and writes the compensation pass address, main test difference bit column, auxiliary test difference bit column, mixed-retention value of the same line, same-value retention state, and test rate level into the mass production test record. The mass production test record sets different judgment marks for passing the normal function test and passing the mixed-relationship compensation test, so that subsequent sampling inspection, verification, or same-model test calls can distinguish between the normal read correct address and the address that has passed the mixed-relationship compensation test.

[0108] When the same line mixed holding state reaches the permissible limit, and the same value holding state does not maintain the same bit value, it means that the complementary readout positions still maintain the opposite bit value relationship, but the same value skipped positions do not maintain the same bit value relationship.

[0109] The ATE test equipment lists the main test address as a high-frequency bit-sensitive address and determines the read preparation interval after the increase. The ATE test equipment rereads the main test address according to the increased read preparation interval to obtain the main test read word after the increased interval, and records the processing method of the main test address as high-frequency bit-sensitive pending processing.

[0110] It should be noted that the same-value interval position is located in the middle of the continuous readout position sequence. When the same-value interval position does not maintain the same position value while the complementary readout position still maintains the opposite position value, it indicates that the overall complementary relationship between the main test readout word and the auxiliary test readout word has not been completely destroyed, but the middle interval position has undergone sensitive changes. Therefore, by increasing the readout preparation interval, it can be determined whether the main test address can be restored to stable readout.

[0111] When the co-line mixed state is not within the permissible limit and the same value state is maintaining the same bit value, the ATE test equipment determines that the co-line mixed relationship formed by the auxiliary test address and the main test address is insufficient to support the compensation judgment, and reselects a new auxiliary test address that uses the same data output line group as the main test address.

[0112] The selection method for the new test address includes: filtering addresses from the address mapping table that use the same data output line group, different storage row, different storage page, and different storage block as the main test address; removing addresses that have already been recorded in the test address anomaly candidate table; and sorting the remaining addresses from largest to smallest according to their physical storage block distance from the main test address, and selecting the address that ranks first as the new test address.

[0113] It should be noted that the candidate list of abnormal test addresses is only used to restrict addresses from continuing to be used as test addresses, and does not indicate that the address itself is a functionally abnormal address; the corresponding address can still be used as the main test address to perform normal functional tests independently.

[0114] Furthermore, the ATE test equipment writes new test data to the new test address.

[0115] Among them, the new test data complements the main test data bit by bit at the complementary readout position, and maintains the same bit value as the main test data at the same interval position.

[0116] The ATE test equipment re-executes the same-line mixed relationship reading to obtain the new companion test main test difference status, the new companion test difference status, the new companion test same-line mixed retention value, and the new companion test same value retention status.

[0117] When the new companion test status indicates that the main test address no longer shows the same read position difference in the main test difference column, the ATE test equipment will list the original companion test address as the companion test address mismatch address and record the processing method of the main test address as companion test address mismatch exclusion.

[0118] When the new test subject difference status indicates that the main test address still has a difference in the same read position in the main test difference column, the ATE test equipment will list the main test address as a function abnormal address and record the processing method of the main test address as a function abnormality.

[0119] When the co-line mixed holding state is not within the permissible limit and the same value holding state is not maintaining the same bit value, it means that the opposite bit value relationship of the complementary readout position and the same bit value relationship of the same value interval position are both destroyed. The ATE test equipment will list the main test address as a functional abnormal address and record the processing method of the main test address as a functional abnormality.

[0120] S4. Generate functional test conclusions by observing the differences between the main test readout words and the main test address at the same readout position after rereading.

[0121] Furthermore, when the main test address is processed in the manner of functional test passing, the ATE test equipment confirms that the bit values ​​of the main test read word and the main test data are consistent in all consecutive read positions, and outputs the conclusion that the functional test has passed.

[0122] When the processing method of the main test address is "compensation for mixed line relationship passes", the ATE test equipment confirms that both the main test difference status and the auxiliary test difference status have differences, confirms that the mixed line maintenance status has reached the permissible limit, confirms that the same value maintenance status has maintained the same bit value, and outputs the conclusion that the mixed line relationship compensation passes.

[0123] It should be noted that the conclusion of the co-line mixed relationship compensation does not directly ignore the read difference. Instead, when read differences occur in both the main test address and the co-test address, it uses the complementary read position opposite bit value relationship and the same value interval bit same bit value relationship retained on the same data output line group to confirm that the read difference is caused by the common influence of the same high frequency of the same data output line, thereby avoiding directly listing the main test address as the function failure address.

[0124] When the main test address is processed as a high-frequency intermittent pending event, the ATE test equipment reads the main test readout word with the added interval, and compares the main test readout word with the main test data bit by bit according to the continuous readout bit order.

[0125] If the bit values ​​of the main test readout word after the interval is increased are consistent with the main test data at all consecutive readout positions, the ATE test equipment outputs a high-frequency intermittent pass conclusion.

[0126] If the main test readout word after adding the interval is still different from the main test data in the same readout position in the main test difference column, the ATE test equipment outputs a functional test failure conclusion.

[0127] When the main test address is processed in a high-frequency bit-sequence sensitive pending mode, the ATE test equipment reads the main test readout word with the added interval, and compares the main test readout word with the main test data bit by bit according to the continuous readout bit sequence.

[0128] If the bit values ​​of the main test readout word after the interval is increased are consistent with the main test data at all consecutive readout positions, the ATE test equipment outputs a high-frequency bit sequence sensitive pass conclusion.

[0129] If the main test readout word after adding the interval is still different from the main test data in the same readout position in the main test difference column, the ATE test equipment outputs a functional test failure conclusion.

[0130] It should be noted that both the high-frequency occasional pass conclusion and the high-frequency bit-sequence sensitive pass conclusion require confirmation by reading again after increasing the read preparation interval; reading again after increasing the read preparation interval can determine whether the read difference of the main test address disappears as the read preparation time recovers, avoiding misjudgment caused by a single repeated read; the high-frequency occasional pass conclusion and the high-frequency bit-sequence sensitive pass conclusion together constitute the high-frequency pass conclusion.

[0131] When the primary test address is handled by eliminating the mismatch between the primary and secondary test addresses, the ATE test equipment reads the new secondary test primary test difference status, the new secondary test difference status, the new secondary test co-line mixed hold value, and the new secondary test same value hold status.

[0132] If the new companion test status indicates that the main test address no longer shows the same read position difference in the main test difference column, the ATE test device outputs the companion test address mismatch exclusion conclusion and writes the original companion test address into the companion test address anomaly candidate table; then the ATE test device replaces the original companion test address with the new companion test address and continues to execute subsequent functional test items.

[0133] If the new test subject shows a difference in the main test status, indicating that the main test address still has a difference in the same read position in the main test difference column, the ATE test device will output a functional test failure conclusion.

[0134] When the main test address is processed as a functional abnormality, the ATE test equipment confirms that the main test address still shows the same read position difference in repeated readings, readings after increasing the read preparation interval, or continuous readings of a new auxiliary test address, and outputs a functional test failure conclusion.

[0135] Furthermore, the ATE test equipment writes the test results of the same-line mixed address group, main test difference status, auxiliary test difference status, main test difference column, auxiliary test difference column, same-line mixed hold value, same-line mixed allowable limit, same value hold status, main test address processing method, and high-frequency noise compensation function into the mass production test record.

[0136] Among them, the mass production test records are indexed according to the model of the memory chip under test, the grouping of data output lines, the test rate level, and the read burst length.

[0137] When performing functional tests on memory chips of the same model under the same data output line grouping, the same test rate level, and the same read burst length, the ATE test equipment will prioritize calling the same line mixed relationship address group that has already formed a mixed relationship compensation conclusion.

[0138] like Figure 5 As shown, the residual anomaly detection rate changes with the number of rereading rounds after implementing the compensation and interpretation strategy. Without in-line compensation, the residual anomaly detection rate decreases slowly, indicating that the common effects of high frequencies will continue to be interpreted as functional anomalies. Only the in-line mixed interpretation method can use the bit value relationship between the main test address and the co-test address to eliminate some misjudgments, but residual anomalies still exist in scenarios with the same value interval position anomaly and bit order sensitivity. The method of this invention performs compensation when the in-line mixed retention value reaches the permissible limit and the same value retention state is established. When the same value interval position does not maintain the same bit value, the readout preparation interval is increased and the main test address is reread. The functional test conclusion is generated by combining the retention of the same readout position difference. Therefore, the residual anomaly detection rate decreases faster and the fluctuation is smaller in the later stage, which shows the effect of improving the stability of high frequency functional testing.

[0139] like Figure 6As shown, the false positive rate changes of different judgment methods before and after the introduction of high-frequency disturbances on the same line. Before the disturbance, the false positive rates of the three methods were all at a low level. After the disturbance, the traditional direct error judgment method, which judges based solely on the difference in reading from the main test address, saw its false positive rate rise rapidly and remain high for a long time. The method of simply increasing the reading preparation interval can alleviate some high-frequency reading anomalies, but it lacks verification of the co-line mixed relationship between the main test address and the co-test address, and the false positive rate still fluctuates significantly. The method of this invention establishes the co-line mixed relationship through complementary reading positions and same-value interval positions, and uses the co-line mixed hold value and same-value hold state for joint judgment, so that the common high-frequency influence can be distinguished from the real functional anomaly. The false positive rate drops rapidly after the disturbance and remains low, demonstrating the effect of reducing the false positive rate in mass production testing.

[0140] This embodiment also provides a computer device applicable to a high-frequency noise compensation test method for memory chips, comprising: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the high-frequency noise compensation test method for memory chips as proposed in the above embodiment.

[0141] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0142] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the high-frequency noise compensation test method for memory chips as proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0143] In summary, this invention achieves the identification of common high-frequency influences on the same line without additional high-frequency waveform acquisition by setting up address groups for mixed relationships on the same line and interval bits for the same value; it achieves the differentiation between high-frequency misjudgments, bit sequence sensitivity, and actual functional abnormalities by jointly judging the mixed holding value, mixed permission limit, and same value holding status on the same line; and it reduces the false alarm rate and improves the test stability of high-frequency function testing of memory chips by selecting compensation pass, increasing the read preparation interval, or reselecting the co-test address according to different judgment states.

[0144] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high-frequency noise compensation test method for memory chips, characterized in that, include: Collect functional test configuration data of the memory chip under test, select the main test address and the co-test address grouped using the same data output line, determine the same value interval bit and complementary read position in the continuous read bit sequence, write the main test data to the main test address, and write the co-test data to the co-test address that is bit-inverse of the main test data at the complementary read position and the same value interval bit, forming a mixed relationship address group on the same line. The same value interval position refers to the readout position in which the auxiliary test data and the main test data maintain the same bit value in the continuous readout sequence; The complementary readout position refers to the readout position in the continuous readout sequence where the test data and the main test data have opposite bit values. The so-called co-line mixed relationship address group refers to the address group formed by the main test address, the auxiliary test address and the corresponding written data according to the bit value relationship of the same value interval and complementary read position; Continuously read the main test address and the companion test address, obtain the main test read words and the companion test read words, and compare them with the main test data and the companion test data to obtain the main test difference data and the companion test difference data; The main test difference state refers to the state of no difference or the state of difference formed by comparing the main test readout character with the main test data bit by bit; the companion test difference state refers to the state of no difference or the state of difference formed by comparing the companion test readout character with the companion data bit by bit. The co-line mixed holding value is calculated based on the number of positions that maintain opposite bit values ​​in the complementary readout positions and the total number of complementary readout positions, and the same value holding state is obtained based on the bit value relationship of the same value interval positions; The co-line hybrid hold value refers to the ratio of the number of complementary readout positions that hold opposite bit values ​​to the total number of complementary readout positions; If the main test difference status and the companion test difference status are both different, the co-line mixed maintenance value reaches the co-line mixed permission limit and the same value maintenance status is to maintain the same bit value, it is determined that the main test address is affected by the high frequency of the same line and compensation is passed. If the same value is not maintained, the main test address is reread after increasing the read preparation interval; Functional test conclusions are generated by rereading the main test words and maintaining the differences in the main test address at the same read position.

2. The high-frequency noise compensation test method for memory chips as described in claim 1, characterized in that, The functional test configuration data includes: address mapping table, data output line grouping table, read burst length, storage row grouping, storage page grouping, storage block grouping, test rate level, functional test items, basic read preparation interval, interval increment step, and maximum read preparation interval.

3. The high-frequency noise compensation test method for memory chips as described in claim 2, characterized in that, The selection of the primary test address and secondary test address that use the same data output line for grouping includes: The address that needs to be determined for read / write functionality in the current functional test project will be designated as the main test address. From the address mapping table, select addresses that use the same data output line group as the main test address, but are different from the main test address in terms of storage row, storage page, and storage block as candidate co-test addresses; When there are multiple candidate test addresses, the test addresses are selected in descending order of their physical storage block distance from the primary test address. When there are no candidate test addresses, the main test address will be redirected to the normal functional test path.

4. The high-frequency noise compensation test method for memory chips as described in claim 2, characterized in that, Determining the same-value interval position and complementary readout position in the continuous readout sequence includes: The consecutive output bits in a single read burst are sequentially numbered according to the read burst length to obtain the consecutive read bit sequence. When the burst length is odd, the middle read position of the consecutive read position is determined as the same value interval position; When the burst length is even, the read position that is close to the middle of the continuous read position sequence and is not at the first or last position is determined as the same value interval position; Readout positions other than those with the same value and interval are designated as complementary readout positions.

5. The high-frequency noise compensation test method for memory chips as described in claim 1 or 4, characterized in that, The address group forming the same line mixed relationship includes: Read the bit values ​​of the main test data at each consecutive readout position; At the complementary readout position, the bit value of the test data is set to the opposite bit value of the corresponding bit value of the master test data; At the same interval position, the bit value of the auxiliary test data is set to the same bit value as the corresponding bit value of the main test data; The address group with the same line is formed by the main test address, the auxiliary test address, the main test data, the auxiliary test data, the complementary readout position, and the same value interval position.

6. The high-frequency noise compensation test method for memory chips as described in claim 1, characterized in that, The main test difference data includes: the main test difference status and the main test difference position; The accompanying test difference data includes the accompanying test difference status and the accompanying test difference ranking; The main test readout word and the main test data are compared bit by bit in the continuous readout position. If the bit value of any readout position is different, the main test difference state is recorded as a difference exists, and the readout position corresponding to the different bit value is recorded as the main test difference position. The test words are compared with the test data in the order of consecutive readings. If the value of any reading position is different, the test difference state is recorded as a difference, and the reading positions corresponding to the different values ​​are recorded as the test difference column.

7. The high-frequency noise compensation test method for memory chips as described in claim 1 or 6, characterized in that, The co-line mixing retention value includes: Compare the position values ​​of the primary and secondary readout words at each complementary readout position; Count the number of positions where the main test word and the accompanying test word maintain opposite position values ​​at complementary readout positions; The ratio of the number of positions that retain opposite bit values ​​to the total number of complementary readout positions is used as the co-line mixed hold value; Compare the position values ​​of the main test readout and the auxiliary test readout at the same interval position. If they are the same, the same position state is recorded as "maintaining the same position value". If they are different, the same position state is recorded as "not maintaining the same position value".

8. The high-frequency noise compensation test method for memory chips as described in claim 1, characterized in that, The conclusions of the generation function test include: When the main test address is determined to be affected by high frequencies on the same line and compensation is passed, the conclusion that compensation for mixed relationships on the same line is passed is output. When the main test readout word reread after increasing the readout preparation interval is consistent with the main test data, the high-frequency recovery pass conclusion is output. If the main test read word reread after increasing the read preparation interval still differs from the main test data at the same read position of the main test address, the function test conclusion is output as "failed". Write the address group of the same line mixed relationship, the main test difference data, the companion test difference data, the same line mixed retention value, the same line mixed permission limit, the same value retention status and the functional test conclusion into the mass production test record. The high-frequency recovery pass conclusions include high-frequency occasional pass conclusions and high-frequency position-sensitive pass conclusions.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the high-frequency noise compensation test method for memory chips as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the high-frequency noise compensation test method for memory chips as described in any one of claims 1 to 8.

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