Memory device

Abstract

A memory device includes a circuit board, a memory die, a plurality of connection resistors and a plurality of measurement contacts. The circuit board includes a plurality of conductive layers. The memory die is disposed on the circuit board and electrically connected to the plurality of conductive layers. The connection resistors are disposed within the circuit board and electrically connected to one of the plurality of conductive layers. The measurement contacts are disposed on the circuit board, wherein each of the plurality of measurement contacts is electrically connected to the memory die through one of the plurality of connection resistors. Accordingly, the measurement efficiency can be effectively improved and the memory device can be prevented from being damaged due to disassembly.

Description

Technical Field

[0001] This invention relates to a memory device. Background Technology

[0002] In the memory industry, quality verification is an indispensable step. Because certain areas of the memory may have structural defects that affect its operation, measurement procedures are required to verify its operational performance by measuring the signals during memory operation. Summary of the Invention

[0003] This invention relates to a memory device, comprising a circuit board, a memory chip, a plurality of connection resistors, and a plurality of measurement contacts. The circuit board includes a plurality of conductive layers. The memory chip is disposed on the circuit board and electrically connected to the plurality of conductive layers. Connection resistors are disposed within the circuit board and electrically connected to one of the plurality of conductive layers. Measurement contacts are disposed on the circuit board, each of the plurality of measurement contacts being electrically connected to the memory chip through one of the plurality of connection resistors.

[0004] In one embodiment, the plurality of measurement contacts include a plurality of high-frequency contacts and a plurality of low-frequency contacts, wherein the frequency of the signals transmitted by the plurality of high-frequency contacts is higher than the frequency of the signals transmitted by the plurality of low-frequency contacts, and the plurality of high-frequency contacts are located between the plurality of low-frequency contacts and the memory chip.

[0005] In one embodiment, the plurality of high-frequency contacts have a first spacing and the plurality of low-frequency contacts have a second spacing, wherein the first spacing is smaller than the second spacing.

[0006] In one embodiment, the first spacing is between 0.5 and 0.8 mm.

[0007] In one embodiment, the second spacing is between 0.6 and 1 mm.

[0008] In one embodiment, the plurality of low-frequency contacts, the plurality of high-frequency contacts, and the plurality of connection resistors are arranged along a first direction, and the distribution width of the plurality of measurement contacts is less than or equal to the width of the memory chip.

[0009] In one embodiment, the circuit board has multiple traces, and the multiple measurement contacts are disposed in a first measurement area between one side of the circuit board and the memory chip, and there are no multiple traces in the first measurement area.

[0010] In one embodiment, each of the plurality of connection resistors is less than 200 ohms.

[0011] In one embodiment, a portion of one of the plurality of conductive layers is exposed on the surface of the circuit board to serve as the plurality of measurement contacts.

[0012] In one embodiment, a portion of one of the plurality of conductive layers is exposed in a second measurement area of ​​the circuit board, the second measurement area being located between the edge connector interface of the memory chip and the memory device.

[0013] The present invention also relates to a memory device comprising a circuit board, a memory chip, and a plurality of measurement contacts. The circuit board includes a plurality of conductive layers. The memory chip is disposed on the circuit board and electrically connected to the plurality of conductive layers. Measurement contacts are disposed in a first measurement area of ​​the circuit board. Each of the plurality of measurement contacts is electrically connected to the memory chip via a connection resistor and at least one of the plurality of conductive layers. A portion of one of the plurality of conductive layers is exposed in a second measurement area of ​​the circuit board to form a conductive contact, and the memory chip is located between the first measurement area and the second measurement area.

[0014] In one embodiment, the plurality of measurement contacts include a plurality of high-frequency contacts and a plurality of low-frequency contacts, wherein the frequency of the signals transmitted by the plurality of high-frequency contacts is higher than the frequency of the signals transmitted by the plurality of low-frequency contacts, and the plurality of high-frequency contacts are located between the plurality of low-frequency contacts and the memory chip.

[0015] In one embodiment, the plurality of high-frequency contacts have a first spacing and the plurality of low-frequency contacts have a second spacing, wherein the first spacing is smaller than the second spacing.

[0016] In one embodiment, the first spacing is between 0.5 and 0.8 mm.

[0017] In one embodiment, the second spacing is between 0.6 and 1 mm.

[0018] In one embodiment, the plurality of low-frequency contacts, the plurality of high-frequency contacts, and the memory chip are arranged along a first direction, and the distribution width of the plurality of measurement contacts is less than or equal to the width of the memory chip.

[0019] In one embodiment, the circuit board has multiple traces, a first measurement area is located on one side of the circuit board between the circuit board and the memory chip, and the multiple traces are not present in the first measurement area.

[0020] In one embodiment, the connection resistance is less than 200 ohms.

[0021] In one embodiment, another portion of one of the plurality of conductive layers is exposed on the surface of the circuit board to serve as the plurality of measurement contacts.

[0022] In one embodiment, the second measurement area is located between the edge connector interface of the memory chip and the memory device. Attached Figure Description

[0023] Figure 1A This is a schematic diagram of a memory device according to a partial embodiment of the present invention.

[0024] Figure 1B This is a schematic diagram of a memory device according to a partial embodiment of the present invention.

[0025] Figure 1C This is a partial schematic diagram of a memory device according to a partial embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of a memory device according to a partial embodiment of the present invention. Detailed Implementation

[0027] Embodiments of the present invention will be described below with reference to the accompanying drawings, but these embodiments are not intended to limit the scope of the invention. Furthermore, the operation of the structures in this invention is not intended to limit the order of implementation. Any device with equivalent function resulting from a structure composed of reconfigurable elements is included within the scope of this invention. The accompanying drawings are for illustrative purposes only and do not limit actual dimensions.

[0028] In this document, when an element is referred to as a “connection” or “coupled,” it may mean an “electrical connection” or “electrical coupling.” “Connection” or “coupled” can also be used to indicate the operation or interaction between two or more elements. Furthermore, although terms such as “first,” “second,” etc., are used herein to describe different elements, these terms are merely used to distinguish elements or operations described using the same technical terms. Unless the context clearly indicates otherwise, these terms do not specifically refer to or imply any order or sequence, nor are they intended to limit the invention.

[0029] Figure 1A The diagram shown is a schematic representation of a memory device 100 according to a partial embodiment of the present invention. The memory device 100 includes a circuit board 110 and one or more memory chips 120. The memory chips 120 are disposed on the circuit board 110, and each memory chip 120 may include peripheral circuitry / control circuitry or one or more memory arrays.

[0030] In one embodiment, the memory array in the memory chip 120 may be implemented by DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or NAND Flash (Not-AND Flash Memory).

[0031] In some embodiments, the memory device 100 further includes an edge connector interface 130 (commonly known as a gold finger). The memory device 100 can be coupled (e.g., mounted or plugged) to an electronic device ED (e.g., a motherboard) via the edge connector interface 130 to enable the memory device 100 to read and write data with the electronic device ED.

[0032] The aforementioned edge connector interface consists of a plurality of conductive terminals arranged on one side of the circuit board 110. The conductive terminals may be formed by etching a conductive layer within the circuit board 110. During installation, the edge connector interface 130 may be inserted into a corresponding slot on the electronic device ED, so that the conductive terminals form an electrical connection with the elastic contacts within the slot, thereby establishing a power and signal connection between the memory device 100 and the electronic device ED.

[0033] Before the memory device 100 leaves the factory, the manufacturer will measure the memory device 100 to verify its performance. For example... Figure 1A As shown, the memory device 100 is electrically connected to the measurement device MD (e.g., an oscilloscope). In test mode, the electronic device ED issues operation commands to the memory device 100, and the measurement device MD measures the signal changes at one or more locations between the memory chip 120 and the electronic device ED to determine whether the signal integrity meets expectations and whether the memory device 100 has electrical defects or design flaws.

[0034] However, the aforementioned measurements require desoldering the memory device 100 to couple it to the measurement device MD using an interpose card. Since desoldering necessitates high-temperature resoldering of the memory chip 120, it may damage the memory chip 120. In other words, the aforementioned measurements are not only time-consuming but may also damage the memory chip 120.

[0035] This invention modifies the structure of the memory device 100 by configuring multiple measurement contacts on it. During measurement, the memory device 100 can be electrically connected to the measurement device MD via these measurement contacts without the need for an additional adapter card. This minimizes potential signal interference during measurement and improves measurement efficiency and accuracy.

[0036] The structure of the memory device 100 provided by the present invention is described below. Please refer to [link / reference]. Figures 1A to 1C ,in Figure 1B The diagram shown is a schematic representation of a memory device 100 according to a partial embodiment of the present invention. Figure 1CThis is a partial schematic diagram of the memory device 100. The memory device 100 includes a circuit board 110, one or more memory chips 120, an edge connector interface 130, multiple connection resistors 140, and multiple measurement contacts 150.

[0037] The circuit board 110 may be a printed circuit board containing multiple conductive layers. The circuit board 110 is used to form multiple traces on its surface and inside to transmit power or signals. Figure 2 The diagram shows a circuit board 110 according to a partial embodiment of the present invention. In this embodiment, the circuit board 110 includes a plurality of conductive layers 210A to 210C and has traces 230 formed thereon. The plurality of conductive layers 210A to 210C are separated by an insulating material 220.

[0038] Memory chip 120 (e.g.) Figure 1C The memory chips 121-123 shown are disposed on the circuit board 110 and electrically connected to conductive layers 210A-210C. An edge connector interface 130 is disposed adjacent to the memory chip 120, such as... Figure 1B The bottom end is shown.

[0039] A connection resistor 140 is disposed inside the circuit board 110 and electrically connected to at least one conductive layer (e.g., connected to a trace). The impedance value of the connection resistor 140 is matched to the measurement path to control the strength of the measurement signal. In one embodiment, the impedance value of the connection resistor 140 is less than 200 ohms, for example, 100 ohms.

[0040] Measurement contacts 150 are disposed on circuit board 110, and each measurement contact is electrically connected to a corresponding memory chip 120 through a corresponding connection resistor 140 and a conductive layer. In other words, each measurement contact corresponds to a connection resistor and a memory chip 120. Since those skilled in the art will understand that the connection resistor 140 is connected to the memory chip 120 and the measurement contact 150 via traces, therefore... Figure 1B The relative positions of the connecting resistor 140, the memory chip 120, and the measurement contact 150 are shown in a simplified manner.

[0041] In one embodiment, all measurement contacts 150 are connected to the same conductive layer to correspond to the same reference potential. In another embodiment, the measurement contacts 150 may be connected to different conductive layers, but the conductive layers connected to the measurement contacts 150 belong to the same reference potential to ensure correct measurement.

[0042] By directly configuring the measurement contact 150 on the circuit board 110, the memory chip 120 can be electrically connected to the measurement device MD via the measurement contact 150 without desoldering the memory chip 120. This effectively improves measurement efficiency and prevents damage to the memory device 100 due to desoldering.

[0043] In one embodiment, the measurement contact 150 is disposed in a first measurement area on the circuit board 110. For example... Figure 1B As shown, the first measurement area can be one side of the circuit board 110 (e.g.: Figure 1B The area between the top of the circuit board 110 and the memory chip 120. No traces will be placed in the portion of the circuit board 110 corresponding to the first measurement area. In other words, there will be no traces in the first measurement area.

[0044] In one embodiment, the memory device 100 further includes a conductive contact 160. The conductive contact 160 is disposed in a second measurement area on the circuit board 110 and can be electrically connected to at least one memory chip 120 via a conductive layer to serve as an auxiliary contact during measurement. No traces will be provided in the portion of the circuit board 110 corresponding to the second measurement area. In one embodiment, the contact area of ​​the conductive contact 160 is larger than the contact area of ​​the measurement contact 150.

[0045] like Figure 1B As shown, the second measurement area can be the other side of the circuit board 110 (e.g.: Figure 1B The area between the bottom end shown and the memory chip 120. In other words, the conductive contact 160 (second measurement area) is located between the edge connector interface 130 and the memory chip 120, and the first measurement area and the second measurement area are located on two corresponding sides of the memory chip 120, respectively.

[0046] Specifically, in some embodiments, one of the conductive layers of the circuit board 110 may be partially exposed on the surface of the circuit board 110 to serve as a measurement contact 150 or a conductive contact 160. For example... Figure 2 As shown, a portion of the conductive layer 210A (such as the conductive portion 240) may be exposed on the first measurement area of ​​the circuit board 110, in order to serve as Figure 1B The measurement contact 150 is shown. Similarly, another portion of the conductive layer 210A (such as the conductive portion 240) may be exposed on the circuit board 110 to serve as a second measurement area. Figure 1B The conductive contact 160 is shown.

[0047] Please see Figure 1B and Figure 1C In some embodiments, the measurement contact 150 includes a plurality of high-frequency contacts 151 (e.g., Figure 1CThe high-frequency contacts 151A and 151C shown) and multiple low-frequency contacts 152 (as shown) Figure 1C (As shown in the low-frequency contact 152A). The frequency of the signal transmitted by the high-frequency contact 151 is higher than the frequency of the signal transmitted by the low-frequency contact 152, and the high-frequency contact 151 is located between the low-frequency contact 152 and the memory chip 120.

[0048] Because high-frequency signals decay more rapidly with transmission distance, positioning the high-frequency contact 151 closer to the memory chip 120 ensures measurement accuracy. Furthermore, the number of high-frequency contacts 151 and low-frequency contacts 152 can be adjusted according to circuit characteristics or measurement requirements, and is not limited to... Figure 1B The quantity shown is limited.

[0049] like Figure 1C As shown, memory chip 121 corresponds to connection resistor 141, high-frequency contact 151A, and low-frequency contact 152A. Memory chip 121 also corresponds to connection resistor 143 and high-frequency contact 151C. A first spacing D1 exists between the plurality of high-frequency contacts, and a second spacing D2 exists between the plurality of low-frequency contacts, with the first spacing D1 being smaller than the second spacing D2. For example, the first spacing D1 is between 0.5 and 0.8 mm, and the second spacing D2 is between 0.6 and 1 mm.

[0050] In some embodiments, the corresponding low-frequency contact 152A, high-frequency contact 151A, connection resistor 141, and memory chip 121 are along a first direction (e.g., Figure 1C The measurement contacts (low-frequency contact 152A or high-frequency contact 151A) are arranged in a vertical direction as shown, and the distribution width of the measurement contacts (low-frequency contact 152A or high-frequency contact 151A) is less than or equal to the width of the memory chip 121. Multiple memory chips 120 (such as memory chips 121-123) are arranged along a second direction (such as...). Figure 1C The two directions are arranged in a horizontal direction as shown, and the second direction is substantially perpendicular to the first direction.

[0051] The present invention utilizes the area on the circuit board 110 adjacent to the memory chip 120 to configure the measurement contacts 150, so that it not only does not affect the existing architecture of the memory module, but also improves the convenience and accuracy of measurement.

[0052] The elements, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of the text description or the order of the drawings in this invention.

[0053] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0054] [Symbol Explanation] 100: Memory device 110: Circuit board 120: Memory chip 121-123: Memory chips 130: Edge connector interface 140: Connection resistor 141: Connection resistor 143: Connection resistor 150: Measurement contact 151: High-frequency contact 151A: High-frequency contact 151C: High-frequency contact 152: Low-frequency contact 152A: Low-frequency contact 160: Conductive contact 210A~210C: Conductive layer 220: Insulating materials 230: Wiring 240: Conductive part D1: First spacing D2: Second spacing ED: Electronic Devices MD: Measurement device.

Claims

1. A memory device, characterized in that, Include: A circuit board contains multiple conductive layers; A memory chip is disposed on the circuit board and electrically connected to the plurality of conductive layers; Multiple connecting resistors are disposed within the circuit board and electrically connected to one of the multiple conductive layers; as well as Multiple measurement contacts are disposed on the circuit board, wherein each of the multiple measurement contacts is electrically connected to the memory chip through one of the multiple connection resistors.

2. The memory device according to claim 1, characterized in that, The plurality of measurement contacts include a plurality of high-frequency contacts and a plurality of low-frequency contacts. The frequency of the signals transmitted by the plurality of high-frequency contacts is higher than the frequency of the signals transmitted by the plurality of low-frequency contacts, and the plurality of high-frequency contacts are located between the plurality of low-frequency contacts and the memory chip.

3. The memory device according to claim 2, characterized in that, The plurality of high-frequency contacts have a first spacing, the plurality of low-frequency contacts have a second spacing, and the first spacing is smaller than the second spacing.

4. The memory device according to claim 3, characterized in that, The first spacing is between 0.5 and 0.8 mm.

5. The memory device according to claim 3, characterized in that, The second spacing is between 0.6 and 1 mm.

6. The memory device according to claim 2, characterized in that, The plurality of low-frequency contacts, the plurality of high-frequency contacts, and the plurality of connecting resistors are arranged along a first direction, and the distribution width of the plurality of measurement contacts is less than or equal to the width of the memory chip.

7. The memory device according to claim 1, characterized in that, The circuit board has multiple traces, and the multiple measurement contacts are located in a first measurement area between one side of the circuit board and the memory chip, and there are no multiple traces in the first measurement area.

8. The memory device according to claim 1, characterized in that, Each of the plurality of connection resistors is less than 200 ohms.

9. The memory device according to claim 1, characterized in that, A portion of one of the plurality of conductive layers is exposed on the surface of the circuit board to serve as the plurality of measurement contacts.

10. The memory device according to claim 1, characterized in that, A portion of one of the plurality of conductive layers is exposed in a second measurement area of ​​the circuit board, the second measurement area being located between the memory chip and the edge connector interface of the memory device.

11. A memory device, characterized in that, Include: A circuit board contains multiple conductive layers; A memory chip is disposed on the circuit board and electrically connected to the plurality of conductive layers; as well as Multiple measurement contacts are disposed in a first measurement area of ​​the circuit board, wherein each of the multiple measurement contacts is electrically connected to the memory chip through a connection resistor and at least one of the multiple conductive layers. A portion of one of the plurality of conductive layers is exposed in the second measurement area of ​​the circuit board to form a conductive contact, and the memory chip is located between the first measurement area and the second measurement area.

12. The memory device according to claim 11, characterized in that, The plurality of measurement contacts include a plurality of high-frequency contacts and a plurality of low-frequency contacts. The frequency of the signals transmitted by the plurality of high-frequency contacts is higher than the frequency of the signals transmitted by the plurality of low-frequency contacts, and the plurality of high-frequency contacts are located between the plurality of low-frequency contacts and the memory chip.

13. The memory device according to claim 12, characterized in that, The plurality of high-frequency contacts are spaced apart by a first spacing, and the plurality of low-frequency contacts are spaced apart by a second spacing, wherein the first spacing is smaller than the second spacing.

14. The memory device according to claim 13, characterized in that, The first spacing is between 0.5 and 0.8 mm.

15. The memory device according to claim 13, characterized in that, The second spacing is between 0.6 and 1 mm.

16. The memory device according to claim 12, characterized in that, The plurality of low-frequency contacts, the plurality of high-frequency contacts, and the memory chip are arranged along a first direction, and the distribution width of the plurality of measurement contacts is less than or equal to the width of the memory chip.

17. The memory device according to claim 11, characterized in that, The circuit board has multiple traces, the first measurement area is located between one side of the circuit board and the memory chip, and there are no traces in the first measurement area.

18. The memory device according to claim 11, characterized in that, The connection resistance is less than 200 ohms.

19. The memory device according to claim 11, characterized in that, Another portion of one of the plurality of conductive layers is exposed on the surface of the circuit board to serve as the plurality of measurement contacts.

20. The memory device according to claim 11, characterized in that, The second measurement area is located between the memory chip and the edge connector interface of the memory device.

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