A performance gain and life degradation evaluation quantification method for eMMc pseudo slc mode

Abstract

The application discloses a performance gain and life attenuation evaluation quantification method for an eMMC pseudo SLC mode, relates to the technical field of memory, and comprises the following steps: configuring part of TLC / QLC space as a pseudo SLC mode by using an eMMC debugging command, and obtaining a pseudo SLC partition, wherein the pseudo SLC partition and a standard partition have the same size; monitoring the partition state of the pseudo SLC partition and the standard partition through a first debugging interface; simulating a high-load scene, and synchronously recording key parameters in the scene; obtaining the average P / E cycle count of the pseudo SLC partition and the standard partition through a second debugging interface, wherein the P / E cycle count represents the programming / erasing times of a flash block; recording the change of the number of bad blocks through a bad block scanning tool; and calculating a performance gain ratio and a life attenuation ratio. The application synchronously compares the pseudo SLC mode and the standard mode under the same hardware and load, eliminates the interference of environmental variables, synchronously collects parameters in real time through the debugging interface, avoids errors in offline analysis, and provides multi-dimensional quantitative evaluation through the formula for calculating the performance gain ratio and the life attenuation ratio.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and more specifically to a quantitative method for evaluating performance gain and lifetime degradation in eMMC pseudo-SLC mode. Background Technology

[0002] Pseudo-SLC (pSLC) mode is an innovative flash memory optimization technology that uses firmware algorithms to simulate TLC (three-level cell, each cell stores 3 bits of data, high capacity but low endurance) or QLC (four-level cell, each cell stores 4 bits of data, even higher capacity but lower endurance) flash memory cells as SLC (single-level cell, each cell stores 1 bit of data, high endurance and speed) mode, thereby significantly improving the write performance and endurance of storage devices. In standard mode, TLC flash memory stores 3 bits of data per cell, while QLC stores 4 bits, resulting in more complex voltage states to handle during read and write operations, thus reducing speed and reliability. pSLC simplifies voltage management by forcing each cell to store only 1 bit of data, making devices perform better in high-speed write and frequent erase scenarios. However, this performance improvement often comes at the cost of reduced lifespan. Since the actual physical cells are still TLC / QLC structures, simulating SLC mode significantly reduces effective storage capacity and accelerates flash memory cell wear, leading to overall lifespan reduction. Furthermore, the industry currently lacks a standardized evaluation framework, making it difficult for system designers to accurately quantify the balance between the advantages and disadvantages of pSLC. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a quantitative method for evaluating performance gain and lifetime degradation in eMMc pseudo-SLC mode.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] This application discloses a quantitative method for evaluating performance gain and lifetime degradation in eMMC pseudo-SLC mode, including:

[0006] Use eMMC debugging commands to configure a portion of the TLC / QLC space as pseudo-SLC mode to obtain a pseudo-SLC partition, wherein the pseudo-SLC partition is the same size as the standard partition.

[0007] Monitor the partition status of the pseudo-SLC partition and the standard partition through the first debugging interface;

[0008] Simulate high-load scenarios and simultaneously record key parameters within those scenarios;

[0009] The average P / E cycle counts of the pseudo-SLC partition and the standard partition are obtained through the second debugging interface. The P / E cycle count represents the number of times the flash memory block is programmed / erased.

[0010] Record changes in the number of bad blocks using a bad block scanning tool;

[0011] Calculate the performance gain ratio and lifetime degradation ratio.

[0012] Furthermore, the first debugging interface includes the eMMC's EXT_CSD register, and the partition status includes mode confirmation, initial number of bad blocks, and temperature sensor readings.

[0013] Furthermore, the simulated high-load scenario includes generating a high-intensity write load for 24 hours continuously using standard storage testing tools, wherein the high-intensity write load includes sequential writes and random writes.

[0014] Furthermore, the synchronous recording of key parameters includes: sampling key parameters at 1-second intervals and storing them as CSV files for subsequent analysis. The key parameters include write speed, latency, power consumption, and chip temperature.

[0015] Furthermore, the second debugging interface includes debugging commands based on manufacturer presets.

[0016] Furthermore, the second debugging interface also includes counting the cumulative amount of data written by the host to the eMMC, and then calculating by dividing the cumulative amount of data written by the eMMC hardware parameters, including the block size and P / E cycle rating.

[0017] Furthermore, the performance gain ratio is calculated using the formula PGR=(SpSLC / Sstd)×(Lstd / LpSLC)×(Pstd / PpSLC), which measures the performance improvement of pseudo-SLC mode relative to standard mode, based on the combined effects of write speed, latency, and power consumption. If PGR > 1, it indicates a performance gain; if PGR < 1, it indicates a performance degradation. Here, SpSLC represents the average write speed of pseudo-SLC mode, Sstd represents the average write speed of standard mode, LpSLC represents the average latency of pseudo-SLC mode, Lstd represents the average latency of standard mode, PpSLC represents the average power consumption of pseudo-SLC mode, and Pstd represents the average power consumption of standard mode.

[0018] Furthermore, the calculation of lifetime degradation ratio includes: based on P / E cycles, data density, and bad block growth, the lifetime degradation ratio LAR is calculated using the formula LAR=(Cstd×Dstd / CpSLC)×(BpSLC-Bstd_init) / (Bstd-Bstd_init). This ratio measures the lifetime loss of the pseudo-SLC mode relative to the standard mode. If LAR > 1, it indicates lifetime degradation; if LAR < 1, it indicates lifetime extension. Where CpSLC represents the P / E cycle count of the pseudo-SLC mode, Cstd represents the P / E cycle count of the standard mode, Dstd represents the data density of the standard mode, BpSLC represents the number of bad blocks after testing in the pseudo-SLC mode, Bstd represents the number of bad blocks after testing in the standard mode, and Bstd_init is the initial number of bad blocks in the standard partition before testing.

[0019] The beneficial effects of this invention are:

[0020] 1) This application proposes to synchronously compare pseudo-SLC and standard modes under the same hardware and load, eliminating interference from environmental variables, and at the same time, to achieve real-time parameter acquisition through the debugging interface, avoiding offline analysis errors.

[0021] 2) The formulas for calculating the performance gain ratio and lifetime degradation ratio in this application comprehensively consider speed, latency, power consumption, P / E cycle, data density and bad block growth, providing a multi-dimensional quantitative evaluation; at the same time, the output performance gain ratio and lifetime degradation ratio directly provide system designers with a basis for selection, improving the optimization efficiency of storage systems. Attached Figure Description

[0022] Figure 1 This is a flowchart illustrating a quantitative method for evaluating performance gain and lifetime degradation in eMMc pseudo-SLC mode according to an embodiment of the present invention. Detailed Implementation

[0023] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] This application discloses a quantitative method for evaluating performance gain and lifetime degradation in eMMC pseudo-SLC mode. A flowchart of the method is shown below. Figure 1As shown, this application conducts parallel comparative tests on pseudo-SLC mode and standard TLC / QLC mode, monitors key parameters in real time, and designs formulas to calculate performance gain ratio (PGR) and lifetime degradation ratio (LAR). The specific process includes three main stages: mode switching and status monitoring, parallel comparative testing, and lifetime degradation comparison; specifically, it includes the following steps:

[0025] Using eMMC debugging commands, a portion of the TLC / QLC space is configured as pseudo-SLC mode to obtain a pseudo-SLC partition, wherein the pseudo-SLC partition and the standard partition are the same size; the eMMC debugging command is, for example, mmc write_reliability; for example, allocating 10GB each to the pseudo-SLC partition and the standard partition to maintain comparison fairness;

[0026] Monitor the partition status of the pseudo-SLC partition and the standard partition through the first debugging interface;

[0027] Simulate high-load scenarios and simultaneously record key parameters within those scenarios;

[0028] The average P / E cycle counts of the pseudo-SLC partition and the standard partition are obtained through the second debugging interface. The P / E cycle count represents the number of times the flash memory block is programmed / erased, which directly reflects the lifespan consumption.

[0029] Before and after the test, the number of bad blocks was recorded using a bad block scanning tool.

[0030] Calculate the performance gain ratio and lifetime degradation ratio.

[0031] Specifically, the first debugging interface includes the eMMC's EXT_CSD register, and the partition status includes mode confirmation, initial number of bad blocks, and temperature sensor readings, etc.

[0032] Specifically, the simulated high-load scenario includes: generating a high-intensity write load for 24 hours continuously using a standard storage testing tool. The high-intensity write load includes sequential writes and random writes. The standard storage testing tool is, for example, fio. The random writes are, for example, 4KB random writes with a queue depth of 32.

[0033] Specifically, the synchronous recording of key parameters includes sampling key parameters at 1-second intervals and storing them as a CSV file for subsequent analysis. The key parameters include write speed, latency, power consumption, and chip temperature. The write speed is measured as the average data volume written per second, in MB / s; the latency is measured as the average write latency, in ms; the power consumption is measured using a power meter, in mW; and the chip temperature is obtained through a built-in temperature sensor, in °C.

[0034] Specifically, the second debugging interface includes manufacturer-preset debugging commands. By calling the manufacturer-preset debugging commands, the raw P / E cycle data recorded in the device firmware is directly read, and after standardization conversion, a relatively comparable P / E cycle count is obtained.

[0035] Specifically, the second debugging interface also includes calculating the P / E cycle count value that is consistent with the manufacturer's preset debugging command counting logic by statistically analyzing the cumulative amount of data written by the host to the eMMC (storage device) and combining the device's hardware parameters (block size, rated P / E cycle).

[0036] Specifically, the performance gain ratio is calculated using the formula PGR=(SpSLC / Sstd)×(Lstd / LpSLC)×(Pstd / PpSLC), which measures the performance improvement of pseudo-SLC mode relative to standard mode, based on the combined effects of write speed, latency, and power consumption. If PGR > 1, it indicates a performance gain; if PGR < 1, it indicates a performance degradation. Here, SpSLC represents the average write speed of pseudo-SLC mode, Sstd represents the average write speed of standard mode, LpSLC represents the average latency of pseudo-SLC mode, Lstd represents the average latency of standard mode, PpSLC represents the average power consumption of pseudo-SLC mode, and Pstd represents the average power consumption of standard mode.

[0037] Specifically, the lifetime degradation ratio is calculated using the formula LAR=(Cstd×Dstd / CpSLC)×(BpSLC-Bstd_init) / (Bstd-Bstd_init) based on P / E cycles, data density, and bad block growth. This LAR measures the lifetime reduction of the pseudo-SLC mode relative to the standard mode. If LAR > 1, it indicates lifetime degradation; if LAR < 1, it indicates lifetime extension. Here, CpSLC represents the P / E cycle count of the pseudo-SLC mode, Cstd represents the P / E cycle count of the standard mode, Dstd represents the data density of the standard mode (3 for TLC, 4 for QLC), BpSLC represents the number of bad blocks after testing in the pseudo-SLC mode, Bstd represents the number of bad blocks after testing in the standard mode, and Bstd_init is the initial number of bad blocks in the standard partition before testing.

[0038] For example, the test environment set in this embodiment is as follows:

[0039] The device uses a Kingston eMMC 5.1 chip (with a capacity of 128GB in QLC mode); the two partitions are configured as follows: 10GB is a pseudo-SLC partition and 10GB is a standard QLC partition; the tools used are fio to generate write loads, mmc-utils for debugging, a power meter to measure power consumption, and a temperature sensor to record chip temperature; the test load is 4KB random write, queue depth 32, duration 24 hours.

[0040] For example, perform the test steps:

[0041] Initialize by enabling pseudo-SLC mode using the command `mmc write_reliability set 1`;

[0042] Scan for bad blocks: The initial number of bad blocks is 0;

[0043] Record the initial P / E cycle: 0 for pseudo-SLC partitions and 0 for standard QLC partitions;

[0044] Parallel testing: Simultaneously start fio write tests on two partitions;

[0045] Real-time data recording: sampling write speed, latency, power consumption, and temperature every second;

[0046] Example data snippets (average of the first 5 minutes) are shown in Table 1.

[0047] Table 1: Example Data Segment

[0048]

[0049] For example, lifespan data collection:

[0050] After testing, the P / E cycle count was read: 500 for pseudo-SLC partitions and 100 for standard QLC partitions.

[0051] Bad block scan: The bad block growth rate for pseudo-SLC partitions is 2, while the bad block growth rate for standard QLC partitions is 1.

[0052] For example, calculate the performance gain ratio and lifetime degradation ratio:

[0053] Using 24-hour average data:

[0054] SpSLC=148 MB / s, Sstd=48 MB / s;

[0055] LpSLC=0.6 ms, Lstd=2.1 ms;

[0056] PpSLC=205 mW, Pstd=105 mW;

[0057] Calculate the performance gain ratio: PGR=(148 / 48)×(2.1 / 0.6)×(105 / 205)=3.08×3.5×0.51≈5.5, that is, the performance improvement in pseudo-SLC mode is about 5.5 times.

[0058] CpSLC=500, Cstd=100, Dstd=4 (QLC)

[0059] BpSLC=2, Bstd=1, Bstd_init=0

[0060] Calculate the lifetime decay ratio: LAR=500 / (100×4)×(2-0) / (1-0)=0.8×2=1.6, which means that the lifetime decay is about 1.6 times in pseudo-SLC mode.

[0061] For example, the results analysis shows that the pseudo-SLC mode significantly improves performance (PGR=5.5), but has a higher lifetime penalty (LAR=1.6). System designers can weigh the trade-offs based on application requirements such as high-performance computing or long-term storage.

[0062] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A quantitative method for evaluating performance gain and lifetime degradation in eMMC pseudo-SLC mode, characterized in that, include: Use eMMC debugging commands to configure a portion of the TLC / QLC space as pseudo-SLC mode to obtain a pseudo-SLC partition, wherein the pseudo-SLC partition is the same size as the standard partition. Monitor the partition status of the pseudo-SLC partition and the standard partition through the first debugging interface; Simulate high-load scenarios and simultaneously record key parameters within those scenarios; The average P / E cycle counts of the pseudo-SLC partition and the standard partition are obtained through the second debugging interface, and the P / E cycle counts represent the number of times the flash memory block is programmed / erased. Record changes in the number of bad blocks using a bad block scanning tool; Calculate the performance gain ratio and lifetime degradation ratio.

2. The method for quantifying performance gain and lifetime degradation assessment for eMMC pseudo-SLC mode according to claim 1, characterized in that: The first debugging interface includes the eMMC's EXT_CSD register, and the partition status includes mode confirmation, initial number of bad blocks, and temperature sensor readings.

3. The method for quantifying performance gain and lifetime degradation assessment for eMMC pseudo-SLC mode according to claim 1, characterized in that, The simulated high-load scenario includes generating a high-intensity write load for 24 hours continuously using standard storage testing tools. The high-intensity write load includes sequential writes and random writes.

4. The method for quantifying performance gain and lifetime degradation assessment for eMMC pseudo-SLC mode according to claim 1, characterized in that, The synchronous recording of key parameters includes: sampling key parameters at 1-second intervals and storing them as CSV files for subsequent analysis. The key parameters include write speed, latency, power consumption, and chip temperature.

5. The method for quantifying performance gain and lifetime degradation assessment for eMMC pseudo-SLC mode according to claim 1, characterized in that: The second debugging interface includes debugging commands based on manufacturer presets.

6. The method for quantifying performance gain and lifetime degradation assessment for eMMC pseudo-SLC mode according to claim 1, characterized in that, The second debugging interface also includes counting the cumulative amount of data written by the host to the eMMC, and then calculating by dividing the cumulative amount of data written by the eMMC hardware parameters, including the block size and P / E cycle rating.

7. The method for quantifying performance gain and lifetime degradation assessment for eMMC pseudo-SLC mode according to claim 1, characterized in that, The performance gain ratio (PGR) is calculated based on the combined effects of write speed, latency, and power consumption. The formula PGR = (SpSLC / Sstd) × (Lstd / LpSLC) × (Pstd / PpSLC) measures the performance improvement of pseudo-SLC mode relative to standard mode. A PGR > 1 indicates a performance gain, while a PGR < 1 indicates a performance decrease. Here, SpSLC represents the average write speed of pseudo-SLC mode, Sstd represents the average write speed of standard mode, LpSLC represents the average latency of pseudo-SLC mode, Lstd represents the average latency of standard mode, PpSLC represents the average power consumption of pseudo-SLC mode, and Pstd represents the average power consumption of standard mode.

8. The method for quantifying performance gain and lifetime degradation assessment for eMMC pseudo-SLC mode according to claim 1, characterized in that, The lifetime degradation ratio (LAR) is calculated based on P / E cycles, data density, and bad block growth using the formula LAR=(Cstd×Dstd / CpSLC)×(BpSLC-Bstd_init) / (Bstd-Bstd_init). This LAR measures the lifetime reduction of the pseudo-SLC mode relative to the standard mode. If LAR > 1, it indicates lifetime degradation; if LAR < 1, it indicates lifetime extension. Where CpSLC represents the P / E cycle count of the pseudo-SLC mode, Cstd represents the P / E cycle count of the standard mode, Dstd represents the data density of the standard mode, BpSLC represents the number of bad blocks after testing in the pseudo-SLC mode, Bstd represents the number of bad blocks after testing in the standard mode, and Bstd_init is the initial number of bad blocks in the standard partition before testing.

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