A solid state disk scheduling defect test method and system based on phase synchronization gain

Abstract

The application discloses a solid state disk scheduling defect test method and system based on phase synchronization gain, and belongs to the technical field of solid state disk reliability test. The application is oriented to a gray box test scene of a known part of hardware architecture and supports a Passthrough instruction of a manufacturer. Target physical Plane mapping calibration is completed through time delay feature clustering combined with single point verification. Normalized programming progress is obtained based on directional read time delay and threshold voltage reference true value inversion. A segmented phase prediction is adopted to determine a multi-Die programming phase synchronization window. Synchronous and non-synchronous state contrast tests are performed to calculate synchronization gain sensitivity. A Gaussian process regression model is constructed, and active point iteration is carried out based on an expected improvement amount criterion to adaptively converge to obtain an individualized fragile phase interval. The application can accurately trigger multi-Die synchronization scheduling type implicit defects, quantify the defect amplification effect of phase synchronization, significantly improve defect detection efficiency and test attribution accuracy, and does not need to modify the hardware and core firmware of the device under test.

Description

Technical Field

[0001] This application relates to the field of solid-state drive (SSD) testing, specifically to a method for testing SSD scheduling defects based on phase synchronization gain. Background Technology

[0002] As NVMe SSDs evolve towards multi-channel, multi-die parallel architectures, the concurrent scheduling capabilities of the controller's flash translation layer (FTL) are continuously improving, making asynchronous programming of multiple physical dies the mainstream operating mode. In actual operation, when the programming phases of multiple dies become synchronized, programming completion interrupts, scheduling queue responses, and data transfer operations will occur simultaneously, leading to controller computing resource contention, bus bandwidth congestion, and instruction arbitration delays. This manifests as increased I / O latency jitter, a higher probability of instruction timeouts, and in extreme cases, scheduling anomalies such as firmware resets. These anomalies are highly critical and sporadic, only exposed within a narrow time window when the programming phases of multiple dies highly overlap. The trigger probability of conventional full-time traversal testing is low, and it is difficult to pinpoint the correlation between defects and phase synchronization.

[0003] Existing SSD reliability testing technologies mainly include two categories: conventional stress testing and black-box structure probing. Conventional stress testing often uses standardized loads such as random read / write and power-down injection to cover all operating conditions and focuses on verifying the overall reliability of the device. Its design does not make targeted optimizations for the critical window of phase synchronization in multi-die programming, and its triggering efficiency for phase-related occasional defects is limited. The test results are not very instructive for firmware scheduling optimization. Black-box structure probing technology identifies die-level address mapping relationships through latency characteristics and is mostly used for reverse analysis of device structure. Its granularity is difficult to support fine-grained inversion of the real-time programming progress of a single die, and it cannot achieve quantitative determination of the degree of phase synchronization between multiple dies.

[0004] In real-world industry scenarios such as mass production reliability sampling and firmware scheduling optimization verification, testers typically know some hardware architecture parameters of the device under test (DUT) and can obtain limited internal state truth values ​​through vendor-specific commands. This is a typical gray-box testing scenario. Both existing technologies are designed based on the premise of black-box testing, failing to fully utilize the known information in this scenario to improve testing accuracy and efficiency. Currently, testing solutions for flash memory programming timing lack a systematic phase dimension testing capability, making it difficult to isolate the inherent vulnerability of the programming progress itself, quantify the impact of phase synchronization on defects, and limiting the accuracy of defect attribution. Phase prediction often uses a unified kinematic model, failing to adapt to the dynamic characteristics of different NAND programming stages, resulting in larger prediction errors at higher progress stages, and test stress operations can interfere with progress measurement. Vulnerable phase intervals are often set using general empirical values, making it difficult to adapt to individual differences between different controllers and media, thus making it difficult to balance testing efficiency and result accuracy. Summary of the Invention

[0005] In view of the above, it is necessary to provide a solid-state drive scheduling defect testing method and system based on phase synchronization gain. In the gray box testing scenario, it can achieve high-precision perception of multi-die programming progress and accurate prediction and triggering of synchronization windows, quantify the amplification effect of phase synchronization on scheduling defects, and obtain individualized vulnerable phase intervals through active learning and adaptive convergence, thereby improving the detection efficiency and test attribution accuracy of multi-die synchronous scheduling defects.

[0006] In a first aspect, embodiments of this application provide a method for testing scheduling defects in solid-state drives based on phase synchronization gain, the method comprising the following steps:

[0007] Establish the mapping relationship between physical dies, physical planes and logical address ranges and complete the plane numbering. Select and lock the logical address range corresponding to the target physical plane with the same number for each physical die. Verify the ratio of read latency increments within the same plane and across planes to confirm that the blocking effect within the same plane is statistically dominant.

[0008] It should be explained that after establishing the correspondence between each Plane and the logical address sub-range within a single physical Die, logical numbers are assigned to each physical Plane according to the following rules: each physical Plane within a single physical Die is assigned consecutive logical numbers in ascending order of the smallest logical address in the logical address sub-range corresponding to each physical Plane, and all physical Dies use the same numbering order rule.

[0009] Directional delay data is collected for the locked logical address range corresponding to the target physical plane. The detection delay is mapped to a normalized programming progress value through nonlinear calibration. The programming speed, programming acceleration and instantaneous velocity after moving average are calculated in segments according to the programming stage.

[0010] Segmented phase prediction is performed based on programming progress value, programming speed, programming acceleration and instantaneous velocity after moving average. The synchronization window of the multi-target physical plane programming phase is determined. Standard scheduling pressure is applied within the synchronization window, and synchronous and asynchronous state tests are performed by writing timing misphase control.

[0011] The average total sensitivity at the same phase point in the synchronous and asynchronous states is subtracted to obtain the synchronization gain sensitivity, which is used as the training label for the Gaussian process regression model.

[0012] A Gaussian process regression model is constructed using the normalized programming progress value of the phase point as input and the synchronization gain sensitivity as output. Based on the Gaussian process regression model, the mean and variance of the predicted synchronization gain sensitivity of the phase point are obtained.

[0013] Based on the expected improvement amount, the target phase of the next round of testing is selected and fed back to the multi-target physical plane programming phase synchronization window determination. A temporary synchronization determination window is established, the programming progress value of the target phase point is added to the input vector, and the synchronization gain sensitivity value is added to the output vector to expand the training samples.

[0014] After the Gaussian process regression model terminates its iteration, an individualized vulnerable phase interval is generated centered on the phase point corresponding to the highest positive value of the synchronization gain sensitivity, and the feedback replaces the initial wide vulnerable phase interval.

[0015] In one embodiment, the process of establishing the mapping relationship is as follows: sequentially initiate exclusive single-stream write to the independent logical address range of the solid-state drive under test, poll the read latency of each logical address range, and classify the logical address ranges with synchronous jump and synchronous fallback characteristics of read latency and write operation into the same physical die.

[0016] Based on the physical die-level mapping, the same plane blocking effect is used to perform plane-level latency feature clustering. Then, the physical plane identifier corresponding to the feature address point is queried by the manufacturer's passthrough instruction for verification and correction, so as to obtain the correspondence between the physical plane and the logical address sub-range.

[0017] In one embodiment, the nonlinear calibration process is as follows: the threshold voltage distribution information of the target physical plane is read through the manufacturer's Passthrough instruction as a reference truth value, the initial threshold voltage distribution of the target physical plane before programming starts is taken as the progress 0 reference state, and the target threshold voltage distribution after programming is taken as the progress 1 reference state, and a nonlinear calibration comparison table of actual programming progress and read delay is established.

[0018] In actual testing, the current probe delay is mapped to a normalized programming progress value by interpolation through a lookup table.

[0019] In one embodiment, the programming phase is segmented into a low-to-medium progress segment and a high-progress vulnerable segment. The low-to-medium progress segment obtains the programming speed by dividing the programming progress difference between adjacent detection cycles by the detection cycle, and obtains the programming acceleration by dividing the programming speed difference between adjacent detection cycles by the detection cycle. The high-progress vulnerable segment only outputs the instantaneous speed after moving average.

[0020] In one embodiment, the segmented phase prediction includes: employing uniform acceleration kinematics formulas for the low-to-medium progress segment. ;

[0021] The moving average velocity prediction formula is used for vulnerable sections with high progress: ;

[0022] in, To predict lead time; The instantaneous velocity after moving average; For the target physics plane at time Programming progress value; For the target physics plane at time The acceleration of programming.

[0023] In one embodiment, the formula for calculating the synchronization gain sensitivity is: ;in This represents the average of the total sensitivity scores obtained from multiple tests in the synchronous state. This represents the average of the total sensitivity scores obtained from multiple asynchronous tests in a single round.

[0024] The total sensitivity score for a single round is the sum of the basic sensitivity score and the bonus score. The formula for calculating the basic sensitivity score is as follows: ;in, The number of idle baseline iterations. The limit number of iterations, The average number of LDPC decoding iterations recorded after each application of standard scheduling pressure;

[0025] The formula for calculating the added components is: Where M represents the anomaly level.

[0026] In one embodiment, the formula for the mean value of the predicted synchronization gain sensitivity is: ;in, The kernel vector is the programming progress value of the phase point to be predicted. The normalized programming progress value corresponding to each phase point is substituted into the Matérn 3 / 2 kernel function to obtain the result;

[0027] The kernel matrix is ​​constructed by substituting the progress values ​​of each pair of phase points into the kernel function; The output vector is formed by the synchronization gain sensitivity values;

[0028] The formula for calculating the prediction variance is as follows: ;in, This is the signal variance parameter in the kernel function.

[0029] In one embodiment, the formula for calculating the desired improvement is:

[0030] ;

[0031] in, It refers to any one of the candidate phase programming progress values ​​within the normalized progress interval after being discretized according to a preset step size; For the Gaussian process regression model, the programming progress value The mean of the predicted synchronization gain sensitivity of the output; The standard deviation of the forecast is given by the variance of the forecast. It is obtained by taking the square root of the arithmetic root; This represents the highest synchronization gain sensitivity value among all currently measured phase points. The cumulative distribution function of the standard normal distribution. The probability density function is the standard normal distribution; when hour, .

[0032] In one embodiment, the individualized vulnerable phase interval is generated as follows: taking the most sensitive phase point corresponding to the highest positive synchronization gain sensitivity as the center, it is extended to both sides by 0.05 to form a locking interval with a total width of 0.1; the locking interval is used to replace the initial wide vulnerable phase interval for subsequent synchronization window determination.

[0033] Secondly, embodiments of this application also provide a solid-state drive scheduling defect testing system based on phase synchronization gain, including a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that the processor executes the computer program to implement a solid-state drive scheduling defect testing method based on any one of claims 1-9.

[0034] This application has at least the following beneficial effects:

[0035] This application verifies the ratio of read delay increments within the same plane and across planes, and establishes a nonlinear calibration reference table using the threshold voltage distribution of the target physical plane as a reference true value. This maps the detection delay to a normalized programming progress value with high precision, enabling fine-grained, non-intrusive sensing of programming progress at the single die and single plane level. No modification to the hardware and core firmware of the device under test is required, providing a reliable data foundation for subsequent synchronization window determination.

[0036] Furthermore, by performing segmented state quantity calculations and segmented phase predictions for low-to-medium progress stages and high-progress vulnerable stages, uniform acceleration extrapolation is performed using programming speed and programming acceleration in the low-to-medium progress stages, while moving average instantaneous velocity is used for prediction in the high-progress vulnerable stages. This adapts to the dynamic characteristics of different stages of NAND programming and significantly improves the prediction accuracy and robustness of the phase synchronization window for multi-objective physical plane programming.

[0037] Furthermore, through comparative testing of synchronous and asynchronous states, the same standard scheduling pressure is applied at the same phase point, and the synchronization gain sensitivity is calculated. The inherent vulnerability of the programming progress itself is removed from the total sensitivity, and only the additional vulnerability increment brought about by phase synchronization is retained. This achieves quantitative attribution of the amplification effect of multi-die phase synchronization on scheduling defects, and provides a clear quantitative basis for firmware scheduling algorithm optimization.

[0038] Furthermore, using the normalized programming progress value of the phase point as input and the synchronization gain sensitivity as output, a Gaussian process regression model is constructed using the Matérn3 / 2 kernel function. Based on the expected improvement criterion, active point selection is performed. By comprehensively exploring and utilizing the balance between the predicted mean and the predicted variance, the test resources are gradually concentrated in the high-gain phase region. The model adaptively converges from the initial wide vulnerable phase interval to an individualized vulnerable phase interval, which greatly improves the defect detection efficiency and avoids the problems of poor individual adaptability and large invalid test overhead caused by the reliance on fixed empirical values ​​in traditional methods.

[0039] Based on the above methods, this application can achieve accurate triggering, quantitative evaluation, and individualized vulnerable phase interval adaptive convergence of latent defects such as multi-die synchronous scheduling in gray-box testing scenarios without modifying the hardware circuit and core firmware logic of the solid-state drive under test. While ensuring mass production testing efficiency, it significantly improves the accuracy of defect detection and the engineering guidance value of test results for firmware optimization, thereby improving product consistency and long-term reliability. Attached Figure Description

[0040] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart illustrating the steps of a solid-state drive scheduling defect testing method based on phase synchronization gain, provided in one embodiment of this application; Detailed Implementation

[0042] In the description of the embodiments in this application, the words "exemplary," "or," and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplary," "or," and "for example" is intended to present the relevant concepts in a specific manner.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. It should be understood that, unless otherwise stated, " / " in this application means "or".

[0044] It should also be noted that the terms "first" and "second" in this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0045] The following, in conjunction with the accompanying drawings, details the specific scheme of the solid-state drive scheduling defect testing method and system based on phase synchronization gain provided in this application.

[0046] Please see Figure 1 This document illustrates a flowchart of a solid-state drive (SSD) scheduling defect testing method based on phase synchronization gain, according to an embodiment of this application. This method is applicable to gray-box testing scenarios where the hardware architecture of the SSD under test is known and basic configuration can be performed via the manufacturer's firmware interface. Known information includes the total number of physical dies, the number of planes per die, support for background task suppression commands, and support for static LBA-Plane mapping anchoring. The method includes the following steps:

[0047] Step S01, Target Physical Plane Mapping Pre-calibration

[0048] Initialize the test environment, specifically by disabling SSD write caching and immediately issuing a Flush command after each write operation to force data flushing; suppressing all non-real-time tasks such as background garbage collection, wear leveling, and read flushing through the Passthrough command; and performing idle wait before testing to ensure the device is in a silent initial state.

[0049] Sequentially initiate exclusive single-stream writes to the independent logical address ranges of the SSD under test, while polling the read latency of all logical address ranges under test at a preset probe frequency; logical address ranges that exhibit synchronous jump and synchronous fallback characteristics between read latency and write operation are grouped into the same physical die, and after traversing all target ranges, a complete mapping relationship is obtained to determine the logical address set corresponding to each physical die.

[0050] Based on the physical die-level mapping relationship, the same-plane blocking effect is used to perform plane-level latency feature clustering: For each logical address sub-interval within the same physical die, the read latency increment is measured with different write address combinations within the same die. Combinations with significantly higher read latency increments are identified as being in the same plane, thus completing the initial correspondence between each physical plane and logical address sub-interval within a single physical die; Feature address points of each logical address sub-interval are selected, and the physical plane identifier corresponding to each feature address point is queried using the manufacturer's Passthrough instruction to verify the correctness of the plane assignment of the sub-interval and correct the assignment error of the boundary interval, establishing the correspondence between each plane and logical address sub-interval within a single physical die; For each physical die, the logical address interval corresponding to the target physical plane with the same number is selected, and the logical address interval is locked using the manufacturer's Passthrough instruction, locking the static mapping relationship between the logical address interval and the target physical plane. During the test, the FTL does not adjust its physical mapping position, ensuring that subsequent write operations and read probe operations always hit the same physical plane. In this embodiment, the manufacturer's Passthrough instruction provides a single-point directional query capability for Plane identifiers. It only supports inputting a specified logical address and returning the Plane number corresponding to that logical address. It does not have the capability to automatically traverse the entire logical address space or batch output a complete LBA-Plane mapping table. If Plane-level logical address ranges are directly divided by querying point by point, the query volume can reach millions or more for the TB-level address space of large-capacity solid-state drives, resulting in extremely low engineering efficiency. Furthermore, the dynamic mapping adjustment of the FTL during the query process can lead to inconsistencies in the query results, making it impossible to obtain a stable and continuous address range.

[0051] The read latency increment during programming within the same die and across different planes within the same die are measured separately. When the ratio of the two values ​​is greater than the preset blocking effect judgment threshold (the example value is 5:1), it is determined that the blocking effect of the same plane has statistical dominance, and the subsequent testing process is initiated.

[0052] Step S02, Real-time Inversion of Target Physics Plane Programming Progress

[0053] A large-capacity continuous write command is issued to the solid-state drive under test. The FTL scheduling mechanism causes multiple physical dies to enter an asynchronous programming state for the target physical planes. The test host allocates an independent NVMe probe channel to each target physical plane, and directional latency data acquisition is achieved by accessing the locked logical address range corresponding to the target physical plane. In this embodiment, the read probe frequency is 10kHz, which can be adjusted by the implementer according to the actual device performance.

[0054] The acquired latency data is first filtered to remove outliers using a three-standard-deviation criterion, and then filtered using a moving average to reduce the noise amplification effect of differential operations before being used for progress calculation. A full-cycle nonlinear calibration is performed based on the processed latency data: the threshold voltage distribution information of the target physical plane is read via the manufacturer's Passthrough command and used as the reference true value for the programming progress. The initial threshold voltage distribution of the target physical plane before programming begins is used as the reference state for progress 0, and the target threshold voltage distribution after programming is used as the reference state for progress 1. Based on the current position of the threshold voltage distribution between the initial and target states, a normalized progress value between 0 and 1 is mapped. During the full-cycle high-density sampling process of the target physical plane's complete page programming, the read detection latency and corresponding true values ​​are simultaneously acquired, establishing a nonlinear calibration comparison table of actual programming progress and read latency.

[0055] When the SSD under test is completely idle, read probe commands are continuously sent to the locked logical address range corresponding to the target physical plane, and the average latency is taken as the idle baseline latency of the target physical plane. After issuing a single-page write command to the locked logical address range corresponding to the target physical plane, read probe commands are densely issued within the time window immediately following the programming start, and the captured latency peak is taken as the maximum blocking latency of the target physical plane.

[0056] In actual testing, the idle reference delay and the maximum blocking delay serve as boundary verification benchmarks for the progress mapping. The actual progress calculation is based on a nonlinear calibration lookup table, mapping the current probe delay to a normalized programmed progress value. The programming progress value ranges from zero to one. A value close to zero indicates that programming is in the initial stage and the level of blockage is the highest; a value close to one indicates that programming is basically complete and the blockage has been cleared. Each calculated progress value is stored in the progress history buffer, forming a sequence of historical programming progress values ​​for multiple consecutive probing cycles.

[0057] A segmented state quantity calculation mechanism is adopted based on the characteristics of the programming stage:

[0058] Low to medium progress stage (0≤ <0.6): After each detection, the programming progress value is compared with the previous programming progress value, and the difference is divided by the detection period to obtain the programming speed; when the history buffer contains the previous programming speed, the current programming speed is subtracted from the previous programming speed and then divided by the detection period to obtain the programming acceleration.

[0059] High-progress vulnerable section (0.6≤ ≤0.98): Only the instantaneous velocity after the moving average is output. The sliding window length is set to 8 detection cycles to achieve a balance between noise suppression and instantaneous velocity preservation. The implementer can adjust the window length according to the detection frequency and noise level.

[0060] The first probe only records the programming progress value and does not calculate the programming speed; the second probe begins to calculate the programming speed and stores it in the history buffer; from the third probe onwards, the programming speed and programming acceleration are calculated synchronously in the low and medium progress segments, and only the smoothed instantaneous speed is output in the high progress vulnerable segment.

[0061] Step S03, Multi-objective physical plane programming phase synchronization window prediction

[0062] This step utilizes the real-time output of programming progress values, programming speed, programming acceleration, and instantaneous velocity after moving average for each target physical plane to perform piecewise phase extrapolation prediction, determine the multi-target physical plane programming phase synchronization window, and trigger a control test within the window. Specifically:

[0063] A segmented phase prediction strategy is adopted, with uniform acceleration kinematics formulas used for prediction in the low and medium progress stages:

[0064] ;

[0065] The moving average velocity prediction formula for high-progress vulnerable sections is as follows:

[0066]

[0067] in, For the first A target physical plane at time The predicted programming progress value ranges from zero to one. For the first A target physical plane at time Programming progress value; For the first A target physical plane at time Programming speed; For the first A target physical plane at time Programming acceleration; Indicates the first A target physical plane at time The instantaneous velocity after the moving average; To predict the lead time, an example value of 100 μs is used.

[0068] It should be noted that before performing the prediction, the stability of the programmed acceleration of each target physical plane is first verified; when the programmed acceleration of any target physical plane participating in the prediction exceeds the preset acceleration fluctuation threshold in multiple consecutive detection cycles, the prediction mode is automatically switched to the high-progression segment.

[0069] After obtaining the predicted programming progress values ​​for all target physical planes, those falling into the vulnerable phase interval are selected. The vulnerable phase interval refers to the progress range where scheduling resource contention is most intense during programming, and where robustness issues are most likely to be exposed under pressure. Initially, it is preset to a wide range, with values ​​from 0.6 to 0.98. If the number of target physical planes falling into the vulnerable phase interval is less than the preset synchronization judgment threshold (exemplarily 3), the multi-target physical plane programming phase synchronization window is determined not to be triggered, and the process waits for the next round of prediction. Conversely, if the number is greater than the preset synchronization threshold (exemplarily 0.02), the multi-target physical plane programming phase synchronization window is determined to occur after the prediction lead time.

[0070] When the multi-target physical plane programming phase synchronization window prediction is successful, test instructions are pre-built, command queue resources are pre-allocated, and trigger timers are set. When the prediction lead timer arrives, the following control test is executed: Experimental group (synchronization state): At the predicted synchronization window time, standard scheduling pressure is directly applied to the solid-state drive under test. The pressure accesses the locked logical address range corresponding to the target physical plane in the synchronization window to obtain the raw test data of the synchronization state.

[0071] Control group (asynchronous state): The order of write commands issued to different channels is adjusted on the host side to create a controllable phase difference at the start time of programming of the target physical plane of each physical die, ensuring that the phase difference between the target physical planes at the phase point is greater than the synchronization threshold. This process only performs coarse-grained phase misalignment at the host command issuance level, without interfering with the scheduling and programming execution logic inside the firmware of the tested solid-state drive, applying the same pressure as the experimental group, and obtaining the raw test data of the asynchronous state.

[0072] The standard scheduling pressure refers to a pre-set set of concurrent read / write mixed instructions with a fixed intensity, including a fixed queue depth, a fixed read / write ratio, and a fixed address randomness. In this embodiment, the standard scheduling pressure parameters are pre-set by the implementer according to the specifications of the device under test before the test and remain unchanged in all subsequent tests.

[0073] After the experimental group completed the pressure application, the average progress value of each participating target physical plane at the time of the synchronization window was recorded as the phase point for this test. Simultaneously, multidimensional test data for this test was recorded. The phase point was used for asynchronous state alignment in the control group. After the control group completed the pressure application, its original test data was saved together with that of the experimental group at the same phase point. The original test data included whether an anomaly was triggered, the severity level of the anomaly, and the average number of LDPC decoding iterations obtained from the tested SSD via the manufacturer's Passthrough command.

[0074] Simultaneously, the test data for each phase point are qualitatively labeled: phase points that do not trigger anomalies are labeled as insensitive; phase points that trigger anomalies are labeled as sensitive, with higher anomaly levels and more average LDPC decoding iterations indicating higher sensitivity of the corresponding phase point. When the same phase point is tested multiple times, the test with the highest sensitivity is used as the final qualitative label for the corresponding phase point.

[0075] In another embodiment, a pure detection calibration round is inserted every three rounds of pressure testing. This pure detection calibration round performs only phase prediction and progress detection without applying any pressure; the measured progress deviation is the pure prediction error. Using only the deviation data from the pure detection calibration round, the prediction lead for each target physical plane is independently corrected. The deviation from the pressure round is only used for recording and does not participate in closed-loop adjustment. The adjustment amount of the prediction lead is proportional to the absolute value of the deviation: the larger the absolute value of the deviation, the larger the adjustment magnitude; the smaller the absolute value of the deviation, the smaller the adjustment magnitude, avoiding overshoot or slow convergence caused by a fixed adjustment amount.

[0076] Step S04, Phase point sensitivity scoring

[0077] This step is based on data obtained from two sets of stress tests, one in synchronous mode and one in asynchronous mode. First, the total sensitivity score for each round of testing is calculated. Then, the average value is taken for the experimental and control groups at the same phase point. Finally, the synchronization gain sensitivity is obtained through the difference, which serves as the training label for the subsequent Gaussian process regression model. Details are as follows:

[0078] Two baseline values ​​are pre-calibrated to eliminate hardware differences between different SSD controllers; one is the number of idle baseline iterations. The other is the limit number of iterations. The idle baseline iteration count is obtained by sending a read probe command to the locked logical address range corresponding to the target physical plane in the SSD's fully idle state, and reading the average iteration count of the plane's LDPC decoding through the manufacturer's Passthrough instruction. This can be obtained synchronously during the idle baseline latency calibration stage. The limit iteration count can be obtained from the SSD controller chip's datasheet.

[0079] Based on the average number of LDPC decoding iterations recorded after each application of standard scheduling pressure. Calculate the basic sensitivity score This reflects the degree of implicit performance degradation caused by media interference and scheduling pressure. The specific formula is as follows: When the numerator is less than or equal to 0, Set the value to 0; if the calculated result exceeds 0.6, it is truncated to 0.6. The range of the basic sensitivity score is [0, 0.6].

[0080] Simultaneously, based on the qualitative markers of the phase points, it is determined whether the phase points have triggered anomalies. If no anomaly is triggered, the additive value is set to 0; if an anomaly is triggered, the additive value is calculated based on the recorded anomaly level M. The specific formula is as follows: Where M=1 corresponds to a level 1 anomaly, M=2 corresponds to a level 2 anomaly, M=3 corresponds to a level 3 anomaly, and the maximum value of the additive component is 0.4.

[0081] The total sensitivity score for a single round is the sum of the basic sensitivity score and the additive score, and its value ranges from [0,1]. The closer the score is to 0, the more stable the SSD scheduling and media status; the closer the score is to 1, the higher the defect sensitivity.

[0082] For the same phase point, the average total sensitivity score of the experimental group (synchronous state) obtained from multiple tests in a single round is taken to obtain the average total sensitivity of the experimental group. The average total sensitivity score of the control group (asynchronous state) obtained from multiple tests in a single round was calculated by averaging the scores. ; Calculate the synchronization gain sensitivity: Among them, synchronization gain sensitivity The value range is [-1, 1]. A positive value indicates that phase synchronization amplifies the defect sensitivity of the phase point; a negative value indicates that phase synchronization reduces the sensitivity of the phase point. The scheduling stability is better in the synchronized state. It is used as the training input for the Gaussian process regression model and is not truncated. It should be noted that during active point selection and final convergence, the highest positive value of the synchronization gain sensitivity is used as the target to locate the phase point with the strongest defect amplification effect.

[0083] When testing the same phase point multiple times, the highest historical level is used for qualitative anomaly labeling, which is only used for anomaly risk classification. Quantitative synchronization gain sensitivity has been calculated from the above average value; the two are independent and do not substitute for each other. The criteria for determining anomaly level M are as follows: M=1, the response delay of a single IO instruction exceeds three times the preset normal threshold, and no timeout occurs; M=2, a single IO instruction times out or a brief retransmission occurs on the PCIe link; M=3, abnormal device reset, user data verification error, or firmware error.

[0084] Step S05, Construction of the Gaussian Process Regression Model

[0085] This step uses the synchronization gain sensitivity values ​​of each phase point as training samples to construct a Gaussian process regression model, fitting the continuous distribution law of the synchronization gain sensitivity within the normalized programming progress value range [0,1]. For any phase point to be predicted, the model outputs a prediction result that follows a Gaussian distribution, described by two parameters: the prediction mean and the prediction variance. The prediction sensitivity mean serves as the best estimate of the synchronization gain sensitivity of the phase point, while the prediction variance characterizes the reliability of the best estimate.

[0086] When the number of phase points with recorded synchronization gain sensitivity accumulates to a preset model construction sample threshold, model construction is initiated. In this embodiment, the preset model construction sample threshold is 12. The construction process is as follows:

[0087] The normalized programming progress values ​​of each phase point are used to construct the input vector. The output vector is composed of the synchronization gain sensitivity values ​​at the corresponding phase points. ,in ≥ , For the first Normalized progress values ​​for each phase point For the first Synchronization gain sensitivity value at each phase point.

[0088] The Matérn 3 / 2 kernel function is used to measure the similarity between programming progress values ​​at two phase points. This kernel function is a standard kernel function in Gaussian process regression, characterized by first-order differentiability and moderate smoothness. It can adapt to the engineering characteristics of continuously changing and locally fluctuating phase sensitivity in SSD programming, avoiding overfitting of the actual defect distribution by infinitely smooth kernel functions. The kernel function includes two hyperparameters: a length scale parameter controls the rate at which similarity decays with phase distance, and a signal variance parameter controls the overall fluctuation amplitude of synchronization gain sensitivity. The specific mathematical form of the kernel function is common knowledge in this field and will not be elaborated further.

[0089] Substitute the phase point programming progress values ​​pairwise into the kernel function to construct the kernel matrix between phase points. Program the phase point to be predicted into a progress value. Substitute the normalized programming progress value corresponding to each phase point into the kernel function to construct the kernel vector. The length of the vector is equal to the total number of phase points.

[0090] Given the normalized progress values ​​and corresponding synchronization gain sensitivity values ​​of a batch of measured phase points, predict the new... The sensitivity score follows a conditional Gaussian distribution, and the mean of the predicted synchronization gain sensitivity is... With prediction variance They are respectively:

[0091] ;

[0092] ;

[0093] in, This is the signal variance parameter in the kernel function, which reaches its maximum value when the normalized programming progress values ​​corresponding to two phase points are the same. The mean of the synchronization gain sensitivity. It is a weighted linear combination of the phase point synchronization gain sensitivity values, with the weights determined by the phase point to be predicted. The similarity between each phase point is then processed by the kernel matrix. The weight of a phase point is determined by scaling the inverse matrix; the closer the phase point to be predicted is to a certain phase point, the higher the weight of that phase point; the farther away it is, the lower the weight.

[0094] Prediction variance characterizes the reliability of the prediction result. When the phase point to be predicted is close to a certain phase point, the measured data provides sufficient information, the variance approaches zero, and the prediction uncertainty is low. When the phase point to be predicted is far from all measured phase points, the prediction variance approaches the signal variance. The forecast is highly uncertain.

[0095] The values ​​of the length scale parameter and the signal variance parameter are automatically determined by maximizing the log-marginal likelihood of the measured data. The log-marginal likelihood is the standard objective function in Gaussian process regression, and its specific mathematical form is common knowledge in this field and will not be elaborated further.

[0096] Step S06: Active point selection based on the expected improvement criterion

[0097] This step utilizes a Gaussian process regression model and employs the expected improvement index to select the target phase for priority testing in the next round. The target phase is then fed back to the phase synchronization window determination stage of the multi-target physical plane programming. After each round of testing, the training samples are expanded and the model is iteratively updated, gradually converging to the real vulnerable phase region of the tested SSD until the termination condition is met.

[0098] Using the expected improvement amount As the sole criterion for active site selection, it can simultaneously consider both the level of prediction sensitivity and the uncertainty of prediction results, thus avoiding site selection from falling into local optima. Its calculation formula is:

[0099] ;

[0100] in, It refers to any one of the candidate phase programming progress values ​​within the normalized progress interval after being discretized according to a preset step size; For the Gaussian process regression model, the programming progress value The mean of the predicted synchronization gain sensitivity of the output; The standard deviation of the forecast is given by the variance of the forecast. It is obtained by taking the square root of the arithmetic root; This represents the highest synchronization gain sensitivity value among all currently measured phase points. The cumulative distribution function of the standard normal distribution. The probability density function is the standard normal distribution; when hour, .

[0101] The specific execution process of active point selection is as follows: First, the normalized programming progress interval [0,1] is discretely sampled according to a preset step size to generate a candidate set of several candidate phase points; then, the programming progress values ​​of all candidate phase points in the candidate set are traversed, and each candidate phase is used as the programming progress value of the phase point to be predicted. Substituting into the Gaussian process regression model, we obtain the mean and variance of the predicted synchronization gain sensitivity, and then substituting them into the formula for expected improvement to calculate each candidate point. Score. If the expected improvement of all candidate phase points is 0, it indicates that the prediction uncertainty of the entire phase interval has been reduced to the minimum, and continuing the test will not obtain effective information gain. In this case, the active point selection process will be terminated directly, and the vulnerable phase interval locking process will begin. Otherwise, the candidate phase point with the largest expected improvement will be selected as the target phase for the next round of testing.

[0102] The selected target phases are fed back to the phase synchronization window determination stage of the multi-target physical plane programming. A temporary synchronization determination window with a width of 0.05 is set with the target phase as the center, replacing the initially preset wide vulnerable phase interval. Subsequent synchronization window determinations are only performed within the temporary synchronization determination window, capturing natural synchronization windows falling within the neighborhood of the target phase and applying test pressure to concentrate the actually measured phase points toward the target phase, improving the relevance of the test points and the efficiency of iterative convergence. The temporary synchronization determination window is only used for adjusting the synchronization determination range in this iteration and is independent of and does not affect the prediction lead.

[0103] After determining the target phase, the entire process from steps S02 to S04 is reused. After each round of target phase testing is completed, the programming progress value of the target phase point is added to the input vector. Synchronous gain sensitivity value is added to the output vector. This expands the training sample set, enabling the Gaussian process regression model to refit based on the expanded sample data, thereby continuously improving the fitting accuracy of the sensitivity distribution across the entire phase interval.

[0104] When the cumulative number of active sampling test rounds reaches the preset maximum number of active sampling iterations (20 rounds), the active point selection and model iteration process is terminated, and the individualized vulnerable phase interval of the tested SSD is locked.

[0105] Step S07, fragile phase interval convergence and locking

[0106] After the active point selection iteration terminates, based on all accumulated phase points and corresponding synchronization gain sensitivity values, the convergence and locking of individualized vulnerable phase intervals is completed, and the results are fed back to the multi-objective physical plane programming phase synchronization window determination stage, as follows:

[0107] First, the synchronization gain sensitivity of all measured phase points is judged as a whole: if the synchronization gain sensitivity of all phase points is negative, it means that under the current test conditions, multi-die phase synchronization does not amplify the defect, and the scheduling stability in the synchronized state is not weaker than that in the asynchronous state. Therefore, the narrow individualized vulnerable phase interval is not generated, the initial wide vulnerable phase interval is maintained unchanged, and the process of this method ends directly.

[0108] If there is a phase point with a positive synchronization gain sensitivity, the most sensitive phase point is determined according to the priority rule: the phase point with the highest measured synchronization gain sensitivity is selected as a candidate; if the highest sensitivity value corresponds to multiple phase points, the phase point with the smallest Gaussian process regression prediction variance is selected as the final most sensitive phase point.

[0109] Centered on the normalized progress value of the most sensitive phase point, expand by 0.05 in both the increasing and decreasing directions to form a locking interval with a total width of 0.1. If the lower limit of the expanded interval is less than 0, then the lower limit is taken as 0; if the upper limit of the expanded interval is greater than 1, then the upper limit is taken as 1, which is the individualized vulnerable phase interval of the tested solid-state drive.

[0110] The width of the locked interval is set to 0.1, which is greater than the width of the temporary synchronization decision window (0.05). This can cover the random dispersion of the natural synchronization window landing points and ensure the feasibility of subsequent orientation tests. It is also much smaller than the initial wide vulnerable phase interval, which achieves significant convergence from global coarse screening to individualized precise positioning and greatly reduces the range of invalid tests.

[0111] This application also provides a solid-state drive (SSD) scheduling defect testing system based on phase synchronization gain, used to execute the aforementioned SSD scheduling defect testing method based on phase synchronization gain. The system adopts a modular architecture design, with each module working collaboratively to accurately trigger, quantitatively evaluate, and adaptively converge in vulnerable phase intervals for multi-die synchronous scheduling-type latent defects. Specifically:

[0112] The mapping and calibration module performs the target physical plane mapping pre-calibration operation, completes the test environment baseline initialization, establishes the correspondence between physical dies, physical planes and logical address ranges through latency feature clustering combined with passthrough single-point verification, and locks the static mapping of the target physical plane.

[0113] The progress inversion module performs real-time inversion of the target physical plane programming progress. It collects directional read delay data through independent probe channels, maps it to normalized programming progress values ​​after noise reduction and filtering, and calculates programming speed and acceleration in segments according to the characteristics of the programming stage, and outputs real-time phase status.

[0114] The synchronization window prediction and stress application module performs multi-target physical plane programming phase synchronization window prediction operation, uses a segmented phase prediction strategy to determine the synchronization window, and completes isobaric tests for the synchronized experimental group and the asynchronous control group respectively, and collects raw test data.

[0115] The sensitivity scoring module performs phase point sensitivity scoring operations, calculates the total sensitivity of a single round based on the number of LDPC decoding iterations and the anomaly level, obtains the synchronization gain sensitivity by the difference between the experimental group and the control group, strips away the inherent vulnerability of the progress, and quantifies the defect amplification effect of phase synchronization.

[0116] Gaussian process regression modeling module: Performs the Gaussian process regression model construction operation, using the measured phase points as training samples, and uses the Matérn 3 / 2 kernel function to construct the regression model, outputting the mean of prediction sensitivity and prediction variance.

[0117] The active point selection iteration module performs active point selection and model iteration update operations. Based on the expected improvement criterion, it selects the target phase for the next round of testing and feeds it back to the synchronous window prediction and pressure application module for directional testing. After each round of testing, the training samples are expanded and the model hyperparameters are re-optimized to gradually improve the fitting accuracy.

[0118] The vulnerable region locking module performs an individualized vulnerable phase region convergence locking operation. After the iteration terminates, it determines the most sensitive phase point according to the rules, generates an individualized vulnerable phase region of corresponding width, and feeds it back to the synchronous window prediction and stress application module for subsequent targeted retesting and defect inspection.

[0119] At the hardware level, the system includes memory, a processor, and a computer program stored in the memory and running on the processor. These functional modules are stored in the memory as program instructions, which are executed by the processor to implement the entire testing process. The system connects to the solid-state drive under test (SSD) via a standard NVMe interface, supports manufacturer passthrough command interaction, and requires no modification to the hardware circuitry or core firmware logic of the device under test.

[0120] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0121] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from its essential characteristics. Therefore, the embodiments described above should be considered exemplary and non-limiting in all respects.

Claims

1. A method for testing scheduling defects in solid-state drives based on phase synchronization gain, characterized in that, The method includes the following steps: Establish the mapping relationship between physical dies, physical planes and logical address ranges and complete the plane numbering. Select and lock the logical address range corresponding to the target physical plane with the same number for each physical die. Verify the ratio of read latency increments within the same plane and across planes to confirm that the blocking effect within the same plane is statistically dominant. Directional delay data is collected for the locked logical address range corresponding to the target physical plane. The detection delay is mapped to a normalized programming progress value through nonlinear calibration. The programming speed, programming acceleration and instantaneous velocity after moving average are calculated in segments according to the programming stage. Segmented phase prediction is performed based on programming progress value, programming speed, programming acceleration and instantaneous velocity after moving average. The synchronization window of the multi-target physical plane programming phase is determined. Standard scheduling pressure is applied within the synchronization window, and synchronous and asynchronous state tests are performed by writing timing misphase control. The average total sensitivity at the same phase point in the synchronous and asynchronous states is subtracted to obtain the synchronization gain sensitivity, which is used as the training label for the Gaussian process regression model. A Gaussian process regression model is constructed using the normalized programming progress value of the phase point as input and the synchronization gain sensitivity as output. Based on the Gaussian process regression model, the mean and variance of the predicted synchronization gain sensitivity of the phase point are obtained. Based on the expected improvement amount, the target phase of the next round of testing is selected and fed back to the multi-target physical plane programming phase synchronization window determination. A temporary synchronization determination window is established, the programming progress value of the target phase point is added to the input vector, and the synchronization gain sensitivity value is added to the output vector to expand the training samples. After the Gaussian process regression model terminates its iteration, an individualized vulnerable phase interval is generated centered on the phase point corresponding to the highest positive value of the synchronization gain sensitivity, and the feedback replaces the initial wide vulnerable phase interval.

2. The solid-state drive scheduling defect testing method based on phase synchronization gain as described in claim 1, characterized in that, The process of establishing the mapping relationship is as follows: sequentially initiate exclusive single-stream write to the independent logical address range of the solid-state drive under test, poll the read latency of each logical address range, and classify the logical address ranges that show synchronous jump and synchronous fallback characteristics of read latency and write operation into the same physical die. Based on the physical die-level mapping, the same plane blocking effect is used to perform plane-level latency feature clustering. Then, the physical plane identifier corresponding to the feature address point is queried by the manufacturer's passthrough instruction for verification and correction, so as to obtain the correspondence between the physical plane and the logical address sub-range.

3. The solid-state drive scheduling defect testing method based on phase synchronization gain as described in claim 1, characterized in that, The nonlinear calibration process is as follows: the threshold voltage distribution information of the target physical plane is read through the manufacturer's Passthrough instruction as the reference truth value, the initial threshold voltage distribution of the target physical plane before programming starts is taken as the progress 0 reference state, and the target threshold voltage distribution after programming is taken as the progress 1 reference state, and a nonlinear calibration comparison table of actual programming progress and read delay is established. In actual testing, the current probe delay is mapped to a normalized programming progress value by interpolation through a lookup table.

4. The solid-state drive scheduling defect testing method based on phase synchronization gain as described in claim 1, characterized in that, The programming phase is divided into low-to-medium progress phase and high-progress vulnerable phase. The programming speed of the low-to-medium progress phase is obtained by dividing the programming progress difference between adjacent detection cycles by the detection cycle, and the programming acceleration is obtained by dividing the programming speed difference between adjacent detection cycles. The high-progress vulnerable segment only outputs the instantaneous velocity after the moving average.

5. The solid-state drive scheduling defect testing method based on phase synchronization gain as described in claim 4, characterized in that, The segmented phase prediction includes: the low and medium progress segments using uniform acceleration kinematics formulas. ; The moving average velocity prediction formula is used for vulnerable sections with high progress: ; in, To predict lead time; The instantaneous velocity after moving average; For the target physics plane at time Programming progress value; For the target physics plane at time The acceleration of programming.

6. The solid-state drive scheduling defect testing method based on phase synchronization gain as described in claim 1, characterized in that, The formula for calculating the synchronization gain sensitivity is as follows: ;in This represents the average of the total sensitivity scores obtained from multiple tests in the synchronous state. This represents the average of the total sensitivity scores obtained from multiple asynchronous tests in a single round. The total sensitivity score for a single round is the sum of the basic sensitivity score and the bonus score. The formula for calculating the basic sensitivity score is as follows: ;in, The number of idle baseline iterations. The maximum number of iterations, The average number of LDPC decoding iterations recorded after each application of standard scheduling pressure; The formula for calculating the added components is: Where M represents the anomaly level.

7. The solid-state drive scheduling defect testing method based on phase synchronization gain as described in claim 1, characterized in that, The formula for the average value of the predicted synchronization gain sensitivity is: ;in, The kernel vector is the programming progress value of the phase point to be predicted. The normalized programming progress value corresponding to each phase point is substituted into the Matérn 3 / 2 kernel function to obtain the result; The kernel matrix is ​​constructed by substituting the progress values ​​of each pair of phase points into the kernel function; The output vector is formed by the synchronization gain sensitivity values; The formula for calculating the prediction variance is as follows: ;in, This is the signal variance parameter in the kernel function.

8. The solid-state drive scheduling defect testing method based on phase synchronization gain as described in claim 1, characterized in that, The formula for calculating the expected improvement is as follows: ; in, It refers to any one of the candidate phase programming progress values ​​within the normalized progress interval after being discretized according to a preset step size; For the Gaussian process regression model, the programming progress value The mean of the predicted synchronization gain sensitivity of the output; The standard deviation of the forecast is given by the variance of the forecast. It is obtained by taking the square root of the arithmetic root; This represents the highest synchronization gain sensitivity value among all currently measured phase points. The cumulative distribution function of the standard normal distribution. The probability density function is the standard normal distribution; when hour, .

9. The solid-state drive scheduling defect testing method based on phase synchronization gain as described in claim 1, characterized in that, The individualized vulnerable phase interval is generated as follows: taking the most sensitive phase point corresponding to the highest positive synchronization gain sensitivity as the center, it is expanded by 0.05 on both sides to form a locking interval with a total width of 0.1; the locking interval replaces the initial wide vulnerable phase interval and is used for subsequent synchronization window determination.

10. A solid-state drive scheduling defect testing system based on phase synchronization gain, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements a solid-state drive scheduling defect testing method based on phase synchronization gain as described in any one of claims 1-9.

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