Plasma generator integrated chip package integration process

Abstract

The application discloses a kind of integrated process of plasma generator integration chip package, the process is sequentially deposited bottom insulating layer, bottom electrode layer, middle insulating layer and sacrificial layer on semiconductor substrate integrated with driving circuit, top insulating layer is deposited after defining discharge cavity area graphically, and release hole is opened, the suspended discharge cavity is formed by etching to remove sacrificial layer, then top electrode layer avoiding release hole is made, finally, wafer level bonding process is used to form sealed atmosphere and enter discharge cavity through release hole, input and output ports are led out after cutting.The application integrates plasma discharge structure and driving circuit on chip scale, significantly reduces system volume and parasitic parameter, improves plasma excitation efficiency and consistency, simplifies external interconnection, and is suitable for micro-propulsion, disinfection and light source and other fields.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and specifically relates to an integrated chip packaging process for a plasma generator. Background Technology

[0002] Plasma generators have wide applications in industrial sterilization, material modification, micro-thrusters, and spectral light sources. Traditional plasma generators typically consist of multiple independent components, including a high-voltage power supply module, discharge electrodes, a gas reaction chamber, and an external gas path control system. These components are manufactured separately and then connected into a complete system via wires, connectors, or pipes. This discrete structure presents several prominent problems.

[0003] First, the connection lines between the drive circuit and the discharge electrodes are relatively long, and the wires contain non-negligible parasitic inductance and capacitance. When plasma is excited using high-frequency or pulsed methods, these parasitic parameters distort the voltage waveform, delaying discharge ignition or even preventing breakdown, and also limiting the upper limit of the drive frequency. Second, the system assembled from multiple discrete components is bulky, making it difficult to meet the lightweight requirements of portable devices or microsatellites. Third, because the manufacturing processes of each component are independent, the parameters vary greatly between batches, resulting in significant differences in plasma discharge characteristics between different devices, making it difficult to guarantee consistent and stable processing results. Finally, external interconnects are prone to surface creep, arcing, or signal crosstalk in humid or high-voltage environments, reducing the reliability and safety of the system.

[0004] In recent years, advancements in microelectromechanical systems (MEMS) technology have enabled the fabrication of micro-discharge cavities on silicon wafers. However, these micro-discharge cavities are still fabricated separately as passive chips and then connected to driver chips via wire bonding or flip-chip bonding. While this hybrid integration is an improvement over traditional cable connections, parasitic parameters and size issues remain, and multi-chip assembly increases packaging costs and process complexity. Therefore, the market needs a new process that can integrate the driver circuitry and discharge structure into a single package during chip manufacturing, fundamentally eliminating external interconnections and thereby improving the integration, consistency, and reliability of plasma generators. Summary of the Invention

[0005] The purpose of this invention is to provide an integrated chip packaging process for plasma generators to solve the technical problems of large parasitic parameters, low integration, poor consistency and reliability under existing hybrid integration methods.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] An integrated chip packaging process for a plasma generator includes the following steps:

[0008] Step 1: Provide a semiconductor substrate on which a drive circuit for driving plasma generation is integrated;

[0009] Step 2: Deposit a bottom insulating layer on the semiconductor substrate, and form a bottom electrode layer on the bottom insulating layer. The bottom electrode layer is electrically connected to the output terminal of the driving circuit.

[0010] Step 3: Deposit an intermediate insulating layer on the bottom electrode layer, and form a sacrificial layer on the intermediate insulating layer. Pattern the sacrificial layer to define the outline and position of the plasma discharge cavity.

[0011] Step 4: Deposit a top insulating layer covering the sacrificial layer and the intermediate insulating layer, and form a release hole in the top insulating layer that connects to the sacrificial layer;

[0012] Step 5: Remove the sacrificial layer by etching through the release hole to form a suspended discharge cavity located between the top insulating layer and the middle insulating layer;

[0013] Step 6: Form a top electrode layer on the top insulating layer. The top electrode layer avoids the area where the release hole is located and is electrically connected to another output terminal of the drive circuit. The projections of the top electrode layer and the bottom electrode layer in the direction perpendicular to the substrate at least partially overlap to form a discharge electrode pair.

[0014] Step 7: Using a wafer-level bonding process, a capping wafer is bonded above the top insulating layer, forming a sealed atmosphere between the capping wafer and the top insulating layer. The sealed atmosphere enters the floating discharge cavity through a release hole. Then, it is diced to form individual devices, and input / output ports that are electrically connected to the bottom and top electrode layers are brought out.

[0015] The above solution simultaneously fabricates the driving circuit and discharge structure on the same semiconductor substrate and uses a sacrificial layer release process to form a suspended discharge cavity. This results in an extremely short electrical connection path between the discharge electrode and the driving circuit, significantly reducing parasitic capacitance and inductance, which is beneficial for achieving rapid response at high frequencies or pulsed high voltages. The design of the top electrode layer avoiding the release hole ensures that the atmosphere can smoothly enter the discharge cavity during packaging, avoiding airflow blockage caused by electrode shielding. Wafer-level bonding and dicing are integrated, resulting in compact size and consistent performance of individual devices. They only require external power and signal lines to operate, reducing subsequent assembly processes.

[0016] As a preferred embodiment of the present invention, in step two, the material of the bottom insulating layer is at least one of silicon oxide, silicon nitride, or silicon oxynitride, and its deposition thickness ranges from 100 nanometers to 5 micrometers; in step three, the material of the sacrificial layer is amorphous silicon, polycrystalline silicon, or photoresist, and its thickness ranges from 500 nanometers to 10 micrometers.

[0017] The above scheme limits the material and thickness range of the bottom insulating layer and the sacrificial layer. On the one hand, it ensures the reliability of electrical isolation between the driving circuit and the discharge structure and prevents the high voltage discharge from breaking down the low voltage devices on the substrate. On the other hand, the thickness range of the sacrificial layer determines the vertical height of the discharge cavity, which is directly related to the plasma excitation voltage and the gas discharge mode. Using amorphous silicon, polycrystalline silicon or photoresist as sacrificial material can be compatible with the deposition and etching equipment in standard semiconductor processes, which facilitates process integration.

[0018] As a preferred embodiment of the present invention, the material of the top insulating layer in step four is at least one of silicon oxide, silicon nitride, or silicon oxynitride, and its deposition thickness ranges from 200 nanometers to 3 micrometers; the diameter of the release hole ranges from 0.5 micrometers to 5 micrometers.

[0019] In the above scheme, the thickness of the top insulating layer is matched with the size of the release hole. A thinner top insulating layer helps reduce the dielectric capacitance between the top electrode and the discharge cavity, thus improving discharge efficiency. The diameter of the release hole is set within a reasonable range, ensuring that the etching gas can smoothly enter and completely remove the sacrificial layer, while avoiding a reduction in the hermeticity or mechanical strength of the subsequent packaging due to an excessively large opening. This range balances the feasibility of the release process and the long-term stability after packaging.

[0020] As a preferred embodiment of the present invention, the etching process for removing the sacrificial layer in step five is an isotropic dry etching process. The etching gas contains at least one of sulfur hexafluoride, nitrogen trifluoride, or xenon difluoride. The etching temperature is controlled within the range of 20 degrees Celsius to 150 degrees Celsius, and the etching chamber pressure is controlled within the range of 0.1 Pa to 50 Pa.

[0021] The above-described method employs isotropic dry etching to remove the sacrificial layer, enabling uniform horizontal hollowing out of the sacrificial layer even with limited release hole size, ensuring the integrity of the discharge cavity's outline and the absence of residue. The coordinated control of etching gas type, temperature, and pressure results in an etching rate for the sacrificial material that is significantly higher than that for the insulating layer, thereby protecting the top and bottom dielectric layers and electrode structures from damage and maintaining the dimensional accuracy and surface quality of the discharge cavity.

[0022] As a preferred embodiment of the present invention, before forming the top electrode layer in step six, a catalytic medium layer or a secondary electron emission layer is deposited on the inner wall surface of the suspended discharge cavity. The material of the catalytic medium layer or the secondary electron emission layer is at least one of magnesium oxide, aluminum oxide or strontium titanate, and its thickness ranges from 5 nanometers to 100 nanometers.

[0023] The above-mentioned scheme deposits a catalytic medium layer or a secondary electron emission layer on the inner wall of the discharge cavity, which can reduce the electric field strength required for gas breakdown, allowing the plasma to ignite at a lower driving voltage. This thin-film material exhibits good chemical stability and electron emission characteristics in the plasma environment, helping to maintain the uniformity and continuity of the discharge. It is particularly suitable for micro-discharge cavities in low-pressure or inert gas environments, reducing sputtering corrosion on the electrode surface and extending the device's lifespan.

[0024] As a preferred embodiment of the present invention, the wafer-level bonding process in step seven is metal eutectic bonding, anodic bonding, or glass paste bonding; the bonding temperature range is 150 degrees Celsius to 450 degrees Celsius, the bonding pressure range is 0.1 MPa to 5 MPa; the sealing atmosphere is inert gas, nitrogen, or low-pressure air, and its absolute pressure range is 10 kPa to 101 kPa.

[0025] The choice of wafer-level bonding process type, temperature, and pressure range in the above schemes determines the bonding strength and hermeticity level between the cap and the device wafer. Metal eutectic bonding provides excellent electrothermal conductivity and sealing performance, anodic bonding is suitable for glass-silicon structures, and glass paste bonding has a high tolerance for surface flatness. The type and pressure of the sealing atmosphere directly affect the plasma excitation characteristics and electron energy distribution, and can be adapted to different application scenarios, such as sterilization, propulsion, or material handling, by adjusting the atmosphere composition.

[0026] As a preferred embodiment of the present invention, the materials of the bottom electrode layer and the top electrode layer are selected from at least one of aluminum, titanium, platinum, gold, copper or titanium nitride, and the thickness of a single layer ranges from 50 nanometers to 1 micrometer; the shape of the overlapping area of ​​the bottom electrode layer and the top electrode layer in the direction perpendicular to the substrate is circular, rectangular or annular, and the minimum feature size of the overlapping area in the horizontal direction ranges from 10 micrometers to 500 micrometers.

[0027] The materials and thicknesses of the bottom and top electrode layers determine the electrode's conductivity, corrosion resistance, and adhesion to the dielectric. Precious metals such as titanium, platinum, and gold are less prone to oxidation in plasma environments, while copper and aluminum are less expensive. The shape and horizontal dimensions of the electrode overlap region determine the effective area for discharge. Circular shapes are suitable for point plasma sources, while rectangular or annular shapes are suitable for linear or planar discharge regions. This range of dimensions covers application requirements from micro to medium scale.

[0028] As a preferred embodiment of the present invention, after step one and before step two, a step of forming a barrier layer on a semiconductor substrate is further included. The barrier layer is made of silicon oxide or silicon nitride and has a thickness ranging from 50 nanometers to 2 micrometers, and is used to isolate the driving circuit from the subsequent deposition layer.

[0029] Adding a barrier layer between the semiconductor substrate and subsequent deposited layers effectively prevents damage to the driving circuit area from etching gases, wet chemical reagents, or high-temperature diffusing substances. Silicon oxide or silicon nitride, as a barrier layer, has good density and chemical inertness, and its thickness is sufficient to block ion bombardment and the migration of metal contaminants, thereby protecting the CMOS circuits already integrated on the substrate and improving the overall process yield.

[0030] As a preferred embodiment of the present invention, it further includes an annealing process after step seven, wherein the annealing temperature ranges from 200 degrees Celsius to 400 degrees Celsius and the annealing time ranges from 30 minutes to 120 minutes, for releasing encapsulation stress and stabilizing the interface.

[0031] Annealing after wafer-level packaging allows for recrystallization or stress relaxation of the metal or glass materials at the bonding interface, eliminating residual stress caused by temperature cycling and pressure. Simultaneously, annealing helps stabilize the interfacial chemical bond between the cap and the device wafer, reducing the risk of leakage during long-term operation and improving the contact quality between the electrodes and the insulating layer, thereby enhancing the reliability and reusability of the plasma generator.

[0032] As a preferred embodiment of the present invention, the height of the suspended discharge cavity is determined by the thickness of the sacrificial layer, and its height ranges from 500 nanometers to 10 micrometers; the minimum distance between the sidewall of the suspended discharge cavity and the bottom electrode layer and the top electrode layer is determined by the thickness of the intermediate insulating layer and the top insulating layer, and the minimum distance ranges from 100 nanometers to 4 micrometers.

[0033] The height and sidewall distance of the suspended discharge cavity are key geometric parameters determining the plasma breakdown voltage. The height is precisely controlled by the sacrificial layer thickness, while the sidewall distance is determined by the combined thickness of the middle and top insulating layers. A shorter cavity can generate micro-discharges at lower voltages, making it suitable for low-voltage or portable devices; a taller cavity can accommodate a larger gas volume, suitable for applications requiring higher reaction rates. By adjusting these two parameters, different gas types and pressure conditions can be flexibly adapted without changing the drive circuit design, expanding the device's applicability.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. The electrical performance of this invention is significantly improved: Because the bottom and top electrodes are only a few micrometers to tens of micrometers away from the output of the drive circuit, the parasitic inductance of the wires can be reduced to the picohen level, and the parasitic capacitance is also extremely small. This allows the pulse waveform generated by the drive circuit to be applied to the discharge electrode with almost no distortion, shortening the ignition delay time and increasing the upper limit of the discharge frequency. Even in the tens of megahertz frequency band, which was previously difficult to achieve, the chip can operate stably. At the same time, because there are no external high-voltage interconnects, the electric field is entirely confined inside the chip by the dielectric layer and the package cover, preventing electromagnetic interference to external circuits and eliminating the safety hazards of high-voltage creepage.

[0036] 2. This invention significantly reduces size and weight: The core components of the plasma generator, along with the drive circuitry, are packaged within a single chip, typically measuring only millimeters to centimeters in size, with a thickness usually not exceeding one millimeter. Compared to traditional systems consisting of independent high-voltage power supplies, discharge tubes, and conduits, the volume can be reduced by tens or even hundreds of times. This effect is particularly pronounced in miniature thrusters and handheld sterilization devices, making previously impossible miniaturized applications possible.

[0037] 3. Significantly improved consistency and repeatability: The geometry of all discharge cavities is controlled by photolithography and thin-film deposition processes with sub-micron precision. Electrode spacing, cavity height, and dielectric layer thickness are virtually identical between different chips on the same wafer. Furthermore, the parameters of the drive circuit are adjusted during wafer testing, resulting in chips produced in batches exhibiting highly consistent ignition voltage, discharge power, and plasma density. Users do not need to recalibrate drive parameters when replacing chips, which is crucial for applications requiring strict repeatability, such as medical sterilization and spectral analysis.

[0038] 4. The reliability and service life of this invention are extended: The sealed atmosphere formed by wafer-level bonding isolates the discharge cavity from the external environment, preventing the intrusion of humid air, dust, or corrosive gases. For low-pressure applications, the seal maintains a stable gas density, preventing loss of propulsion capability due to leakage. For atmospheric pressure applications, the sealed structure prevents electrode oxidation. The secondary electron emission layer or catalyst layer deposited on the inner wall not only reduces the ignition voltage but also reduces the direct bombardment of electrodes by ions, thereby extending electrode life several times over. Annealing further eliminates bonding stress and improves the long-term stability of the sealed interface.

[0039] 5. This invention significantly improves ease of use: the resulting chip only requires low-voltage DC power to operate, eliminating the need for bulky high-voltage power supplies, RF matching devices, or gas cylinders. This greatly reduces the development difficulty and cost of terminal devices, enabling plasma technology to enter the consumer market, such as portable disinfection pens, miniature spectrometers, and even wearable wound care patches.

[0040] In summary, this invention, through integrated chip packaging technology, fundamentally changes the traditional split architecture of plasma generators, achieving substantial progress in electrical performance, size, consistency, reliability, and ease of use. Three specific embodiments respectively verify the feasibility of this technology in the fields of propulsion, sterilization, and light source, and the test data of each embodiment demonstrate the significant advantages of the integrated solution compared to hybrid integrated solutions. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only examples of embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the integrated chip package structure of the plasma generator in an embodiment of the present invention;

[0043] Figure 2 This is a flowchart of an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0045] In the description of the embodiments of the present invention, it should be understood that the terms "upper", "lower", "front", "rear", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention.

[0046] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, an integral connection, or a detachable connection; they can refer to the internal connection of two components; they can refer to a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present invention can be understood according to the specific circumstances.

[0047] See Figures 1-2 As shown, this specific implementation provides the following three embodiments.

[0048] Example 1: Low-pressure micro plasma thruster chip:

[0049] This embodiment provides a miniature ion thruster chip for CubeSat attitude control, and its manufacturing process is as follows.

[0050] A six-inch silicon wafer is provided, on which a high-voltage pulse driving circuit is integrated using a 0.18-micron CMOS process. This circuit is capable of generating negative polarity pulses with amplitudes ranging from 1,000 to 2,000 volts and frequencies from 5,000 Hz to 20,000 Hz. An 800-nanometer-thick silicon oxide layer is grown on the wafer surface using plasma-enhanced chemical vapor deposition as a bottom insulating layer. A 150-nanometer-thick layer of titanium and a 200-nanometer-thick layer of platinum are deposited by magnetron sputtering, and then photolithographically etched and etched to form a bottom electrode layer. This electrode is a circular sheet with a diameter of 180 micrometers and is connected to the high-voltage output terminal of the driving circuit.

[0051] A 300-nanometer-thick silicon oxide layer was deposited as an intermediate insulating layer using plasma-enhanced chemical vapor deposition (PECVD). Polyimide photoresist, with a thickness controlled between 4 and 6 micrometers, was spin-coated. After pre-baking, exposure, and development, a 200-micrometer-diameter circular opening was formed directly above the bottom electrode, serving as a sacrificial layer. A 1.2-micrometer-thick silicon oxide layer was then deposited as the top insulating layer. In the central region of the corresponding sacrificial layer, reactive ion etching was used to create an array of release holes with diameters of 2 to 3 micrometers and a hole spacing of 15 micrometers.

[0052] Using a xenon difluoride isotropic dry etching system, with a temperature controlled at 35-45 degrees Celsius and a chamber pressure of 5-20 Pa, the polyimide sacrificial layer was removed through a release orifice, and etching continued for 12 minutes to form a suspended discharge cavity. After etching, an aluminum oxide thin layer with a thickness of 8-12 nanometers was grown on the inner wall of the discharge cavity using atomic layer deposition (ALD) as a secondary electron emission layer. Subsequently, titanium and gold were sputtered, with a total thickness of 250 nanometers, and photolithography and etching were performed to form the top electrode layer. The mask design of the top electrode layer avoided the release orifice region, and the overlapping area with the projection of the bottom electrode was a circle with a diameter of 150 micrometers.

[0053] The wafer is eutectic bonded to a silicon-capped wafer with pre-drilled gas vias using gold-tin eutectic bonding at a temperature of 280°C to 320°C and a pressure of 0.8 MPa to 1.2 MPa. The bonding atmosphere is high-purity xenon at a pressure of 40 kPa to 60 kPa. During bonding, xenon gas enters the suspended discharge chamber through a release via. Finally, the wafer is diced along the dicing path, and input / output pads connected to the bottom and top electrodes are led out from the wafer surface.

[0054] The driving circuit applies a negative high-voltage pulse between the bottom and top electrodes. Since the discharge chamber is filled with low-pressure xenon gas and its inner wall is covered with an alumina secondary electron emission layer, when the pulse amplitude exceeds the breakdown threshold, the xenon gas in the chamber undergoes dielectric barrier discharge, generating plasma containing xenon ions. The alumina layer releases secondary electrons under ion bombardment, maintaining the stability of the discharge. Under the influence of the electric field, the xenon ions are accelerated and ejected outwards from the release hole or a dedicated nozzle on the package cover, generating a reverse thrust. Because the entire discharge chamber and driving circuit are integrated into the same chip, the capacitive coupling path between the electrodes is extremely short, and the pulse rise time loss is small, thus achieving considerable propulsion efficiency at a relatively low supply voltage.

[0055] Compared to thrusters using discrete high-voltage power supplies and independent discharge chambers, this integrated chip reduces its size to less than a quarter of the original. The connection inductance between the drive circuit and the discharge electrodes is significantly reduced, and the rise-edge distortion of the pulse waveform is noticeably decreased. This results in faster and more stable discharge ignition at the same pulse voltage amplitude. The sealed xenon atmosphere inside the package ensures the purity of the propellant, preventing thrust fluctuations caused by external air intrusion. The introduction of an alumina thin layer reduces the ignition voltage by approximately 30%, extending the electrode's service life.

[0056] Experimental data:

[0057] Ten chips prepared according to the above scheme were tested. The driving pulse voltage was set to 1200 volts and the frequency to 10,000 Hz. The thrust was measured using an ion collecting electrode, and the average thrust of a single chip was measured to be 8.5 micronewtons to 10.2 micronewtons, with thrust fluctuations of less than 5%. Ignition voltage measurements showed that the ignition voltage of the control chip without an alumina layer was 1050 to 1100 volts, while the ignition voltage of the chip with an alumina layer decreased to 720 to 780 volts. After 100 hours of continuous operation, the thrust decay was less than 8%, while the unpackaged control chip without an alumina layer decayed by more than 25% under the same conditions.

[0058] Example 2: Atmospheric pressure plasma sterilization chip:

[0059] This embodiment provides an atmospheric pressure plasma jet chip for handheld disinfection devices, which can directly generate low-temperature plasma in the air.

[0060] A four-inch silicon wafer is selected, and an RF oscillation driver circuit is integrated on the substrate. The center frequency is 13.56 MHz, and the output power is adjustable from 0.5 watts to 2 watts. The matching network is integrated on-chip. A 1.5-micrometer-thick silicon nitride layer is grown as the bottom insulating layer using low-pressure chemical vapor deposition. A 500-nanometer-thick copper layer is deposited as the bottom electrode layer, and a rectangular electrode with a length of 400 micrometers and a width of 100 micrometers is formed by photolithography and etching, which is connected to the RF output terminal of the driver circuit.

[0061] A 500-nanometer-thick silicon oxide layer was deposited as an intermediate insulating layer using plasma-enhanced chemical vapor deposition (PECVD). A 2-3 micrometer-thick layer of polymethyl methacrylate (PMMA) photoresist was spin-coated, and a rectangular window with the same shape as the bottom electrode was defined by photolithography as a sacrificial layer. The window was 380 micrometers long and 80 micrometers wide. A 1-micrometer-thick layer of silicon oxide was deposited as the top insulating layer. Release holes with a diameter of 1.5-2.5 micrometers were formed at the boundary of the sacrificial layer, with six release holes arranged along the long side of each rectangular cavity.

[0062] The polymethyl methacrylate (PMMA) sacrificial layer was removed using an oxygen plasma ashing process. The ashing temperature was 60°C, the oxygen flow rate was 200 mL / min, the chamber pressure was 30 Pa, and the processing time was 8 minutes. After ashing, without depositing any secondary electron emission layer, titanium and copper were directly sputtered to a total thickness of 400 nm, and then photolithographically etched to form the top electrode layer. The mask design of the top electrode layer avoided all release holes, and its projection completely overlapped with the bottom electrode. The size of the overlap area was consistent with the sacrificial layer window.

[0063] The wafer is packaged with a glass-covered wafer via anodic bonding at a temperature of 320°C to 380°C and a voltage of 600V to 1000V. The sealing atmosphere is ambient air at a pressure of 101kPa. During bonding, air enters the suspended discharge chamber through a release port. After packaging, the RF input port and ground port are led out from the back of the wafer, and individual chips are obtained by dicing.

[0064] The driving circuit generates a 13.56 MHz radio frequency signal, which is applied between the bottom and top electrodes. Since the discharge chamber is filled with atmospheric pressure air and the electrodes are covered by a silicon oxide dielectric layer, a dielectric barrier discharge structure is formed. When the radio frequency voltage amplitude is sufficiently high, the air inside the chamber is ionized, generating a low-temperature plasma containing reactive oxygen species, nitrogen oxides, and electrons. These reactive species diffuse out of the chip through the release holes, producing a bactericidal effect on nearby biological surfaces. The design of the top electrode avoiding the release holes allows the plasma to escape smoothly from the chamber while preventing direct sputtering contamination of the electrode metal.

[0065] This chip operates directly in atmospheric conditions, requiring no additional gas supply system, making it suitable for handheld sterilization devices. The integrated design of the drive circuit and discharge chamber eliminates the bulk of external coaxial cables and matching networks, allowing the entire device to be thinner than a one-yuan coin. Because the electrode spacing is precisely controlled by the dielectric layer thickness, the discharge characteristics across multiple chips are highly consistent, ensuring uniform sterilization effects during mass production. The size and layout of the release orifices are optimized to allow efficient diffusion of active species without causing electric field leakage and extinguishing the discharge due to excessively large orifices.

[0066] Experimental data:

[0067] Ten chips were subjected to disinfection testing in an atmospheric environment. The radio frequency output power was set to one watt, and the chip surface was placed two millimeters away from an agar plate coated with E. coli for 30 seconds. After treatment, the bacterial survival rate was measured, with an average log reduction of 3.2 to 3.8. The same test was performed using Staphylococcus aureus, with a log reduction of 2.9 to 3.4. The control chip, driven by an external radio frequency source without integrated drive circuitry, showed a log reduction of only 2.1 to 2.5 at the same output power and distance, with significant fluctuations. Simultaneously, the chip surface temperature was measured; in this embodiment, the chip's surface temperature rise after 30 seconds of treatment was less than 15 degrees Celsius, meeting the safety requirements for handheld devices. The same chip was reused 200 times without a significant decrease in sterilization effect.

[0068] Example 3: Miniature Plasma Light Source Chip:

[0069] This embodiment provides a miniature vacuum ultraviolet light source chip for portable spectrometers, which uses deuterium as the working gas to generate radiation in the 120-160 nanometer wavelength range.

[0070] A 3-inch silicon-on-insulator (SiO2) substrate is provided, with a top silicon layer 10 micrometers thick. A low-voltage DC drive circuit is integrated within the top silicon layer via deep trench isolation and ion implantation. This circuit can boost a 5-volt input to a DC bias of 300-500 volts and superimpose a 100-volt pulse at a frequency of 1 kilohertz. A 200-nanometer thick silicon oxide and 50-nanometer thick silicon nitride stack is deposited on the substrate surface as a bottom insulating layer. A 100-nanometer thick platinum layer is deposited by electron beam evaporation as a bottom electrode layer, and photolithographic lift-off forms a ring electrode with an outer diameter of 250 micrometers and an inner diameter of 150 micrometers, which is connected to the high-voltage output terminal of the drive circuit.

[0071] A 150-nanometer-thick aluminum oxide layer is deposited as an intermediate insulating layer. A 5- to 7-micrometer-thick polybenzoxazole photoresist is spin-coated, and a circular sacrificial layer with a diameter of 140 micrometers is defined by photolithography, corresponding to the inner diameter of the bottom annular electrode. A 400-nanometer-thick aluminum oxide layer is deposited as a top insulating layer, and a 2-micrometer-diameter release hole is etched above the sacrificial layer, located at the center of the circle.

[0072] The polybenzoxazole sacrificial layer was removed using xenon difluoride etching at a temperature of 25°C, a pressure of 5 Pa, and a time of 15 minutes. Following etching, a 5-nanometer-thick hafnium oxide thin layer was grown on the inner wall of the discharge chamber using atomic layer deposition. This thin layer exhibits high reflectivity to vacuum ultraviolet light and can also serve as a cathode to enhance electron emission. Subsequently, a 100-nanometer-thick platinum layer was sputtered to form the top electrode layer. The top electrode mask was designed as a ring, with an outer diameter identical to that of the bottom electrode and an inner diameter larger than the diameter of the release hole to ensure that the release hole was not covered. The overlapping area of ​​the projected top and bottom electrodes was a 50-micrometer-wide annular band.

[0073] The wafer was bonded to a quartz cover wafer coated with an aluminum reflective film using glass paste at a bonding temperature of 350 degrees Celsius and a pressure of 0.5 MPa. Before bonding, the cavity was evacuated to a vacuum using a vacuum system and then refilled with a mixture of deuterium and argon gases, with a deuterium partial pressure of 10 kPa and an argon partial pressure of 20 kPa. After bonding, the wafer was diced and separated, and power and signal ports were led out from the back of the wafer.

[0074] The driving circuit applies a DC bias voltage with superimposed pulses between the bottom and top annular electrodes. At the rising edge of the pulse, the deuterium gas in the discharge cavity is broken down to form plasma. Deuterium molecules dissociate and become excited by electron collisions, emitting photons in the vacuum ultraviolet band when the excited molecules transition back to the ground state. The alumina and hafnium oxide dielectric layers limit the discharge current, preventing transition to arc mode. Simultaneously, the hafnium oxide thin layer has high reflectivity for light wavelengths below 160 nanometers, reflecting some of the back-propagating light towards the quartz cover plate. The annular electrode structure concentrates the discharge in the annular region, while the central transparent region allows direct light emission. Due to the small size of the discharge cavity and the pure atmosphere, the emission spectrum is narrow and stable, making it suitable as a light source for spectrometers.

[0075] The light-emitting area of ​​this chip is only 150 micrometers in diameter, making it a point light source and easy to couple with optical fibers or micro-gratings. With the driving circuit integrated with the light source, the entire device only requires an external low-voltage DC power supply, eliminating the need for the high-voltage power supply module and ballast circuit required in traditional deuterium lamps. The introduction of the hafnium oxide reflective layer more than doubles the light extraction efficiency in the same direction. Argon gas in the sealed atmosphere acts as a buffer gas, helping to stabilize the discharge and extend electrode life, without affecting the characteristic emission wavelength of deuterium.

[0076] Experimental data:

[0077] Photoelectric testing was performed on ten chips. Under conditions of a driving voltage of 350 volts, a pulse frequency of 1 kHz, and a duty cycle of 50%, light intensity was measured 5 mm above a quartz cover using a vacuum ultraviolet photomultiplier tube. The measured radiation intensity at the center wavelength of 160 nm was 0.3 mW to 0.4 mW per square centimeter, with intensity fluctuations of less than 6%. The control chip without a deposited hafnium oxide reflective layer showed a radiation intensity of 0.13 mW to 0.18 mW per square centimeter under the same conditions. After 500 hours of continuous operation, the radiation intensity decayed by less than 15%. Using this light source chip in conjunction with a portable grating spectrometer, the absorption peak of nitrate in water near 230 nm was successfully detected, with a signal-to-noise ratio exceeding 12 dB. Traditional commercial miniature deuterium lamps are approximately 30 times the size of the chip in this embodiment and require a starting voltage of over 1 kilovolts.

[0078] In summary, the working principle of the integrated chip packaging process for plasma generators provided in this embodiment of the invention is as follows:

[0079] The purpose of this invention is to directly construct the two electrodes and the discharge cavity required for plasma discharge on a semiconductor substrate that already contains a driving circuit, and to obtain a suspended sealed or semi-sealed cavity through a dielectric layer and sacrificial layer release process.

[0080] During operation, the driving circuit integrated in the substrate generates a specific electrical signal, which can be a high-voltage pulse, an radio frequency AC voltage, or a pulse voltage superimposed with a DC bias. This electrical signal is directly transmitted to the bottom electrode layer through the metal interconnect layer inside the substrate, and simultaneously transmitted to the top electrode layer through another interconnect. The bottom and top electrodes are separated by an intermediate insulating layer and a suspended discharge cavity. Since the top electrode layer is disposed on top of the top insulating layer, and the bottom electrode layer is disposed on top of the bottom insulating layer, there is no direct metal path between the two electrode layers; instead, a loop is formed through the gas within the discharge cavity.

[0081] When the voltage amplitude output by the driving circuit exceeds the breakdown threshold of the gas in the discharge cavity, the gas molecules are ionized, generating electrons, ions, and active particles. These charged particles oscillate in the alternating electric field and further collide with neutral gas molecules to form a stable plasma. Because the sidewalls, bottom, and top of the discharge cavity are covered with insulating dielectric layers, the discharge mode is dielectric barrier discharge, which can prevent excessive current from transitioning to arc discharge, thereby protecting the electrodes from ablation.

[0082] Depending on the application requirements, a secondary electron emission layer or catalyst layer can be pre-deposited on the inner wall of the discharge chamber to reduce the ignition voltage or alter the chemical composition of the plasma. The sealing atmosphere is pre-filled during wafer-level bonding; the gas type and pressure can be adjusted according to the target application: low-pressure xenon is suitable for ion propulsion, atmospheric pressure air is suitable for sterilization, and a mixture of deuterium and argon is suitable for vacuum ultraviolet light sources. Because the entire discharge chamber and drive circuit are packaged within the same chip, the transmission path of electrical signals is only at the micrometer level, and parasitic effects are almost negligible. Therefore, the drive circuit can couple electrical energy to the plasma load with very high efficiency.

[0083] The plasma generator chip prepared using this invention is very simple. After packaging and dicing, the chip has several input / output ports on its surface, typically including a positive power supply, a ground power supply, and possibly an enable signal port. Users only need to connect these ports to a DC power supply or control signal source of the appropriate voltage level to make the chip work, without the need for any external high-voltage power supply module or tuning matching network.

[0084] For the miniature ion thruster chip described in Example 1, during use, the chip is fixed to the structural plate of a satellite or micro-spacecraft, with the nozzle on the release port or encapsulation cover facing the opposite direction to where thrust is needed. A DC current of several volts to tens of volts is applied to the drive circuit, and the internal circuit automatically generates a high-voltage pulse to excite the xenon plasma within the discharge chamber. Ions in the plasma are accelerated by the electric field and ejected from the nozzle, generating micronewton-level thrust, which can be used for attitude adjustment or orbital fine-tuning. The user can change the thrust magnitude by adjusting the input voltage or pulse frequency.

[0085] For the atmospheric pressure plasma disinfection chip in Example 2, the chip is placed directly close to the surface of the object to be treated, such as a wound, medical device, or food packaging. A low-voltage direct current is applied to the chip, and a low-temperature plasma jet containing reactive oxygen species and nitrogen oxides continuously escapes from the chip surface through the release orifice. The user holds the chip and moves it to scan the target area, utilizing the active species in the plasma to kill bacteria or degrade organic pollutants. Throughout the process, the chip surface temperature remains within a safe range, allowing direct contact with the skin.

[0086] For the miniature light source chip in Example 3, during use, the chip is fixed to the optical path incident end of the spectrometer, with the quartz cover facing the grating or optical fiber. After connecting the DC power supply, the deuterium plasma inside the chip emits a characteristic spectrum in the vacuum ultraviolet band. The user can adjust the light intensity by controlling the duty cycle of the driving voltage. Due to its very small luminescent area, this chip is suitable for coupling with microlenses or optical fibers for portable water quality detection, gas analysis, and other applications.

[0087] In summary, the chip of this invention adopts a plug-and-play mode, and users do not need to have high voltage or radio frequency engineering experience. They only need to provide low voltage DC power to obtain a stable plasma source.

[0088] The above description illustrates the basic principles of the present invention. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. The above embodiments and descriptions in the specification are only for illustrating the principles of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present invention without departing from the scope of the present invention should be included within the protection scope of the present invention.

Claims

1. An integrated chip packaging process for a plasma generator, characterized in that... Includes the following steps: Step 1: Provide a semiconductor substrate on which a drive circuit for driving plasma generation is integrated; Step 2: Deposit a bottom insulating layer on the semiconductor substrate, and form a bottom electrode layer on the bottom insulating layer. The bottom electrode layer is electrically connected to the output terminal of the driving circuit. Step 3: Deposit an intermediate insulating layer on the bottom electrode layer, and form a sacrificial layer on the intermediate insulating layer. Pattern the sacrificial layer to define the outline and location of the plasma discharge cavity. Step 4: Deposit a top insulating layer covering the sacrificial layer and the intermediate insulating layer, and form a release hole in the top insulating layer that communicates with the sacrificial layer; Step 5: Remove the sacrificial layer by etching through the release hole to form a suspended discharge cavity located between the top insulating layer and the middle insulating layer; Step 6: A top electrode layer is formed on the top insulating layer. The top electrode layer avoids the area where the release hole is located and is electrically connected to another output terminal of the driving circuit. The projections of the top electrode layer and the bottom electrode layer in the direction perpendicular to the substrate at least partially overlap to form a discharge electrode pair. Step 7: Using a wafer-level bonding process, a capping wafer is bonded above the top insulating layer to form a sealing atmosphere between the capping wafer and the top insulating layer. The sealing atmosphere enters the suspended discharge cavity through the release hole. Then, it is diced to form a single device and an input / output port electrically connected to the bottom electrode layer and the top electrode layer is led out.

2. The integrated chip packaging process for a plasma generator according to claim 1, characterized in that: The bottom insulating layer in step two is made of at least one of silicon oxide, silicon nitride, or silicon oxynitride, and its deposition thickness ranges from 100 nanometers to 5 micrometers; the sacrificial layer in step three is made of amorphous silicon, polycrystalline silicon, or photoresist, and its thickness ranges from 500 nanometers to 10 micrometers.

3. The integrated chip packaging process for a plasma generator according to claim 1, characterized in that: The material of the top insulating layer in step four is at least one of silicon oxide, silicon nitride, or silicon oxynitride, and its deposition thickness ranges from 200 nanometers to 3 micrometers; the diameter of the release hole ranges from 0.5 micrometers to 5 micrometers.

4. The integrated chip packaging process for a plasma generator according to claim 1, characterized in that: In step five, the sacrificial layer is removed by etching using an isotropic dry etching process. The etching gas contains at least one of sulfur hexafluoride, nitrogen trifluoride, or xenon difluoride. The etching temperature is controlled within the range of 20 degrees Celsius to 150 degrees Celsius, and the etching chamber pressure is controlled within the range of 0.1 Pa to 50 Pa.

5. The integrated chip packaging process for a plasma generator according to claim 1, characterized in that: Before forming the top electrode layer in step six, a catalytic medium layer or a secondary electron emission layer is deposited on the inner wall surface of the suspended discharge cavity. The material of the catalytic medium layer or the secondary electron emission layer is at least one of magnesium oxide, aluminum oxide or strontium titanate, and its thickness ranges from 5 nanometers to 100 nanometers.

6. The integrated chip packaging process for a plasma generator according to claim 1, characterized in that: The wafer-level bonding process described in step seven is metal eutectic bonding, anodic bonding, or glass paste bonding; the bonding temperature range is 150 degrees Celsius to 450 degrees Celsius, and the bonding pressure range is 0.1 MPa to 5 MPa; the sealing atmosphere is an inert gas, nitrogen, or low-pressure air, with an absolute pressure range of 10 kPa to 101 kPa.

7. The integrated chip packaging process for a plasma generator according to claim 1, characterized in that: The materials of the bottom electrode layer and the top electrode layer are selected from at least one of aluminum, titanium, platinum, gold, copper or titanium nitride, and the thickness of a single layer ranges from 50 nanometers to 1 micrometer. The shape of the overlapping area of ​​the bottom electrode layer and the top electrode layer in the direction perpendicular to the substrate is circular, rectangular or annular, and the minimum feature size of the overlapping area in the horizontal direction ranges from 10 micrometers to 500 micrometers.

8. The integrated chip packaging process for a plasma generator according to claim 1, characterized in that: After step one and before step two, a step of forming a barrier layer on the semiconductor substrate is also included. The barrier layer is made of silicon oxide or silicon nitride and has a thickness ranging from 50 nanometers to 2 micrometers. It is used to isolate the driving circuit from the subsequent deposition layer.

9. The integrated chip packaging process for a plasma generator according to claim 1, characterized in that: It also includes an annealing process following step seven, with an annealing temperature ranging from 200 degrees Celsius to 400 degrees Celsius and an annealing time ranging from 30 minutes to 120 minutes, to release encapsulation stress and stabilize the interface.

10. The integrated chip packaging process for a plasma generator according to any one of claims 1-9, characterized in that: The height of the suspended discharge cavity is determined by the thickness of the sacrificial layer, and its height ranges from 500 nanometers to 10 micrometers; the minimum distance between the sidewall of the suspended discharge cavity and the bottom and top electrode layers is determined by the thickness of the intermediate insulating layer and the top insulating layer, and the minimum distance ranges from 100 nanometers to 4 micrometers.

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