SiC microchannel scattering heat dissipation InP-based 4.6μm QCL and preparation method

Abstract

The application relates to a SiC micro-channel scattering heat dissipation InP-based 4.6 mu m QCL and a preparation method, and belongs to the field of mid-infrared semiconductor lasers. The application comprises an InP-based 4.6 mu m QCL chip and a SiC heat sink. The chip is a three-well single-LO phonon resonance active region structure, and is inversely bonded on the upper surface of the heat sink through a P surface. A micro-channel is etched in the heat sink. Scattering turbulence units are arranged in an array in the micro-channel. The scattering turbulence units are rhombic bosses, cylindrical turbulence columns or zigzag channel protrusions. Cooling liquid input and output ports are arranged at the two ends of the micro-channel. A metallized solder layer is arranged on the upper surface of the heat sink, and the chip is welded on the metallized solder layer area through solder. Through the construction of a three-dimensional heat dissipation system of "active region source heat reduction-chip lateral temperature equalization heat conduction-packaging end forced convection heat dissipation", the thermal roll-off effect under the high-power working state is significantly reduced, and the single-tube room-temperature continuous wave power breaks through 2 W.

Description

Technical Field

[0001] This invention relates to a SiC microchannel scattering heat dissipation InP-based 4.6μm QCL and its preparation method, which is used for 4.6μm band applications such as infrared spectroscopy detection, gas sensing, infrared countermeasures, and environmental monitoring, and belongs to the field of mid-infrared semiconductor laser technology. Background Technology

[0002] The 4.6 μm wavelength corresponds to the strongest absorption line of the carbon monoxide molecule's fundamental frequency. InP-based quantum cascade lasers (QCLs), with their advantages of room-temperature continuous lasing, high electro-optical conversion efficiency, and precise controllable operating wavelength, have become the core mid-infrared light source for atmospheric environmental monitoring and industrial process analysis. The mainstream industrial structure in this band is a triple-well single-LO phonon resonance diagonal transition cascade structure, which relies on phonon resonance extraction to reduce subband nonradiative recombination loss.

[0003] Existing high-power 4.6μm InP-based QCLs have the following four technical shortcomings:

[0004] 1. Severe Joule heat buildup under high current conditions, with thermal roll-off limiting the power limit. Cascaded structures have multiple series stages and high operating voltages. Solid SiC and AlN passive heat sinks combined with TEC cooling generally limit the output power of a single tube to 1~2W at room temperature continuous wave. Under high current, the junction temperature spikes, leading to threshold voltage rise, spectral mode skipping, and output saturation.

[0005] 2. Conflict between high-power heat dissipation solutions and long-term packaging reliability. Diamond microchannel liquid cooling has excellent heat transfer performance, but the thermal expansion coefficients of diamond and InP substrates are mismatched. Only indium solder flip chip can be used. Indium solder has defects such as creep migration, high-temperature oxidation, and temperature cycling delamination. After hundreds of high and low temperature cycles, chip debonding and solder layer void expansion are likely to occur, which cannot meet the requirements for long-term stable service at the equipment level.

[0006] 3. Insufficient lateral thermal conductivity of the chip. Conventional dry etching exposes the ridge waveguide, and the heat is conducted to the heat sink only in the vertical direction. The large lateral temperature gradient in the active area and the uneven gain distribution further aggravate heat loss. Although buried heterojunction can improve lateral thermal conductivity, it does not form a complete closed-loop process system with active liquid cooling heat sink and stress-matched hard soldering packaging.

[0007] 4. Homogeneous microchannel flow structure, resulting in insufficient exploitation of heat transfer efficiency. The fluid inside traditional straight microchannels is mainly in a laminar flow state, with a large heat transfer boundary layer thickness and a low convective heat transfer coefficient. A few turbulence enhancement structures are only sporadically applied to high-power LD heat sinks, and no engineering adaptation schemes have been found for 4.6μm long cavity QCL SiC liquid-cooled substrates. At the same time, there is a lack of array bar integration and expansion schemes, and high-power beam combining can only rely on external optical coupling, which is bulky and has high losses.

[0008] Existing water-cooled heat sink solutions often employ simple straight microchannel structures, resulting in thick coolant boundary layers and large stagnant zones within the channels, thus limiting heat transfer efficiency. Furthermore, most existing solutions focus on single-chip cooling and lack micro-turbulence scattering heat dissipation structures adapted for flip-chip integration of multi-chip bar arrays. In summary, current technologies struggle to simultaneously meet the high-power output requirements of a 4.6μm QCL single tube and the high-power operation demands of multi-chip bar modules. Summary of the Invention

[0009] To overcome the problems of significant thermal roll-off under high power in existing 4.6 μm InP-based QCLs, incompatibility between active liquid cooling and packaging reliability, and low heat transfer efficiency of flat microchannels, this invention provides a SiC microchannel scattering heat dissipation InP-based 4.6 μm QCL and its preparation method. By constructing a three-dimensional heat conduction system of "active region source heat reduction - chip lateral temperature uniform heat conduction - forced convection heat dissipation at the packaging end", the single tube room temperature continuous wave power exceeds 2W.

[0010] The present invention adopts the following technical solution:

[0011] A SiC microchannel scattering heat dissipation InP-based 4.6μm QCL includes an InP-based 4.6μm QCL chip and a microchannel scattering active heat dissipation SiC heat sink;

[0012] The InP-based 4.6μm QCL chip is a triple-well single-LO phonon resonant active region structure and is bonded to the upper surface of the SiC heat sink using a P-side flip-chip method.

[0013] The SiC heat sink has microchannels etched inside, and scattering and turbulence-dissipating units are arranged in an array inside the microchannels. The scattering and turbulence-dissipating units are selected from at least one of rhomboid bosses, cylindrical turbulence-dissipating columns, and serrated flow channel protrusions. Coolant inlet and coolant outlet are respectively provided at both ends of the microchannels to form a liquid-cooled active heat dissipation path.

[0014] A metallized solder layer is provided on the upper surface of the SiC heat sink, and the InP-based 4.6μm QCL chip is soldered to the metallized solder layer area using solder.

[0015] Furthermore, the epitaxial wafer of the InP-based 4.6μm QCL chip comprises, from bottom to top, an InP substrate, an n-InP buffer layer, a lower waveguide confinement layer, a multi-period resonant active region, an upper waveguide confinement layer, and a p-type contact layer. The multi-period resonant active region is formed by cycling a single-period resonant active region 25-35 times. For the single-period resonant active region, it is composed of, in sequence, an injection barrier, a doped injection well, a tunneling isolation barrier, an intrinsic upper-level radiative transition quantum well, an energy level isolation barrier, a lower-level extraction well, and a LO phonon resonant extraction thick barrier. The intrinsic upper-level radiative transition quantum well is an InP substrate. 0.66 Ga0.34 As a compressive strain material, the energy level isolation barrier is In. 0.36 Al 0.64 As tensile strain material;

[0016] The injection region is formed by the injection barrier, the doped injection well, and the tunneling isolation barrier. The luminescent transition region is formed by the intrinsic upper energy level radiative transition quantum well and the energy level isolation barrier. The relaxation region is formed by the lower energy level extraction well. The LO phonon resonance extraction thick barrier is formed by the extraction region.

[0017] The injection region is used to resonantly tunnel the output electrons of the previous cycle into the upper energy level of the laser in the luminescent transition region of the current cycle; in the luminescent transition region, electrons undergo stimulated emission transitions between subbands to generate 4.6μm laser photons; in the relaxation region, the lower energy level electrons of the laser are rapidly nonradiatively relaxed through longitudinal optical phonon scattering; the extraction region extracts the relaxed electrons and transports them to the injection region of the next cycle, realizing electron cascade transport and multiphoton generation.

[0018] Furthermore, a ridge waveguide mesa is etched on the epitaxial wafer. The etching extends from top to bottom through the p-type contact layer, the upper waveguide confinement layer, and the multi-period resonant active region, stopping inside the lower waveguide confinement layer. Grooves are formed on both sides of the ridge waveguide mesa.

[0019] The trench is filled with an Fe:InP semi-insulating layer, which is formed by doping Fe with semi-insulating InP, and the Fe doping concentration is 1~2×10⁻⁶. 17 cm -3 .

[0020] The Fe:InP semi-insulating layer of this invention completely encapsulates the multi-period resonant active region, achieving lateral heat conduction. Compared with the existing exposed etched ridge structure, the heat conduction effect is improved by 2 to 3 times.

[0021] Furthermore, a main channel is provided at each of the two ends of the SiC heat sink, and multiple parallel rectangular microchannels are etched between the two main channels. Fins are formed between the rectangular microchannels, and the scattering and turbulence unit is located inside the rectangular microchannel.

[0022] In existing technologies, SiC heat sinks only have two main channels, which do not circulate between them, resulting in poor heat dissipation. This application etches multiple rectangular microchannels between the two main channels, increasing the flow area. Furthermore, the scattering and turbulence-inducing units force the coolant to generate strong turbulence (the height of the scattering and turbulence-inducing units is 0.4-0.8 times the height of the microchannels), thinning the heat transfer boundary layer and improving the heat transfer coefficient by more than 10% compared to straight microchannels.

[0023] Furthermore, the height of the scattering and turbulence-inducing unit is 0.4-0.8 times the height of the microchannel; the distance between the centers of adjacent scattering and turbulence-inducing units is 100-600 μm. If the distance between the centers of adjacent scattering and turbulence-inducing units is less than 100 μm, the turbulence-inducing units are too densely arranged, the effective flow area of ​​the channel decreases, the fluid pressure drop increases sharply, and the pump load of the cooling system is too high; if the distance between the centers of adjacent scattering and turbulence-inducing units is greater than 600 μm, the turbulence-inducing units are too sparse, the fluid boundary layer cannot be effectively broken, the heat transfer enhancement effect of scattering and turbulence is greatly weakened, and the efficient extraction of high-power QCL heat flux cannot be achieved. The hydraulic diameter of the microchannel is:

[0024]

[0025] W is the width of the microchannel (usually taken as 200µm), H is the depth of the microchannel (typically 300µm), and D is controlled between 50-300µm (typically 240µm).

[0026] Rectangular microchannels are sealed with SiC-SiC low-temperature homogeneous direct-bonded SiC channel caps, forming closed coolant channels. The hydraulic diameter of the microchannels is controlled between 50-300 μm. Inside the undisturbed, straight microchannels, the coolant flows in a laminar state. A continuously thickening flow thermal boundary layer forms on the solid walls, and stagnant dead zones with extremely low flow rates appear at the corners of the channel sidewalls. The boundary layer has poor thermal conductivity, and the fluid in the stagnant dead zones cannot be replaced and remove heat in time, resulting in local hot spots and increasing the thermal resistance of the device. This invention incorporates a scattering and turbulence-inducing unit within a microchannel, comprising rhomboid protrusions, cylindrical turbulence-inducing columns, and serrated flow channel protrusions. Taking a 45° arrangement of rhomboid scattering protrusions as an example: the coolant flows forward along the flow channel, impacting the turbulence-inducing unit, causing fluid diversion and reversal, inducing numerous separation vortices and secondary backflow; the high-speed mainstream fluid rushes into the wall, tearing and thinning the thermal boundary layer; simultaneously, the vortices scour the corner areas of the flow channel, driving previously stagnant fluid to participate in the flow, eliminating dead zones within the flow channel, and promoting the transformation of the fluid from laminar to turbulent flow, enhancing convective heat transfer between the solid and liquid layers, and improving the overall heat dissipation capacity of the heat sink. The cylindrical turbulence-inducing columns generate Karman vortex streets through flow around them, and the serrated deflection channel achieves equivalent boundary layer stripping and elimination of dead zones through continuous flow direction deflection.

[0027] Furthermore, the coolant is deionized water or an aqueous solution of ethylene glycol, and the working flow rate of the coolant is 0.5-5 m / s.

[0028] Furthermore, a bar array composed of multiple InP-based 4.6μm QCL chips is flip-chip mounted on the same metallized solder layer of a microchannel scattering active heat dissipation SiC heat sink to form a high-power QCL bar module.

[0029] A method for preparing the above-mentioned SiC microchannel scattering heat dissipation InP-based 4.6μm QCL includes the following steps:

[0030] S1, Growth of InP-based 4.6μm QCL epitaxial wafer: Using MBE molecular beam epitaxy equipment, an n-InP buffer layer, a lower waveguide confinement layer, a multi-period resonant active region, an upper waveguide confinement layer, and a p-type contact layer are sequentially grown on an InP substrate. The epitaxial wafer is then cleaned, cleaved, and coated to obtain a bare QCL chip.

[0031] S2, SiC heat sink processing: The heat sink substrate is precisely etched to process microchannels and array-type scattering and turbulence units; coolant inlet and coolant outlet are processed at both ends of the channel; Ti / Pt / Au metallization treatment is performed on the upper surface of the SiC heat sink to form a metallized solder layer;

[0032] S3, Solder prefabrication: Prefabricate an Au-Sn solder layer on the metallized solder layer of the SiC heat sink;

[0033] S4, Flip Bonding: A single QCL chip or a bar array composed of multiple QCL chips is flip-mounted with the P-side facing down onto the Au-Sn solder layer area of ​​the SiC heat sink, and then hot-pressed and reflowed to achieve metallurgical bonding between the chip and the SiC heat sink.

[0034] S5, Channel sealing and pipeline assembly: The SiC microchannel is sealed and encapsulated, and connected to an external liquid cooling circulation pipeline; electrode wire bonding is completed to obtain the finished quantum cascade laser device.

[0035] Furthermore, the epitaxial wafer is photolithographically and etched to form a ridge waveguide mesa. The etching proceeds from top to bottom through the p-type contact layer, the upper waveguide confinement layer, and the multi-period resonant active region, stopping inside the lower waveguide confinement layer without completely etching through it. Grooves are formed on both sides of the ridge waveguide mesa.

[0036] A Fe:InP semi-insulating layer was grown using MOCVD equipment in a secondary epitaxial growth process. The Fe:InP semi-insulating layer filled the trenches on both sides of the ridge waveguide. The Fe:InP semi-insulating layer completely wrapped the left and right sidewalls of the multi-period resonant active region, forming a BH buried heterojunction. The sample was then chemically polished to expose the p-type contact layer on the top of the ridge waveguide mesa.

[0037] Furthermore, the heat sink substrate is 6H-SiC. The coefficient of thermal expansion of 6H-SiC heat sink is 4.0 × 10⁻⁶. -6 K -1 The coefficient of thermal expansion of the InP substrate is 4.6 × 10⁻⁶. -6 K -1 The difference in their coefficients of thermal expansion is only 0.6 × 10⁻⁶. -6 K -1The chip is free from warping, buried ridge microcracks, and cleavage surface chipping defects, and can withstand thousands of high and low temperature cycles from -40℃ to 70℃.

[0038] In step S4, the solder used is an Au-Sn eutectic solder layer, with Au accounting for 80% and Sn accounting for 20% by mass percentage.

[0039] The SiC microchannel scattering heat dissipation InP-based 4.6μm QCL prepared by this invention can be widely used in at least one of the following fields:

[0040] (1) TDLAS tunable laser absorption spectroscopy CO trace gas high-precision online monitoring light source, used for continuous online monitoring system of flue gas emissions from thermal power boilers, metallurgical kilns and chemical plants;

[0041] (2) Infrared spectroscopy long-distance inspection and detection equipment for trace leaks in long-distance oil and gas pipelines;

[0042] (3) High-power pump source generated by frequency conversion and difference frequency generation of mid-infrared nonlinear optical crystal;

[0043] (4) Infrared directional infrared photoelectric countermeasures light source for airborne and vehicle-mounted platforms.

[0044] For any details not covered in this invention, please refer to the prior art.

[0045] The beneficial effects of this invention are as follows:

[0046] 1. The active region of the present invention adopts a strain-compensated trap-barrier structure, which reduces dislocations and crystal defects in the MBE epitaxial layer. Through optimization of the active region's energy band, doping, and strain, the total amount of heat generated inside the active region is reduced, thus achieving heat reduction at the source in the active region.

[0047] This invention uses a Fe:InP semi-insulating layer to completely wrap the left and right sidewalls of the active region. After heat is generated in the active region, lateral temperature equalization is first performed inside the chip to eliminate local hot spots and avoid local overheating and burnout, heat roll-off, and spectral drift in the active region, thus achieving lateral temperature equalization and heat conduction of the chip.

[0048] This invention relies on the scattering and turbulence unit of the microchannel to force convection during the encapsulation of the heat sink, ultimately carrying the heat away from the device body and completing the entire heat conduction mechanism, thus achieving forced convection heat dissipation at the encapsulation end.

[0049] This invention significantly reduces the thermal roll-off effect under high-power operation by constructing a three-dimensional heat conduction system consisting of "active area source heat reduction - chip lateral temperature equalization heat conduction - forced convection heat dissipation at the packaging end", achieving a breakthrough of 2 W in single-tube room temperature continuous wave power.

[0050] 2. This invention uses 6H-SiC as the heat sink substrate. Compared with CuW and pure copper heat sinks, its thermal expansion coefficient is more compatible with InP chips. Under flip-chip high-temperature reflow and high-current operating temperature cycling conditions, it significantly reduces the thermomechanical stress between the chip and the heat sink, reducing the risk of chip cracking and solder layer detachment failure. The high thermal conductivity of 6H-SiC itself can ensure that the chip heat is quickly conducted to the microfluidic heat exchange interface.

[0051] 3. The microchannel of the present invention is provided with a scattering turbulence unit, which can be selected from various configurations such as diamond boss, cylindrical turbulence column, and sawtooth flow channel; the turbulence structure destroys the flow boundary layer of coolant, eliminates the stagnation dead zone inside the flow channel, and significantly improves the convective heat transfer coefficient. Compared with ordinary straight microchannel heat dissipation, the junction temperature can be significantly reduced under the same coolant flow rate, supporting higher continuous operating power of QCL chip.

[0052] 4. The same heat sink surface of the present invention supports single-chip packaging as well as multi-chip array bar flip-chip integration, realizing high-power QCL modules and expanding the upper limit of device output power.

[0053] 5. The device of the present invention is designed for the 4.6μm band and can be directly used in industrial scenarios such as CO gas detection, thus possessing practical engineering value. Attached Figure Description

[0054] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0055] Figure 1 This is a schematic diagram of the overall cross-sectional structure of the present invention;

[0056] Figure 2 A top view of the microchannels with rhomboid protrusions inside a SiC heat sink;

[0057] Figure 3 This is a top view of a cylindrical scattering and turbulence-inducing unit.

[0058] Figure 4 A top view of the assembly of a multi-chip bar array flip-mounted on the same SiC heat sink;

[0059] Figure 5 This is a schematic diagram comparing the output power of Example 1 and the comparative example;

[0060] In the figure, 1-InP-based 4.6μm QCL chip, 2-SiC heat sink, 3-metallized solder layer, 4-solder, 5-coolant inlet, 6-coolant outlet, 7-mainstream channel, 8-rectangular microchannel, 9-fins, 10-Fe:InP semi-insulating layer. Detailed Implementation

[0061] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. However, this is not the only description; all aspects not described in detail herein are based on conventional techniques in the art.

[0062] Example 1

[0063] A SiC microchannel scattering heat dissipation InP-based 4.6μm QCL, such as Figure 1 As shown, it includes an InP-based 4.6μm QCL chip 1 and a microchannel scattering active heat dissipation SiC heat sink 2;

[0064] The InP-based 4.6μm QCL chip 1 is a triple-well single-LO phonon resonant active region structure, and is bonded to the upper surface of the SiC heat sink using a P-side flip-chip method.

[0065] The SiC heat sink 2 has microchannels etched inside, and scattering and turbulence-disrupting units are arranged in an array inside the microchannels; such as Figure 1 As shown, in this embodiment, the scattering and turbulence-disrupting unit is a rhomboid boss; coolant inlet 5 and coolant outlet 6 are respectively provided at both ends of the microchannel to form a liquid-cooled active heat dissipation path;

[0066] A metallized solder layer 3 is disposed on the upper surface of the SiC heat sink 2, and the InP-based 4.6μm QCL chip 1 is soldered to the area of ​​the metallized solder layer 3 by solder 4.

[0067] The epitaxial wafer of the InP-based 4.6μm QCL chip 1 comprises, from bottom to top, an InP substrate, an n-InP buffer layer, a lower waveguide confinement layer, a multi-period resonant active region, an upper waveguide confinement layer, and a p-type contact layer. The multi-period resonant active region is formed by cycling a single-period resonant active region 30 times. For the single-period resonant active region, it consists of, in sequence, an injection barrier, a doped injection well, a tunneling isolation barrier, an intrinsic upper-level radiative transition quantum well, an energy level isolation barrier, a lower-level extraction well, and a LO phonon resonant extraction thick barrier. The intrinsic upper-level radiative transition quantum well is an InP substrate. 0.66 Ga 0.34 As a compressive strain material, the energy level isolation barrier is In. 0.36 Al 0.64 As tensile strain material;

[0068] The injection region is formed by the injection barrier, the doped injection well, and the tunneling isolation barrier. The luminescent transition region is formed by the intrinsic upper energy level radiative transition quantum well and the energy level isolation barrier. The relaxation region is formed by the lower energy level extraction well. The LO phonon resonance extraction thick barrier is formed by the extraction region.

[0069] The injection region is used to resonantly tunnel the output electrons of the previous cycle into the upper energy level of the laser in the luminescent transition region of the current cycle; in the luminescent transition region, electrons undergo stimulated emission transitions between subbands to generate 4.6μm laser photons; in the relaxation region, the lower energy level electrons of the laser are rapidly nonradiatively relaxed through longitudinal optical phonon scattering; the extraction region extracts the relaxed electrons and transports them to the injection region of the next cycle, realizing electron cascade transport and multiphoton generation.

[0070] The precise parameters of the single-cycle resonant active region are as follows (after 30 cycles):

[0071] ① i-In 0.36 Al 0.64 As 2.9nm implantation barrier (i indicates intrinsic, undoped);

[0072] ② In 0.66 Ga 0.34 As 4.5nm, Si δ-plane doping 6.7×10 10 cm -2 Doped implantation well;

[0073] ③ i- In 0.36 Al 0.64 As 1.3nm ultrathin tunneling isolation barrier;

[0074] ④ In 0.66 Ga 0.34 As 6.1nm intrinsic upper level radiative transition quantum well;

[0075] ⑤ i- In 0.36 Al 0.64 As a 1.2nm energy level isolation barrier;

[0076] ⑥ In 0.66 Ga 0.34 As a 3.8nm energy level plucked well;

[0077] ⑦ i-In 0.36 Al 0.64 As 4.1nm LO phonon resonance extraction thick barrier;

[0078] Global strains cancel each other out; only the doped implanted wells are doped with Si pulsed δ-plane doping, while the other wells and barriers are not intrinsically doped to reduce free carrier infrared absorption; the growth temperature of the well and barrier regions is fixed at 490 ℃, and a 3 s pause is made after each beam switching to ensure a steep abrupt change in the interface;

[0079] The total thickness of a single cycle is 23.9 nm, and the total thickness of the active region over 30 cycles is 717 nm.

[0080] The epitaxial wafer is etched with a ridge waveguide mesa. The etching extends from top to bottom through the p-type contact layer, the upper waveguide confinement layer, and the multi-period resonant active region, stopping inside the lower waveguide confinement layer. Grooves are formed on both sides of the ridge waveguide mesa.

[0081] The trench is filled with an Fe:InP semi-insulating layer 10, which is formed by doping Fe with semi-insulating InP. The Fe doping concentration is 1~2×10⁻⁶. 17 cm -3 .

[0082] The chip cavity is 3mm long and the ridge width is 12μm; the P-side is flip-chip bonded.

[0083] The Fe:InP semi-insulating layer of this invention completely encapsulates the multi-period resonant active region, achieving lateral heat conduction. Compared with the existing exposed etched ridge structure, the heat conduction effect is improved by 2 to 3 times.

[0084] like Figure 2 As shown, a main channel 7 is provided at each of the two ends of the SiC heat sink. Multiple parallel rectangular microchannels 8 are etched between the two main channels 7. Fins 9 are formed between the rectangular microchannels (coolant does not flow at the fin positions). The scattering and turbulence unit is located in the rectangular microchannels 8.

[0085] In existing technologies, SiC heat sinks only have two main channels, which do not circulate between them, resulting in poor heat dissipation. This application etches multiple rectangular microchannels between the two main channels, increasing the flow area. Furthermore, the scattering and turbulence-inducing units force the coolant to generate strong turbulence (the height of the scattering and turbulence-inducing units is 0.4-0.8 times the height of the microchannels), thinning the heat transfer boundary layer and improving the heat transfer coefficient by more than 10% compared to straight microchannels.

[0086] Furthermore, the height of the scattering and turbulence-inducing unit is 0.4-0.8 times the height of the microchannel; the distance between the centers of adjacent scattering and turbulence-inducing units is 100-600 μm. If the distance between the centers of adjacent scattering and turbulence-inducing units is less than 100 μm, the turbulence-inducing units are too densely arranged, the effective flow area of ​​the channel decreases, the fluid pressure drop increases sharply, and the pump load of the cooling system is too high; if the distance between the centers of adjacent scattering and turbulence-inducing units is greater than 600 μm, the turbulence-inducing units are too sparse, the fluid boundary layer cannot be effectively broken, the heat transfer enhancement effect of scattering and turbulence is greatly weakened, and the efficient extraction of high-power QCL heat flux cannot be achieved. The hydraulic diameter of the microchannel is:

[0087]

[0088] W is the width of the microchannel, which is 200µm in this embodiment; H is the depth of the microchannel, which is 300µm; and D is 240µm.

[0089] Rectangular microchannels are sealed with SiC-SiC low-temperature homogeneous direct-bonded SiC channel caps, forming closed coolant channels. The hydraulic diameter of the microchannels is controlled between 50-300 μm. Inside the undisturbed, straight microchannels, the coolant flows in a laminar state. A continuously thickening flow thermal boundary layer forms on the solid walls, and stagnant dead zones with extremely low flow rates appear at the corners of the channel sidewalls. The boundary layer has poor thermal conductivity, and the fluid in the stagnant dead zones cannot be replaced and remove heat in time, resulting in local hot spots and increasing the thermal resistance of the device. This invention incorporates a scattering and turbulence-inducing unit within a microchannel, comprising rhomboid protrusions, cylindrical turbulence-inducing columns, and serrated flow channel protrusions. Taking a 45° arrangement of rhomboid scattering protrusions as an example: the coolant flows forward along the flow channel, impacting the turbulence-inducing unit, causing fluid diversion and reversal, inducing numerous separation vortices and secondary backflow; the high-speed mainstream fluid rushes into the wall, tearing and thinning the thermal boundary layer; simultaneously, the vortices scour the corner areas of the flow channel, driving previously stagnant fluid to participate in the flow, eliminating dead zones within the flow channel, and promoting the transformation of the fluid from laminar to turbulent flow, enhancing convective heat transfer between the solid and liquid layers, and improving the overall heat dissipation capacity of the heat sink. The cylindrical turbulence-inducing columns generate Karman vortex streets through flow around them, and the serrated deflection channel achieves equivalent boundary layer stripping and elimination of dead zones through continuous flow direction deflection.

[0090] Example 2

[0091] A SiC microchannel scattering and heat dissipation InP-based 4.6μm QCL, as described in Example 1, differs in that the scattering and turbulence-dissipating unit is a cylindrical turbulence-dissipating column, such as... Figure 3 As shown, the cylinder diameter is 80μm, the cylinder height is 0.6 times the flow channel height, and the distance between the centers of adjacent cylindrical turbulence columns is 250μm; the other materials, dimensions, and process parameters remain unchanged.

[0092] Example 3

[0093] A SiC microchannel scattering heat dissipation InP-based 4.6μm QCL, as described in Example 1, differs in that 10 4.6μm QCL chips are simultaneously flip-chip-bonded in the same SiC heat sink metallization layer 3 region to form a bar array, constituting a high-power QCL bar module, as shown below. Figure 4 As shown, all chips are flip-chip mounted on the same SiC heat sink with integrated microchannel scattering and turbulence on their P-sides; they share the same set of coolant input and output channels; and each chip has its own independent electrode bonding.

[0094] This module can achieve power superposition of multiple chips and relies on SiC microchannel scattering heat dissipation to suppress the temperature rise of the overall module, making it suitable for application scenarios that require high total output power.

[0095] From a manufacturing perspective, all the key processes of this invention are based on standard semiconductor processing equipment, which can achieve high consistency and large-scale production. Its low power consumption, high reliability and long lifespan make it widely applicable in the industrial, scientific research and defense fields.

[0096] Example 4

[0097] A method for preparing a SiC microchannel scattering and heat dissipation InP-based 4.6μm QCL includes the following steps:

[0098] S1, epitaxial wafer for growing InP-based 4.6μm QCL chips: MBE molecular beam epitaxy equipment was used, with (100)-oriented n-type Si-doped InP single-crystal wafers as substrates. Growth was performed using a solid-state source MBE equipment, with As2 molecular beams supplied throughout the process, and a constant V / III beam ratio of 18:1. The overall epitaxial stack from top to bottom is as follows:

[0099] n-InP buffer layer, 500 nm thick, grown at 510 ℃;

[0100] Lower waveguide confinement layer, n-type InP, Si uniform doping concentration 2.0 × 10⁻⁶ 17 cm -3 Thickness 1500 nm;

[0101] Multi-period resonant active region, cyclically grown 30-stage 4.6 μm triple-well single-LO phonon resonant strain-compensated periodic structure; well layer is In. 0.66 Ga 0.34 As is a compressive strain material, with In as the barrier layer. 0.36 Al 0.64 As a tensile strain material, the global strain cancels each other out; only the injection well is doped with Si pulsed δ-plane, while the other wells and barriers are intrinsically undoped to reduce the infrared absorption of free carriers; the growth temperature of the well and barrier regions is fixed at 490 ℃, and a 3 s pause is made after each beam switching to ensure a steep abrupt change in the interface;

[0102] The precise parameters of the single-cycle resonant active region are as follows (after 30 cycles):

[0103] ① i-In 0.36 Al 0.64 As 2.9nm implantation barrier (i indicates intrinsic, undoped);

[0104] ② In 0.66 Ga 0.34 As 4.5nm, Si δ-plane doping 6.7×10 10 cm -2 Doped implantation well;

[0105] ③ i- In 0.36 Al0.64 As 1.3nm ultrathin tunneling isolation barrier;

[0106] ④ In 0.66 Ga 0.34 As 6.1nm intrinsic upper level radiative transition quantum well;

[0107] ⑤ i- In 0.36 Al 0.64 As a 1.2nm energy level isolation barrier;

[0108] ⑥ In 0.66 Ga 0.34 As a 3.8nm energy level plucked well;

[0109] ⑦ i-In 0.36 Al 0.64 As 4.1nm LO phonon resonance extraction thick barrier;

[0110] The MBE source furnace temperatures are fixed: In source 845℃, Ga source 910℃, Al source 1125℃, Si doped source 1280℃. The Si source shutter pulse is only opened to introduce silicon beam during the second Si-δ doped implantation well of each cycle. The Si source shutter is closed during the growth stages of the remaining layers. The remaining wells and barrier layers achieve an intrinsic state without intentional doping. The As pyrolysis furnace is 950℃. Throughout the entire MBE growth process, from the InP buffer layer to the top p-InP contact layer, the pyrolysis source valve remains open, continuously outputting the As2 molecular beam and maintaining a constant V / III beam ratio of 18:1. The As pyrolysis source valve is closed after all epitaxial growth is completed.

[0111] Upper waveguide confinement layer, n-type InP, Si uniform doping concentration 2.0 × 10⁻⁶ 17 cm -3 Thickness 1500nm;

[0112] p-type contact layer, heavily doped with n + -InP, Si doping concentration 1×10 19 cm -3 Thickness 300nm.

[0113] The epitaxial wafer is cleaned, cleaved, and coated to obtain the QCL bare chip;

[0114] For the epitaxial photoresist mask, ICP dry etching is used to form ridge waveguide mesa. The etching proceeds from top to bottom through the p-type contact layer, the upper waveguide confinement layer, and the multi-period resonant active region, stopping inside the lower waveguide confinement layer without completely penetrating it. This creates multiple parallel gain ridge mesa with a width of 10-12 μm on the wafer surface. Trenches are formed on the left and right sides of the gain ridge mesa, which are used for subsequent secondary epitaxial Fe:InP semi-insulating buried material.

[0115] A Fe:InP semi-insulating layer was grown using MOCVD equipment in a secondary epitaxial phase. The Fe:InP semi-insulating layer filled the trenches on both sides of the ridge waveguide. The Fe:InP semi-insulating layer completely wrapped the left and right sidewalls of the multi-period resonant active region, forming the thermally conductive structure of the BH buried heterojunction. CMP chemical mechanical polishing was performed to planarize the entire structure and eliminate the height difference of the epitaxial step.

[0116] PECVD deposits a Si3N4 insulating passivation layer, and photolithography creates windows to expose the ohmic contact area;

[0117] Electron beam evaporation of Ti / Au top electrode on P-side; back-side grinding and wet etching of InP substrate to thin to 40-60 μm; evaporation of low-resistivity N-side ohmic electrode of Ge / Au / Ni / Au to complete wafer-level chip fabrication.

[0118] Chip cleavage and high-reliability cavity surface optical coating:

[0119] The wafer is cleaved along the natural InP cleavage plane to fabricate a laser bar with a cavity length of 8mm; a multilayer dielectric HR high-reflectivity film is deposited on the back cavity surface with a reflectivity ≥98.5%; an AR antireflection film is deposited on the front cavity surface with a residual reflectivity ≤0.5%; a Si3N4 protective layer is superimposed on the surface to improve the COD optical catastrophic damage threshold of the cavity surface; the wafer is cleaved under a high-purity nitrogen atmosphere to obtain a single bare chip, which is stored in a clean environment for later use.

[0120] S2, SiC heat sink processing: The heat sink substrate is precisely etched to process microchannels and array-type scattering and turbulence-causing units; coolant inlet and coolant outlet are processed at both ends of the channel; Ti / Pt / Au metallization treatment is performed on the upper surface of the SiC heat sink to form a metallized solder layer;

[0121] The heat sink substrate is 6H-SiC. The coefficient of thermal expansion of 6H-SiC heat sink is 4.0 × 10⁻⁶. -6 K -1 The coefficient of thermal expansion of the InP substrate is 4.6 × 10⁻⁶. -6 K -1 The difference in their coefficients of thermal expansion is only 0.6 × 10⁻⁶. -6 K -1 The chip is free from warping, buried ridge microcracks, and cleavage surface chipping defects, and can withstand thousands of high and low temperature cycles from -40℃ to 70℃.

[0122] The microchannel is equipped with periodic scattering and turbulence-inducing units. In this embodiment, a rhomboid protrusion is selected with the following geometric dimensions: main channel width 250μm, depth 220μm, fin width 100μm; rhomboid protrusion side length 80μm, height 180μm; unetched SiC solids, i.e., fins, are retained between the microchannels of this invention; periodic rhomboid protrusions (turbulence-inducing protrusions) are etched inside each microchannel cavity; then, a SiC cover plate is homogeneously bonded and sealed, and the trench becomes a closed coolant flow cavity.

[0123] The SiC cover plate is installed on the etched back side of the SiC heat sink substrate, where microchannels are machined. It achieves a sealed bond with the substrate through a low-temperature homogeneous direct bonding process between SiC and SiC. It connects to external cooling pipes only through coolant inlets and outlets, forming a pressure-resistant, leak-proof, sealed liquid-cooled cavity. The sealed liquid-cooled cavity can withstand a pressure of ≥0.3MPa to prevent coolant leakage.

[0124] S3, Solder prefabrication: Prefabricate an Au-Sn solder layer on the metallized solder layer of the SiC heat sink;

[0125] The solder used is an Au-Sn eutectic solder layer, with Au accounting for 80% and Sn accounting for 20% by mass percentage.

[0126] S4, Flip Bonding: A single QCL chip or a bar array composed of multiple QCL chips is flip-chip mounted with the P-side facing down onto the Au-Sn solder layer area of ​​the SiC heat sink. The chip is then welded at a constant temperature of 280 ℃ in a vacuum eutectic furnace to achieve metallurgical bonding between the chip and the SiC heat sink. C-SAM ultrasonic scanning detects a void rate of ≤3% in the solder layer, ensuring low thermal resistance at the vertical thermal interface.

[0127] S5, Channel sealing and piping assembly: The SiC microchannel is sealed and encapsulated, and connected to an external liquid cooling circulation pipeline. The coolant is deionized water or ethylene glycol aqueous solution, and the working flow rate of the coolant is 0.5-5m / s.

[0128] The heat sink is fixed to the cold end of the secondary TEC semiconductor cooler and the whole unit is installed in a metal hermetically sealed tube shell. The electrodes are led out by low-impedance gold wire bonding. An external drive and temperature control system is connected to start the liquid cooling cycle and complete the fabrication of a single tube high-power 4.6μm QCL device.

[0129] Comparative example:

[0130] The heat sink uses a common Cu water-cooled heat sink for heat dissipation. This heat sink has only two unconnected main channels, and the rest of the structure is the same as that in Example 1.

[0131] In continuous light operation mode at room temperature, the microchannel SiC heat sink assembly was connected to a coolant circulation system with a coolant temperature of 25°C and a coolant flow rate set to 350 mL / min. Comparative experiments were conducted between the microchannel SiC liquid-cooled heat sink sample of Example 1 of this invention and a conventional heat sink, with output power tests performed under identical room temperature and driving conditions. The results are as follows: Figure 5 As shown, Figure 5 The horizontal axis represents the device input current in A; the vertical axis represents the laser output optical power in W; the orange curve represents the QCL device of Example 1; the blue curve represents the QCL device using a common heat sink.

[0132] from Figure 5 As can be seen, the threshold current for both is approximately 0.72A, indicating that the active region and gain structure of the chip itself remain unchanged; the heat sink heat dissipation structure does not alter the photoelectric gain and lasing threshold characteristics of the laser, making the two sets of comparative experiments comparable. However, under the same current, the microchannel scattering turbulence SiC active liquid cooling scheme of this invention effectively reduces the thermal saturation effect, resulting in a significant increase in output power.

[0133] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A SiC microchannel scattering heat dissipation InP-based 4.6μm QCL, characterized in that, This includes an InP-based 4.6μm QCL chip and a microchannel scattering active heat dissipation SiC heat sink; The InP-based 4.6μm QCL chip is a triple-well single-LO phonon resonant active region structure and is bonded to the upper surface of the SiC heat sink using a P-side flip-chip method. The SiC heat sink has microchannels etched inside, and scattering and turbulence-dissipating units are arranged in an array inside the microchannels. The scattering and turbulence-dissipating units are selected from at least one of rhomboid bosses, cylindrical turbulence-dissipating columns, and serrated flow channel protrusions. Coolant inlet and coolant outlet are respectively provided at both ends of the microchannels to form a liquid-cooled active heat dissipation path. A metallized solder layer is provided on the upper surface of the SiC heat sink, and the InP-based 4.6μm QCL chip is soldered to the metallized solder layer area using solder.

2. The SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 1, characterized in that, The epitaxial wafer of the InP-based 4.6μm QCL chip comprises, from bottom to top, an InP substrate, an n-InP buffer layer, a lower waveguide confinement layer, a multi-period resonant active region, an upper waveguide confinement layer, and a p-type contact layer. The multi-period resonant active region is formed by cycling a single-period resonant active region 25-35 times. For the single-period resonant active region, it is composed of, in sequence, an injection barrier, a doped injection well, a tunneling isolation barrier, an intrinsic upper-level radiative transition quantum well, an energy level isolation barrier, a lower-level extraction well, and an LO phonon resonant extraction thick barrier. The intrinsic upper-level radiative transition quantum well is an InP substrate. 0.66 Ga 0.34 As a compressive strain material, the energy level isolation barrier is In. 0.36 Al 0.64 As tensile strain material; The injection region is composed of an injection barrier, a doped injection well, and a tunneling isolation barrier. The luminescent transition region is composed of an intrinsic upper energy level radiative transition quantum well and an energy level isolation barrier. The relaxation region is composed of a lower energy level extraction well and an LO phonon resonance extraction thick barrier.

3. The SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 2, characterized in that, The epitaxial wafer is etched with a ridge waveguide mesa. The etching extends from top to bottom through the p-type contact layer, the upper waveguide confinement layer, and the multi-period resonant active region, and stops inside the lower waveguide confinement layer. Grooves are formed on both sides of the ridge waveguide mesa. The trench is filled with an Fe:InP semi-insulating layer, which is formed by doping Fe with semi-insulating InP, and the Fe doping concentration is 1~2×10⁻⁶. 17 cm -3 .

4. The SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 3, characterized in that, The SiC heat sink has a main channel at each of its two ends. Multiple parallel rectangular microchannels are etched between the two main channels. Fins are formed between the rectangular microchannels, and the scattering and turbulence unit is located inside the rectangular microchannel.

5. The SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 4, characterized in that, The height of the scattering and turbulence-disrupting unit is 0.4-0.8 times the height of the microchannel; the distance between the centers of adjacent scattering and turbulence-disrupting units is 100-600 μm.

6. The SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 5, characterized in that, The coolant is deionized water or ethylene glycol aqueous solution, and the working flow rate of the coolant is 0.5-5 m / s.

7. The SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 1, characterized in that, A bar array composed of multiple InP-based 4.6μm QCL chips is flip-chip mounted on the same metallized solder layer of a microchannel scattering active heat dissipation SiC heat sink to form a high-power QCL bar module.

8. The method for preparing SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 1, characterized in that, Includes the following steps: S1, Growth of InP-based 4.6μm QCL epitaxial wafer: Using MBE molecular beam epitaxy equipment, an n-InP buffer layer, a lower waveguide confinement layer, a multi-period resonant active region, an upper waveguide confinement layer, and a p-type contact layer are sequentially grown on an InP substrate. The epitaxial wafer is then cleaned, cleaved, and coated to obtain a bare QCL chip. S2, SiC heat sink processing: The heat sink substrate is etched to process microchannels and array-type scattering and turbulence-inducing units; coolant inlet and coolant outlet are processed at both ends of the channel; Ti / Pt / Au metallization treatment is performed on the upper surface of the SiC heat sink to form a metallized solder layer; S3, Solder prefabrication: Prefabricate an Au-Sn solder layer on the metallized solder layer of the SiC heat sink; S4, Flip Bonding: A single QCL chip or a bar array composed of multiple QCL chips is flip-mounted with the P-side facing down onto the solder area of ​​the SiC heat sink, and then hot-pressed and reflowed to achieve metallurgical bonding between the chip and the SiC heat sink. S5, Channel sealing and pipeline assembly: The SiC microchannel is sealed and encapsulated, and connected to an external liquid cooling circulation pipeline; electrode wire bonding is completed to obtain the finished quantum cascade laser device.

9. The method for preparing SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 8, characterized in that, In step S1, the epitaxial wafer is photolithographically etched and etched to form a ridge waveguide mesa. The etching extends from top to bottom through the p-type contact layer, the upper waveguide confinement layer, and the multi-period resonant active region, stopping inside the lower waveguide confinement layer. Grooves are formed on both sides of the ridge waveguide mesa. A Fe:InP semi-insulating layer was grown using a secondary epitaxial growth method with an MOCVD device. The Fe:InP semi-insulating layer filled the trenches on both sides of the ridge waveguide. The sample was then chemically polished to expose the p-type contact layer on top of the ridge waveguide mesa.

10. The method for preparing SiC microchannel scattering heat dissipation InP-based 4.6μm QCL according to claim 8, characterized in that, In step S2, the heat sink substrate is 6H-SiC; In step S4, the solder uses an Au-Sn eutectic solder layer, with Au accounting for 80% and Sn accounting for 20% by mass percentage.

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