Coating method of laser chip, laser chip and packaging structure thereof

Abstract

The application provides a coating method of a laser chip, the laser chip and a packaging structure thereof. The coating method comprises the following steps: providing an epitaxial wafer, growing a first metal layer on a P surface and / or an N surface of the epitaxial wafer; performing a patterning treatment on the epitaxial wafer to expose a preset wrap coating area; forming an induction layer on the first metal layer in the wrap coating area; growing a second metal layer on the induction layer in the wrap coating area and on the first metal layer outside the wrap coating area; cleaving the epitaxial wafer into bars, and the wrap coating area is a region close to a cavity surface edge on the P surface and / or the N surface of the bar; performing an annealing treatment on the bar to form a roughened metal surface with a precipitation structure on the second metal layer in the wrap coating area; and coating an optical film on the cavity surface of the bar, so that the optical film is wrapped on the roughened metal surface to form a wrap coating film. The application solves the problem that the wrap coating film is easy to fall off from the metal surface and the overflow of the solder causes catastrophic damage to the cavity surface in the prior art.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser technology, and in particular to a coating method for a laser chip and a laser chip and its packaging structure. Background Technology

[0002] As a core component of the optoelectronic industry, laser chips possess advantages such as high electro-optical conversion efficiency, small size, and stable performance, and are widely used in industrial processing, optical communication, medical aesthetics, and lidar. Laser chips typically require an anti-reflection coating on the front cavity surface to reduce light reflection loss and increase output power, and a high-reflection coating on the rear cavity surface to improve the efficiency of the laser chip.

[0003] When an optical film is deposited on the cavity surface of a laser chip, there is a width difference between the bar (true bar, LD bar) and the siding bar (also known as false bar, SP bar) formed by the cleavage of the laser chip. That is, the bar is wide and the siding bar is narrow. The optical film layer is not only deposited on the cavity surface of the bar, but also deposited around the metal electrodes on the front (P side) and back (N side) of the bar, forming an optical film flipping, that is, a wrap-around coating.

[0004] However, in existing processes, the adhesion between the optical film and the metal electrodes on the front and back sides of the laser chip is poor. During the packaging process, when the molten solder comes into contact with the edge of the wrap-around film, the optical film is easily lifted and peeled off by the solder due to insufficient adhesion between the optical film and the underlying metal. After the wrap-around film falls off, a tear occurs at the edge connection between the wrap-around film and the cavity optical film, resulting in edge damage to the cavity optical film and affecting its quality. At the same time, the gap formed after the fall-off will further guide the solder to continue flowing, directly overflowing into the core optical film area of ​​the front and back cavity surfaces of the laser chip, causing catastrophic optical damage (COD). Summary of the Invention

[0005] The purpose of this invention is to provide a coating method for laser chips and a laser chip, so as to solve the problems in the prior art where the coating easily falls off the surface of the metal electrode and the solder overflow causes catastrophic damage to the cavity surface.

[0006] To achieve one of the above-mentioned objectives, the present invention provides a coating method for a laser chip, the method comprising the following steps: An epitaxial wafer is provided, wherein a first metal layer is grown on the P-side and / or N-side of the epitaxial wafer; The epitaxial wafer is patterned to expose a pre-defined area around the coating layer. An induction layer is formed on the first metal layer exposed in the area surrounding the coating; A second metal layer is grown on the inducing layer within the coating region and on the first metal layer outside the coating region; The epitaxial wafer is cleaved into bar strips, and the coating area is the region near the cavity edge on the P-side and / or N-side of the bar strip; The bar is annealed to form a roughened metal surface with a precipitation structure on the second metal layer in the area surrounding the coating. An optical film is deposited on the cavity surface of the bar, and then the optical film is deposited around the roughened metal surface to form a wrap-around coating.

[0007] According to one embodiment of the present invention, the first metal layer includes at least an adhesion layer and a barrier functional layer sequentially stacked along the epitaxial direction, wherein the material of the adhesion layer is Ti or Cr, and the material of the barrier functional layer is Pt or Pd.

[0008] According to one embodiment of the present invention, the barrier functional layer is a Pt layer; forming an induction layer on the first metal layer exposed in the surrounding coating area includes: treating the first metal layer exposed in the surrounding coating area with oxygen plasma for a treatment time of 10s to 30s, and forming an oxide layer with a thickness of 1nm to 5nm on the surface of the barrier functional layer, the oxide layer including a PtO layer and / or a PtO2 layer.

[0009] According to one embodiment of the present invention, annealing the bar includes: controlling the substrate temperature of the bar to a preset temperature, the preset temperature being not lower than the decomposition temperature of the oxide layer; in the coating region, the oxide layer is heated and decomposes to release oxygen, the gas pressure generated by the oxygen and the thermal stress generated by annealing jointly drive the second metal layer in the coating region to locally protrude, and cause the grains of the second metal layer to grow, so as to form a roughened metal surface with precipitation structure in the coating region; Outside the area surrounding the coating, the second metal layer remains flat and is bonded to the first metal layer.

[0010] According to one embodiment of the present invention, the blocking functional layer is a Pd layer; Forming an induction layer on the first metal layer exposed in the area surrounding the coating includes: irradiating the first metal layer exposed in the area surrounding the coating with argon plasma, wherein the ion energy of the argon plasma is not greater than 200 eV and the treatment time is 10 s to 30 s, and forming an irradiation damage layer with lattice defects on the surface of the barrier functional layer, wherein the thickness of the irradiation damage layer is not greater than 5 nm.

[0011] According to one embodiment of the present invention, annealing the bar includes: controlling the substrate temperature of the bar to a preset temperature; in the area around the coating, lattice defects in the irradiation-damaged layer form nanovoids during the annealing process, and the stress generated by the aggregation of the nanovoids and the thermal stress generated by the annealing jointly drive the second metal layer in the area around the coating to locally protrude, so as to form a roughened metal surface with precipitation structure in the area around the coating.

[0012] Outside the area surrounding the coating, the second metal layer remains flat and is bonded to the first metal layer.

[0013] According to one embodiment of the present invention, the preset temperature is set to 350°C~400°C; And / or, the preset temperature is positively correlated with the wavelength of the laser chip; And / or, the annealing process time is set to 30 min to 40 min; And / or, the processing time of the annealing process is set according to the wavelength gradient of the laser chip. When the wavelength of the laser chip is greater than or equal to 700nm and less than 800nm, the processing time of the annealing process is 30min; when the wavelength of the laser chip is greater than or equal to 800nm ​​and less than 900nm, the processing time of the annealing process is 35min; when the wavelength of the laser chip is greater than or equal to 900nm, the processing time of the annealing process is 40min.

[0014] According to one embodiment of the present invention, a first metal layer is grown on the P-side and / or N-side of the epitaxial wafer, comprising: growing a first metal layer on the P-side of the epitaxial wafer, wherein the thickness of the adhesion layer in the first metal layer on the P-side is 50±10nm, and the thickness of the barrier functional layer is 100±20nm. And / or, a first metal layer is grown on the N-side of the epitaxial wafer, the first metal layer on the N-side further comprising an ohmic contact layer near the substrate side of the epitaxial wafer, the ohmic contact layer comprising an AuGe layer and a Ni layer sequentially stacked along the epitaxial direction, wherein the thickness of the AuGe layer is 200±20nm and the thickness of the Ni layer is 80±10nm; the thickness of the adhesion layer in the first metal layer on the N-side is 20±5nm and the thickness of the barrier layer is 50±10nm.

[0015] According to one embodiment of the present invention, growing a second metal layer on the induction layer within the coating region and on a first metal layer outside the coating region includes: controlling the substrate temperature of the epitaxial wafer to be below 150°C; depositing the second metal layer by electron beam evaporation; the second metal layer is an Au layer with a thickness of 500±20 nm; And / or, after growing the second metal layer, the coating method further includes: electroplating a third metal layer on the second metal layer outside the coating area on the P-side, the third metal layer being an Au layer with a thickness of 3000±200nm. And / or, patterning the epitaxial wafer to expose a preset coating area around the epitaxial wafer includes: coating a photoresist on the surface of the first metal layer; patterning and developing the coating area to remove the photoresist from the coating area, thereby exposing the first metal layer in the coating area and covering the first metal layer in other areas with the photoresist. After forming an induction layer on the first metal layer exposed in the area surrounding the coating, the coating method further includes removing the photoresist.

[0016] According to one embodiment of the present invention, before annealing the bar strip, the cavity surface of the bar strip is further cleaned and passivated: The bar strip and the auxiliary strip are arranged in the coating fixture, wherein the width of the bar strip along the length of the cavity is greater than the width of the auxiliary strip along the length of the cavity, so as to expose the coating area of ​​the bar strip. The coating fixture is placed into the growth chamber, and the air pressure inside the growth chamber is maintained at no higher than 1×10⁻⁶. - 8 Torr; The bar strips are heated to a temperature not lower than 200°C for 10 to 20 minutes. The pressure of the Ar and H2 mixture introduced into the growth chamber reaches 1×10⁻⁶. -5 Torr, turn on the radio frequency plasma source, and perform cavity surface treatment on the bar strip for a processing time of not less than 50 minutes; Ar gas is turned off, N2 gas is introduced, and the ratio of N2 to H2 is controlled to be 6:1 to 10:1. A passivation film with a thickness of at least 10 nm is deposited on the cavity surface of the bar by electron beam evaporation. And / or, the cavity surface includes the front cavity surface and the rear cavity surface of the bar; depositing an optical film on the cavity surface of the bar includes: depositing an antireflective film on the front cavity surface of the bar and depositing a high reflective film on the rear cavity surface of the bar; the optical film includes at least one high refractive index material selected from Si, HfO2, and Ta2O5, and at least one low refractive index material selected from SiO2, Al2O3, and MgF2.

[0017] The present invention also provides a laser chip, the laser chip comprising: Epitaxial wafer; A first metal layer is disposed on the P-plane and / or N-plane of the epitaxial wafer. The first metal layer includes an adhesion layer and a barrier layer that are sequentially stacked along the epitaxial direction. The second metal layer includes a roughened metal surface with a precipitation structure formed in the coating region near the cavity surface on the P-side and / or N-side of the laser chip, wherein the roughness of the roughened metal surface is greater than the roughness of the surface of other regions of the second metal layer. A coating is applied around the roughened metal surface within the area covered by the coating.

[0018] The present invention also provides a laser chip packaging structure, including a heat sink, solder, and a laser chip as described in the above embodiments; the laser chip is fixed to the heat sink by the solder; the coating is attached to the roughened metal surface to prevent the solder from overflowing to the cavity surface.

[0019] The beneficial effects of this invention are as follows: By pre-embedding an induction layer (PtO / PtO2 oxide layer or Pd irradiation damage layer) on the first metal layer in the coating region and covering it with a second metal layer (Au layer), and then using high-temperature annealing, the induction layer forms a roughened metal surface with a precipitation structure in situ within the coating region. This roughened metal surface interlocks with the subsequently deposited optical film coated onto the coating region, forming a physical interlocking structure. Compared to the film adhesion maintained solely by intermolecular forces on a flat metal surface, the interfacial bonding strength between the coating and the second metal layer is significantly improved. During the packaging process, even if the molten solder impacts and entrains the edges of the coating, the coating can still firmly adhere to the roughened metal surface, making it difficult to be lifted or peeled off by the solder. This avoids solder overflow into the core optical film area of ​​the front and rear cavity surfaces of the chip, preventing catastrophic cavity damage (COD) and significantly improving the packaging yield and long-term operational reliability of the laser chip.

[0020] This invention uses patterning to roughen only the area around the coating layer, leaving the surface of the second metal layer in other areas of the chip smooth, without affecting subsequent bonding and packaging processes. At the same time, the coating method can directly utilize existing mass production processes without the need for additional complex equipment, demonstrating good feasibility and compatibility. Attached Figure Description

[0021] Figure 1 This is a schematic flowchart of a laser chip coating method provided in an embodiment of the present invention; Figure 2 Schematic diagram of the steps involved in fabricating the electrode structure for a laser chip; Figure 3 This is a top view of the structure of a laser chip on the P-side according to an embodiment of the present invention; Figure 4This is a schematic diagram showing the arrangement of the bar strips and the auxiliary strips in the coating fixture according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a coating growth chamber provided in an embodiment of the present invention; Figure 6 This is a comparative schematic diagram of the metal surface morphology before and after annealing and roughening, provided in an embodiment of the present invention. Figure 7 This is a comparative schematic diagram of the coating morphology of a normal metal surface and a roughened metal surface provided in an embodiment of the present invention. Among them, 1. Epitaxial wafer; 11. Coating area; 12. Cavity surface; 2. First metal layer; 3. Second metal layer; 4. Third metal layer; 5. Optical film; 51. Coating area; 6. Parallel bar; 7. Bar bar; 8. Single-tube laser chip; 100. Substrate heater; 200. Radio frequency plasma source; 300. Electron beam evaporation device; 400. Coating fixture. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0024] For ease of explanation, this document uses terms indicating relative spatial position, such as "above," "below," "behind," and "front," to describe the relationship of one unit or feature shown in the accompanying drawings relative to another unit or feature. Terms indicating relative spatial position can include different orientations of the device during use or operation besides those shown in the figures. For example, if the device in the figures is flipped, a unit described as being "below" or "above" other units or features will be located "below" or "above" other units or features. Therefore, the exemplary term "below" can encompass both "below" and "above" spatial orientations.

[0025] This invention provides a coating method for laser chips; please refer to [the relevant documentation]. Figure 1 The laser chip coating method provided in one embodiment of the present invention includes the following steps: Step S1: Provide an epitaxial wafer 1, and grow a first metal layer 2 on at least one side surface of the epitaxial wafer 1.

[0026] Specifically, please refer to Figure 2 Epitaxial wafer 1 is a wafer that has completed epitaxial growth, and P-side and N-side electrode structures are to be fabricated. In this embodiment, the first metal layer 2 is grown on the P-side (front side) and N-side (back side) respectively by electron beam evaporation.

[0027] The first metal layer 2 includes at least an adhesion layer and a barrier layer sequentially stacked along the epitaxial direction. The adhesion layer is made of Ti or Cr and is used to enhance the adhesion between the first metal layer 2 and the surface of the epitaxial wafer 1. The barrier layer is made of Pt or Pd and its function is to prevent the upper metal layer from diffusing downwards through the adhesion layer during high-temperature annealing or encapsulation, preventing the upper metal layer from reacting with the epitaxial wafer 1 to generate high-resistivity defects, and isolating the adhesion layer from the mutual solubility of the upper metal layer. The barrier layer also serves as a functional layer for subsequent induction processing.

[0028] In one embodiment, the first metal layer 2 on the P-side is a first stack formed by an adhesion layer and a barrier layer. The adhesion layer is a Ti layer or a Cr layer with a thickness of 50 ± 10 nm, used to enhance the adhesion between the first metal layer 2 and the surface of the epitaxial wafer 1. The barrier layer is a Pt layer or a Pd layer with a thickness of 100 ± 20 nm. This thickness setting ensures that the barrier layer on the P-side has sufficient thickness to provide adequate diffusion blocking capability.

[0029] The first metal layer 2 on the N-side is a second stacked layer formed by an ohmic contact layer, an adhesion layer, and a barrier layer. Specifically, the first metal layer 2 on the N-side is a second stacked layer formed by an AuGe layer, a Ni layer, a Ti layer or a Cr layer, and a Pt layer or a Pd layer. The ohmic contact layer includes an AuGe layer and a Ni layer stacked sequentially along the epitaxial direction. The AuGe layer has a thickness of 200±20 nm and is used to reduce the contact resistance between the first metal layer 2 and the epitaxial wafer 1. During annealing, Ge elements diffuse into N-GaAs to form a heavily doped alloy layer, achieving extremely low N-type contact resistance. The Ni layer, as a diffusion barrier layer, has a thickness of 80±10 nm and is used to prevent mutual diffusion between the AuGe layer and subsequent metal layers. The adhesion layer is a Ti layer or a Cr layer with a thickness of 20±5 nm, and the barrier layer is a Pt layer or a Pd layer with a thickness of 50±10 nm.

[0030] In this embodiment, the first metal layer 2 includes a barrier functional layer, namely a Pt layer or a Pd layer, which can be processed and induced to roughen in subsequent processes. When the barrier functional layer is Pt, a PtO / PtO2 oxide layer can be formed by oxygen plasma oxidation as the inducing layer; when the barrier functional layer is Pd, a lattice defect layer can be formed by argon plasma irradiation as the inducing layer. Specific implementations of the two schemes will be described in detail in the subsequent step S3.

[0031] It should be noted that the specific materials and thicknesses of the above layers can be adjusted according to actual process requirements, and the present invention is not limited to the specific values ​​mentioned above. The first metal layer 2 can also be provided only on the P-side or only on the N-side, as long as a barrier layer containing Pt or Pd is provided on the surface where the coating 51 needs to be formed subsequently.

[0032] Step S2: Perform patterning processing on the epitaxial wafer 1 to expose the preset coating area 11 of the epitaxial wafer 1.

[0033] In this embodiment, the coating region 11 refers to a specific edge region on the P-side and / or N-side of the epitaxial wafer 1 that is close to the cavity surface 12. This region will be covered by the optical film 5 during the subsequent coating process of the cavity surface 12, forming a coating 51, and will act as a barrier to prevent solder flow during the subsequent packaging process.

[0034] The length of the coating region 11 along the cavity length direction, that is, the distance extending from the edge of the cavity surface 12 towards the center of the chip, is 15μm to 25μm. If the length of the coating region 11 along the cavity length direction is too small, for example, less than 15μm, the coverage area of ​​the coating 51 on the chip surface will be insufficient, making it difficult to reliably block the lateral flow of molten solder during the packaging process. The solder may still overflow across the coating 51 into the cavity surface 12 area.

[0035] If the length of the coating area 11 along the cavity length is too large, for example, greater than 25μm, it will result in an excessively large coverage area of ​​the coating 51, occupying too much area on the chip surface. This will make it easy for subsequent inspection processes to judge it as a contaminated or abnormal film layer, affecting product yield. Furthermore, the coating area 11 is located outside the third metal layer 4 on the P-side. If this area is too long, it will encroach on the area of ​​the central third metal layer 4 on the P-side, affecting the normal spread of solder on the third metal layer 4, and thus affecting the soldering quality between the chip and the heat sink. In addition, an excessively long coating area will also reduce the effective heat dissipation area of ​​the third metal layer 4, affecting the heat dissipation performance of the chip.

[0036] The length of the coating area 11 along the cavity length direction can be adjusted according to parameters such as the cavity length of the laser chip and the total length of the bar 7. Those skilled in the art can flexibly set it according to actual packaging requirements.

[0037] Specifically, the graphical processing includes the following steps: First, photoresist is coated on the surface of the first metal layer 2. The type of photoresist can be either positive or negative; in this embodiment, positive photoresist is preferred to facilitate subsequent patterning exposure and development.

[0038] Next, the area around the coating 11 is patterned by exposure and development. The area around the coating 11 is exposed to ultraviolet light through a mask, and after development, the photoresist in that area is removed, exposing the first metal layer 2 of the area around the coating 11, while the first metal layer 2 in other areas remains covered by photoresist.

[0039] Through the above patterning process, the area around the coating 51 is exposed in a localized manner. Only the first metal layer 2 in the edge region where the coating 51 will be formed is exposed, while the first metal layer 2 in other areas of the epitaxial wafer 1 is protected by photoresist and will not be affected by subsequent processing. This localized processing method ensures that the roughening process only occurs in specific areas at the edge of the laser chip, without affecting the metal surface morphology and electrical properties of other areas of the laser chip, thus guaranteeing the consistency of the overall performance of the laser chip.

[0040] Step S3: Form an induction layer on the first metal layer 2 exposed in the surrounding coating region 11.

[0041] The present invention provides two different implementation methods depending on the material of the barrier functional layer in the first metal layer 2.

[0042] In one embodiment, when the barrier layer is a Pt layer, the first metal layer 2 exposed around the coating region 11 is treated with oxygen plasma. Specifically, the patterned epitaxial wafer 1 is fed into a plasma treatment apparatus, O2 is introduced, and oxygen plasma is used for treatment under low vacuum conditions.

[0043] The active oxygen in the oxygen plasma reacts with the exposed Pt surface of the barrier functional layer, forming an oxide layer on the Pt surface containing a PtO layer and / or a PtO2 layer. The thickness of the oxide layer can be controlled from 1 nm to 5 nm by setting the processing time. If the oxide layer is too thin, such as less than 1 nm, the oxygen atoms precipitated during subsequent annealing may not be sufficient to drive the sufficient recombination and growth of the metal grains, making it difficult to form an effective roughening structure. If the oxide layer is too thick, such as greater than 5 nm, it may affect the structural integrity of the first metal layer 2, adversely affecting the electrical performance of the chip.

[0044] The oxygen plasma treatment time is controlled within the range of 10s to 30s, which ensures that the oxidation reaction is fully carried out while avoiding excessive oxidation that could damage the Pt layer.

[0045] After an oxide layer is formed on the first metal layer 2 exposed in the coating region 11, the photoresist covering other areas is removed.

[0046] In another embodiment, when the barrier functional layer is a Pd layer, the first metal layer 2 exposed around the coating region 11 is irradiated with argon plasma. Specifically, the patterned epitaxial wafer 1 is fed into a plasma processing apparatus, Ar is introduced, and argon plasma is used for processing under low vacuum conditions.

[0047] Since the oxide decomposition temperature of Pd layers is typically above 700°C, the interdiffusion between the Pd layer and the subsequently grown second metal layer becomes extremely intense at this temperature, leading to alloying of the first and second metal layers and resulting in device structure destruction. Therefore, Pd layers cannot adopt the same oxidation decomposition path as Pt layers. This invention provides a method that uses low-energy argon plasma physical bombardment to introduce lattice defects into the surface of the Pd layer.

[0048] The ion energy of the argon plasma needs to be controlled below 200 eV, preferably 100 eV to 180 eV, and the processing time should be 10 s to 30 s. Too high an energy will result in processing the Pd layer too deeply or even sputtering off a large amount of Pd film, while too low an energy will make it difficult to form effective lattice defects.

[0049] Through the above treatment, an irradiation-damaged layer, i.e. an induced layer, with lattice defects is formed on the surface of the barrier functional layer. The thickness of this irradiation-damaged layer is no more than 5 nm. The irradiation-damaged layer contains a large number of vacancies, dislocations, lattice distortions, and surface compressive stress. At the same time, some Ar atoms are trapped on the surface of the Pd layer. These lattice defects will serve as the driving force for roughening during the subsequent annealing process.

[0050] After forming an irradiation damage layer on the first metal layer 2 exposed in the coating region 11, the photoresist covering other areas is removed.

[0051] Step S4: Grow a second metal layer 3 on the surface of the first metal layer 2 and the induction layer.

[0052] In this embodiment, the substrate temperature of the epitaxial wafer 1 is controlled to be below 150°C, and the second metal layer 3 is deposited by electron beam evaporation. The second metal layer 3 is an Au layer with a thickness of 500±20 nm.

[0053] The key role of low-temperature deposition is that, during the growth of the second metal layer 3, the previously formed inducing layer (PtO / PtO2 oxide layer or Pd irradiation-damaged layer) must not decompose or anneal. If the substrate temperature is too high, the inducing layer may begin to change during the deposition of the second metal layer 3, resulting in the inability to effectively induce the recombination and growth of metal grains during subsequent annealing, thus affecting the roughening effect.

[0054] Au, as the second metal layer 3, possesses excellent electrical conductivity and chemical stability, making it a commonly used material for semiconductor laser electrodes. Furthermore, Au exhibits good thermal stability at subsequent annealing temperatures, enabling it to form a stable, roughened metal surface with precipitated structures during the induced grain recombination process following changes in the induced layer.

[0055] It should be noted that the second metal layer 3 is deposited using electron beam evaporation in this embodiment, but the present invention is not limited to this. In other embodiments, other suitable physical vapor deposition methods such as thermal evaporation and sputtering can also be used, as long as the second metal layer 3 can be grown under low-temperature conditions.

[0056] Furthermore, in some embodiments of the present invention, after growing the second metal layer 3, a third metal layer 4 is electroplated and grown in a predetermined region of the second metal layer 3 on the P-side. The predetermined region is a central electrode region or bonding region other than the coating region 11, where the third metal layer 4 is grown to meet the requirements of current injection and electrode thickness.

[0057] Specifically, the P-side is patterned to expose a predetermined area, while the remaining areas are covered with photoresist. Then, a third metal layer 4, an Au layer, is grown using electroplating with a thickness of 3000±200 nm. This Au layer provides sufficient thickness for subsequent packaging and soldering, ensuring soldering reliability and ohmic contact performance. Compared to electron beam evaporation, electroplating offers advantages such as lower cost and faster deposition rate, making it suitable for large-scale fabrication of thick Au layers.

[0058] Step S5: The epitaxial wafer 1 is cleaved into bar strips 7, and the bar strips 7 are annealed to form a roughened metal surface with precipitation structure on the second metal layer 3 within the coating region 11.

[0059] In this embodiment, such as Figure 2 and 3 As shown, the epitaxial wafer 1 is first cleaved into bar strips 7 using automated equipment in an atmospheric environment. Bar strip 7 is a long strip-shaped chip unit formed by cleaving the epitaxial wafer 1 along a direction perpendicular to the cavity length. Each bar strip 7 contains multiple unseparated single-tube laser chips 8. The aforementioned coating area is the region on the P-face and / or N-face of the bar strip 7 near the edge of the cavity surface 12.

[0060] Subsequently, referring to Figure 4As shown, bar 7 and auxiliary bar 6 (SP Bar) are arranged in the coating fixture 400. The width of bar 7 along the cavity length direction is greater than the width of auxiliary bar 6 along the cavity length direction, so as to expose the coating area 11 of bar 7. The coating area 11 of bar 7, that is, the edge area of ​​bar 7 along the cavity length direction, protrudes from auxiliary bar 6. This arrangement ensures that the cavity surface 12 of bar 7 will not be blocked by auxiliary bar 6 during subsequent cavity surface 12 coating, so that optical film 5 can completely cover cavity surface 12. On the other hand, it allows optical film 5 to be coated around the edge area of ​​bar 7 on the P and / or N surfaces of bar 7 through the part of bar 7 protruding from auxiliary bar 6 during coating, forming a coating 51.

[0061] In one embodiment, the cavity surface 12 of the bar strip 7 is cleaned and passivated before the annealing process.

[0062] Specifically, such as Figure 5 As shown, the coating fixture 400, which has bar strips 7 and auxiliary strips 6 arranged in a row, is placed into the vacuum growth chamber, and the vacuum is evacuated until the gas pressure in the growth chamber does not exceed 1×10⁻⁶. -8 Torr. The high vacuum environment can prevent the cavity surface 12 from being oxidized or contaminated during the heating process.

[0063] The bar strip 7 is heated by the substrate heater 100 to a temperature not lower than 200°C for 10 to 20 minutes to remove moisture and volatile contaminants adsorbed on the cavity surface 12. This step prevents moisture and contaminants on the cavity surface 12 from affecting the adhesion and optical performance of the optical film 5, thereby improving the coating quality of the cavity surface 12.

[0064] Next, a mixture of Ar and H2 gas is introduced into the growth chamber until the pressure reaches 1×10⁻⁶. -5 Torr-level, the radio frequency plasma source 200 is turned on to treat the cavity surface 12 of the bar 7 for no less than 50 minutes, with the power set to 500W. Ar / H2 plasma treatment can further clean the cavity surface 12, removing surface oxides and organic contaminants. At the same time, the reduction effect of H2 can passivate the cavity surface 12, reducing the surface state density.

[0065] Then, the Ar gas was shut off, and N2 gas was introduced, controlling the N2 to H2 ratio to be 6:1 to 10:1. A passivation film with a thickness of at least 10 nm was deposited on the cavity surface 12 of bar 7 using electron beam evaporation. During deposition, either a Si or Al crucible could be used. Specifically, when using a Si crucible, the Si evaporation rate was controlled at 0.4 to 0.5 Å / s; when using an Al crucible, the Al evaporation rate was controlled at 0.05 to 0.1 Å / s. The resulting passivation film material was SiN:H x Or AlN:H xThe passivation film serves as a protective layer for the cavity surface 12, protecting it from contamination or damage during subsequent annealing processes.

[0066] After cleaning and passivation of the cavity surface 12, an annealing roughening process is performed. Specifically, the bar strips 7 arranged in the coating fixture 400 are placed into the growth chamber, and the substrate heater 100 is heated to a preset temperature to perform annealing on the bar strips 7.

[0067] For the PtO / PtO2 oxide layer induction scheme, the preset temperature is not lower than the decomposition temperature of the induced layer; for the Pd irradiation damage layer induction scheme, the preset temperature is not lower than the activation temperature. In this embodiment, the preset temperature is uniformly set to 350°C~400°C. The annealing treatment time is set to 30min~40min.

[0068] The selection of annealing temperature and time is the key parameter for achieving controllable roughening in this invention.

[0069] Depending on the type of induction layer, its mechanism of action is as follows: If a PtO / PtO2 oxide layer is formed on the surface of the first metal layer 2 around the coating region 11 in step S3, when the annealing temperature rises to 350°C~400°C, the oxygen atoms in the PtO / PtO2 oxide layer gain enough energy to begin precipitation. The PtO / PtO2 oxide layer decomposes from about 350°C in a high vacuum environment, usually following a two-step process from PtO2 to PtO and from PtO to Pt. The oxygen generated by the decomposition of the oxide layer forms a gas pressure between the closed metal layers. This gas pressure acts as the main driving force, driving the second metal layer 3 (Au layer) covering the oxide layer to bulge upwards. At the same time, combined with the effect of thermal stress, the precipitation of oxygen atoms breaks the thermodynamic equilibrium state of the metal surface, allowing the metal grains of the second metal layer 3 covering the oxide layer and the Pt layer in the first metal layer 2 within the coating region 11 to gain additional energy for migration and rearrangement. Driven by thermodynamics, these metal grains gradually recombine and grow, forming larger grain aggregates, and eventually forming a roughened metal surface with precipitation structures.

[0070] Since the oxidation treatment in step S3 only acts on the surface region of the Pt layer, the Pt layer itself remains in a metallic state, and its diffusion barrier capability is fully preserved. During the annealing process, although the surface PtO / PtO2 decomposes, the Pt layer generated after decomposition remains in situ, forming a continuous metallic layer with the underlying unoxidized Pt layer. Therefore, the overall density and diffusion barrier function of the Pt layer are not affected.

[0071] Within the coating region 11, the combined effect of O2 gas pressure and thermal stress causes the upper second metal layer 3 (Au layer) to bulge upwards, forming a precipitation structure. Outside the coating region 11, in areas not treated with oxygen plasma, the Au layer remains flat and firmly bonded to the Pt layer. This selective roughening ensures the flatness of the electrode surface in the central region of the laser chip, without affecting subsequent bonding and packaging processes.

[0072] If, in step S3, an irradiation-damaged layer is formed on the surface of the first metal layer 2 surrounding the coating region 11, when the annealing temperature rises to 350°C~400°C, lattice defects in the irradiation-damaged layer, such as vacancies, dislocations, and lattice distortions, gain energy during annealing and migrate and aggregate, forming nanovoids. Simultaneously, some Ar atoms trapped near the surface of Pd also promote void formation. The aggregation of these nanovoids, combined with thermal stress, drives the second metal layer 3 (Au layer) covering the irradiation-damaged layer to bulge upwards, forming a raised precipitation structure, ultimately resulting in a roughened metal surface with precipitation structures. The preset temperature is not lower than the activation temperature of the irradiation-damaged layer to ensure that lattice defects can fully migrate and aggregate.

[0073] Because the energy of argon plasma irradiation is strictly controlled below 200 eV and the processing time is 10-30 s, the irradiation damage only affects a region of no more than 5 nm on the surface of the Pd layer. The underlying Pd layer remains intact, with a complete crystal structure, and its function of preventing the downward diffusion of the second metal layer 3 (Au layer) is preserved. Due to the thinness of the damaged layer, the migration and aggregation of defects during annealing only occur near the surface and do not substantially affect the overall structural integrity of the Pd layer.

[0074] Within the coating region 11, the aggregation of Pd near-surface nanopores and the combined effect of thermal stress cause the Au layer to bulge upwards, forming a precipitation structure. Outside the coating region 11, in areas not irradiated by argon plasma, the Au layer remains flat and firmly bonded to the Pd layer. This selective roughening ensures the flatness of the electrode surface in the central region of the laser chip, without affecting subsequent bonding and packaging processes.

[0075] The roughening process formed by the two implementation methods does not require the introduction of external materials or physical bombardment of the surface. Instead, it is achieved through the grain recombination and growth of the first and second metal layers themselves. The roughened metal surface with precipitation structure is metallurgically bonded to the first metal layer 2, and there is no weak interface layer, resulting in extremely high structural stability.

[0076] During the annealing roughening process, it is necessary to control the appropriate annealing temperature and annealing time. If the temperature is too low or the time is too short, the induced layer change will be incomplete, the oxide layer decomposition will be insufficient, or the defect migration will be insufficient. The metal grains will not be able to obtain enough energy for migration and recombination, and the roughening effect will be insignificant. If the temperature is too high or the time is too long, it may lead to excessive growth of metal grains and excessive roughness, which will have an adverse effect on other structures of the chip.

[0077] In some embodiments of the present invention, the preset temperature can also be adjusted according to the wavelength of the laser chip. Specifically, the preset temperature is positively correlated with the wavelength of the laser chip. The longer the wavelength of the laser chip, the thicker its film system is usually, and the greater the stress accumulation. Accordingly, the annealing temperature is increased to obtain a greater surface roughness, so as to provide stronger mechanical bonding force and anti-peeling ability. Conversely, for laser chips with shorter wavelengths, the annealing temperature can be appropriately reduced to avoid excessive roughening leading to increased brittleness of the coating 51.

[0078] In some embodiments of the present invention, the annealing time can also be adjusted according to the wavelength of the laser chip. Laser chips with different wavelengths have different thicknesses of optical films on the cavity surface 12 and different degrees of stress accumulation in the film layers. By adjusting the annealing time, a roughness suitable for different film thicknesses can be obtained, thereby optimizing the adhesion effect between the coated film 51 and the metal surface and improving product reliability.

[0079] Specifically, the annealing time is positively correlated with the wavelength of the laser chip. The longer the wavelength of the laser chip, the thicker its film system and the greater the stress accumulation. Correspondingly, extending the annealing time can obtain a greater surface roughness, thereby providing stronger mechanical bonding force and anti-peeling ability. Conversely, for laser chips with shorter wavelengths, the annealing time can be appropriately shortened to avoid excessive roughening that would increase the brittleness of the coating 51.

[0080] The annealing time can be set according to the wavelength gradient of the laser chip. When the wavelength of the laser chip is greater than or equal to 700nm and less than 800nm, the annealing time is 30 minutes; when the wavelength of the laser chip is greater than or equal to 800nm ​​and less than 900nm, the annealing time is 35 minutes; and when the wavelength of the laser chip is greater than or equal to 900nm, the annealing time is 40 minutes. These time settings are determined based on the differences in film thickness and stress accumulation of chips at different wavelengths, ensuring that chips in each wavelength range achieve suitable roughness.

[0081] Preferably, the annealing time should not exceed 40 minutes. Excessive heating time will cause the decomposition of the cavity passivation layer (SiN:Hx or AlN:Hx), affecting the reliability and lifespan of the chip.

[0082] Through the above annealing process, a roughened metal surface with precipitation structure is formed in the coating area 11. The microstructure of this roughened metal surface exhibits an uneven granular or island-like structure, and its surface roughness is greater than that of the untreated area.

[0083] like Figure 6 As shown, through comparative observation using scanning electron microscopy, the normal metal surface (unroughened area) exhibits a relatively smooth grain morphology with minimal surface undulation. However, the metal surface of the coating area 11 after annealing and roughening treatment displays densely distributed micron / submicron-level protrusions and pits, with the surface roughness Ra increasing from tens of nanometers to hundreds of nanometers or even micrometers.

[0084] Step S6: Deposit an optical film 5 on the cavity surface 12 of the bar 7, so that the optical film 5 is deposited around the roughened metal surface to form a wrap-around coating 51.

[0085] In this embodiment, an electron beam evaporation apparatus 300 is used with an RF plasma source 200 to deposit an optical film 5 on the cavity surface 12 of the bar 7. Specifically, an anti-reflection film (AR film) is deposited on the front cavity surface of the bar 7 to reduce light reflection loss and increase output power; a high-reflection film (HR film) is deposited on the rear cavity surface of the bar 7 to improve the efficiency of the laser chip.

[0086] The optical film 5 comprises alternating layers of high-refractive-index and low-refractive-index materials. The film system design is determined based on the emission wavelength of the laser chip and the required reflectivity. The high-refractive-index material can be selected from any one or more of Si, HfO2, Ta2O5, etc.; the low-refractive-index material can be selected from any one or more of SiO2, Al2O3, MgF2, etc. By alternating the stacking of high-refractive-index and low-refractive-index layers, the desired anti-reflection or high-reflectivity optical properties can be achieved.

[0087] During the coating process on the cavity surface 12, since the width of the bar 7 in the cavity length direction is greater than the width of the auxiliary bar 6 in the cavity length direction, the coating area 11 of the bar 7 protrudes from the auxiliary bar 6. Therefore, while the optical film 5 is coated on the cavity surface 12 of the bar 7, it will also be coated around the edge area of ​​the P-side and / or N-side of the bar 7 through the part of the bar 7 that protrudes from the auxiliary bar 6, i.e., the coating area 11 after the aforementioned roughening treatment. As a result, a coating 51 is formed on the roughened metal surface.

[0088] Since a roughened metal surface has been formed around the coating area 11, the optical film 5 will be embedded in the uneven structure of the roughened metal surface during the deposition process, forming a mechanical interlocking effect between the film and the metal, increasing the contact area between the optical film 5 and the metal electrode, and forming a physical interlocking structure, which greatly improves the interfacial bonding strength between the optical film 5 and the metal.

[0089] Compared to the adhesion of a film layer on a smooth metal surface, which relies solely on intermolecular forces, the mechanical interlocking effect between the roughened metal surface and the optical film 5 provides additional anchoring force. During subsequent packaging, even if molten solder impacts and entrains the edges of the coating 51, the coating 51 remains firmly attached to the roughened metal surface due to the mechanical interlocking effect, making it difficult for the solder to lift or peel it off.

[0090] like Figure 7 As shown, comparative observation using a scanning electron microscope reveals that the coating 51 on a normal metal surface is relatively smooth, with a clear separation gap between the coating 51 and the metal interface, indicating poor bonding strength. However, in the area roughened using this method, the edge of the coating 51 is tightly bonded to the roughened metal surface, with no obvious peeling gaps, demonstrating good interfacial bonding.

[0091] After completing the cavity surface 12 coating process of the bar 7, the coated bar 7 can be removed from the coating fixture 400 and sent to the subsequent chip cleaving and testing process to obtain a finished laser chip that meets the design requirements. The bar 7 can be cleaved according to the preset single-tube chip size to obtain an independent laser chip unit; or the coated bar 7 can be directly fabricated into a bar chip for application in stacked or linear array laser products.

[0092] The coating method of this embodiment performs induced layer-assisted annealing roughening treatment on the coating area 11 of the laser chip. Without affecting the electrical performance and surface morphology of other areas of the chip, a roughened metal surface with high bonding strength is obtained only in the edge coating area. This can significantly improve the adhesion between the coating 51 and the metal electrode, effectively avoid the problem of the coating 51 being peeled off by the solder during the packaging process, and significantly improve the packaging yield and long-term working reliability of the laser chip.

[0093] The laser chip coating method provided by this invention involves a series of processes, including regional metal exposure in the coating region 11 around the chip edge, forming an induction layer on a first metal layer, low-temperature deposition of a second metal layer 3, and annealing-induced roughening, to form a roughened metal surface with precipitation structures in the coating region 11. Compared with the prior art, the mechanical interlocking effect formed between the roughened metal surface and the optical film 5 significantly enhances the interfacial bonding strength between the coating 51 and the metal electrode.

[0094] During the encapsulation process, even if the molten solder has high fluidity and wettability, it is difficult to push or peel the coating 51 off the roughened metal surface. Thus, since the coating 51 is firmly attached to the roughened metal surface, the molten solder is blocked when it comes into contact with the edge of the coating 51 and cannot flow further toward the cavity surface 12. This avoids the problem of solder overflowing into the core optical film 5 area of ​​the cavity surface 12 and causing catastrophic damage to the cavity surface 12.

[0095] This invention only roughens the coating area 11, while the surface morphology and performance of the metal in other areas of the chip remain unaffected, ensuring the consistency of the overall electrical performance and reliability of the chip.

[0096] Meanwhile, the laser chip coating method provided by this invention can directly utilize existing mass production processes without the need for additional complex equipment. Patterning, oxygen plasma treatment, electron beam evaporation, and annealing are all mature processes in the semiconductor manufacturing field, possessing good feasibility and repeatability.

[0097] The present invention also provides a laser chip, which can be fabricated using the coating method described in the above embodiments. The laser chip includes an epitaxial wafer 1, a first metal layer 2, a second metal layer 3, and a coating layer 51.

[0098] A first metal layer 2 is disposed on the P-plane and / or N-plane of the epitaxial wafer 1. The first metal layer 2 includes at least an adhesion layer and a barrier layer sequentially stacked along the epitaxial direction. The adhesion layer is made of Ti or Cr, and the barrier layer is made of Pt or Pd.

[0099] The second metal layer 3 covers the first metal layer 2. Specifically, on the P-side and / or N-side, within the coating region 11 near the cavity surface 12, the second metal layer 3 forms a roughened metal surface with a precipitation structure; outside the coating region 11, the second metal layer 3 covers the first metal layer 2 and remains flat.

[0100] The roughened metal surface is formed by inducing the formation of the barrier functional layer and then annealing it. Its roughness is greater than that of other areas of the second metal layer 3.

[0101] A coating 51 is applied around the roughened metal surface within the coating region 11. The coating 51 is formed by coating the optical film 5 onto the roughened metal surface during the deposition of the optical film 5 on the cavity surface 12 of the laser chip. The coating 51 and the roughened metal surface are mechanically interlocked through the precipitation structure, thereby ensuring that the coating 51 is firmly attached to the roughened metal surface.

[0102] Furthermore, a third metal layer 4 is provided on the second metal layer 3 outside the coating area 11 on the P-side. The third metal layer 4 is an Au layer, which is used to provide sufficient thickness for subsequent packaging soldering, ensuring the reliability of the soldering and ohmic contact performance.

[0103] This invention also provides a packaging structure for a laser chip, comprising a heat sink, solder, and the aforementioned laser chip. The laser chip is fixed to the heat sink by solder. Because the coating region 11 of the laser chip has a roughened metal surface, the coating 51 is firmly attached thereto. During the packaging process, the spreading boundary of the molten solder on the laser chip surface stops at the coating region 11, preventing it from overflowing beyond the coating 51 towards the cavity surface 12. This effectively avoids damage to the optical film 5 and catastrophic damage to the cavity surface 12 caused by solder overflow, improving the reliability and yield of the packaging structure.

[0104] In summary, this invention pre-embeds an induction layer (PtO / PtO2 oxide layer or Pd irradiation damage layer) on the first metal layer 2 around the coating region, and covers it with a second metal layer 3 (Au layer). Then, high-temperature annealing causes the induction layer to form a roughened metal surface with a precipitation structure in situ within the coating region 11. This roughened metal surface interlocks with the subsequently deposited optical film 5 around the coating region 11, forming a physical interlocking structure. Compared to the film adhesion maintained only by intermolecular forces on a flat metal surface, the interfacial bonding strength between the coating 51 and the second metal layer 3 is significantly improved. During the packaging process, even if the molten solder impacts and entrains the edge of the coating 51, the coating 51 can still adhere firmly to the roughened metal surface and is not easily lifted or peeled off by the solder. This prevents the solder from overflowing into the core optical film area of ​​the front and rear cavity surfaces 12 of the chip, prevents the occurrence of catastrophic cavity surface damage (COD), and significantly improves the packaging yield and long-term operational reliability of the laser chip.

[0105] This invention uses patterning to roughen only the area around the coating 11, leaving the surface of the second metal layer 3 in other areas of the laser chip smooth, without affecting subsequent bonding and packaging processes. At the same time, the coating method can directly utilize existing mass production processes without the need for additional complex equipment, demonstrating good feasibility and compatibility.

[0106] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0107] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A coating method for a laser chip, characterized in that, The method includes the following steps: An epitaxial wafer is provided, wherein a first metal layer is grown on the P-side and / or N-side of the epitaxial wafer; The epitaxial wafer is patterned to expose a pre-defined area around the coating layer. An induction layer is formed on the first metal layer exposed in the area surrounding the coating; A second metal layer is grown on the inducing layer within the coating region and on the first metal layer outside the coating region; The epitaxial wafer is cleaved into bar strips, and the coating area is the region near the cavity edge on the P-side and / or N-side of the bar strip; The bar is annealed to form a roughened metal surface with a precipitation structure on the second metal layer in the area surrounding the coating. An optical film is deposited on the cavity surface of the bar, and then the optical film is deposited around the roughened metal surface to form a wrap-around coating.

2. The coating method for a laser chip according to claim 1, characterized in that, The first metal layer includes at least an adhesion layer and a barrier layer stacked sequentially along the epitaxial direction. The material of the adhesion layer is Ti or Cr, and the material of the barrier layer is Pt or Pd.

3. The coating method for a laser chip according to claim 2, characterized in that, The barrier functional layer is a Pt layer; forming an induction layer on the first metal layer exposed in the coating area includes: treating the first metal layer exposed in the coating area with oxygen plasma for 10s to 30s, and forming an oxide layer with a thickness of 1nm to 5nm on the surface of the barrier functional layer, the oxide layer including a PtO layer and / or a PtO2 layer.

4. The coating method for a laser chip according to claim 3, characterized in that, Annealing the bar strip includes: The substrate temperature of the bar is controlled at a preset temperature, which is not lower than the decomposition temperature of the oxide layer; Within the coating area, the oxide layer decomposes upon heating and releases oxygen. The gas pressure generated by the oxygen and the thermal stress generated by annealing together drive the second metal layer within the coating area to locally bulge and cause the grains of the second metal layer to grow, thereby forming a roughened metal surface with a precipitation structure within the coating area. Outside the area surrounding the coating, the second metal layer remains flat and is bonded to the first metal layer.

5. The coating method for a laser chip according to claim 2, characterized in that, The blocking functional layer is a Pd layer; Forming an induction layer on the first metal layer exposed in the area surrounding the coating includes: irradiating the first metal layer exposed in the area surrounding the coating with argon plasma, wherein the ion energy of the argon plasma is not greater than 200 eV and the treatment time is 10 s to 30 s, and forming an irradiation damage layer with lattice defects on the surface of the barrier functional layer, wherein the thickness of the irradiation damage layer is not greater than 5 nm.

6. The coating method for a laser chip according to claim 5, characterized in that, Annealing the bar strip includes: The substrate temperature of the epitaxial wafer is controlled to a preset temperature; Within the coating region, lattice defects in the irradiation-damaged layer form nanovoids during annealing. The stress generated by the aggregation of the nanovoids and the thermal stress generated by annealing together drive the second metal layer within the coating region to locally bulge, thereby forming a roughened metal surface with precipitation structure within the coating region. Outside the area surrounding the coating, the second metal layer remains flat and is bonded to the first metal layer.

7. The coating method for a laser chip according to claim 4 or 6, characterized in that, The preset temperature is set to 350°C~400°C; And / or, the preset temperature is positively correlated with the wavelength of the laser chip; And / or, the annealing process time is set to 30 min to 40 min; And / or, the processing time of the annealing process is set according to the wavelength gradient of the laser chip. When the wavelength of the laser chip is greater than or equal to 700nm and less than 800nm, the processing time of the annealing process is 30min; when the wavelength of the laser chip is greater than or equal to 800nm ​​and less than 900nm, the processing time of the annealing process is 35min; when the wavelength of the laser chip is greater than or equal to 900nm, the processing time of the annealing process is 40min.

8. The coating method for a laser chip according to claim 2, characterized in that, Growing a first metal layer on the P-side and / or N-side of the epitaxial wafer includes: growing a first metal layer on the P-side of the epitaxial wafer, wherein the thickness of the adhesion layer in the first metal layer on the P-side is 50±10nm, and the thickness of the barrier functional layer is 100±20nm. And / or, a first metal layer is grown on the N-side of the epitaxial wafer, the first metal layer on the N-side further comprising an ohmic contact layer near the substrate side of the epitaxial wafer, the ohmic contact layer comprising an AuGe layer and a Ni layer sequentially stacked along the epitaxial direction, wherein the thickness of the AuGe layer is 200±20nm and the thickness of the Ni layer is 80±10nm; the thickness of the adhesion layer in the first metal layer on the N-side is 20±5nm and the thickness of the barrier layer is 50±10nm.

9. The coating method for a laser chip according to claim 1, characterized in that, Growing a second metal layer on the induction layer within the coating region and on the first metal layer outside the coating region includes: controlling the substrate temperature of the epitaxial wafer to be below 150°C; depositing the second metal layer by electron beam evaporation; the second metal layer is an Au layer with a thickness of 500±20 nm; And / or, after growing the second metal layer, the coating method further includes: electroplating a third metal layer on the second metal layer outside the coating area on the P-side, the third metal layer being an Au layer with a thickness of 3000±200nm. And / or, patterning the epitaxial wafer to expose a preset coating area around the epitaxial wafer includes: coating a photoresist on the surface of the first metal layer; patterning and developing the coating area to remove the photoresist from the coating area, thereby exposing the first metal layer in the coating area and covering the first metal layer in other areas with the photoresist. After forming an induction layer on the first metal layer exposed in the area surrounding the coating, the coating method further includes removing the photoresist.

10. The coating method for a laser chip according to claim 1, characterized in that, Before annealing the bar strip, the cavity surface of the bar strip is cleaned and passivated: the bar strip and the accompanying strip are arranged in a coating fixture, the width of the bar strip along the cavity length direction is greater than the width of the accompanying strip along the cavity length direction, so as to expose the coating area around the bar strip; the coating fixture is placed in the growth chamber, and the gas pressure in the growth chamber is maintained not higher than 1×10 - 8 Torr; The bark strips are heated to a temperature not lower than 200°C for 10-20 minutes; A mixture of Ar and H2 gas is introduced into the growth chamber to achieve a pressure of 1×10⁻⁶. -5 Torr, turn on the radio frequency plasma source, perform cavity surface treatment on the bar strip, and the treatment time is not less than 50 minutes; turn off the Ar gas, introduce N2 gas, control the ratio of N2 to H2 to be 6:1~10:1, and deposit a passivation film with a thickness of at least 10 nm on the cavity surface of the bar strip by electron beam evaporation. And / or, the cavity surface includes a front cavity surface and a rear cavity surface of the bar; depositing an optical film on the cavity surface of the bar includes: depositing an antireflective film on the front cavity surface of the bar and depositing a high reflective film on the rear cavity surface of the bar; the optical film includes at least one high refractive index material selected from Si, HfO2, and Ta2O5, and at least one low refractive index material selected from SiO2, Al2O3, and MgF2.

11. A laser chip, characterized in that, The laser chip includes: Epitaxial wafer; A first metal layer is disposed on the P-plane and / or N-plane of the epitaxial wafer. The first metal layer includes an adhesion layer and a barrier layer that are sequentially stacked along the epitaxial direction. The second metal layer includes a roughened metal surface with a precipitation structure formed in the coating region near the cavity surface on the P-side and / or N-side of the laser chip. The roughness of the roughened metal surface is greater than the roughness of other areas of the second metal layer. The length of the coating region along the cavity length direction is 15μm to 25μm. A coating is applied around the roughened metal surface within the area covered by the coating.

12. A laser chip packaging structure, characterized in that, It includes a heat sink, solder, and a laser chip as described in claim 11; the laser chip is fixed to the heat sink by the solder; the coating is attached to the roughened metal surface to prevent the solder from overflowing into the cavity surface.

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