Method for manufacturing a semiconductor tunnel junction, semiconductor tunnel junction and laser

Abstract

The application discloses a semiconductor tunnel junction preparation method, a semiconductor tunnel junction and a laser. The preparation method comprises the following steps: providing an epitaxial structure, wherein the epitaxial structure comprises a semiconductor layer with a first conductive type; forming a dielectric layer on the surface of the epitaxial structure; patterning the dielectric layer to form at least one diffusion window on the dielectric layer; preparing a diffusion source layer, wherein the diffusion source layer comprises a doped element with a second conductive type; forming a photo-thermal conversion layer on the diffusion source layer; irradiating the photo-thermal conversion layer with a laser beam to form a first doped region with the second conductive type, and the first doped region and the semiconductor layer form a tunnel junction; and removing the photo-thermal conversion layer, the residual diffusion source layer and the dielectric layer. The semiconductor tunnel junction preparation method, the semiconductor tunnel junction and the laser can realize the preparation of an ultra-shallow planar tunnel junction, and can ensure high doping concentration and ultra-shallow junction depth while maintaining surface planarization.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor microelectronics and optoelectronic device manufacturing technology, specifically relating to a method for preparing a semiconductor tunnel junction, the semiconductor tunnel junction, and a laser. Background Technology

[0002] Current limiting technology is a key process determining the performance of vertical-cavity surface-emitting lasers (VCSELs). In GaAs-based VCSELs, the mainstream approach is to wet-oxidize a high-alumina composition layer to form insulating apertures, but this oxidation process has reliability issues and is not conducive to device miniaturization. In InP-based long-wavelength VCSELs, where a stable oxidation process is lacking, buried tunnel junction (BTJ) technology has become the main current limiting solution.

[0003] Conventional BTJ (Transient Tunnel Junction) processes require selective etching and epitaxial regrowth to form lateral tunnel junctions. This process is complex and demands extremely high precision in layer thickness control, sidewall etching quality, and regrowth interface control. Even minor process deviations can introduce leakage paths, degrading device electrothermal performance and even causing tunnel junction failure. While ion implantation tunnel junctions (ITJ) avoid epitaxial regrowth, forming ultra-shallow junctions (<100nm) on III-V compound semiconductors requires a precise balance between implantation damage repair, impurity activation, and diffusion suppression, resulting in a narrow process window. Furthermore, in traditional thermal diffusion processes, III-V material dopants (such as Zn) have high diffusion coefficients and strong concentration dependence. Prolonged high-temperature annealing makes it difficult to precisely control the junction depth within 100nm and easily leads to diffusion tailing, causing junction characteristic degradation.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a semiconductor tunnel junction, the semiconductor tunnel junction itself, and a laser, which enables the fabrication of ultra-shallow planar tunnel junctions without complex etching and regeneration processes, while maintaining a high doping concentration (>1E19cm). -3 It maintains surface planarization while achieving ultra-shallow junction depth (<100nm), effectively suppressing material damage and leakage paths. The process is simple, low-cost, and widely compatible.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] A method for fabricating a semiconductor tunnel junction, comprising:

[0008] An epitaxial structure is provided, the epitaxial structure comprising a semiconductor layer having a first conductivity type;

[0009] A dielectric layer is formed on the surface of the epitaxial structure;

[0010] The dielectric layer is patterned to form at least one diffusion window on the dielectric layer, the diffusion window exposing the target doped region on the surface of the epitaxial structure;

[0011] A diffusion source layer is prepared on one side of the epitaxial structure where a dielectric layer is formed. The diffusion source layer includes a dopant element having a second conductivity type, which is opposite to the first conductivity type.

[0012] A photothermal conversion layer is formed on the diffusion source layer;

[0013] The photothermal conversion layer is irradiated with a laser beam, which thermally activates the doping elements in the diffusion source layer. The doping elements diffuse into the epitaxial structure through the opening, forming a first doped region with a second conductivity type. The first doped region and the semiconductor layer form a tunnel junction.

[0014] Remove the photothermal conversion layer, the remaining diffusion source layer, and the dielectric layer.

[0015] In one or more embodiments of the present invention, the diffusion source layer is prepared by atomic layer deposition or magnetron sputtering, and the thickness control precision of the diffusion source layer is less than 1 nm.

[0016] In one or more embodiments of the present invention, the photothermal conversion layer is configured to have absorption characteristics for laser light of a specific wavelength;

[0017] Irradiating the photothermal conversion layer with a laser beam includes:

[0018] The photothermal conversion layer is irradiated with a laser beam that matches the absorption characteristics of the photothermal conversion layer. The photothermal conversion layer converts the laser energy into heat energy in nanosecond to microsecond time through the photothermal effect and conducts it to the diffusion source layer to activate the doping elements in the diffusion source layer.

[0019] In one or more embodiments of the present invention, the photothermal conversion layer is irradiated with a laser beam using a single pulse, multiple pulse irradiation method, or a spot scanning method.

[0020] The pulse width is 1ns-1000ns, and the energy density is 0.05J / cm². 2 -0.5J / cm 2 .

[0021] In one or more embodiments of the present invention, the pulse width is 10ns-100ns and the energy density is 0.2J / cm². 2 -0.3J / cm 2 .

[0022] In one or more embodiments of the present invention, the material of the photothermal conversion layer is selected from at least one of amorphous silicon, germanium, amorphous carbon, diamond-like carbon, graphite carbon, metal oxides or metal nitrides.

[0023] In one or more embodiments of the present invention, the doping concentration of the first doped region is higher than 1E19cm. -3 ; and / or,

[0024] The junction depth of the first doped region is 10nm-100nm.

[0025] In one or more embodiments of the present invention, the epitaxial structure is a semiconductor layer having a first conductivity type, wherein the semiconductor layer is a heavily doped epitaxial layer with a doping concentration greater than 1E19cm. -3 The first doped region is formed within the heavily doped epitaxial layer.

[0026] In one or more embodiments of the present invention, the epitaxial structure includes a semiconductor layer having a first conductivity type and a top epitaxial layer located on the semiconductor layer, wherein the top epitaxial layer is an unintentionally doped epitaxial layer, an intrinsic epitaxial layer, or a high-resistivity epitaxial layer, and the first doped region is formed within the unintentionally doped epitaxial layer, the intrinsic epitaxial layer, or the high-resistivity epitaxial layer.

[0027] In one or more embodiments of the present invention, the semiconductor layer is a heavily doped epitaxial layer with a doping concentration greater than 1E19cm. -3 ; and / or ;

[0028] The carrier concentration of the unintentionally doped epitaxial layer or the intrinsic epitaxial layer is less than 1E16cm. -3 The resistivity of the high-resistivity epitaxial layer is higher than 1E3Ω·cm.

[0029] In one or more embodiments of the present invention, the material of the epitaxial structure is selected from group III-V binary compound semiconductors containing As, P, and Sb elements, or ternary or higher-order multi-element alloys containing In, Al, Ga, and N elements with lattice matching or lattice mismatch less than 1.5% with the group III-V binary compound semiconductor; and / or,

[0030] The thickness of the dielectric layer is 10nm-500nm; and / or,

[0031] The material of the dielectric layer is selected from alumina, silicon oxide, or silicon nitride; and / or,

[0032] The size of the diffusion window is 0.5 μm-100 μm; and / or,

[0033] The diffusion source layer is a solid compound diffusion source film; and / or,

[0034] The thickness of the diffusion source layer is 5nm-300nm; and / or,

[0035] When the first conductivity type is N-type, the diffusion source layer contains a P-type dopant element; when the first conductivity type is P-type, the diffusion source layer contains an N-type dopant element. The P-type dopant element is selected from at least one of Zn, Mg, or Cd, and the N-type dopant element is selected from at least one of S, Se, or Te.

[0036] In one or more embodiments of the present invention, the preparation method further includes:

[0037] The steps of forming an epitaxial structure, forming a dielectric layer, forming a diffusion source layer, forming a photothermal conversion layer, and laser irradiation are repeated on the surface of the epitaxial structure. At least one additional tunnel junction is formed on the already formed tunnel junction to form a vertically stacked multi-level tunnel junction structure.

[0038] In one or more embodiments of the present invention, the preparation method further includes:

[0039] The steps of forming a dielectric layer, opening windows, forming a diffusion source layer, forming a photothermal conversion layer, and laser irradiation are repeatedly performed on the surface of the epitaxial structure to form a second doped region with a third conductivity type at a horizontal position adjacent to the first doped region. The third conductivity type is opposite to the second conductivity type, thus forming a lateral tunnel junction structure.

[0040] A semiconductor tunnel junction, comprising:

[0041] An epitaxial structure, the epitaxial structure comprising a semiconductor layer having a first conductivity type;

[0042] A first doped region having a second conductivity type is located in the epitaxial structure, the second conductivity type being opposite to the first conductivity type, and the first doped region and the semiconductor layer form a tunnel junction;

[0043] The junction depth of the first doped region is 10nm-100nm, and the doping concentration is higher than 1E19cm. -3 .

[0044] In one or more embodiments of the present invention, the epitaxial structure is a semiconductor layer having a first conductivity type, wherein the semiconductor layer is a heavily doped epitaxial layer with a doping concentration greater than 1E19cm. -3 The first doped region is formed within the heavily doped epitaxial layer.

[0045] In one or more embodiments of the present invention, the epitaxial structure includes a semiconductor layer having a first conductivity type and a top epitaxial layer located on the semiconductor layer, wherein the top epitaxial layer is an unintentionally doped epitaxial layer, an intrinsic epitaxial layer, or a high-resistivity epitaxial layer, and the first doped region is formed within the unintentionally doped epitaxial layer, the intrinsic epitaxial layer, or the high-resistivity epitaxial layer.

[0046] In one or more embodiments of the present invention, the semiconductor layer is a heavily doped epitaxial layer with a doping concentration greater than 1E19cm. -3 ; and / or ;

[0047] The carrier concentration of the unintentionally doped epitaxial layer or the intrinsic epitaxial layer is less than 1E16cm. -3 The resistivity of the high-resistivity epitaxial layer is higher than 1E3Ω·cm.

[0048] In one or more embodiments of the present invention, the material of the epitaxial structure is selected from group III-V binary compound semiconductors containing As, P, and Sb elements, or ternary or higher-order multi-element alloys containing In, Al, Ga, and N elements with lattice matching or lattice mismatch less than 1.5% with the group III-V binary compound semiconductor; and / or,

[0049] The lateral dimension of the first doped region is 0.5 μm-100 μm; and / or,

[0050] When the first conductivity type is N-type, the diffusion source layer contains a P-type dopant element; when the first conductivity type is P-type, the diffusion source layer contains an N-type dopant element. The P-type dopant element is selected from at least one of Zn, Mg, or Cd, and the N-type dopant element is selected from at least one of S, Se, or Te.

[0051] In one or more embodiments of the present invention, the semiconductor tunnel junction further includes:

[0052] At least one additional tunnel junction is located on the extensional structure, and the additional tunnel junction is stacked with the tunnel junction in the vertical direction to form a multi-level tunnel junction structure.

[0053] In one or more embodiments of the present invention, the semiconductor tunnel junction further includes:

[0054] The second doped region, which is located in the epitaxial structure and is horizontally adjacent to the first doped region, has a third conductivity type that is opposite to the second conductivity type. The second doped region and the first doped region form a lateral tunnel junction structure.

[0055] A laser comprising the aforementioned semiconductor tunnel junction.

[0056] Compared with existing technologies, the semiconductor tunnel junction and laser of the present invention employ a diffusion source layer deposition combined with a photothermal conversion layer and laser annealing process to achieve the fabrication of ultra-shallow (junction depth less than 100nm) planar tunnel junctions without complex etching and regeneration processes. Simultaneously, the thermal budget of the entire thermal diffusion process is limited to the minimum level necessary to achieve a shallow junction, effectively avoiding the concentration kinking and diffusion tailing problems caused by abnormal diffusion dependent on dopant concentration in traditional thermal diffusion processes.

[0057] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention, by precisely controlling the thickness of the diffusion source layer (combined with atomic-level deposition process), the energy conversion efficiency of the photothermal conversion layer, and the energy density and pulse width of pulsed laser annealing, can stably control the diffusion-doped junction depth within 100 nm.

[0058] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention employ nanosecond-level pulsed laser annealing. Its rapid melting-quenching process allows the solid solubility of the dopant element in the compound semiconductor epitaxial layer to far exceed the equilibrium solid solubility, with a peak doping concentration reaching 1E¹⁹ cm⁻¹. -3 The above fully meets the requirements of high doping concentration for tunnel junctions.

[0059] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention selectively dope only the diffusion window region, without etching micro-mesa. After removing the dielectric layer, the surface of the epitaxial structure remains highly flat, without steps or depressions, avoiding the surface morphology fluctuations introduced by etching micro-mesa in the traditional BTJ process. The flattened surface is seamlessly compatible with subsequent planar processes such as epitaxial regrowth and wafer-level bonding.

[0060] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention avoid the problems of sidewall roughness, interface contamination, and lattice defects caused by selective etching and epitaxial regrowth in the traditional BTJ process. It also avoids lattice damage caused by high-energy ion bombardment in the ion implantation process. Except for point defects introduced by doping, it does not produce other material damage and process failure modes, effectively reducing the risk of device leakage and improving the electrical performance and reliability of the tunnel junction.

[0061] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention do not require expensive ion implantation equipment, complex selective etching mesa fabrication, and epitaxial regeneration processes. The process flow is simple, has good compatibility with traditional semiconductor planar processes, and can be widely applied to various III-V compound semiconductor surface-emitting lasers and edge-emitting lasers containing As, P, and Sb elements. At the same time, it can also be extended to other microelectronic and optoelectronic device fields that require steep abrupt doping, and has good versatility and promotional value. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a process flow diagram of the method for preparing the semiconductor tunnel junction in this invention;

[0064] Figures 2a-2f This is a process step diagram of a method for preparing a semiconductor tunnel junction according to an embodiment of the present invention;

[0065] Figure 3 This is a structural diagram of a semiconductor tunnel junction according to another embodiment of the present invention;

[0066] Figure 4 This is a structural diagram of a semiconductor tunnel junction in another embodiment of the present invention;

[0067] Figures 5a-5f This is a process step diagram of a method for preparing a semiconductor tunnel junction in another embodiment of the present invention. Detailed Implementation

[0068] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0069] Current limiting technology is one of the key processes determining the performance of vertical-cavity surface-emitting lasers (VCSELs). In GaAs-based VCSELs, the mainstream current limiting scheme is wet oxidation of a high-alumina composition layer to form insulating oxide apertures. However, this oxidation process has reliability issues and is not conducive to further miniaturization of the device. In InP-based long-wavelength (>1100nm) VCSELs, where a stable oxidation process is lacking, buried tunnel junction (BTJ) technology has become the main current limiting scheme. With the rapid development of artificial intelligence computing centers, the demand for small-sized surface-emitting laser arrays in short-distance optical communication is becoming increasingly urgent, placing higher demands on the precision, reliability, and process compatibility of tunnel junction fabrication technology.

[0070] Conventional BTJ (Transient Bit-Jet) technology forms lateral tunnel junctions through selective etching and epitaxial regrowth. The fabrication process involves complex steps including primary epitaxy, etching to form micromesa, and secondary epitaxial regrowth. The regrowth is used to coat and passivate the pre-etched tunnel junction mesa. This process places extremely stringent requirements on the control of epitaxial growth layer thickness and doping, the control of sidewall morphology during micromesa etching, and the quality of the epitaxial regrowth interface. Even minute deviations in tunnel junction growth parameters, side roughness during micromesa etching, and contamination can introduce leakage paths, reduce current limiting effectiveness, degrade device thermal / electrical performance, and even lead to electrical malfunction of the tunnel junction.

[0071] Ion-implanted tunnel junctions (ITJs) create current channels by disrupting the conductivity of the surrounding material through ion implantation. However, forming ultra-shallow junctions with depths below 100 nm requires low-energy ion implantation with precise dose control. The fabrication of ion-implanted shallow junctions on III-V compound semiconductors such as GaAs and InP is more complex than silicon-based processes. Optimal processes require a precise balance between repairing implantation damage, effectively activating impurity atoms, and accurately suppressing impurity diffusion, resulting in an extremely narrow process window. Furthermore, in traditional thermal diffusion processes, III-V material dopants (such as Zn) have high diffusion coefficients and strong concentration dependence. Prolonged high-temperature annealing makes it difficult to precisely control the junction depth within 100 nm and easily causes impurity diffusion tailing, leading to junction characteristic degradation.

[0072] To address the limitations of existing BTJ, ITJ, and thermal diffusion processes, such as process complexity, reliance on expensive specialized equipment, and difficulties in process control, this invention proposes a method for fabricating a semiconductor tunnel junction, a semiconductor tunnel junction itself, and a laser. In the semiconductor tunnel junction fabrication method, a doping region is defined by opening windows in the dielectric layer. A diffusion source layer with atomically controllable thickness is used to provide doping elements. Rapid low-temperature doping is achieved through laser annealing assisted by a photothermal conversion layer, resulting in a doping concentration higher than 1E19cm⁻¹. -3 Furthermore, while achieving a high-quality tunnel junction with a depth of less than 100 nm, this invention avoids micro-mesa etching, maintains surface planarity, and effectively suppresses material damage and process failures other than doping point defects. The planarized surface is more conducive to subsequent epitaxial regrowth and wafer-level bonding processes, providing a new technical path for the fabrication of high-performance VCSELs and other optoelectronic devices. The technical solution of this invention can be widely applied to various III-V compound semiconductor surface-emitting lasers and edge-emitting lasers containing As, P, and Sb elements, and can also be extended to other microelectronic and optoelectronic device fields requiring steep abrupt doping.

[0073] like Figure 1 As shown, the method for preparing the semiconductor tunnel junction in this invention specifically includes the following steps:

[0074] S1 provides an epitaxial structure, the epitaxial structure including a semiconductor layer having a first conductivity type.

[0075] S2 forms a dielectric layer on the surface of the epitaxial structure.

[0076] S3, pattern the dielectric layer to form at least one diffusion window on the dielectric layer, the diffusion window exposing the target doped region on the surface of the epitaxial structure.

[0077] S4, a diffusion source layer is prepared on the side of the epitaxial structure where a dielectric layer is formed. The diffusion source layer includes a dopant element having a second conductivity type, which is opposite to the first conductivity type.

[0078] S5 forms a photothermal conversion layer on the diffusion source layer.

[0079] S6 uses a laser beam to irradiate the photothermal conversion layer, which thermally activates the doped elements in the diffusion source layer. These elements diffuse into the epitaxial structure through the opening, forming a first doped region with a second conductivity type. The first doped region and the semiconductor layer form a tunnel junction.

[0080] S7, remove the photothermal conversion layer, residual diffusion source layer and dielectric layer.

[0081] In step S4, a diffusion source layer is prepared using atomic layer deposition or magnetron sputtering. The thickness of the diffusion source layer is 5nm-300nm, and the thickness control precision of the diffusion source layer is less than 1nm.

[0082] In step S5, the photothermal conversion layer is configured to absorb laser light of a specific wavelength, enabling it to convert laser energy into heat energy within nanoseconds to microseconds via a photothermal effect and conduct it to the diffusion source layer to activate the doped elements in the diffusion source layer. The material of the photothermal conversion layer is selected from at least one of amorphous silicon, germanium, amorphous carbon, diamond-like carbon, graphite carbon, metal oxides, or metal nitrides.

[0083] In step S6, the laser beam is defined as a laser beam that matches the absorption characteristics of the photothermal conversion layer. The photothermal conversion layer is irradiated with the laser beam using a single-pulse or multi-pulse irradiation method; wherein the pulse width is 1ns-1000ns, preferably 10ns-100ns; and the energy density is 0.05J / cm³. 2 -0.5J / cm 2 The preferred value is 0.2 J / cm. 2 -0.3J / cm 2 The doping concentration of the first doped region is higher than 1E19cm. -3 The junction depth of the first doped region is 10nm-100nm.

[0084] This invention employs a diffusion source layer deposition combined with a photothermal conversion layer and laser annealing to achieve the fabrication of ultra-shallow (junction depth less than 100 nm) planar tunnel junctions without complex etching and regeneration processes. Simultaneously, the thermal budget of the entire thermal diffusion process is limited to the minimum level necessary to achieve a shallow junction, effectively avoiding the concentration kinking and diffusion tailing problems caused by abnormal diffusion dependent on dopant concentration in traditional thermal diffusion processes. By precisely controlling the thickness of the diffusion source layer (combined with atomic-level deposition), the energy conversion efficiency of the photothermal conversion layer, and the energy density and pulse width of the pulsed laser annealing, the diffusion-doped junction depth is stably controlled within 100 nm.

[0085] The method for preparing the semiconductor tunnel junction of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0086] In one embodiment of the present invention:

[0087] like Figure 2a As shown, a substrate is provided on which a monolayer epitaxial structure 20 is formed using epitaxial growth techniques such as molecular beam epitaxy (MBE) or metal-organic vapor deposition (MOCVD).

[0088] The substrate can be a single crystal substrate 10, such as a III-V compound semiconductor substrate containing As, P, and Sb elements, such as GaAs, InP, GaSb, InAs, or a single crystal substrate 10 that already contains a pre-formed epitaxial layer 11.

[0089] The monolayer epitaxial structure 20 itself has a doping concentration greater than 1E19cm. -3 The epitaxial layer is heavily doped. The material of the epitaxial layer is selected from group III-V binary compound semiconductor materials containing at least one element of As, P, and Sb, such as GaAs, InP, GaSb, and InAs. The material of the epitaxial layer can also be selected from ternary or multi-element alloys with a lattice match or lattice mismatch of less than 1.5% with the binary compound semiconductor material, including but not limited to alloys containing one or more of In, Al, Ga, and N elements such as AlGaAs, InGaAs, InAlAs, InAsSb, InGaAsP, InAlGaAs, InAlAsP, InGaAsN, AlInAsSb, AlGaAsSb, and InAlGaAsP. The thickness of the epitaxial layer is controlled to be between 10 nm and 100 nm.

[0090] like Figure 2b As shown, a dielectric layer 30 is deposited on the surface of the single-layer epitaxial structure 20 as a diffusion mask. The dielectric layer 30 is patterned by photolithography and etching processes to form at least one diffusion window 31 on the dielectric layer 30.

[0091] The thickness of the dielectric layer 30 can range from 10 nm to 500 nm, and its material can be selected from Al2O3, silicon oxide (SiO2), and silicon nitride (SiN). x Materials with the ability to mask the diffusion of impurities, such as dielectric layer 20, can be used. The deposition method for dielectric layer 20 can be a conventional chemical vapor deposition or physical vapor deposition method in the art.

[0092] The diffusion window 31 formed on the dielectric layer 30 by photolithography and etching processes exposes the surface of the underlying epitaxial layer. The size of the diffusion window 31 region is controlled to range from 0.5 μm to 100 μm. In the unopened region, the dielectric layer 30 is retained, forming a diffusion mask to prevent impurity atoms from diffusing into the epitaxial layer in the unopened region during subsequent processes.

[0093] like Figure 2c As shown, after the diffusion mask patterning is completed, a diffusion source layer 40 containing doped elements is deposited on the side of the monolayer epitaxial structure 20 where the dielectric layer 30 is formed, using methods such as atomic layer deposition (ALD) or magnetron sputtering. The diffusion source layer 40 is a solid compound diffusion source thin film.

[0094] The diffusion source film is uniformly coated on the surface of the dielectric layer 30 and the surface of the epitaxial layer exposed by the diffusion window 31. The thickness of the diffusion source film is controlled from 5 nm to 300 nm, with a thickness control accuracy better than 1 nm.

[0095] The doping type of the diffusion source film is opposite to that of the heavily doped epitaxial layer in the monolayer epitaxial structure. Specifically, if the heavily doped epitaxial layer is N-type, a P-type dopant compound is selected as the diffusion source film; if the heavily doped epitaxial layer is P-type, an N-type dopant compound is selected as the diffusion source film. The P-type dopant compound contains at least one of Group II elements such as zinc (Zn), magnesium (Mg), and cadmium (Cd); the N-type dopant compound contains at least one of Group VI elements such as sulfur (S), selenium (Se), and tellurium (Te).

[0096] like Figure 2d As shown, after depositing the diffusion source layer 40, a photothermal conversion layer 50 is deposited on it. The material of this photothermal conversion layer 50 has a high absorption coefficient for the laser wavelength used in subsequent steps, and can efficiently convert the absorbed laser energy into heat energy, and heat the surface of the underlying diffusion source layer 40 and epitaxial layer through thermal conduction within nanosecond to microsecond time.

[0097] The photothermal conversion layer 50 is made of at least one material selected from amorphous silicon (α-Si), germanium (Ge), amorphous carbon / diamond-like carbon / graphite carbon, metal oxides (such as ITO, IGZO, etc.), and metal nitrides (such as TiN, GaN, AlN, etc.). The photothermal conversion layer 50 made of the above materials has strong absorption characteristics for lasers in the wavelength range of 200 nm to 2000 nm.

[0098] like Figure 2e As shown, the photothermal conversion layer 50 is irradiated with a laser beam that matches the absorption characteristics of the photothermal conversion layer 50.

[0099] For example, a pulsed laser is used to irradiate the surface of a substrate carrying the above-described stacked structure. The emission wavelength of the selected pulsed laser should match the absorption characteristics of the photothermal conversion layer 50. The pulse width of the laser is controlled between 1 ns and 1000 ns, preferably between 10 ns and 100 ns. The laser energy density is controlled to be 0.05 J / cm². 2 Up to 0.5 J / cm 2 The preferred value is 0.2 J / cm. 2 Up to 0.3 J / cm 2 This value is precisely optimized based on the absorption efficiency of the photothermal conversion layer 50 and the target junction depth. The irradiation method can be single-pulse irradiation, multi-pulse irradiation, or a spot scanning method to achieve large-area uniform processing.

[0100] During laser irradiation, the photothermal conversion layer 50 rapidly heats up, quickly heating the diffusion source layer 40 below it and the surface of the epitaxial layer in contact with the diffusion source layer 40 through thermal conduction. Within a timescale of nanoseconds (ns) to microseconds (μs), the surface of the epitaxial layer in the diffusion window 31 region is heated to a high temperature above 300°C. This high temperature excites and drives the dopant impurity atoms in the diffusion source layer 40 to rapidly diffuse into the surface of the heavily doped epitaxial layer below.

[0101] Due to the extremely rapid heating and cooling rates and the extremely short duration of the high temperature, the diffusion distance of impurity atoms is precisely controlled at the nanoscale, thereby forming an ultra-shallow junction with a depth of 10 nm to 100 nm on the epitaxial layer surface below the diffusion window 31. The doping concentration of this doped region 60 is higher than 1E19 cm⁻¹. -3 Its doping type is the opposite of the original doping type of the heavily doped epitaxial layer.

[0102] like Figure 2f As shown, after pulsed laser annealing-driven diffusion is completed, selective etching is performed sequentially to completely remove the photothermal conversion layer 50 and the remaining diffusion source layer 40. Subsequently, the dielectric layer 30, which serves as a diffusion mask, is removed, exposing the original flat surface of the epitaxial structure.

[0103] Thus, the preparation of the ultra-shallow planar tunnel structure was completed.

[0104] Furthermore, on the flat surface where the ultra-shallow planar tunnel junction has been formed, other functional structural layers can be fabricated. For example, other epitaxial layers with specific optical and / or electrical functions can be grown using epitaxial growth techniques such as MBE or MOCVD to form the core structure of optoelectronic devices and microelectronic devices such as vertical-cavity surface-emitting lasers and heterojunction bipolar transistors. Alternatively, wafer bonding technology can be used to bond another substrate containing an epitaxial layer with specific optical and / or electrical functions to the flat surface, thereby achieving more complex functional integration.

[0105] In another embodiment of the present invention, the flat surface with ultra-shallow planar tunnel knots formed by the above embodiments can be used to further extend the structure and construct a multi-level tunnel knot structure in the vertical direction.

[0106] like Figure 3 As shown, to construct a multi-stage tunnel structure in the vertical direction, one can... Figure 2f On the flat surface where the structure shown has already been formed, one or more fabrication cycles are performed. Each fabrication cycle includes, as follows: Figures 2a to 2f The steps shown include reforming the epitaxial layer, preparing the dielectric layer and diffusion window, depositing the diffusion source layer and photothermal conversion layer, performing pulsed laser annealing, and removing the photothermal conversion layer, diffusion source layer, and dielectric layer. By aligning the diffusion window positions in each cycle and alternately selecting the diffusion source doping type, multiple tunnel junctions can be stacked in the vertical direction to form a multi-level vertical tunnel junction.

[0107] In another embodiment of the present invention, the flat surface with ultra-shallow planar tunnel knot formed by the above embodiments can be used to further extend the structure and construct a transverse tunnel knot structure in the horizontal direction.

[0108] like Figure 4 As shown, to construct a horizontal tunnel structure, one can... Figure 2f On the flat surface of the same epitaxial layer of the structure shown, through multiple executions such as Figures 2b to 2f The steps shown involve preparing the dielectric layer and diffusion window, depositing the diffusion source layer and photothermal conversion layer, performing pulsed laser annealing, and removing the photothermal conversion layer, diffusion source layer, and dielectric layer. Using photolithography alignment, P-type heavily doped regions 60 and N-type heavily doped regions 70 with opposite doping types are selected and formed within adjacent diffusion windows on the surface. These adjacent, heavily doped regions with opposite doping types constitute a lateral tunnel junction.

[0109] Furthermore, on the flat surface where the ultra-shallow planar tunnel junction has been formed, other functional structural layers can be fabricated. For example, other epitaxial layers with specific optical and / or electrical functions can be grown using epitaxial growth techniques such as MBE or MOCVD to form the core structure of optoelectronic devices and microelectronic devices such as vertical-cavity surface-emitting lasers and heterojunction bipolar transistors. Alternatively, wafer bonding technology can be used to bond another substrate containing an epitaxial layer with specific optical and / or electrical functions to the flat surface, thereby achieving more complex functional integration.

[0110] In yet another embodiment of the present invention:

[0111] like Figure 5a As shown, a substrate is provided on which a bilayer epitaxial structure is formed using epitaxial growth techniques such as molecular beam epitaxy (MBE) or metal-organic vapor deposition (MOCVD).

[0112] The substrate can be a single crystal substrate 10, such as a III-V compound semiconductor substrate containing As, P, and Sb elements, such as GaAs, InP, GaSb, InAs, or a single crystal substrate 10 that already contains a pre-formed epitaxial layer 11.

[0113] The bilayer epitaxial structure comprises a top layer 21 and a top layer 22 situated above the sub-top layer 21. The sub-top layer 21 has a doping concentration greater than 1E19cm⁻¹. -3 The top layer 22 is a heavily doped epitaxial layer; the top layer 22 is an unintentionally doped epitaxial layer, an intrinsic epitaxial layer, or a high-resistivity epitaxial layer, and the carrier concentration of the unintentionally doped epitaxial layer and the intrinsic epitaxial layer is less than 1E16cm. -3 The resistivity of the high-resistivity epitaxial layer is higher than 1E3Ω·cm.

[0114] The epitaxial layer is selected from group III-V binary compound semiconductor materials containing at least one element of As, P, and Sb, such as GaAs, InP, GaSb, and InAs. The epitaxial layer material can also be selected from ternary or multi-element alloys with a lattice match or lattice mismatch of less than 1.5% with the binary compound semiconductor material, including but not limited to alloys containing one or more of In, Al, Ga, and N elements such as AlGaAs, InGaAs, InAlAs, InAsSb, InGaAsP, InAlGaAs, InAlAsP, InGaAsN, AlInAsSb, AlGaAsSb, and InAlGaAsP. The single-layer thickness of each epitaxial layer is controlled to be between 10 nm and 100 nm.

[0115] like Figure 5bAs shown, a dielectric layer 30 is deposited on the surface of the above-mentioned double-layer epitaxial structure as a diffusion mask. The dielectric layer 30 is patterned by photolithography and etching processes to form at least one diffusion window 31 on the dielectric layer 30.

[0116] The thickness of the dielectric layer 30 can range from 10 nm to 500 nm, and its material can be selected from Al2O3, silicon oxide (SiO2), and silicon nitride (SiN). x Materials with the ability to mask the diffusion of impurities, such as dielectric layer 20, can be used. The deposition method for dielectric layer 20 can be a conventional chemical vapor deposition or physical vapor deposition method in the art.

[0117] The diffusion window 31 formed on the dielectric layer 30 by photolithography and etching processes exposes the surface of the underlying epitaxial layer. The size of the diffusion window 31 region is controlled to range from 0.5 μm to 100 μm. In the unopened region, the dielectric layer 30 is retained, forming a diffusion mask to prevent impurity atoms from diffusing into the epitaxial layer in the unopened region during subsequent processes.

[0118] like Figure 5c As shown, after patterning the diffusion mask, a diffusion source layer 40 containing doped elements is deposited on one side of the bilayer epitaxial structure where the dielectric layer 30 is formed, using methods such as atomic layer deposition (ALD) or magnetron sputtering. The diffusion source layer 40 is a solid compound diffusion source film.

[0119] The diffusion source film is uniformly coated on the surface of the dielectric layer 30 and the surface of the epitaxial layer exposed by the diffusion window 31. The thickness of the diffusion source film is controlled from 5 nm to 300 nm, with a thickness control accuracy better than 1 nm.

[0120] The doping type of the diffusion source film is opposite to that of the heavily doped epitaxial layer in the bilayer epitaxial structure. Specifically, if the heavily doped epitaxial layer is N-type, a P-type dopant compound is selected as the diffusion source film; if the heavily doped epitaxial layer is P-type, an N-type dopant compound is selected as the diffusion source film. The P-type dopant compound contains at least one of Group II elements such as zinc (Zn), magnesium (Mg), and cadmium (Cd); the N-type dopant compound contains at least one of Group VI elements such as sulfur (S), selenium (Se), and tellurium (Te).

[0121] like Figure 5d As shown, after depositing the diffusion source layer 40, a photothermal conversion layer 50 is deposited on it. The material of this photothermal conversion layer 50 has a high absorption coefficient for the laser wavelength used in subsequent steps, and can efficiently convert the absorbed laser energy into heat energy, and heat the surface of the underlying diffusion source layer 40 and epitaxial layer through thermal conduction within nanosecond to microsecond time.

[0122] The photothermal conversion layer 50 is made of at least one material selected from amorphous silicon (α-Si), germanium (Ge), amorphous carbon / diamond-like carbon / graphite carbon, metal oxides (such as ITO, IGZO, etc.), and metal nitrides (such as TiN, GaN, AlN, etc.). The photothermal conversion layer 50 made of the above materials has strong absorption characteristics for lasers in the wavelength range of 200 nm to 2000 nm.

[0123] like Figure 5e As shown, the photothermal conversion layer 50 is irradiated with a laser beam that matches the absorption characteristics of the photothermal conversion layer 50.

[0124] For example, a pulsed laser is used to irradiate the surface of a substrate carrying the above-described stacked structure. The emission wavelength of the selected pulsed laser should match the absorption characteristics of the photothermal conversion layer 50. The pulse width of the laser is controlled between 1 ns and 1000 ns, preferably between 10 ns and 100 ns. The laser energy density is controlled to be 0.05 J / cm². 2 Up to 0.5 J / cm 2 The preferred value is 0.2 J / cm. 2 Up to 0.3 J / cm 2 This value is precisely optimized based on the absorption efficiency of the photothermal conversion layer 50 and the target junction depth. The irradiation method can be single-pulse irradiation, multi-pulse irradiation, or a spot scanning method to achieve large-area uniform processing.

[0125] During laser irradiation, the photothermal conversion layer 50 rapidly heats up, quickly heating the diffusion source layer 40 below it and the surface of the epitaxial layer in contact with the diffusion source layer 40 through thermal conduction. Within a timescale of nanoseconds (ns) to microseconds (μs), the surface of the epitaxial layer in the diffusion window 31 region is heated to a high temperature above 300°C. This high temperature excites and drives the dopant impurity atoms in the diffusion source layer 40 to rapidly diffuse into the surface of the heavily doped epitaxial layer below.

[0126] Due to the extremely rapid heating and cooling rates and the extremely short duration of the high temperature, the diffusion distance of impurity atoms is precisely controlled at the nanoscale, thereby forming an ultra-shallow junction with a depth of 10 nm to 100 nm on the epitaxial layer surface below the diffusion window 31. The doping concentration of this doped region 60 is higher than 1E19 cm⁻¹. -3 Its doping type is the opposite of the original doping type of the heavily doped epitaxial layer.

[0127] like Figure 5f As shown, after pulsed laser annealing-driven diffusion is completed, selective etching is performed sequentially to completely remove the photothermal conversion layer 50 and the remaining diffusion source layer 40. Subsequently, the dielectric layer 30, which serves as a diffusion mask, is removed, exposing the original flat surface of the epitaxial structure.

[0128] Thus, the preparation of the ultra-shallow planar tunnel structure was completed.

[0129] Furthermore, on the flat surface where the ultra-shallow planar tunnel junction has been formed, other functional structural layers can be fabricated. For example, other epitaxial layers with specific optical and / or electrical functions can be grown using epitaxial growth techniques such as MBE or MOCVD to form the core structure of optoelectronic devices and microelectronic devices such as vertical-cavity surface-emitting lasers and heterojunction bipolar transistors. Alternatively, wafer bonding technology can be used to bond another substrate containing an epitaxial layer with specific optical and / or electrical functions to the flat surface, thereby achieving more complex functional integration.

[0130] In other embodiments of the present invention, the flat surface with ultra-shallow planar tunnel knots formed by the above embodiments can also be used to further extend the structure and construct a multi-level tunnel knot structure in the vertical direction or a transverse tunnel knot structure in the horizontal direction.

[0131] For example, it is possible to Figure 5f On the flat surface where the structure shown has already been formed, one or more fabrication cycles are performed. Each fabrication cycle includes, as follows: Figures 5a to 5f The steps shown include reforming the epitaxial layer, preparing the dielectric layer and diffusion window, depositing the diffusion source layer and photothermal conversion layer, performing pulsed laser annealing, and removing the photothermal conversion layer, diffusion source layer, and dielectric layer. By aligning the diffusion window positions in each cycle and alternately selecting the diffusion source doping type, multiple tunnel junctions can be stacked in the vertical direction to form a multi-level vertical tunnel junction.

[0132] Another example is that... Figure 5f On the flat surface of the same epitaxial layer of the structure shown, through multiple executions such as Figures 5b to 5f The steps shown involve preparing the dielectric layer and diffusion window, depositing the diffusion source layer and photothermal conversion layer, performing pulsed laser annealing, and removing the photothermal conversion layer, diffusion source layer, and dielectric layer. Using photolithography alignment, P-type and N-type heavily doped regions with opposite doping types are selectively formed within adjacent diffusion windows on the surface. These adjacent, heavily doped regions with opposite doping types constitute a lateral tunnel junction.

[0133] Furthermore, on the flat surface where the ultra-shallow planar tunnel junction has been formed, other functional structural layers can be fabricated. For example, other epitaxial layers with specific optical and / or electrical functions can be grown using epitaxial growth techniques such as MBE or MOCVD to form the core structure of optoelectronic devices and microelectronic devices such as vertical-cavity surface-emitting lasers and heterojunction bipolar transistors. Alternatively, wafer bonding technology can be used to bond another substrate containing an epitaxial layer with specific optical and / or electrical functions to the flat surface, thereby achieving more complex functional integration.

[0134] The present invention also provides a semiconductor tunnel junction, which is prepared by the above-described method for preparing a semiconductor tunnel junction.

[0135] The semiconductor tunnel junction of the present invention comprises:

[0136] An epitaxial structure, comprising a semiconductor layer having a first conductivity type;

[0137] A first doped region with a second conductivity type located in the epitaxial structure, the second conductivity type being opposite to the first conductivity type, and the first doped region and the semiconductor layer forming a tunnel junction;

[0138] The junction depth of the first doped region is 10nm-100nm, and the doping concentration is higher than 1E19cm. -3 .

[0139] The epitaxial structure is a semiconductor layer having a first conductivity type, or the epitaxial structure includes a semiconductor layer having a first conductivity type and a top epitaxial layer located on the semiconductor layer, wherein the top epitaxial layer is an unintentionally doped epitaxial layer, an intrinsic epitaxial layer, or a high-resistivity epitaxial layer, and the first doped region is formed in the unintentionally doped epitaxial layer, the intrinsic epitaxial layer, or the high-resistivity epitaxial layer.

[0140] For example, the epitaxial structure is a heavily doped epitaxial layer. The material of the heavily doped epitaxial layer is selected from group III-V binary compound semiconductor materials containing at least one element of As, P, and Sb, such as GaAs, InP, GaSb, InAs, etc.; or selected from ternary or multi-element alloys with a lattice match or lattice mismatch of less than 1.5% with the binary compound semiconductor material, including but not limited to AlGaAs, InGaAs, InAlAs, InAsSb, InGaAsP, InAlGaAs, InAlAsP, InGaAsN, AlInAsSb, AlGaAsSb, InAlGaAsP, etc. The thickness of the heavily doped epitaxial layer is 10 nm to 100 nm, and its doping concentration is greater than 1E19 cm⁻¹. -3 The doping type is either P-type or N-type.

[0141] At least one ultra-shallow doped region is formed in the surface region of the heavily doped epitaxial layer. This ultra-shallow doped region is formed by the diffusion of dopant elements from the surface of the epitaxial layer inward. The junction depth of the ultra-shallow doped region is 10 nm to 100 nm, and its doping concentration is higher than 1E19 cm⁻¹. -3The conductivity type of the ultra-shallow doped region is opposite to that of the heavily doped epitaxial layer: if the heavily doped epitaxial layer is N-type, then the ultra-shallow doped region is P-type, and the doping element contained therein is at least one P-type doping element selected from zinc (Zn), magnesium (Mg), and cadmium (Cd); if the heavily doped epitaxial layer is P-type, then the ultra-shallow doped region is N-type, and the doping element contained therein is at least one N-type doping element selected from sulfur (S), selenium (Se), and tellurium (Te).

[0142] Between the heavily doped epitaxial layer and the ultra-shallow doped region on its surface, an ultra-shallow planar tunnel junction is formed at the interface due to high concentration of inversion doping. The depth of this tunnel junction is determined by the depth of the ultra-shallow doped region.

[0143] In another exemplary embodiment, the epitaxial structure includes a heavily doped epitaxial layer as the second-to-top layer. A top epitaxial layer is disposed above the heavily doped epitaxial layer. The material, thickness, doping concentration, and doping type of the heavily doped epitaxial layer are the same as in the example described above.

[0144] The top epitaxial layer is either an unintentionally doped epitaxial layer, an intrinsic epitaxial layer, or a high-resistivity epitaxial layer. The carrier concentration of the unintentionally doped epitaxial layer or the intrinsic epitaxial layer is lower than 1E16cm⁻¹. -3 The resistivity of the high-resistivity epitaxial layer is higher than 1E3 Ω·cm. The thickness of the top epitaxial layer is 10 nm to 100 nm, and its material is selected from III-V group binary compound semiconductor materials or ternary or higher alloy materials that are the same as or different from those of the heavily doped epitaxial layer. Preferably, the lattice matching or lattice mismatch between the material of the top epitaxial layer and the material of the heavily doped epitaxial layer is less than 1.5%.

[0145] At least one ultra-shallow doped region is formed in the surface region of the top epitaxial layer. This ultra-shallow doped region penetrates the top epitaxial layer and extends to a certain depth into the surface of the heavily doped epitaxial layer. The total depth of the ultra-shallow doped region (i.e., the junction depth measured from the surface of the top epitaxial layer) is 10 nm to 100 nm. The doping concentration of this ultra-shallow doped region is higher than 1E19 cm⁻¹. -3 Its conductivity type is opposite to that of the heavily doped epitaxial layer. The types of dopants contained in the ultra-shallow doped region are consistent with those in the above example.

[0146] An ultra-shallow planar tunnel junction is formed at the interface between the heavily doped epitaxial layer and the ultra-shallow doped region extending into it. This tunnel junction is covered by the top epitaxial layer, forming a buried structure.

[0147] The semiconductor tunnel junction of the present invention further includes a vertical multi-level tunnel junction structure or a transverse tunnel junction structure.

[0148] The vertical multi-level tunnel junction structure includes at least two tunnel junction units stacked in the vertical direction. Each tunnel junction unit can be a single-layer ultra-shallow planar tunnel junction as described in the above examples, or a double-layer ultra-shallow planar tunnel junction as described in the above examples, or a combination of both.

[0149] Adjacent tunnel junction units are electrically connected through their respective heavily doped epitaxial layers or ultra-shallow doped regions. The conductivity types of the dopants contained in the ultra-shallow doped regions of each tunnel junction are alternately arranged in the vertical direction to form a series-connected stack of tunnel junctions. The projected positions of each tunnel junction on the substrate surface can completely overlap or be partially offset to form a cascaded structure in the vertical direction.

[0150] A transverse tunnel junction structure is formed within the flat surface of the same epitaxial layer. This epitaxial layer can be a heavily doped epitaxial layer, or an unintentionally doped, intrinsic, or high-resistivity epitaxial layer.

[0151] Within the same surface plane of the epitaxial layer, at least one ultra-shallow doped region of a third conductivity type and at least one ultra-shallow doped region of a second conductivity type are disposed adjacent to each other in the horizontal direction and spaced apart. The ultra-shallow doped region of the third conductivity type is a P-type heavily doped region, and the doping element contained therein is at least one selected from zinc (Zn), magnesium (Mg), and cadmium (Cd); the ultra-shallow doped region of the second conductivity type is an N-type heavily doped region, and the doping element contained therein is at least one selected from sulfur (S), selenium (Se), and tellurium (Te).

[0152] The horizontal spacing between the third conductivity type ultra-shallow doped region and the second conductivity type ultra-shallow doped region can be determined according to the device design requirements. The epitaxial layer region between the two forms the barrier region of the lateral tunnel junction, thereby forming a lateral ultra-shallow planar tunnel junction.

[0153] The present invention also provides a laser comprising the above-described semiconductor tunnel junction.

[0154] Compared with existing technologies, the semiconductor tunnel junction and laser of the present invention employ a diffusion source layer deposition combined with a photothermal conversion layer and laser annealing process to achieve the fabrication of ultra-shallow (junction depth less than 100nm) planar tunnel junctions without complex etching and regeneration processes. Simultaneously, the thermal budget of the entire thermal diffusion process is limited to the minimum level necessary to achieve a shallow junction, effectively avoiding the concentration kinking and diffusion tailing problems caused by abnormal diffusion dependent on dopant concentration in traditional thermal diffusion processes.

[0155] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention, by precisely controlling the thickness of the diffusion source layer (combined with atomic-level deposition process), the energy conversion efficiency of the photothermal conversion layer, and the energy density and pulse width of pulsed laser annealing, can stably control the diffusion-doped junction depth within 100 nm.

[0156] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention employ nanosecond-level pulsed laser annealing. Its rapid melting-quenching process allows the solid solubility of the dopant element in the compound semiconductor epitaxial layer to far exceed the equilibrium solid solubility, with a peak doping concentration reaching 1E¹⁹ cm⁻¹. -3 The above fully meets the requirements of high doping concentration for tunnel junctions.

[0157] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention selectively dope only the diffusion window region, without etching micro-mesa. After removing the dielectric layer, the surface of the epitaxial structure remains highly flat, without steps or depressions, avoiding the surface morphology fluctuations introduced by etching micro-mesa in the traditional BTJ process. The flattened surface is seamlessly compatible with subsequent planar processes such as epitaxial regrowth and wafer-level bonding.

[0158] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention avoid the problems of sidewall roughness, interface contamination, and lattice defects caused by selective etching and epitaxial regrowth in the traditional BTJ process. It also avoids lattice damage caused by high-energy ion bombardment in the ion implantation process. Except for point defects introduced by doping, it does not produce other material damage and process failure modes, effectively reducing the risk of device leakage and improving the electrical performance and reliability of the tunnel junction.

[0159] The semiconductor tunnel junction fabrication method, semiconductor tunnel junction, and laser of the present invention do not require expensive ion implantation equipment, complex selective etching mesa fabrication, and epitaxial regeneration processes. The process flow is simple, has good compatibility with traditional semiconductor planar processes, and can be widely applied to various III-V compound semiconductor surface-emitting lasers and edge-emitting lasers containing As, P, and Sb elements. At the same time, it can also be extended to other microelectronic and optoelectronic device fields that require steep abrupt doping, and has good versatility and promotional value.

[0160] Example 1:

[0161] This embodiment focuses on InP-based material systems, preparing N... + InP / P + The InGaAs type ultra-shallow planar tunnel junction uses amorphous silicon (α-Si) as the photothermal conversion layer, matched with a 532nm green nanosecond pulsed laser, and the diffusion source is a zinc oxide (ZnO) thin film containing zinc (Zn) as the dopant element.

[0162] A semi-insulating InP substrate is provided, on which a 300 nm undoped InP layer and a 500 nm N-type doped silicon 5E18 cm layer have been sequentially grown by MOCVD. -3 InGaAs layer, 50nm N-type doped silicon 1E19cm -3InP layer with 50nm unintentional doping (background carrier concentration 5E15cm) -3 The InGaAs layer, and the last layer is the region where ultra-shallow doped regions are formed. Among them, the N-type silicon doped layer is 1E19cm. -3 The InP layer is the second-to-top heavily doped epitaxial layer, and the unintentionally doped InGaAs layer is the top high-resistivity epitaxial layer. Together, they form a bilayer epitaxial structure.

[0163] After organic cleaning and surface oxide removal, a 150 nm thick SiO2 layer was deposited as a diffusion mask using PECVD at 350 °C. Following spin-coating with UV photoresist, the image was exposed and developed through a mask to form diffusion window patterns with a width of 3.0 μm and a spacing of 3.0 μm. The mask layer was etched using reactive ion etching (RIE) until the window area exposed the epitaxial wafer surface. After etching, the photoresist was removed, and the exposed InGaAs surface was treated with dilute hydrochloric acid.

[0164] A 20 nm ZnO thin film was deposited as a solid-state diffusion source layer using ALD at 200 °C with precise cycle control, ensuring high uniformity of ZnO coverage at the bottom and sidewalls of the window. This solid-state diffusion source layer contains Zn as the p-type dopant, which has the opposite conductivity type to the next-top N-type heavily doped epitaxial layer. A 100 nm thick α-Si layer (with a band gap of approximately 1.1 eV) was deposited on the ZnO surface using PECVD as a photothermal conversion layer. This α-Si exhibits a high absorption coefficient for 532 nm wavelength laser light (approximately 2.33 eV).

[0165] A fiber laser was used, frequency-doubled to 532nm, with a pulse width of 10ns-20ns and an energy density of 0.25J / cm². 2 During laser irradiation, the α-Si photothermal conversion layer rapidly heats up to over 1000℃ after absorbing 532nm laser energy. Through thermal conduction, the ZnO / InGaAs interface region reaches over 600℃ in a very short time, driving the rapid diffusion of the dopant Zn into the InGaAs layer. With a laser energy density of 0.25 J / cm² and irradiation for 20 ns, the expected junction depth is approximately 30nm-50nm, and the peak Zn concentration is 1E19cm³. -3 The stability of the laser pulse energy should be controlled within ±3%, and the uniformity of the spot energy distribution should be >95% to ensure the consistency of junction depth in each window area within the wafer.

[0166] The α-Si photothermal conversion layer was selectively removed using a 25% aqueous solution of tetramethylammonium hydroxide (TMAH), the residual ZnO on the surface was dissolved and removed using dilute hydrochloric acid (HCl:H2O=1:10), and the SiO2 diffusion mask layer was removed using buffered oxide etchant (BOE) to expose the flat surface of the epitaxial wafer.

[0167] Example 2:

[0168] This embodiment focuses on GaAs-based material systems and the preparation of P + GaAs / N + The InGaAsN-type ultra-shallow planar tunnel junction uses germanium (Ge) as the photothermal conversion layer and is matched with a 1064nm near-infrared nanosecond pulsed laser. The diffusion source is a tellurium (Te)-containing oxide film, and the doping element is tellurium (Te).

[0169] A semi-insulating GaAs substrate is provided, on which a 300 nm undoped GaAs layer and a 500 nm p-type carbon-doped 5E18 cm⁻¹ layer have been sequentially grown by MOCVD. -3 AlGaAs layer, 30nm P-type carbon-doped 1E19cm -3 A GaAs layer followed by a 30nm unintentionally doped (background carrier concentration 1E16cm⁻³) InGaAsN layer, and finally, an ultra-shallow doped region. The p-type carbon doped region is 1E19cm⁻³. -3 The GaAs layer is the second-to-top heavily doped epitaxial layer, and the unintentionally doped InGaAsN layer is the top high-resistivity epitaxial layer, together forming a bilayer epitaxial structure.

[0170] After organic cleaning and surface oxide removal, a 100 nm thick SiNx layer was deposited as a diffusion mask using PECVD at 400 °C. Following spin-coating with UV photoresist, the image was exposed and developed through the mask to form diffusion window patterns with a width of 3.0 μm and a spacing of 3.0 μm. The mask layer was etched using reactive ion etching (RIE) until the window area exposed the epitaxial wafer surface. After etching, the photoresist was removed, and the exposed InGaAsN surface was treated with dilute hydrochloric acid.

[0171] A 5 nm TeO2 thin film was deposited as a solid-state diffusion source layer using ALD at 150 °C with precise cycle control, ensuring high uniformity of TeO2 coverage at the bottom and sidewalls of the window. The N-type dopant in this solid-state diffusion source layer is Te, which has the opposite conductivity type to the next-top layer of heavily p-type doped epitaxial layer. A 100 nm thick α-Ge layer (with a band gap of approximately 0.67 eV) was deposited on the TeO2 surface using PECVD as a photothermal conversion layer. This α-Ge exhibits a high absorption coefficient for 1064 nm wavelength laser light (approximately 1.17 eV).

[0172] A 1064nm Nd:YAG nanosecond pulsed laser was used, with a pulse width of 10-20ns and an energy density of 0.22J / cm². 2During laser irradiation, the α-Ge photothermal conversion layer rapidly heats up to over 1000℃ after absorbing 1064nm laser energy. Through thermal conduction, the TeO2 / InGaAsN interface region reaches over 600℃ in a very short time, driving Te atoms to diffuse rapidly into the InGaAsN layer. With a laser energy density of 0.22J / cm² and irradiation for 10ns, the expected junction depth is approximately 20nm-30nm, and the peak Te concentration is 2E19cm². -3 The stability of the laser pulse energy should be controlled within ±3%, and the uniformity of the spot energy distribution should be >95% to ensure the consistency of junction depth in each window area within the wafer.

[0173] The α-Ge photothermal conversion layer was selectively removed using hydrogen peroxide solution, residual TeO2 on the surface was removed by dissolving it with dilute hydrochloric acid (HCl:H2O=1:10), and SiN was removed using hot phosphoric acid (H3PO4) solution. X A diffusion mask layer is used to expose the flat surface of the epitaxial wafer.

[0174] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0175] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for fabricating a semiconductor tunnel junction, characterized in that, include: An epitaxial structure is provided, the epitaxial structure comprising a semiconductor layer having a first conductivity type; A dielectric layer is formed on the surface of the epitaxial structure; The dielectric layer is patterned to form at least one diffusion window on the dielectric layer, the diffusion window exposing the target doped region on the surface of the epitaxial structure; A diffusion source layer is prepared on one side of the epitaxial structure where a dielectric layer is formed. The diffusion source layer includes a dopant element having a second conductivity type, which is opposite to the first conductivity type. A photothermal conversion layer is formed on the diffusion source layer; The photothermal conversion layer is irradiated with a laser beam, which thermally activates the doping elements in the diffusion source layer. The doping elements diffuse into the epitaxial structure through the opening, forming a first doped region with a second conductivity type. The first doped region and the semiconductor layer form a tunnel junction. Remove the photothermal conversion layer, the remaining diffusion source layer, and the dielectric layer.

2. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, The diffusion source layer is prepared by atomic layer deposition or magnetron sputtering, and the thickness of the diffusion source layer is controlled with an accuracy of less than 1 nm.

3. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, The photothermal conversion layer is configured to have absorption properties for laser light of a specific wavelength; Irradiating the photothermal conversion layer with a laser beam includes: The photothermal conversion layer is irradiated with a laser beam that matches the absorption characteristics of the photothermal conversion layer. The photothermal conversion layer converts the laser energy into heat energy in nanosecond to microsecond time through the photothermal effect and conducts it to the diffusion source layer to activate the doping elements in the diffusion source layer.

4. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, The photothermal conversion layer is irradiated with a laser beam using a single-pulse, multi-pulse irradiation method, or a spot scanning method. The pulse width is 1ns-1000ns, and the energy density is 0.05J / cm². 2 -0.5J / cm 2 .

5. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, The material of the photothermal conversion layer is selected from at least one of amorphous silicon, germanium, amorphous carbon, diamond-like carbon, graphite carbon, metal oxides, or metal nitrides.

6. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, The doping concentration of the first doped region is higher than 1E19cm. -3 ; and / or, The junction depth of the first doped region is 10nm-100nm.

7. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, The epitaxial structure is a semiconductor layer having a first conductivity type, and the semiconductor layer is a heavily doped epitaxial layer with a doping concentration greater than 1E19cm⁻¹. -3 The first doped region is formed within the heavily doped epitaxial layer.

8. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, The epitaxial structure includes a semiconductor layer having a first conductivity type and a top epitaxial layer located on the semiconductor layer. The top epitaxial layer is an unintentionally doped epitaxial layer, an intrinsic epitaxial layer, or a high-resistivity epitaxial layer. The first doped region is formed within the unintentionally doped epitaxial layer, the intrinsic epitaxial layer, or the high-resistivity epitaxial layer.

9. The method for preparing a semiconductor tunnel junction according to claim 8, characterized in that, The semiconductor layer is a heavily doped epitaxial layer with a doping concentration greater than 1E19cm⁻¹. -3 ; and / or ; The carrier concentration of the unintentionally doped epitaxial layer or the intrinsic epitaxial layer is less than 1E16cm. -3 The resistivity of the high-resistivity epitaxial layer is higher than 1E3Ω·cm.

10. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, The material of the epitaxial structure is selected from group III-V binary compound semiconductors containing As, P, and Sb elements, or ternary or higher-order multi-element alloys containing In, Al, Ga, and N elements with lattice matching or lattice mismatch less than 1.5% with the group III-V binary compound semiconductor; and / or, The thickness of the dielectric layer is 10nm-500nm; and / or, The material of the dielectric layer is selected from alumina, silicon oxide, or silicon nitride; and / or, The size of the diffusion window is 0.5 μm-100 μm; and / or, The diffusion source layer is a solid compound diffusion source film; and / or, The thickness of the diffusion source layer is 5nm-300nm; and / or, When the first conductivity type is N-type, the diffusion source layer contains a P-type dopant element; when the first conductivity type is P-type, the diffusion source layer contains an N-type dopant element. The P-type dopant element is selected from at least one of Zn, Mg, or Cd, and the N-type dopant element is selected from at least one of S, Se, or Te.

11. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, Also includes: The steps of forming an epitaxial structure, forming a dielectric layer, forming a diffusion source layer, forming a photothermal conversion layer, and laser irradiation are repeated on the surface of the epitaxial structure. At least one additional tunnel junction is formed on the already formed tunnel junction to form a vertically stacked multi-level tunnel junction structure.

12. The method for preparing a semiconductor tunnel junction according to claim 1, characterized in that, Also includes: The steps of forming a dielectric layer, opening windows, forming a diffusion source layer, forming a photothermal conversion layer, and laser irradiation are repeatedly performed on the surface of the epitaxial structure to form a second doped region with a third conductivity type at a horizontal position adjacent to the first doped region. The third conductivity type is opposite to the second conductivity type, thus forming a lateral tunnel junction structure.

13. A semiconductor tunnel junction, characterized in that, include: An epitaxial structure, the epitaxial structure comprising a semiconductor layer having a first conductivity type; A first doped region having a second conductivity type is located in the epitaxial structure, the second conductivity type being opposite to the first conductivity type, and the first doped region and the semiconductor layer forming a tunnel junction; The junction depth of the first doped region is 10nm-100nm, and the doping concentration is higher than 1E19cm. -3 .

14. The semiconductor tunnel junction according to claim 13, characterized in that, The epitaxial structure is a semiconductor layer having a first conductivity type, and the semiconductor layer is a heavily doped epitaxial layer with a doping concentration greater than 1E19cm⁻¹. -3 The first doped region is formed within the heavily doped epitaxial layer.

15. The semiconductor tunnel junction according to claim 13, characterized in that, The epitaxial structure includes a semiconductor layer having a first conductivity type and a top epitaxial layer located on the semiconductor layer. The top epitaxial layer is an unintentionally doped epitaxial layer, an intrinsic epitaxial layer, or a high-resistivity epitaxial layer. The first doped region is formed within the unintentionally doped epitaxial layer, the intrinsic epitaxial layer, or the high-resistivity epitaxial layer.

16. The semiconductor tunnel junction according to claim 15, characterized in that, The semiconductor layer is a heavily doped epitaxial layer with a doping concentration greater than 1E19cm⁻¹. -3 ; and / or ; The carrier concentration of the unintentionally doped epitaxial layer or the intrinsic epitaxial layer is less than 1E16cm. -3 The resistivity of the high-resistivity epitaxial layer is higher than 1E3Ω·cm.

17. The semiconductor tunnel junction according to claim 13, characterized in that, The material of the epitaxial structure is selected from group III-V binary compound semiconductors containing As, P, and Sb elements, or ternary or higher-order multi-element alloys containing In, Al, Ga, and N elements with lattice matching or lattice mismatch less than 1.5% with the group III-V binary compound semiconductor; and / or, The lateral dimension of the first doped region is 0.5 μm-100 μm; and / or, When the first conductivity type is N-type, the diffusion source layer contains a P-type dopant element; when the first conductivity type is P-type, the diffusion source layer contains an N-type dopant element. The P-type dopant element is selected from at least one of Zn, Mg, or Cd, and the N-type dopant element is selected from at least one of S, Se, or Te.

18. The semiconductor tunnel junction according to claim 13, characterized in that, Also includes: At least one additional tunnel junction is located on the extensional structure, and the additional tunnel junction is stacked with the tunnel junction in the vertical direction to form a multi-level tunnel junction structure.

19. The semiconductor tunnel junction according to claim 13, characterized in that, Also includes: The second doped region, which is located in the epitaxial structure and is horizontally adjacent to the first doped region, has a third conductivity type that is opposite to the second conductivity type. The second doped region and the first doped region form a transverse tunnel junction structure.

20. A laser, characterized in that, Includes a semiconductor tunnel junction as described in any one of claims 13-19.

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