A DSP control system protection circuit

Abstract

The embodiment of the application discloses a DSP control system protection circuit, which comprises an operational amplifier, a rectification protection circuit and a detection and output circuit. The non-inverting input end of the operational amplifier is connected with the PWM signal output pin of the DSP, and the inverting input end is connected with the reference voltage through a voltage dividing circuit, which is used for converting the PWM signal into a first output signal. The input end of the rectification protection circuit is connected with the output end of the operational amplifier, which is used for rectifying the first output signal to generate a second output signal and implementing overvoltage or overcurrent protection on the rear-end circuit. The input end of the detection and output circuit is connected with the output end of the rectification protection circuit, which is used for extracting the alternating current pulse component in the second output signal and judging whether the PWM signal is in the abnormal state of continuous high level according to the output state of the alternating current pulse component. Thus, the fault that the signal of the DSP control system is stuck at the high level can be effectively identified, and the safety of system operation is improved.

Description

Technical Field

[0001] This invention relates to the field of motor control, and more particularly to a protection circuit for a DSP control system. Background Technology

[0002] In the field of motor drive control, Digital Signal Processors (DSPs), with their high-speed data processing capabilities and flexible algorithm implementations, have become the core control devices in modern variable frequency speed control systems, industrial servo drives, and electric vehicle control units. DSPs generate multiple high-precision pulse width modulation (PWM) signals to control the on / off timing of power switching devices, thereby achieving precise regulation of motor speed and torque. To ensure safe system operation, existing technologies typically employ strategies such as software watchdog timers, program execution status monitoring, or overcurrent and overvoltage fault detection interrupts based on ADC sampling, attempting to block the PWM output through software intervention when abnormal PWM output occurs.

[0003] However, the aforementioned monitoring schemes that rely on software operation have inherent flaws. When the DSP encounters strong electromagnetic interference, drastic power supply fluctuations, or uncaught "dangling pointers" and logical infinite loops in the program itself, the program counter may go out of control, the kernel clock may lock up, or the interrupt vector table may become abnormal, resulting in program crashes or system freezes. Under such extreme faults, the DSP core is unable to execute any preset fault response instructions, and the software watchdog loses its reset capability because the kernel stops feeding it, causing the physical state of the PWM output pins to be randomly locked.

[0004] Therefore, there is an urgent need for a pure hardware protection circuit that is independent of the DSP digital arithmetic unit and does not rely on any software instructions for execution. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a protection circuit for a DSP control system to solve the problem that existing DSP control systems lack a hardware-level protection mechanism independent of software, which leads to motor drive malfunction when the program runs out of control.

[0006] In a first aspect, embodiments of the present invention provide a protection circuit for a DSP control system, comprising: The operational amplifier has its non-inverting input connected to the PWM signal output pin of the DSP, and its inverting input connected to a voltage divider circuit to receive a reference voltage. It is configured to convert the PWM signal into the first output signal. The rectifier protection circuit has its input terminal connected to the output terminal of the signal conditioning circuit. It is used to rectify the first output signal to obtain the second output signal and to protect the downstream circuit. The detection and output circuit has its input terminal connected to the output terminal of the rectifier protection circuit. It is used to detect the AC pulse component of the second output signal to determine whether the PWM signal is in an abnormal state of continuous high level.

[0007] In some embodiments, the reference voltage is 0.7V.

[0008] In some embodiments, the rectifier protection circuit includes a diode, the anode of which is connected to the output terminal of the operational amplifier, and the cathode is connected to the input terminal of the detection and output circuit.

[0009] In some embodiments, the diode is a 1N4148 type switching diode.

[0010] In some embodiments, the operational amplifier operates in comparator mode to compare the PWM signal with the reference voltage.

[0011] In some embodiments, the output terminal of the detection and output circuit is connected to a signal output terminal, which is used to connect to the control terminal of the subsequent power drive module. The detection and output circuit is configured as follows: When the PWM signal is a normal pulse signal, an effective drive signal with the same frequency as the PWM signal is output to the signal output terminal. When the PWM signal is continuously high or continuously low, an invalid level is output to the signal output terminal.

[0012] In some embodiments, the input terminal of the DSP control system protection circuit is adapted to the PWM output interface of the TMS320 series DSP or STM32 series MCU.

[0013] In some embodiments, the circuit further includes: The output compensation circuit is connected between the inverting input of the operational amplifier and the detection and output circuit to compensate for the edge characteristics of the pulse signal.

[0014] In some embodiments, the output compensation circuit includes a compensation capacitor with a capacitance of 0.001nF.

[0015] Secondly, embodiments of the present invention provide a DSP control system, the DSP control system including a protection circuit, the protection circuit comprising: The operational amplifier has its non-inverting input connected to the PWM signal output pin of the DSP, and its inverting input connected to a voltage divider circuit to receive a reference voltage. It is configured to convert the PWM signal into the first output signal. The rectifier protection circuit has its input terminal connected to the output terminal of the signal conditioning circuit. It is used to rectify the first output signal to obtain the second output signal and to protect the downstream circuit. The detection and output circuit has its input terminal connected to the output terminal of the rectifier protection circuit. It is used to detect the AC pulse component of the second output signal to determine whether the PWM signal is in an abnormal state of continuous high level.

[0016] The technical solution of this invention includes an operational amplifier, a rectifier protection circuit, and a detection and output circuit in the protection circuit of the DSP control system. The non-inverting input of the operational amplifier is connected to the PWM signal output pin of the DSP, and the inverting input is connected to a reference voltage through a voltage divider circuit to convert the PWM signal into a first output signal. The input of the rectifier protection circuit is connected to the output of the operational amplifier to rectify the first output signal to generate a second output signal and to provide overvoltage or overcurrent protection for the downstream circuit. The input of the detection and output circuit is connected to the output of the rectifier protection circuit to extract the AC pulse component in the second output signal and to determine whether the PWM signal is in an abnormal state of continuous high level based on the output state of the AC pulse component. Therefore, it can effectively identify faults where the signal of the DSP control system is stuck at a high level, improving the safety of system operation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the protection circuit of the DSP control system provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a signal generator simulating a 5kHz square wave output by a DSP, provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the signal generator simulating a high-level DSP output provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a signal generator simulating a low-level DSP output provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] Figure 1 This is a schematic diagram of the protection circuit of the DSP control system provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the DSP control system protection circuit according to this embodiment of the invention includes an operational amplifier 11, a rectifier protection circuit 12, a detection and output circuit 13, and an output compensation circuit 14. The non-inverting input of the operational amplifier 11 is connected to the PWM signal output pin of the DSP, and the inverting input is connected to a voltage divider circuit to receive a reference voltage. The input of the rectifier protection circuit 12 is connected to the output of the signal conditioning circuit. The input of the detection and output circuit is connected to the output of the rectifier protection circuit, and its output is connected to [other components]. The output compensation circuit 14 is connected between the inverting input of the operational amplifier and the detection and output circuit.

[0021] In the actual implementation of the DSP control system protection circuit provided in this embodiment of the invention, the operational amplifier 11 preferably adopts the AD8042 high-speed operational amplifier. This type of device has sufficient bandwidth and slew rate, and can process the high-frequency PWM signal output by the DSP without distortion. The non-inverting input terminal of the operational amplifier 11 serves as the input terminal of the entire protection circuit and is directly connected to the PWM signal output pin of the DSP to receive the PWM signal output by the DSP. The inverting input terminal of the operational amplifier 11 is connected to a voltage divider circuit, which is composed of resistors R1 and R2 connected in series. One end of R1 is connected to a reference voltage, for example, +3.3V, and the other end of R1 is connected to one end of R2 and the inverting input terminal of the operational amplifier 11. The other end of R2 is grounded, thereby providing a stable reference voltage for the inverting input terminal.

[0022] In one specific embodiment of the present invention, the reference voltage is set to 0.7V. The selection of this voltage value can ensure effective discrimination of common TTL or CMOS level PWM signals. However, those skilled in the art should understand that the reference voltage is not fixed and can be flexibly set to other voltage values ​​by adjusting the resistance ratio of R1 and R2 according to the actual amplitude of the DSP output signal. The embodiments of the present invention do not impose any restrictions on this.

[0023] Operational amplifier 11 is configured to operate in comparator mode in this circuit. Its function is to compare the PWM signal voltage received at the non-inverting input with the reference voltage at the inverting input. When the voltage amplitude of the PWM signal is higher than the reference voltage, it outputs a high level; otherwise, it outputs a low level. This shapes the original PWM signal into a first output signal with steep edges and standard amplitude. On the one hand, this provides a stable processing basis for subsequent circuits, and on the other hand, it effectively isolates the preceding and following circuits, enhancing the signal's driving capability.

[0024] The input terminal of the rectifier protection circuit 12 is connected to the output terminal of the operational amplifier 11. It receives the aforementioned first output signal and rectifies it to obtain the second output signal, while simultaneously protecting the downstream circuitry from reverse voltage or current surges. In an optional implementation of the invention, the rectifier protection circuit 12 is specifically composed of a diode. The anode of the diode is connected to the output terminal of the operational amplifier 11, and the cathode is connected to the input terminal of the detection and output circuit 13. Utilizing the unidirectional conductivity of the diode, it allows positive pulses to pass through while blocking any possible reverse voltage or negative pulses, thereby rectifying the signal into a unidirectional pulsating DC form, i.e., obtaining the second output signal. This provides the correct signal polarity for the downstream detection circuit and also prevents abnormal voltages in subsequent circuits from backfiring on the operational amplifier 11, thus protecting the downstream circuitry.

[0025] Furthermore, in a preferred embodiment of the present invention, the diode is selected as a 1N4148 high-speed switching diode. The 1N4148 is a general-purpose small-signal high-frequency switching diode with a typical reverse recovery time of only 4 nanoseconds and a junction capacitance of approximately 4 picofarads. Since the PWM signal emitted by the DSP control system is usually at a high frequency, its edges contain rich high-frequency harmonic components. The 1N4148 diode, with its extremely short reverse recovery time and low junction capacitance, can follow the rapid edge changes of the PWM pulse without distortion and with high fidelity. This ensures that the critical timing and duty cycle information of the high-speed pulse signal will not be distorted or lost due to the hysteresis effect of the rectifier element when passing through this protection circuit. At the same time, this type of diode is inexpensive and widely applicable, making it a preferred solution that balances performance and cost.

[0026] The input terminal of the detection and output circuit 13 is connected to the output terminal of the rectifier protection circuit 12, and its output terminal is connected to the signal output terminal, which is used to connect to the control terminal of the subsequent power drive module. In a specific embodiment of the present invention, the detection and output circuit 13 is mainly composed of a series coupling capacitor C1 with a capacitance of 10μF. The entire detection and output circuit utilizes the basic characteristics of a capacitor to pass AC and block DC to realize its function.

[0027] Specifically, when the DSP is working normally, its PWM signal is a pulse sequence that changes continuously from high to low. After being processed by the operational amplifier 11 and the rectifier protection circuit 12, the signal becomes a positive pulse sequence with the same frequency as the PWM signal, which is the second output signal. When this pulse sequence passes through the series coupling capacitor, due to the high signal frequency and small capacitive reactance, the AC component of the pulse can pass smoothly, thereby obtaining an effective AC drive signal with the same frequency as the PWM signal at the signal output terminal. This drive signal is used to drive the subsequent power module to work normally.

[0028] When the DSP's PWM pin is locked to a continuous high level due to program crashes or system freezes, the signal input to operational amplifier 11 becomes a constant DC high level. This high level, after passing through the comparator and rectifier diode, is still a constant DC voltage. At this time, for the series coupling capacitor, the frequency f of the DC component is 0, and its capacitive reactance Xc approaches infinity, which is equivalent to an open circuit. Therefore, the DC high level is completely blocked and cannot be transmitted to the signal output terminal. The signal output terminal outputs an invalid level due to the pull-down effect of the subsequent circuit or because the capacitor has no charging or discharging current. Similarly, when the DSP has no output or the output pin is locked to a continuous low level, operational amplifier 11 outputs a continuous low level, which is also a constant DC signal. It is also blocked when passing through the series coupling capacitor, and the signal output terminal also outputs an invalid level, thereby disabling the operation of the subsequent power module.

[0029] Through the above mechanism, the detection and output circuit 13 realizes real-time monitoring of the PWM signal status, that is, only the normally alternating pulse signal can be effectively transmitted, and any abnormal DC level lock-in state will be identified and blocked, thereby effectively suppressing the DSP software runaway at the hardware level.

[0030] The input terminal of the DSP control system protection circuit provided in this embodiment of the invention, namely the non-inverting input terminal of operational amplifier 11, has high compatibility. Its interface design is adapted to the PWM output interface of TMS320 series DSPs or STM32 series MCUs. Since the PWM output of these two mainstream control chips is typically TTL or CMOS level, such as 3.3V or 5V, the 0.7V reference voltage set in this invention can reliably distinguish between the effective level and the ineffective level. This allows the protection circuit to be directly connected in series between the DSP or MCU and the subsequent drive circuit without any level conversion or interface matching components. This facilitates integration and upgrades on existing systems, and has strong versatility and plug-and-play characteristics, effectively reducing the complexity and cost of system modification.

[0031] Output compensation circuit 14 is connected between the inverting input of operational amplifier 11 and detection and output circuit 13, and is used to compensate for the edge characteristics of pulse signals. In a specific embodiment of the present invention, output compensation circuit 14 includes a compensation capacitor C2 with a capacitance of 0.001nF. This small pF capacitor acts as a high-frequency bypass or acceleration capacitor, providing a low-impedance, fast path for the high-frequency components in the signal. When the edge of the PWM signal, especially the rising edge, arrives, the capacitor can be turned on instantaneously to provide a steep starting pulse, thereby effectively compensating for the edge softening that may occur after long-link transmission, ensuring that the final output drive signal has a sufficiently steep edge to meet the strict requirements of the subsequent power drive module for signal timing and integrity.

[0032] To facilitate a clear and intuitive display of the waveforms at each node and verification of the circuit's operating status, this embodiment of the invention also includes an oscilloscope 15. The first channel of the oscilloscope 15 is connected to the PWM signal output pin of the DSP or the output of the signal generator, used to acquire and display the original PWM signal waveform. The second channel of the oscilloscope is connected to the output of the operational amplifier to observe the first output signal waveform after comparator shaping. The third channel of the oscilloscope is connected to the output of the rectifier protection circuit to observe the second output signal waveform after rectification. The fourth channel of the oscilloscope is connected to the signal output terminal, i.e., the output of the detection and output circuit, used to acquire and display the final output drive signal waveform after processing by the protection circuit. In actual testing, the first and fourth channels of the oscilloscope use the same voltage amplitude scale and time base scale to facilitate a clear and intuitive comparison and analysis of the input and output signals.

[0033] Those skilled in the art should understand that the number of channels and connection nodes of an oscilloscope can be adjusted according to actual testing needs, and the embodiments of the present invention do not impose any limitations on this.

[0034] Figures 2 to 4 The measured waveforms of the circuit of this invention are shown. Figure 2 This is a schematic diagram of a signal generator simulating a 5kHz square wave output by a DSP, provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the signal generator simulating a high-level DSP output provided in an embodiment of the present invention. Figure 4 This is a schematic diagram illustrating the low-level output of a DSP by a signal generator according to an embodiment of the present invention. Specifically, Figure 2 The diagram shows the waveform of a 5kHz square wave output by a signal generator simulating a normal DSP output. As can be seen from the diagram, the final output signal of channel 4, i.e., this protection circuit, is consistent with the output waveform of the signal generator. Both are pulse sequences with the same frequency. This indicates that under normal conditions, the protection circuit has almost no attenuation or distortion of the effective signal and can reliably transmit the drive signal. Figure 3 The waveform diagram is shown when the signal generator simulates a DSP overspeeding fault and outputs a continuous high level. At this time, the final output signal of channel 4 immediately becomes low level, i.e. invalid level. This intuitively demonstrates the core function of the circuit of this invention, that is, once the PWM signal is abnormally locked to high, the protection circuit will instantly cut off the output, eliminating the possibility of the power module losing control and accelerating due to receiving a 100% duty cycle drive signal. Figure 4 This is a waveform diagram illustrating a signal generator simulating a DSP with no output, a system crash, or a continuously low output level. Figure 3 Similarly, the final output signal of channel 4 is also clamped to a low level, so the subsequent power drive module cannot receive the drive signal and is in a safe shutdown state, thus achieving comprehensive hardware-level safety protection.

[0035] Accordingly, this invention also provides a DSP control system, which includes the protection circuit described in any of the above embodiments. In this DSP control system, the protection circuit, as a hardware module independent of the DSP software, is connected in series between the PWM output pin of the DSP and the control terminal of the subsequent power drive module. Through this protection circuit, the system allows the PWM drive signal to pass through to drive the subsequent power module when the DSP is working normally. However, when the DSP is abnormally locked to a continuous high or low level due to interference, power fluctuations, or program logic errors, the protection circuit can immediately and automatically cut off the drive signal and lock it at an invalid level. This effectively suppresses DSP software overrunning faults through pure hardware, fundamentally improving the safety and reliability of key application scenarios such as motor control and frequency conversion drive.

Claims

1. A protection circuit for a DSP control system, characterized in that, include: The operational amplifier has its non-inverting input connected to the PWM signal output pin of the DSP, and its inverting input connected to a voltage divider circuit to receive a reference voltage. It is configured to convert the PWM signal into the first output signal. The rectifier protection circuit has its input terminal connected to the output terminal of the signal conditioning circuit. It is used to rectify the first output signal to obtain the second output signal and to protect the downstream circuit. The detection and output circuit has its input terminal connected to the output terminal of the rectifier protection circuit. It is used to detect the AC pulse component of the second output signal to determine whether the PWM signal is in an abnormal state of continuous high level.

2. The circuit according to claim 1, characterized in that, The reference voltage is 0.7V.

3. The circuit according to claim 1, characterized in that, The rectifier protection circuit includes a diode, with the positive terminal of the diode connected to the output terminal of the operational amplifier and the negative terminal connected to the input terminal of the detection and output circuit.

4. The circuit according to claim 3, characterized in that, The diode is a 1N4148 type switching diode.

5. The circuit according to claim 1, characterized in that, The operational amplifier operates in comparator mode and is used to compare the PWM signal with the reference voltage.

6. The circuit according to claim 1, characterized in that, The output terminal of the detection and output circuit is connected to the signal output terminal, which is used to connect to the control terminal of the subsequent power drive module. The detection and output circuit is configured as follows: When the PWM signal is a normal pulse signal, an effective drive signal with the same frequency as the PWM signal is output to the signal output terminal. When the PWM signal is continuously high or continuously low, an invalid level is output to the signal output terminal.

7. The circuit according to claim 1, characterized in that, The input terminal of the DSP control system protection circuit is compatible with the PWM output interface of the TMS320 series DSP or STM32 series MCU.

8. The circuit according to claim 1, characterized in that, Also includes: The output compensation circuit is connected between the inverting input of the operational amplifier and the detection and output circuit to compensate for the edge characteristics of the pulse signal.

9. The circuit according to claim 8, characterized in that, The output compensation circuit includes a compensation capacitor with a capacitance of 0.001nF.

10. A DSP control system, characterized in that, The DSP control system includes a protection circuit, which includes: The operational amplifier has its non-inverting input connected to the PWM signal output pin of the DSP, and its inverting input connected to a voltage divider circuit to receive a reference voltage. It is configured to convert the PWM signal into the first output signal. The rectifier protection circuit has its input terminal connected to the output terminal of the signal conditioning circuit. It is used to rectify the first output signal to obtain the second output signal and to protect the downstream circuit. The detection and output circuit has its input terminal connected to the output terminal of the rectifier protection circuit. It is used to detect the AC pulse component of the second output signal to determine whether the PWM signal is in an abnormal state of continuous high level.

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