Overcurrent detection protection circuit

Abstract

The embodiment of the specification provides an overcurrent detection protection circuit, a current limiting pin is arranged, and a detection circuit inside a chip is configured. The detection circuit collects a voltage signal of the current limiting pin when a high side switch is opened. A comparison determination module automatically identifies a current mode. No additional configuration or external signal intervention of a user is needed. Intelligent mode differentiation is realized. According to an identification result, a current source output end automatically outputs corresponding positive temperature coefficient current or zero temperature coefficient current. Temperature drift of a conduction resistance of a Rdson mode power tube or a high-precision threshold of an Rsense mode is respectively compensated. Overcurrent protection is stable and reliable in a full temperature range. An overcurrent trigger module detects whether a voltage of the current limiting pin is zero at an inductance current trough moment before a low side switch is closed. Fast overcurrent response is realized cycle by cycle. Wave trough detection avoids switch noise interference. The accuracy and robustness of protection action are improved.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of equipment operation and maintenance technology, and in particular to overcurrent detection and protection circuits. Background Technology

[0002] In existing BUCK power control chips, overcurrent protection circuits typically support only a single current sensing method, such as sampling via a series sampling resistor or sampling via the power transistor's on-resistance. The series sampling resistor method offers advantages such as high accuracy and low temperature drift, but introduces additional conduction losses and occupies PCB area, making it unsuitable for high-power applications. The power transistor on-resistance sampling method has no additional losses, but it is highly susceptible to temperature and process variations, has lower accuracy, and usually requires complex differential sampling circuitry to handle high-voltage switching noise at the SW node. Existing power control chips often have current limiting pins designed for a single mode, preventing users from flexibly selecting the sensing method on the same chip based on specific power levels and accuracy requirements. This limits the chip's application range and increases the variety and cost of components in system design. Furthermore, existing detection circuits cannot effectively distinguish the current external detection configuration when the high-side switch is open, resulting in insufficient mode recognition reliability. They also cannot automatically adapt to current sources with different temperature characteristics based on the recognition results, making it difficult to balance temperature compensation for overcurrent protection thresholds across different modes.

[0003] Therefore, a better solution is urgently needed. Summary of the Invention

[0004] In view of this, embodiments of this specification provide an overcurrent detection and protection circuit to address the technical deficiencies existing in the prior art.

[0005] According to a first aspect of the embodiments of this specification, an overcurrent detection and protection circuit is provided, comprising: The chip has a current limiting pin. The current limiting pin is configured to support a first mode and a second mode, the first mode being the Rdson mode implemented by connecting a resistor to the SW pin of the chip, and the second mode being the Rsense mode implemented by connecting a resistor to the source of the low-side switch of the chip. The chip has an internal detection circuit, the input of which is connected to the current limiting pin. The detection circuit is configured to acquire the voltage signal of the current limiting pin when the high-side switch of the chip is turned on. The detection circuit further includes a comparison and determination module, which is configured to determine that the current mode is the first mode when the voltage signal of the current limiting pin is high, and to determine that the current mode is the second mode when the voltage signal of the current limiting pin is low. The detection circuit also includes a current source output terminal, which is connected to the current limiting pin. The current source output terminal is configured to output a corresponding current from the current limiting pin according to the determination result, wherein the positive temperature coefficient current is output for the first mode and the zero temperature coefficient current is output for the second mode. The detection circuit also includes an overcurrent trigger module. The input terminal of the overcurrent trigger module is connected to the current limiting pin. The overcurrent trigger module is configured to generate an overcurrent protection action based on whether the voltage of the current limiting pin crosses zero before the low-side switch of the chip is turned off.

[0006] In one possible implementation, the detection circuit includes a first detection sub-circuit configured to detect only the voltage of the current-limiting pin. In the first detection sub-circuit: the current-limiting pin is connected to the source of a first high-voltage transistor; the gate of the first high-voltage transistor is connected to the internal low-voltage power supply terminal of the chip; the drain of the first high-voltage transistor is connected to the input of a first inverter; the output of the first inverter is connected to the input of a delay unit; the output of the delay unit is connected to the clock terminal of a first flip-flop; the data input of the first flip-flop is connected to the internal low-voltage power supply terminal; and the output of the first flip-flop outputs a mode distinction signal. The first detection sub-circuit is configured such that: in the first mode, when the high-side switch is open, the voltage of the current-limiting pin is the same as the voltage of the SW pin and is higher than the voltage of the internal low-voltage power supply terminal, and the output of the first flip-flop outputs a low-level signal; in the second mode, the voltage of the current-limiting pin is low, and the output of the first flip-flop outputs a high-level signal.

[0007] In one possible implementation, the detection circuit includes a second detection sub-circuit configured to simultaneously detect the voltages of the current-limiting pin and the SW pin. In the second detection sub-circuit: the output of the system enable signal is connected to the input of a first logic gate; the output of the first logic gate is connected to the control terminals of a first switching transistor and a second switching transistor; the first switching transistor is connected between the current-limiting pin and the source of a second high-voltage transistor; the second switching transistor is connected between the SW pin and the source of a third high-voltage transistor; the drain of the second high-voltage transistor is connected to the first input of a first AND gate; the drain of the third high-voltage transistor is connected to the second input of the first AND gate; the output of the first AND gate is connected to the input of a latch circuit. The output terminals of the circuit output a first control signal and a second control signal, respectively. The first control signal and the second control signal are connected to the control terminals of the first switch and the second switch to turn off the detection input. The second detection sub-circuit is configured as follows: in the initial state, the first control signal is high and the second control signal is low, and the first switch and the second switch are turned on. In the first mode, the voltage of the current limiting pin is the same as the voltage of the SW pin, which is high, and the first AND gate outputs a low level. In the second mode, the voltage of the SW pin is high and the voltage of the current limiting pin is low, and the first AND gate outputs a high level. The latching circuit locks the first control signal and the second control signal according to the output of the first AND gate.

[0008] In one possible implementation, the first mode is configured to be applied when the power demand is greater than a preset threshold, and the first mode uses the on-resistance of the power transistor for detection, the on-resistance of the power transistor increasing with increasing temperature; the second mode is configured to be applied when the power demand is less than the preset threshold, and the second mode uses an external resistor for detection, the temperature coefficient of the external resistor being stable.

[0009] In one possible implementation, the overcurrent protection action is configured to occur at a time before the low-side switch is turned off, at the trough of the inductor current.

[0010] In one possible implementation, the overcurrent protection action is triggered when the voltage of the current limiting pin crosses zero. The voltage of the current limiting pin is determined when the low-side switch is turned on by the following method: the product of the current flowing out of the current limiting pin and the external resistor connected to the current limiting pin, minus the product of the inductor valley current and the sensing resistor, wherein the inductor valley current is the average inductor current minus half of the peak-to-peak inductor current, and the sensing resistor is the on-resistance of the low-side switch in the first mode and the Rs resistor in the second mode.

[0011] In one possible implementation, in the first mode, the voltage of the current limiting pin is: the product of the positive temperature coefficient current flowing out of the current limiting pin and the external resistor minus the product of the inductor valley current and the on-resistance of the low-side switch; the overcurrent trigger module is configured to trigger the overcurrent protection action when the voltage of the current limiting pin is negative.

[0012] In one possible implementation, in the second mode, the voltage of the current limiting pin is: the product of the zero temperature coefficient current flowing out of the current limiting pin and the external resistor minus the product of the inductor valley current and the Rs resistor; the overcurrent trigger module is configured to trigger the overcurrent protection action when the voltage of the current limiting pin is negative.

[0013] In one possible implementation, the detection circuit further includes a mode control logic module. The input of the mode control logic module is connected to the output of the comparison and determination module, and the output of the mode control logic module is connected to the control terminal of the controllable current source. The output of the controllable current source is connected to the current limiting pin. The mode control logic module is configured to control the controllable current source according to the determination result, such that the positive temperature coefficient current is output from the current limiting pin in the first mode, and the zero temperature coefficient current is output from the current limiting pin in the second mode.

[0014] In one possible implementation, the overcurrent protection action includes shutting down the power transistor inside the chip or putting the chip into a hiccup protection mode, wherein the hiccup protection mode is to intermittently restart the chip.

[0015] This specification provides an overcurrent detection and protection circuit. By setting a single current limiting pin and configuring the chip's internal detection circuit, it can simultaneously support both Rdson and Rsense overcurrent detection modes. Users can flexibly choose according to the power and accuracy requirements of the application scenario, expanding the chip's applicability. The detection circuit acquires the current limiting pin voltage signal when the high-side switch is turned on, and automatically identifies the current mode through a comparison and judgment module, without requiring additional user configuration or external signal intervention, achieving intelligent mode differentiation. Based on the identification result, the current source output terminal automatically outputs the corresponding positive temperature coefficient current or zero temperature coefficient current, respectively compensating for the temperature drift of the power transistor's on-resistance in Rdson mode or maintaining the high-precision threshold in Rsense mode, making the overcurrent protection stable and reliable across the entire temperature range. The overcurrent triggering module detects whether the current limiting pin voltage crosses zero at the trough of the inductor current before the low-side switch is turned off, achieving a fast overcurrent response cycle by cycle. Furthermore, trough detection avoids switching noise interference, improving the accuracy and robustness of the protection action. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an overcurrent detection and protection circuit provided in one embodiment of this specification; Figure 2a This is a schematic diagram of an overcurrent detection and protection circuit in Rdson mode according to one embodiment of this specification; Figure 2b This is a schematic diagram of the Rsense mode of an overcurrent detection and protection circuit provided in one embodiment of this specification; Figure 3a This is a schematic diagram of a first detection scheme for an overcurrent detection and protection circuit provided in one embodiment of this specification; Figure 3b This is a schematic diagram of a second detection scheme for an overcurrent detection and protection circuit provided in one embodiment of this specification; Figure 4 This is a schematic diagram of a current scheme for an overcurrent detection and protection circuit provided in one embodiment of this specification; Figure 5 This is a timing diagram of the overcurrent protection operation of an overcurrent detection and protection circuit provided in one embodiment of this specification. Detailed Implementation

[0017] Many specific details are set forth in the following description to provide a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this specification. Therefore, this specification is not limited to the specific implementations disclosed below.

[0018] The terminology used in one or more embodiments of this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this specification. The singular forms “a” and “the” as used in one or more embodiments of this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0019] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this specification, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this specification, and similarly, second may also be referred to as first. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0020] This specification provides an overcurrent detection and protection circuit, which will be described in detail in the following embodiments.

[0021] See Figure 1 , Figure 1 This diagram illustrates a system schematic of an overcurrent detection and protection circuit according to an embodiment of this specification. Specifically, it includes a chip with a current limiting pin. The current limiting pin is configured to support a first mode and a second mode. The first mode is an Rdson mode implemented by connecting a resistor to the SW pin of the chip, and the second mode is an Rsense mode implemented by connecting a resistor to the source of the low-side switch of the chip. A detection circuit is internally located within the chip, and its input is connected to the current limiting pin. The detection circuit is configured to acquire a voltage signal from the current limiting pin when the high-side switch of the chip is turned on. The detection circuit also includes a comparison and determination module configured to... When the voltage signal of the current limiting pin is high, the current mode is determined to be the first mode; when the voltage signal of the current limiting pin is low, the current mode is determined to be the second mode. The detection circuit also includes a current source output terminal, which is connected to the current limiting pin. The current source output terminal is configured to output the corresponding current from the current limiting pin according to the determination result, where the positive temperature coefficient current is output for the first mode and the zero temperature coefficient current is output for the second mode. The detection circuit also includes an overcurrent trigger module, the input terminal of which is connected to the current limiting pin. The overcurrent trigger module is configured to generate an overcurrent protection action based on whether the voltage of the current limiting pin crosses zero before the low-side switching transistor of the chip is turned off.

[0022] The current limiting pin refers to a dedicated pin on the chip used for overcurrent protection detection. Different overcurrent detection modes are adapted by connecting different external resistor networks. The first mode (Rdson mode) uses the on-resistance of the power MOSFET (low-side switch) as the current sensing element, implemented by connecting an external resistor to the SW pin. The second mode (Rsense mode) uses an external independent sampling resistor as the current sensing element, implemented by connecting a resistor in series with the source of the low-side switch. The detection circuit refers to the internal circuit unit of the chip that processes the current limiting pin voltage signal and identifies the mode. The comparison and determination module refers to the circuit that compares the current limiting pin voltage with a reference voltage and outputs the mode determination result. A positive temperature coefficient current refers to a current source output whose current value increases with increasing temperature. A zero temperature coefficient current refers to a current source output whose current value remains essentially unchanged with temperature. The overcurrent trigger module refers to the circuit that determines whether an overcurrent has occurred and generates a protection action based on whether the current limiting pin voltage crosses zero.

[0023] The present invention will be further described below through a detailed embodiment: In the aforementioned overcurrent detection and protection circuit, a step-down DC-DC power management chip is used as an example. The chip's current-limiting pin is brought out externally. When the user wants to use Rdson mode, a resistor is connected between the chip's SW pin and the current-limiting pin; when the user wants to use Rsense mode, a resistor is connected between the source of the chip's low-side switching transistor and the current-limiting pin. After the chip is powered on, the internal detection circuit samples the voltage of the current-limiting pin at the moment the high-side switch is turned on in each switching cycle. The comparison and determination module in the detection circuit has a built-in reference voltage, such as the chip's internal low-voltage supply voltage of 5V. If the sampled voltage of the current-limiting pin is higher than 5V, the comparison and determination module outputs a first-mode valid signal; if the sampled voltage is close to 0V, it outputs a second-mode valid signal. This determination result is transmitted to the current source output terminal. The current source output terminal includes two selectable current sources: one outputs a positive temperature coefficient current, and the other outputs a zero temperature coefficient current. According to the determination result, the corresponding current source is selected and connected to the current-limiting pin to output current. Meanwhile, before the low-side switch is about to turn off in each switching cycle (i.e., at the trough of the inductor current), the overcurrent trigger module detects whether the voltage at the current limit pin changes from positive to negative. When the load current increases to the point that this voltage crosses zero, the overcurrent trigger module outputs an overcurrent protection trigger signal, and the chip immediately turns off the power transistor or enters hiccup protection mode.

[0024] The beneficial effects of this embodiment include at least the following: two overcurrent detection modes are supported simultaneously through a single current limiting pin, allowing users to flexibly choose according to power level and accuracy requirements, thus expanding the application range of the chip; the detection circuit automatically identifies the current mode and outputs the corresponding temperature characteristic current, ensuring the accuracy of the overcurrent protection threshold in different modes; the overcurrent trigger module detects the voltage crossing to zero at the trough, realizing cycle-by-cycle protection with fast response speed.

[0025] In one possible implementation, the detection circuit includes a first detection sub-circuit configured to detect only the voltage of the current-limiting pin. In the first detection sub-circuit: the current-limiting pin is connected to the source of a first high-voltage transistor; the gate of the first high-voltage transistor is connected to the internal low-voltage power supply of the chip; the drain of the first high-voltage transistor is connected to the input of a first inverter; the output of the first inverter is connected to the input of a delay unit; the output of the delay unit is connected to the clock terminal of a first flip-flop; the data input of the first flip-flop is connected to the internal low-voltage power supply; and the output of the first flip-flop outputs a mode-distinguishing signal. The first detection sub-circuit is configured such that: in a first mode, when the high-side switch is open, the voltage of the current-limiting pin is the same as the voltage of the SW pin and is higher than the voltage of the internal low-voltage power supply, and the output of the first flip-flop outputs a low-level signal; in a second mode, when the voltage of the current-limiting pin is low, the output of the first flip-flop outputs a high-level signal.

[0026] The first detection sub-circuit can refer to a circuit structure that distinguishes between two modes solely based on the voltage signal at the current-limiting pin, without involving the SW pin signal. The first high-voltage transistor can refer to a MOS transistor capable of withstanding high voltages (e.g., up to 100V), used to convert high-voltage signals into signals that can be processed by the chip's internal low-voltage circuitry. The internal low-voltage power supply terminal can refer to a stable voltage (e.g., 5V) generated internally by a low-dropout linear regulator, used to power the internal logic circuitry. The first inverter can refer to a circuit that logically inverts the input signal. The delay unit can refer to a circuit used to generate a short time delay, such as a series inverter or RC delay circuit, used to filter out narrow pulse interference. The first flip-flop can refer to a rising-edge triggered D flip-flop. The mode distinction signal can refer to the final output logic level signal used to indicate the current detection mode.

[0027] The present invention will be further described below through a detailed embodiment, which is referred to in conjunction with the foregoing embodiments: In an overcurrent detection and protection circuit, one specific implementation of the first detection sub-circuit is as follows: The current limiting pin is directly connected to the source of the first high-voltage transistor. The gate of the first high-voltage transistor is connected to the internal 5V low-voltage power supply of the chip, so the first high-voltage transistor is in a normally conducting state, capable of stepping down the high voltage on the current limiting pin (e.g., 12V or higher from the SW pin) to a low voltage signal at the drain of the first high-voltage transistor that does not exceed 5V. The drain of the first high-voltage transistor is connected to the input of the first inverter. The output of the first inverter is connected to the input of the delay unit. The output of the delay unit is connected to the clock input of the first flip-flop. The data input of the first flip-flop is fixedly connected to the internal 5V low-voltage power supply.

[0028] When the chip operates in the first mode (Rdson mode), at the moment the high-side switch is turned on, the voltage at the current-limiting pin is the same as the voltage at the SW pin, which is close to the input voltage VIN (e.g., 12V). This high voltage is stepped down by the first high-voltage transistor, resulting in a high-level output from the drain of the first high-voltage transistor. After being inverted by the first inverter, it becomes a low-level output. This low-level output reaches the clock input of the first flip-flop after a delay. Since no rising edge occurs at the clock input (the input is low and unchanged), the first flip-flop does not trigger, and its output remains at its initial low level. When the chip operates in the second mode (Rsense mode), the voltage at the current-limiting pin is always low (close to 0V). The low-level output from the drain of the first high-voltage transistor is inverted by the first inverter, resulting in a high-level output. This high-level output reaches the clock input of the first flip-flop after a delay, generating a rising edge. This rising edge latches the high level at the data input to the output, so the output of the first flip-flop outputs a high level. Ultimately, the output signal of the first flip-flop serves as the mode distinction signal: a low level indicates the first mode, and a high level indicates the second mode. The purpose of the delay unit is to prevent false triggering caused by transient noise on the current limiting pin.

[0029] The beneficial effects of this embodiment include at least the following: the first detection sub-circuit has a simple structure, requires only a few components to achieve mode differentiation, occupies a small chip area, and has low cost; the first high-voltage tube is used to achieve level conversion, enabling the detection circuit to withstand high-voltage input; the addition of the delay unit improves the anti-interference capability.

[0030] In one possible implementation, the detection circuit includes a second detection sub-circuit configured to simultaneously detect the voltages of the current-limiting pin and the SW pin. In the second detection sub-circuit: the output of the system enable signal is connected to the input of a first logic gate; the output of the first logic gate is connected to the control terminals of a first and second switching transistor; the first switching transistor is connected between the current-limiting pin and the source of the second high-voltage transistor; the second switching transistor is connected between the SW pin and the source of a third high-voltage transistor; the drain of the second high-voltage transistor is connected to the first input of a first AND gate; the drain of the third high-voltage transistor is connected to the second input of the first AND gate; and the output of the first AND gate is connected to the input of a latch circuit. The latch circuit outputs a first control signal and a second control signal, respectively. The first and second control signals are connected to the control terminals of the first and second switching transistors to close the detection input. The second detection sub-circuit is configured as follows: in the initial state, the first control signal is high and the second control signal is low, and the first and second switching transistors are turned on. In the first mode, the voltage of the current limiting pin is the same as the voltage of the SW pin, which is high, and the first AND gate outputs a low level. In the second mode, the voltage of the SW pin is high and the voltage of the current limiting pin is low, and the first AND gate outputs a high level. The latch circuit locks the first and second control signals according to the output of the first AND gate.

[0031] The second detection sub-circuit can refer to a circuit structure that simultaneously detects both the current limit pin and the SW pin to distinguish modes, offering higher reliability. The system enable signal can refer to a flag signal generated internally by the chip; this signal goes high once the internal power supply, reference voltage, and reference current are established. The first logic gate can refer to a logic circuit used to control the opening or closing of the detection input channel. The first and second switching transistors can refer to transistor switches used to connect or disconnect the current limit pin, SW pin, and internal detection path. The second and third high-voltage transistors can refer to high-voltage resistant devices with the same function as the first high-voltage transistor. The first AND gate can refer to a two-input AND gate that outputs a high level only when both inputs are high. The latch circuit can refer to a sequential logic circuit used to lock the mode determination result and generate control signals.

[0032] The present invention will be further described below through a detailed embodiment, which is referred to in conjunction with the foregoing embodiments: In the overcurrent detection and protection circuit, the second detection sub-circuit provides a more robust pattern recognition scheme. After the system powers on, the internal reference module is established, and the system enable signal transitions from low to high. Initially, the first control signal output by the latch circuit is high, and the second control signal is low. The first control signal controls the first switching transistor, and the second control signal controls the second switching transistor through the first logic gate. Therefore, both the first and second switching transistors are turned on. The current limiting pin signal reaches the source of the second high-voltage transistor through the first switching transistor, and the SW pin signal reaches the source of the third high-voltage transistor through the second switching transistor. The gates of the second and third high-voltage transistors are also connected to the internal low-voltage power supply, serving as level conversion terminals. The drain of the second high-voltage transistor is connected to the first input of the first AND gate, and the drain of the third high-voltage transistor is connected to the second input of the first AND gate.

[0033] At each moment the high-side switch is turned on (when the synchronization signal LS_ON is high), the first AND gate performs a logical AND operation on the two input signals. In the first mode, both the current limit pin voltage and the SW pin voltage are high, so both inputs of the first AND gate are high, and the first AND gate outputs a high level. This high level is sent to the latch circuit. After judgment, the latch circuit pulls the first control signal low and the second control signal high, thereby turning off the first and second switches, completing mode detection and latching. Finally, the output G point potential of the latch circuit is low (indicating the first mode). In the second mode, the SW pin voltage is high, the current limit pin voltage is low, one input of the first AND gate is high and the other is low, so the first AND gate outputs a low level. The output G point potential of the latch circuit is high (indicating the second mode). To further avoid false triggering, the latch circuit also contains a counter. When the second mode is detected, the latch circuit does not lock immediately. Instead, it waits for the system to continuously count (e.g., count 2 to the power of 10 switching cycles) to confirm that the mode is stable before pulling the first control signal low and the second control signal high to complete the locking. This design ensures the reliability of pattern recognition in noisy environments.

[0034] The beneficial effects of this embodiment include at least the following: simultaneously detecting both the current limit pin and the SW pin eliminates interference that may occur during single-point detection; the latch circuit closes the input channel after completing the detection, reducing the power consumption of subsequent circuits and preventing mode mis-flipping; the counting delay introduced for the second mode further improves the anti-interference capability, enabling the circuit to correctly identify the mode even in a strong noise environment.

[0035] In one possible implementation, a first mode is configured to be applied when the power demand is greater than a preset threshold. The first mode uses the on-resistance of the power transistor for detection, and the on-resistance of the power transistor increases with increasing temperature. A second mode is configured to be applied when the power demand is less than the preset threshold. The second mode uses an external resistor for detection, and the temperature coefficient of the external resistor is stable.

[0036] In this context, "situations where power demand exceeds a preset threshold" refers to application scenarios with large load current and high output power, such as server motherboard power supply and industrial motor drive. The on-resistance (Rdson) of a power transistor refers to the drain-source resistance of the power MOSFET in its fully on state. This resistance has a positive temperature coefficient, increasing with temperature. External resistors refer to externally set sampling resistors, typically alloy or precision resistors, whose resistance value changes very little with temperature.

[0037] The present invention will be further described below through a detailed embodiment, which is referred to in conjunction with the foregoing embodiments: In practical applications, chip designers assign different target power ranges to the two modes based on the intended use case. The first mode (Rdson mode) is recommended for high-power applications with larger output currents (e.g., exceeding 10 amps) because the on-resistance of the power transistor is very small, resulting in lower conduction losses and higher efficiency. Although the on-resistance of the power transistor increases with chip temperature, this change is compensated for by a positive temperature coefficient current in the overcurrent protection design. Therefore, the first mode is suitable for high-power applications with high efficiency requirements and significant power transistor temperature rise. The second mode (Rsense mode) is recommended for low-to-medium power applications with smaller output currents (e.g., less than 5 amps). In this mode, the power consumption of the peripheral sampling resistor is an acceptable proportion of the total power consumption, and the peripheral resistor has a low temperature coefficient, providing more accurate current sensing. Therefore, users should prioritize the second mode in applications requiring precise current limiting or constant current control (such as LED drivers and battery charging). The chip's datasheet clearly indicates the applicable power range for both modes, allowing users to choose according to their actual needs.

[0038] The beneficial effects of this embodiment include at least the following: it distinguishes application scenarios according to power level, providing users with clear design guidance; the Rdson mode utilizes the power transistor's own resistance, with no additional loss, making it suitable for high-efficiency, high-power applications; the Rsense mode utilizes external resistors, has good temperature stability, and is suitable for small to medium power and precise current limiting applications.

[0039] In one possible implementation, the overcurrent protection action is configured to occur at the moment before the low-side switch turns off, which is the trough of the inductor current.

[0040] In a BUCK DC-DC converter, the moment before the low-side switch turns off refers to the instant before the low-side power MOSFET switches from the on state to the off state. The trough of the inductor current refers to the moment when the inductor current drops to its minimum value in each switching cycle, typically occurring at the end of the low-side switch's on-state, just before it turns off.

[0041] The present invention will be further described below through a detailed embodiment, which is referred to in conjunction with the foregoing embodiments: The overcurrent trigger module is designed to detect current at specific points in time within each switching cycle. Specifically, the chip's internal timing control circuitry generates a narrow pulse signal that is valid before the falling edge of the low-side switch drive signal (e.g., tens of nanoseconds in advance). This pulse signal serves as the sampling enable signal for the overcurrent trigger module. When this sampling enable signal is valid, the overcurrent trigger module reads the voltage value at the current limit pin. Since the inductor current is at its trough (i.e., at its minimum value) at this time, this current value reflects the baseline level of the load current. When the load experiences an overcurrent or the output is short-circuited, the overall average value of the inductor current rises, and the trough current also rises accordingly. By detecting whether the voltage at the current limit pin crosses zero at the trough moment, the system can promptly determine whether an overcurrent has occurred. Compared to detecting peak current, trough current detection is less affected by switching noise and is better compatible with slope compensation in current-mode control.

[0042] The beneficial effects of this embodiment include at least the following: detection is performed at the trough of the inductor current, avoiding voltage spike interference during switch switching, resulting in more stable detection results; trough current detection can reflect the average value of the inductor current, making it suitable as a basis for overcurrent protection judgment.

[0043] In one possible implementation, the overcurrent protection is triggered when the voltage of the current limiting pin crosses zero. The voltage of the current limiting pin is determined when the low-side switch is turned on by the following method: the product of the current flowing out of the current limiting pin and the external resistor connected to the current limiting pin, minus the product of the inductor valley current and the sensing resistor, where the inductor valley current is the average inductor current minus half of the peak-to-peak inductor current, and the sensing resistor is the on-resistance of the low-side switch in the first mode and the Rs resistor in the second mode.

[0044] Among these, "voltage zero crossing" refers to the state where the voltage of the current limiting pin changes from positive to negative. "External resistor" refers to the external resistor connected between the current limiting pin and ground or the SW pin. "Inductor valley current" refers to the instantaneous current value of the inductor at its trough. "Average inductor current" refers to the average inductor current over one switching cycle. "Peak-to-peak inductor current" refers to the peak-to-peak value of the inductor current ripple. "Sense resistor" refers to the resistive element used for current sampling, with different physical devices corresponding to different modes.

[0045] The present invention will be further described below through a detailed embodiment, which is referenced in conjunction with the foregoing embodiments: In the aforementioned overcurrent detection and protection circuit, when the low-side switch is turned on, the voltage at the current-limiting pin consists of two parts. The first part is the positive voltage generated by the internal current source flowing out of the current-limiting pin and through the external resistor. The second part is the negative voltage generated by the inductor valley current flowing through the detection resistor (because the current direction is from ground to the SW pin). These two voltages are superimposed to obtain the actual voltage at the current-limiting pin. The overcurrent trigger module compares this voltage with zero level (usually the chip's analog ground). When the load current is small, the first part of the voltage dominates, and the current-limiting pin voltage is positive. As the load current increases, the inductor valley current increases, and the amplitude of the second negative voltage also increases. When the inductor valley current increases to a certain extent, making the absolute value of the second negative voltage greater than the first positive voltage, the current-limiting pin voltage becomes negative. The overcurrent trigger module detects the voltage crossing zero (i.e., changing from positive to negative) and immediately triggers the overcurrent protection action. The relationship between the inductor's valley current, average inductor current, and peak-to-peak inductor current is as follows: the valley current equals the average current minus half of the peak-to-peak current. This relationship is determined by the triangular wave shape of the inductor current.

[0046] The beneficial effects of this embodiment include at least the following: overcurrent protection is achieved through zero-crossing voltage detection without the need for an additional analog-to-digital converter, resulting in a simple circuit; zero-crossing detection is insensitive to temperature drift because the detection threshold is fixed at zero; and this method can accurately reflect whether the inductor valley current exceeds the set threshold.

[0047] In one possible implementation, in the first mode, the voltage of the current limiting pin is: the product of the positive temperature coefficient current flowing out of the current limiting pin and the external resistance minus the product of the inductor valley current and the on-resistance of the low-side switch; the overcurrent trigger module is configured to trigger overcurrent protection when the voltage of the current limiting pin is negative.

[0048] Among these, positive temperature coefficient current refers to current whose value increases linearly with increasing temperature. External resistor refers to the resistor connected by the user between the current limiting pin and the SW pin (in Rdson mode). Inductor valley current refers to the inductor current at its trough. Low-side switch on-resistance refers to the drain-source resistance of the low-side switch when it is turned on, and this resistance has temperature characteristics. Overcurrent trigger module refers to the zero-crossing comparator and its subsequent logic.

[0049] The present invention will be further described below through a detailed embodiment, which is referenced in conjunction with the foregoing embodiments: Once the system is identified as being in the first mode (Rdson mode), the chip internally connects a positive temperature coefficient (PTC) current source to the current limiting pin. This PTC current is designed to increase with temperature, and the increase is precisely to compensate for the change in the low-side switch's on-resistance with temperature. In practical applications, the user connects a resistor (called Rlim) between the external SW pin and the current limiting pin. When the low-side switch is turned on, the inductor valley current flows from ground through the low-side switch's on-resistance to the SW pin, generating a voltage drop across the on-resistance (in the direction where the SW pin voltage is lower than ground). The current limiting pin is connected to the SW pin through the external resistor Rlim, while the internal PTC current flows out from the current limiting pin, through Rlim, and to the SW pin. Therefore, the voltage of the current limiting pin relative to ground is equal to the product of the PTC current and Rlim (positive voltage) minus the product of the inductor valley current and the on-resistance (negative voltage). The overcurrent trigger module continuously monitors the current limiting pin voltage. When the load current increases to the point that the inductor valley current exceeds a preset threshold, the aforementioned voltage crosses zero, and the overcurrent trigger module outputs a protection signal. Since the temperature changes in the positive temperature coefficient current and the on-resistance cancel each other out, the overcurrent protection threshold remains essentially constant at different temperatures.

[0050] The beneficial effects of this embodiment include at least the following: in the first mode, the positive temperature coefficient current compensates for the temperature drift of the power transistor's on-resistance, so that the overcurrent protection threshold remains constant over the entire temperature range; no external temperature sensor or complex temperature compensation circuit is required.

[0051] In one possible implementation, in the second mode, the voltage of the current limiting pin is: the product of the zero temperature coefficient current flowing out of the current limiting pin and the external resistance minus the product of the inductor valley current and the Rs resistance; the overcurrent trigger module is configured to trigger overcurrent protection when the voltage of the current limiting pin is negative.

[0052] Zero temperature coefficient current refers to a current source whose current value remains essentially unchanged with temperature. Rs resistor refers to the external sampling resistor that the user connects between the source of the low-side switching transistor and power ground. External resistor refers to the resistor connected between the current limiting pin and ground (in Rsense mode, the current limiting pin is usually pulled down to ground via a resistor).

[0053] The present invention will be further described below through a detailed embodiment, which is referred to in conjunction with the foregoing embodiments: Once the system is determined to be in the second mode (Rsense mode), the chip internally connects a zero-temperature coefficient current source to the current limiting pin. This zero-temperature coefficient current is generated by an internal bandgap reference source and hardly changes with temperature. The user connects an external resistor (called Rlim) between the current limiting pin and ground, and a sampling resistor (called Rsense) between the source of the low-side switch and power ground. When the low-side switch is turned on, the inductor valley current flows from ground through the Rs resistor to the source of the low-side switch, generating a voltage drop across the Rs resistor. The current limiting pin is connected to ground through Rlim, while the internal zero-temperature coefficient current flows out from the current limiting pin, through Rlim, and to ground. Therefore, the voltage at the current limiting pin is equal to the product of the zero-temperature coefficient current and Rlim (positive voltage) minus the product of the inductor valley current and Rs (negative voltage). The overcurrent trigger module detects whether this voltage crosses zero. Because the temperature coefficients of both the zero-temperature coefficient current and the Rs resistor are very small, the overcurrent protection threshold is very stable across the entire temperature range. When the load current exceeds the set value, the voltage at the current limiting pin becomes negative, triggering overcurrent protection. In this mode, the overcurrent protection accuracy is high, making it suitable for applications requiring precise current limiting.

[0054] The beneficial effects of this embodiment include at least the following: In the second mode, the zero temperature coefficient current, combined with the low temperature coefficient external Rs resistor, achieves a high-precision overcurrent protection threshold that is unaffected by temperature changes; it is suitable for occasions requiring precise current limiting or constant current output.

[0055] In one possible implementation, the detection circuit further includes a mode control logic module. The input of the mode control logic module is connected to the output of the comparison and determination module, and the output of the mode control logic module is connected to the control terminal of the controllable current source. The output of the controllable current source is connected to the current limiting pin. The mode control logic module is configured to control the controllable current source according to the determination result, so that a positive temperature coefficient current is output from the current limiting pin in the first mode, and a zero temperature coefficient current is output from the current limiting pin in the second mode.

[0056] The mode control logic module can refer to a combinational logic circuit that generates corresponding control signals based on the pattern recognition signal output by the comparison and determination module. The controllable current source can refer to a current source circuit that can select and output currents with different temperature characteristics based on the control signal; for example, it may include two current sources and a selection switch.

[0057] The present invention will be further described below through a detailed embodiment, which is referenced in conjunction with the foregoing embodiments: The detection circuit internally includes a mode control logic module. The input of this module receives a mode discrimination signal from the comparison and determination module (e.g., low level represents the first mode, high level represents the second mode). The output of this module is connected to the control terminal of a controllable current source. The controllable current source integrates two current sources: one generates a positive temperature coefficient current (e.g., through a resistor with a positive temperature coefficient or a PTAT current source), and the other generates a zero temperature coefficient current (e.g., through dividing a bandgap reference voltage by a resistor with a constant temperature coefficient). These two current sources share an output node, which is connected to a current limiting pin. Based on the input discrimination signal, the mode control logic module controls an analog switch: when the discrimination signal is for the first mode, the switch connects the positive temperature coefficient current source to the output node; when it is for the second mode, the switch connects the zero temperature coefficient current source to the output node. This control process is executed immediately after the chip is powered on and mode recognition is completed, and remains unchanged throughout the entire operation (unless powered on again). In this way, the current limiting pin always receives a current matching the current detection mode.

[0058] The beneficial effects of this embodiment include at least the following: the cooperation between the mode control logic module and the controllable current source enables automatic adaptation of the current source without the need for additional configuration by the user; the two current sources share the same pin, saving the number of chip pins; and automatic switching avoids overcurrent protection threshold deviation caused by incorrect current type.

[0059] In one possible implementation, the overcurrent protection action includes shutting down the power transistor inside the chip or putting the chip into a hiccup protection mode, which involves intermittently restarting the chip.

[0060] In this context, "shutting down the power transistors inside the chip" can refer to immediately turning off both the high-side and low-side switches, thereby cutting off the energy transfer path. "Hiccup protection mode" can refer to a fault recovery mechanism where, after an overcurrent occurs, the chip shuts down all power transistors and remains so for a relatively long period (e.g., a few milliseconds), then attempts to restart. If the overcurrent fault persists, it shuts down again and waits, repeating this cycle, resembling a hiccup.

[0061] The present invention will be further described below through a detailed embodiment, which is referenced in conjunction with the foregoing embodiments: When the overcurrent trigger module detects that the voltage at the current limiting pin has crossed zero, it generates an internal overcurrent flag signal. This flag signal is sent to the chip's main control logic circuit. The main control logic circuit selects a response mode based on the chip's configuration register (or a fixed design). The first response mode is immediate shutdown protection: the main control logic simultaneously invalidates the high-side drive signal and the low-side drive signal, causing both the high-side power transistor and the low-side switch transistor to be in the off state. At this time, the inductor current will slowly decrease through the body diode, the output capacitor will discharge, and the load will no longer receive energy. The chip maintains this state until it receives a restart command (e.g., the enable signal toggles again). The second response mode is hiccup protection mode: when the main control logic receives the overcurrent flag, it immediately shuts down the power transistor and starts a long timer (e.g., a timer duration of 10 milliseconds). During the timer period, the chip enters a low-power standby state. After the timer ends, the chip re-executes the soft-start process, gradually turning on the power transistor and checking whether the overcurrent still exists. If the overcurrent fault has been eliminated, the chip resumes normal operation; if the overcurrent still exists, it shuts down again and enters the next hiccup cycle. The advantage of hiccup protection mode is that it avoids heat accumulation in the power transistor under continuous overcurrent conditions, and the system can automatically recover when the fault is removed.

[0062] The beneficial effects of this embodiment include at least the following: it provides two overcurrent protection response modes, which users can choose according to application requirements; the immediate shutdown protection has a fast response speed, which is suitable for systems with poor short-circuit tolerance; the hiccup protection mode reduces average power consumption and thermal stress, and has self-recovery capability, which improves the ease of use and reliability of the system.

[0063] In one overall embodiment, the solution of this application is: to set a current limiting pin for the chip for overcurrent protection detection; and there are two detection methods, which gives users more choices compared to the previous single method, making the current chip more widely applicable. Specifically, these two detection methods are: Figure 2a The Rdson mode is achieved by connecting a resistor to the SW pin; and Figure 2b The Rsense mode is achieved by connecting a resistor to the source of the low-side switch. The detection circuits are different for the two modes. The detection principle is as follows: When the high-side switch is open, the voltage of the current limit pin is high (greater than the internal low-voltage power supply of 5V) in Rdson mode and low (close to 0V) in Rsense mode. The two detection schemes are: 1. Detect only the voltage of the current limiting pin; 2. Detect the voltage of both the current limiting pin and the SW pin simultaneously. The detection principle is the voltage signal of the current limiting pin Ilim when the high-side switch is turned on. Therefore, under normal circumstances, it can be directly achieved by only detecting the voltage of the current limiting pin. However, in circuit applications, in order to prevent interference from other signals, it is more reliable to detect both the current limiting pin and the SW pin at the same time. At the same time, the circuit design of the second scheme is more complex. A solution that only detects the voltage at the current-limiting pin: such as Figure 3a In the middle, the current limiting pin is the chip's peripheral PAD, corresponding to Figure 1 In Rdson mode, when the high side is on, the voltage of the current limiting pin in / 2 is the same as the voltage of the SW pin, close to the VIN voltage (greater than 7V). At this time, the voltage at point A is relatively high (Vdd) in the low-voltage system. I3 acts as a delay to prevent false triggering interference. The d input of the I7 flip-flop is usually high (Vdd), which is a one-time trigger action. As long as there is a high trigger edge of the clock, the trigger output q will be high. Under the above logic circuit, when the current limiting pin is relatively high, the potential at point B is low. In Rsense mode, since the current limiting pin is connected to the source terminal of the low-side switching transistor, it is impossible for the system to be high during operation. Therefore, the current limiting pin is usually low. Under the above logic circuit, the potential at point B is high. Through the above logic, the two modes are distinguished and the switching action is performed. The internal circuit further processes the signal. Among them, M1 is a high-voltage transistor, and the VIN power supply can be up to 100V. SW is a current-limiting pin voltage that is close to the VIN voltage when the voltage is high, up to 100V. M1 is a high-voltage device used for voltage reduction.

[0064] A solution that simultaneously detects the current limiting pin and the SW pin: For example... Figure 3bIn the diagram, enH is the system enable signal, initially low. Once the internal power supply, reference voltage, reference current, and other basic modules are established, the enable signal goes high. Therefore, after system startup, the initial state signals at points H and E are high, and at point F is low. At this time, switching transistors M4 and M6 are turned on, while M5 and M7 are turned off. Therefore, when the high-side switch is opened (LS_ON is the high-side switch synchronization signal), the Ilim and SW pin signals can be input into the internal circuit system, connecting M2 and M... Transistor 3, like transistor M1, is a high-voltage transistor used for withstand voltage. When the current limiting pin is high and LS_ON is high, the potential at point C is high. When the SW pin is high and LS_ON is high, the potential at point D is high. In Rdson mode, when the high side is open, the voltage at the current limiting pin and the voltage at the SW pin are both high; at this time, the potential at the circuit logic output point G is low. In Rsense mode, when the high side switch is open, the SW pin is high and the current limiting pin is low. Since I12 requires both inputs to be high for the output to be high, the circuit logic outputs a high potential at point G. Therefore, the G potential in the above circuit can already distinguish between two modes. Subsequent circuit logic requires mode locking to avoid interference and false triggering. The I17-I24 circuit logic outputs control signals E and F. Initially, based on the enH signal, E is high, transmitting the signal. In Rdson mode, the G output is low and H is low, locking the I17 logic, simultaneously controlling E to be low and F to be high, completing the detection mode and closing the detection input. In Rsense mode, the G output is high and H is high. In this case, the locking logic needs to count the high-side control switch. After 210 count cycles, the I20 input is low, the control logic E is low and F is high, completing the detection mode. The above circuit is more complex than the former, with more detection items, making it more stable and reliable in actual operation. Both can achieve the same circuit control results.

[0065] The difference between the two modes in application is as follows: In Rsense detection mode, a detection resistor Rs is added. Rs is an external resistor with a relatively stable temperature coefficient. However, when the current is large, the power consumption across the resistor is large, resulting in excessive power waste. Therefore, it is more suitable for applications with lower power requirements. In Rdson detection mode, the Rdson of the power transistor is detected. Since the Rdson of the power transistor itself is greatly affected by temperature, the higher the temperature, the smaller the Rdson. Therefore, it is more suitable for applications with higher power requirements. In response to the above application differences, after completing Figure 2bAfter the detection circuit is completed, the chip needs to design corresponding current schemes for the two modes. In Rsense mode, a zero-temperature-drift current Ilim needs to flow out from the current-limiting pin. In Rdson mode, a current Ilim with a positive temperature-drift coefficient needs to flow out from the current-limiting pin. Figure 2b The logic output is controlled and implemented; the specific implementation is as follows: Figure 4 As shown.

[0066] Furthermore, the overcurrent protection action occurs before the low-side switch is turned off, i.e., at the trough of the inductor current; specifically as follows: Figure 5 As shown, the above detection occurs at the moment circled in red, and the detection metric is whether the current limit pin voltage crosses zero. The specific calculation formula is as follows: In Rdson mode, when the low side is on, the current limit pin voltage is: ; Where Ilim is the positive temperature coefficient current flowing out from the LIM pin, Rlim is the current limiting pin resistance, Rdson is the internal resistance of the low-side switch, I0 is the average inductor current, and ΔIL is the peak-to-peak inductor current. In the above formula, the output value is positive under normal conditions and will not trigger OCP protection. When the inductor current is larger, I0 will be larger and the value of the above formula will be negative. At this time, OCP protection is triggered, and the system will take action to protect the entire system after judgment. In Rsense mode, when the low side is on, the current limiting pin voltage is: ; Similar to Rdson mode analysis, when the current is too large, the above formula becomes negative, triggering OCP to perform protection action.

[0067] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments in this specification are not limited to the described order of actions, because according to the embodiments in this specification, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments in this specification.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0069] The preferred embodiments disclosed above are merely illustrative of this specification. Optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments described herein. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the embodiments, thereby enabling those skilled in the art to better understand and utilize this specification. This specification is limited only by the claims and their full scope and equivalents.

Claims

1. An overcurrent detection and protection circuit, characterized in that, include: The chip has a current limiting pin. The current limiting pin is configured to support a first mode and a second mode, the first mode being the Rdson mode implemented by connecting a resistor to the SW pin of the chip, and the second mode being the Rsense mode implemented by connecting a resistor to the source of the low-side switch of the chip. The chip has an internal detection circuit, the input of which is connected to the current limiting pin. The detection circuit is configured to acquire the voltage signal of the current limiting pin when the high-side switch of the chip is turned on. The detection circuit further includes a comparison and determination module, which is configured to determine that the current mode is the first mode when the voltage signal of the current limiting pin is high, and to determine that the current mode is the second mode when the voltage signal of the current limiting pin is low. The detection circuit also includes a current source output terminal, which is connected to the current limiting pin. The current source output terminal is configured to output a corresponding current from the current limiting pin according to the determination result, wherein the current with a positive temperature coefficient is output when corresponding to the first mode, and the current with a zero temperature coefficient is output when corresponding to the second mode. The detection circuit also includes an overcurrent trigger module. The input terminal of the overcurrent trigger module is connected to the current limiting pin. The overcurrent trigger module is configured to generate an overcurrent protection action based on whether the voltage of the current limiting pin crosses zero before the low-side switch of the chip is turned off.

2. The overcurrent detection and protection circuit according to claim 1, characterized in that, The detection circuit includes a first detection sub-circuit, which is configured to detect only the voltage of the current limiting pin. In the first detection sub-circuit: the current limiting pin is connected to the source of a first high-voltage transistor, the gate of the first high-voltage transistor is connected to the internal low-voltage power supply terminal of the chip, the drain of the first high-voltage transistor is connected to the input terminal of a first inverter, the output terminal of the first inverter is connected to the input terminal of a delay unit, the output terminal of the delay unit is connected to the clock terminal of a first flip-flop, the data input terminal of the first flip-flop is connected to the internal low-voltage power supply terminal, and the output terminal of the first flip-flop outputs a mode differentiation signal. The first detection sub-circuit is configured such that: in the first mode, when the high-side switch is turned on, the voltage of the current limiting pin is the same as the voltage of the SW pin and is higher than the voltage of the internal low-voltage power supply terminal, and the output terminal of the first trigger outputs a low-level signal; in the second mode, the voltage of the current limiting pin is low, and the output terminal of the first trigger outputs a high-level signal.

3. The overcurrent detection and protection circuit according to claim 1, characterized in that, The detection circuit includes a second detection sub-circuit, which is configured to simultaneously detect the voltage of the current limiting pin and the SW pin. In the second detection sub-circuit: the output of the system enable signal is connected to the input of a first logic gate; the output of the first logic gate is connected to the control terminals of a first switch and a second switch; the first switch is connected between the current limiting pin and the source of a second high-voltage transistor; the second switch is connected between the SW pin and the source of a third high-voltage transistor; the drain of the second high-voltage transistor is connected to the first input of a first AND gate; the drain of the third high-voltage transistor is connected to the second input of the first AND gate; the output of the first AND gate is connected to the input of a latch circuit; the output of the latch circuit outputs a first control signal and a second control signal; the first control signal and the second control signal are connected to the control terminals of the first switch and the second switch, respectively, to disable the detection input. The second detection sub-circuit is configured such that: in the initial state, the first control signal is high and the second control signal is low, and the first and second switching transistors are turned on; in the first mode, the voltage of the current limiting pin is the same as the voltage of the SW pin, which is high, and the first AND gate outputs a low level; in the second mode, the voltage of the SW pin is high and the voltage of the current limiting pin is low, and the first AND gate outputs a high level; the latching circuit locks the first control signal and the second control signal according to the output of the first AND gate.

4. The overcurrent detection and protection circuit according to claim 1, characterized in that, The first mode is configured to be applied when the power demand is greater than a preset threshold. The first mode uses the on-resistance of the power transistor for detection, and the on-resistance of the power transistor increases with increasing temperature. The second mode is configured to be applied when the power demand is less than the preset threshold. The second mode uses an external resistor for detection, and the temperature coefficient of the external resistor is stable.

5. The overcurrent detection and protection circuit according to claim 1, characterized in that, The overcurrent protection action is configured to occur at a time before the low-side switch is turned off, which is the trough of the inductor current.

6. The overcurrent detection and protection circuit according to claim 5, characterized in that, The overcurrent protection action is triggered when the voltage of the current limiting pin crosses zero. The voltage of the current limiting pin is determined when the low-side switch is turned on by the following method: the product of the current flowing out of the current limiting pin and the external resistor connected to the current limiting pin, minus the product of the inductor valley current and the sensing resistor, wherein the inductor valley current is the average inductor current minus half of the peak-to-peak inductor current, and the sensing resistor is the on-resistance of the low-side switch in the first mode and the Rs resistor in the second mode.

7. The overcurrent detection and protection circuit according to claim 6, characterized in that, In the first mode, the voltage of the current limiting pin is: the product of the positive temperature coefficient current flowing out of the current limiting pin and the external resistor minus the product of the inductor valley current and the on-resistance of the low-side switch; the overcurrent trigger module is configured to trigger the overcurrent protection action when the voltage of the current limiting pin is negative.

8. The overcurrent detection and protection circuit according to claim 6, characterized in that, In the second mode, the voltage of the current limiting pin is: the product of the zero temperature coefficient current flowing out of the current limiting pin and the external resistor minus the product of the inductor valley current and the Rs resistor; the overcurrent trigger module is configured to trigger the overcurrent protection action when the voltage of the current limiting pin is negative.

9. The overcurrent detection and protection circuit according to claim 1, characterized in that, The detection circuit further includes a mode control logic module. The input of the mode control logic module is connected to the output of the comparison and determination module, and the output of the mode control logic module is connected to the control terminal of the controllable current source. The output of the controllable current source is connected to the current limiting pin. The mode control logic module is configured to control the controllable current source according to the determination result, so that in the first mode, the current with the positive temperature coefficient is output from the current limiting pin, and in the second mode, the current with the zero temperature coefficient is output from the current limiting pin.

10. The overcurrent detection and protection circuit according to claim 1, characterized in that, The overcurrent protection action includes shutting down the power transistor inside the chip or putting the chip into a hiccup protection mode, wherein the hiccup protection mode is to intermittently restart the chip.

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