Method, device, controller, storage medium and photovoltaic system for preventing damage to a boost circuit

Abstract

The application provides a method, device, controller, storage medium and photovoltaic system for preventing damage of a boost circuit. The method comprises: when the boost circuit meets a preset stable condition, starting to acquire an integral value of a voltage control loop of a flying capacitor; thereby firstly filtering transient integral fluctuation caused by load transient and the like, and avoiding false detection. If the integral value exceeds a preset integral threshold value within a first preset time length, blocking a driving signal of a switching bridge arm unit, cutting off a capacitor hedge short circuit loop formed by switching tube conduction, and preventing damage of a third diode from the root. Compared with a traditional after-occurrence protection which acts after a fault occurs, the present scheme can block a destructive short circuit in advance, and effectively reduces the hardware damage probability of a photovoltaic boost device.

Description

Technical Field

[0001] This invention relates to the field of boost circuit technology, and in particular to a method, apparatus, controller, storage medium, and photovoltaic system for preventing damage to boost circuits. Background Technology

[0002] In fields such as new energy photovoltaic power generation, electrochemical energy storage, industrial DC power supply, and new energy vehicle on-board power supplies, DC-DC boost converter circuits are the core power conversion units for achieving voltage level matching, efficient power transmission, and regulation. Their operational stability and reliability directly determine the safe service capability of the entire power electronic system. Among them, the flying capacitor type multilevel DC-DC boost circuit has been widely used in high-voltage, high-power boost scenarios due to its advantages such as low voltage stress of series-connected switching transistors, high conversion efficiency, and excellent electromagnetic interference characteristics.

[0003] However, the inherent risk of midpoint clamping branch failure in flying capacitor-type multilevel DC boost circuits remains a bottleneck restricting their reliability improvement. In actual operation, if the power switch of the series-connected switch arm experiences uncontrollable failures such as gate breakdown or drive circuit abnormalities, it will lead to complete loss of control of the midpoint potential of the bridge arm, which in turn will cause diode overcurrent and overheating breakdown failure, ultimately resulting in a serious accident such as DC bus short circuit and complete machine failure. Existing protection schemes for this topology are mostly post-fault remedial protections, which only trigger drive pulse blocking and shutdown protection after the circuit has shown obvious fault characteristics such as short circuit high current and device junction temperature exceeding the standard, and cannot effectively avoid the risk of device failure. Summary of the Invention

[0004] This invention provides a method, apparatus, controller, storage medium, and photovoltaic system for preventing damage to boost circuits, thereby addressing the problems of poor protection and high risk of failure in existing flyaway capacitor-type boost circuits.

[0005] In a first aspect, embodiments of the present invention provide a method for preventing damage to a boost circuit, the boost circuit comprising: a switching bridge arm unit, a flying capacitor, and a clamping unit; The flying capacitor is connected in parallel between the midpoint of the bridge arm of the switching bridge unit and the node of the switching transistor. The clamping unit is used to clamp the midpoint of the bridge arm to the midpoint of the output voltage divider; The method includes: When the boost circuit meets the preset stability conditions, the integral value of the voltage control loop of the flying capacitor is obtained; If the integral value exceeds a preset integral threshold within a first preset time period, the drive signal of the switch arm unit is blocked.

[0006] Secondly, embodiments of the present invention provide a device for preventing damage to a boost circuit, the boost circuit comprising: a switching bridge arm unit, a flying capacitor, and a clamping unit; The flying capacitor is connected in parallel between the midpoint of the bridge arm of the switching bridge unit and the node of the switching transistor. The clamping unit is used to clamp the midpoint of the bridge arm to the midpoint of the output voltage divider; The device includes: An integral acquisition module is used to acquire the integral value of the voltage control loop of the flying capacitor when the boost circuit meets the preset stability conditions. The drive blocking module is used to block the drive signal of the switch bridge arm unit if the integral value exceeds a preset integral threshold within a first preset time period.

[0007] Thirdly, embodiments of the present invention provide a controller, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method for preventing damage to the boost circuit as described in any possible implementation of the first aspect above.

[0008] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method for preventing damage to the boost circuit as described in any possible implementation of the first aspect above.

[0009] Fifthly, embodiments of the present invention provide a photovoltaic system, which includes a boost circuit and a controller as described in the third aspect above.

[0010] This invention provides a method, apparatus, controller, storage medium, and photovoltaic system for preventing damage to boost circuits. The method only begins acquiring the integral value of the voltage control loop of the flying capacitor when the boost circuit meets preset stability conditions; thus, it first filters out instantaneous integral fluctuations caused by load transients, avoiding false detections. If the integral value exceeds a preset integral threshold within a first preset time period, the drive signal of the switching bridge unit is blocked, cutting off the capacitor-counteracting short-circuit loop formed by the switching transistor's conduction, preventing damage to the third diode at its source. Furthermore, this embodiment reuses the existing voltage PI control loop, eliminating the need for additional current and temperature sampling hardware, resulting in low hardware modification costs. Compared to traditional reactive protection that only activates after a fault occurs, this solution can proactively block destructive short circuits, effectively reducing the probability of hardware damage to photovoltaic boost equipment. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the boost circuit provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the implementation of the method for preventing damage to the boost circuit provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of the device for preventing damage to the boost circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the controller provided in an embodiment of the present invention. Detailed Implementation

[0013] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0014] To make the objectives, technical solutions, and advantages of the present invention clearer, specific embodiments will be described below in conjunction with the accompanying drawings.

[0015] Figure 1 A schematic diagram of the boost circuit provided in an embodiment of the present invention is shown below. Figure 1 As shown, the boost circuit includes: a switching bridge arm unit, a flying capacitor, and a clamping unit; the flying capacitor is connected in parallel between the midpoint of the bridge arm of the switching bridge arm unit and the node of the switching transistor, and the clamping unit is used to clamp the midpoint of the bridge arm to the midpoint of the output voltage divider.

[0016] In this embodiment, the flying capacitor C1 is connected across the layered nodes of the switch bridge arm to form a floating voltage balancing branch. The clamping unit connects the flying capacitor and the midpoint of the output voltage divider to evenly distribute the output bus voltage.

[0017] Specifically, the switching transistor node can be either the first or second end of the switching bridge arm unit, with the first end connected to the positive input terminal of the boost circuit and the second end connected to the negative input terminal of the boost circuit. (Reference) Figure 1The boost circuit includes: a boost inductor L, a switching bridge arm unit, a flying capacitor C1, a clamping unit, and an output energy storage unit; the switching bridge arm unit is connected in parallel across the input side of the boost circuit, the boost inductor L is connected in series between the positive terminal of the input side and the first end of the switching bridge arm unit, the output energy storage unit is connected in parallel across the two ends of the switching bridge arm unit, and the output energy storage unit includes multiple bus capacitors; the flying capacitor C1 is connected in parallel between the first end of the switching bridge arm unit and the midpoint of the bridge arm, and the midpoint of the bridge arm is connected to the midpoint of the bus capacitor unit through the clamping unit, and the midpoint of the bus capacitor unit is the connection point between two adjacent bus capacitors.

[0018] refer to Figure 1 The switching bridge arm unit includes a first switching transistor Q1 and a second switching transistor Q2; the output energy storage unit includes a first bus capacitor C2 and a second bus capacitor C3; the clamping unit includes a third diode D3; the boost circuit also includes an input capacitor Cpv, a first diode D1, a second diode D2, a fourth diode D4, a first resistor R1, and an output resistor R. L .

[0019] Specifically, the first terminal of the first switch Q1 is connected to the positive terminal of the input side, the second terminal of the first switch Q1 is connected to the first terminal of the second switch Q2, the second terminal of the second switch Q2 is connected to the negative terminal of the input side, and the input capacitor Cpv is also connected between the two terminals of the input side. The first terminal of the first switch Q1 is also connected to the positive terminal of the first diode D1, and the negative terminal of the first diode D1 is connected to the first terminal of the flying capacitor C1, the positive terminal of the second diode D2, and the negative terminal of the fourth diode D4. The negative terminal of the second diode D2 is connected to the first terminal of the first bus capacitor C2, the second terminal of the first bus capacitor C2 is connected to the first terminal of the second bus capacitor C3, the negative terminal of the third diode D3, and the first terminal of the first resistor, and the second terminal of the first resistor is connected to the positive terminal of the fourth diode D4. The second terminal of the flying capacitor C1 is connected to the midpoint of the switch bridge arm unit and the positive terminal of the third diode D3. The second terminal of the second bus capacitor C3 is connected to the output resistor R. L The second end of the transistor is connected to the second end of the second switch Q2.

[0020] The boost circuit adapted to the embodiments of the present invention is not limited to a single topology. It can be a flying capacitor type three-level boost boost circuit or other boost circuits with two core components: a flying capacitor and a clamping unit. As long as the circuit configuration includes a flying capacitor and a clamping unit, and the clamping unit is used to achieve the clamping of the bus voltage divider midpoint potential, it can be adapted to the protection logic of the present invention. This embodiment only uses a flying capacitor type three-level boost boost circuit as a typical example for explanation.

[0021] Taking the flying capacitor type three-level boost circuit as an example, during normal operation, Q1 and Q2 are turned on alternately with a 180° phase difference, and the power boost conversion is completed through three working modes. Under steady state, the voltage of the flying capacitor C1, the first bus capacitor C2, and the second bus capacitor C3 are all stable at 1 / 2 of the output bus voltage, and the voltage stress of all switching devices is only half of the total output voltage.

[0022] Specifically, when both transistors are on simultaneously, the boost inductor L stores energy, all diodes are off, and bus capacitors C2 and C3 supply power to the load; when the first switch Q1 is on and the second switch Q2 is off, the inductor L releases energy, the third diode D3 is forward-biased, and the inductor L and the flying capacitor C1 together charge the second bus capacitor C3, while the flying capacitor C1 releases its charge; when the first switch Q1 is off and the second switch Q2 is on, the freewheeling current in the inductor L causes the first diode D1 to conduct, charging the first bus capacitor C2 through D2 and replenishing the charge of the flying capacitor C1.

[0023] During steady-state operation, the flying capacitor's charge and discharge are balanced within one switching cycle, resulting in uniform voltage distribution on the bus and stable boost output. When the second switch Q2 fails and becomes uncontrollable, it directly disrupts the normal charge and discharge balance of the flying capacitor C1, causing its actual voltage to continuously deviate from the rated reference value. The error in the voltage closed-loop regulation cannot be offset, causing the integral value to show a unidirectional and continuous accumulation trend. This abnormal integral characteristic can indicate in advance that Q2 has failed and become uncontrollable, thus predicting that the midpoint potential shift of the bridge arm will cause the midpoint clamping diode D3 to conduct for a long time due to overcurrent, overheat and break down, and eventually cause a short circuit on the bus and a machine explosion.

[0024] To address the aforementioned technical problems, this embodiment provides a method for preventing damage to the boost circuit, see [link to relevant documentation]. Figure 2 The flowchart illustrating the implementation of the method for preventing damage to the boost circuit provided in the embodiment of the present invention is described in detail below: S101: When the boost circuit meets the preset stability conditions, obtain the integral value of the voltage control loop of the flying capacitor.

[0025] In this embodiment, after the second switch Q2 experiences a continuous conduction anomaly, it will first disrupt the periodic charge-discharge balance of the flying capacitor, causing a continuous unidirectional deviation in the flying capacitor voltage. This deviation is extremely small in the early stages of the fault, making it difficult for direct voltage sampling to distinguish between normal ripple and abnormal offset, thus failing to provide early warning. The integral value of the flying capacitor voltage control loop naturally possesses error accumulation and amplification characteristics. Under steady-state conditions, when the flying capacitor's charge-discharge balance is achieved, the voltage deviation approaches zero, and the integral value fluctuates only slightly. Once Q2 becomes uncontrolled, causing a continuous voltage deviation, the integral value will continuously spike unidirectionally over time. This abnormal characteristic is a precursor signal that the clamping diode D3 is under excessive electrical stress and is about to break down. It appears much earlier than the significant fault characteristics such as large short-circuit current and device temperature rise that occur after D3 is completely short-circuited. Therefore, this embodiment can predict whether the clamping diode is about to fail based on the change in the integral value of the flying capacitor, using the integral value as the core basis for fault determination, triggering protective actions before a destructive failure occurs.

[0026] Specifically, during transient processes such as load step changes, the flyover capacitor in the boost circuit has not yet entered a periodic equilibrium state during charging and discharging. The actual value of the flyover capacitor voltage deviates significantly from the given value. Therefore, the integral value of the control loop of the flyover capacitor voltage will naturally accumulate in one direction and fluctuate greatly. This offset is a normal phenomenon of circuit transients and cannot be used as a predictive feature of clamping unit failure. If the integral value is directly collected and fault judgment is performed without steady-state condition determination, it is very easy to misidentify the normal transient integral offset as a fault, falsely triggering drive blocking, resulting in the circuit failing to start normally or abnormal dynamic response.

[0027] This embodiment filters out unsteady-state scenarios such as load transients by pre-setting stable conditions. It ensures that fault detection is performed only when the charge of the flying capacitor is balanced and the integral value is in a steady state with normal small fluctuations. This eliminates the cause of false detection from the source and ensures that the protection logic has fault identification capabilities without interfering with the normal operation of the circuit.

[0028] S102: If the integral value exceeds a preset integral threshold within a first preset time period, then the drive signal of the switch arm unit is blocked.

[0029] In this embodiment, when the boost circuit is in steady-state operation, if the second switch Q2 experiences a runaway conduction failure, it will continuously charge the flying capacitor C1, causing the voltage of the flying capacitor C1 to rise continuously in one direction. The integral value of its voltage control loop will also accumulate continuously. The controller monitors the integral value of the voltage control loop. If the integral value is detected to exceed the preset integral threshold for a first preset time period, it indicates that the flying capacitor C1 has deviated from the steady-state operating point for a long time, and the clamping diode D3 is under continuous and large electrical stress impact and is about to break down. At this time, the controller blocks the drive signal of the switch bridge arm unit, which can cut off the fault path before D3 is completely short-circuited and forms a capacitor counter-current circuit, thus achieving fault prevention.

[0030] For example, the preset integration threshold can be 90% to 95% of the maximum integration value.

[0031] In one possible implementation, the specific implementation process of S102 above can also be as follows: If the integral value exceeds the second integral threshold within a first preset time period, and the integral value continues to increase within the first preset time period, then the drive signal of the switch arm unit is blocked. The second integral threshold is less than the preset integral threshold.

[0032] As can be seen from the above embodiments, this embodiment only begins to acquire the integral value of the voltage control loop of the flying capacitor when the boost circuit meets the preset stability conditions; thus, it first filters out instantaneous integral fluctuations caused by power-on disturbances, load transients, etc., to avoid false detection. If the integral value exceeds the preset integral threshold within a first preset time period, the drive signal of the switching bridge arm unit is blocked, and the capacitor offset short-circuit loop formed by the switching transistor is cut off, preventing damage to the third diode from the root. In addition, this embodiment reuses the original voltage PI control loop, eliminating the need to add current and temperature sampling hardware, resulting in low hardware modification costs; compared with traditional post-fault protection that only operates after a fault occurs, this embodiment can prevent destructive short circuits in advance, effectively reducing the probability of hardware damage to the photovoltaic boost equipment.

[0033] In one possible implementation, the preset stability condition is that the boost circuit is within a second preset time period after power-on.

[0034] The power-on phase is a high-risk period where the second switching transistor Q2 fails to conduct uncontrollably and the third diode D3 fails due to an impact. At the moment of power-on, there is a voltage stress step. If Q2 has a hidden gate defect or fails to conduct uncontrollably due to driving disturbances, the continuously conducting Q2 will cause the flying capacitor C1 circuit to continuously apply voltage and current impacts to the clamping diode D3, accelerating D3's aging and breakdown. Once D3 fails due to a short circuit, the flying capacitor C1 and the lower half-bus capacitor C3 will form an unbuffered discharge circuit, instantly generating a huge inrush current that could cause the entire unit to explode. Furthermore, traditional overcurrent protection has not yet reached a stable operating state during the power-on phase, resulting in a significant protection blind spot. Therefore, positioning the fault detection window during the power-on phase can accurately cover the high-risk scenario of D3 failure while avoiding integral offset interference caused by load fluctuations during steady-state normal operation, effectively reducing the probability of false triggering.

[0035] To further ensure the accuracy of the test results, the testing window needs to avoid the strong oscillation phase at the initial power-on stage. Integral testing is only performed during the smooth ramp-up period after soft-start. Therefore, the preset stability condition is limited to: after the power-on command of the boost circuit is issued for a third preset duration, and within the second preset duration after power-on. The second preset duration can be set to 3-7 minutes, and the third preset duration can be set to no more than 30 seconds. This limitation eliminates interference from the violent voltage and current oscillations at the initial power-on stage. During the smooth ramp-up phase after soft-start, the soft-start setpoint rises uniformly, the flyover capacitor voltage rises controllably according to the expected trajectory, the charging and discharging process enters a predictable and regular state, and the integral change has a clear normal boundary. This allows for accurate prediction of the failure risk of the third diode based on the integral value of the flyover capacitor voltage control loop.

[0036] This embodiment limits the fault detection window to a second preset time after power-on, corresponding to the smooth ramp-up phase of the circuit's soft start. During this time, the circuit's charging and discharging process is controllable and predictable. If the second switch Q2 has a gate defect or is uncontrolled to conduct due to startup disturbance, it will continuously charge the flying capacitor C1, breaking the periodic charge balance of the flying capacitor from the initial startup stage, causing the integral value of the voltage control loop to exhibit a continuous unidirectional accumulation characteristic. The occurrence of this abnormal signal is much earlier than the large current of the capacitor offset short circuit formed after D3 is completely broken down, corresponding to the critical state where the clamping diode D3 is continuously subjected to excessive electrical stress and is about to break down and fail. Based on this, the drive blockade is triggered, which can cut off the fault path before D3 completely fails and forms a destructive circuit. This solution not only accurately covers the high-risk startup period when Q2 uncontrolled failure induces D3 failure, achieving fault pre-blocking, but also avoids the risk of misjudgment and control resource occupation caused by steady-state full-time detection. It makes up for the protection shortcomings in the startup stage with extremely simple timing judgment logic, effectively reducing the risk of device damage at the moment of startup.

[0037] In one possible implementation, prior to S102, the method provided in this embodiment further includes: Obtain the current flowing through the boost inductor L in the boost circuit and use it as the input current; The first preset duration is determined based on the input current, and the input current and the first preset duration are negatively correlated.

[0038] In this embodiment, the input current is the current flowing through the boost inductor L, which represents the current load power level of the boost circuit. The larger the current, the higher the output power.

[0039] This embodiment adds a step before the fault determination step, where the first preset time is adaptively adjusted based on the sampled input current. This dynamically matches the fault determination time threshold based on the current load level of the circuit. Under heavy load, faults develop rapidly and are highly destructive; shortening the determination time can accelerate the protection response. Under light load, faults develop slowly but have a high proportion of interference noise; extending the determination time can improve anti-interference capability, achieving a dynamic balance between protection sensitivity and anti-interference.

[0040] Specifically, the input current is divided into multiple continuous current intervals, each corresponding to a fixed first preset duration. The higher the amplitude of the current interval, the shorter the corresponding first preset duration. In practical applications, the controller samples the input current in real time, determines the current interval to which the input current belongs, and uses the duration parameter of the corresponding current interval as the first preset duration. This method can significantly reduce the amount of computation and improve control efficiency.

[0041] As another specific embodiment, a first preset duration and an inverse proportional function relationship between the input current can be established in advance. The controller can input the currently sampled input current into the inverse proportional function to calculate the corresponding first preset duration, thereby achieving continuous and smooth adaptive adjustment.

[0042] In one possible implementation, after determining the corresponding first preset duration based on the input current, if the rate of change of the input current is detected to be greater than a preset rate of change threshold, the first preset duration is further reduced.

[0043] In one possible implementation, prior to S102, the method provided in this embodiment further includes: Obtain the current flowing through the boost inductor in the boost circuit and use it as the input current; The preset integration threshold is determined based on the input current, and the input current and the preset integration threshold are negatively correlated.

[0044] This embodiment adds a step of adaptively adjusting the preset integral threshold based on the sampled input current. The controller can dynamically match the amplitude threshold for fault judgment based on the current load level of the circuit. Under heavy load, the rate of charge imbalance of the flying capacitor is faster, and a small integral offset can quickly develop into a serious short circuit fault. Therefore, the preset integral threshold is reduced to improve sensitivity. Under light load, the proportion of integral ripple during normal operation is higher. The preset integral threshold is increased to filter out normal ripple interference and avoid false triggering of protection.

[0045] Specifically, a correspondence between different current ranges of the input current and a preset integration threshold is established in advance. The higher the current range of the input current, the smaller the corresponding preset integration threshold. After sampling the input current in real time, the current range of the current input current is determined, and then the preset integration threshold corresponding to the current current range is found and determined. This preset integration threshold is used as the amplitude benchmark for fault judgment.

[0046] In addition, the controller can establish a linear function relationship between the input current and a preset integral threshold. After sampling the input current, the input current can be substituted into the linear function to calculate the corresponding preset integral threshold.

[0047] In one possible implementation, after S102, the method provided in this embodiment further includes: If the integral value is less than the integral recovery threshold, the blocking of the drive signal of the switch arm unit is released.

[0048] In this embodiment, the integral recovery threshold is less than a preset integral threshold. If the preset integral threshold is 95% of the maximum integral value, then the integral recovery threshold can be 80% of the maximum integral value. After blocking the drive signal of the switch arm unit, if the controller detects that the integral value is less than the integral recovery threshold within a fourth preset time period, then it releases the blocking of the drive signal of the switch arm unit.

[0049] Specifically, since the preset integral threshold decreases as the input current increases, in order to ensure control consistency, this embodiment sets the integral recovery threshold as the product of the preset integral threshold and the preset proportional coefficient, forming a hysteresis band. After the drive is locked, the integral value is continuously monitored. When the integral value is continuously lower than the integral recovery threshold for a fourth preset time period, the fault is determined to be eliminated, and the drive lockout is released. The preset proportional coefficient can be 85%~95%.

[0050] In one possible implementation, the specific implementation process of S101 includes: When the boost circuit meets the preset stability condition and the duty cycle of the drive signal of the switching bridge arm unit is not within the preset duty cycle range, the integral value of the voltage control loop of the flying capacitor is obtained.

[0051] In this embodiment, the preset duty cycle range includes an upper limit and a lower limit for duty cycle detection, wherein the upper limit for duty cycle detection can be 0.65~0.75, and the lower limit for duty cycle detection can be 0.4~0.5. For example, the preset duty cycle range can be [0.5, 0.7].

[0052] This embodiment only implements the method to prevent damage to the boost circuit when the duty cycle is not within the preset duty cycle range. Specifically, when the duty cycle is less than 0.5, the switching transistor conduction sequence is asymmetrical, the charge mismatch occurs during the single-cycle charging and discharging of the flying capacitor, and the commutation frequency and current change rate of the third diode D3 increase significantly. The reverse recovery process will be subjected to higher voltage spikes and current surges, and the electrical stress far exceeds the steady-state condition. If Q2 conduction is out of control, it will further aggravate the instantaneous overcurrent surge of D3, which can easily lead to diode breakdown failure. When the duty cycle is greater than 0.7, the conduction ratio of the lower switching transistor Q2 is too high, the charging time of the flying capacitor C1 is too long, and the stored energy continues to accumulate. The amplitude of the freewheeling current when D3 is forward conducting increases significantly, and the conduction loss and thermal stress increase simultaneously. At the same time, the voltage jump amplitude at the moment of turn-off is larger, which accelerates the aging and deterioration of D3. This is a high-incidence condition for clamping diode breakdown failure. Therefore, the low failure risk range of 0.5~0.7 is set as the non-detection range, and detection is only initiated in the high-risk range. This can not only accurately cover the high-risk operating conditions of D3 failure and block the risk of machine failure, but also reduce the use of control resources by invalid calculations, while avoiding the problem of false protection in the steady-state low-risk range, thus improving the economy and reliability of the protection logic.

[0053] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0054] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0055] Figure 3 A schematic diagram of the device for preventing damage to the boost circuit provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below: like Figure 3 As shown, the device 100 for preventing damage to the boost circuit includes: The integral acquisition module 110 is used to acquire the integral value of the voltage control loop of the flying capacitor when the boost circuit meets the preset stability conditions. The drive blocking module 120 is used to block the drive signal of the switch bridge arm unit if the integral value exceeds a preset integral threshold within a first preset time period.

[0056] In one possible implementation, the preset stability condition is that the boost circuit is within a second preset time period after power-on.

[0057] In one possible implementation, the device further includes a first preset duration determination module, used for: Before blocking the drive signal of the switch bridge arm unit if the integral value exceeds a preset integral threshold within a first preset time period, the current flowing through the boost inductor in the boost circuit is acquired and used as the input current. The first preset duration is determined based on the input current, and the input current and the first preset duration are negatively correlated.

[0058] In one possible implementation, the device further includes a preset integral determination module, used for: Before blocking the drive signal of the switch bridge arm unit if the integral value exceeds a preset integral threshold within a first preset time period, the current flowing through the boost inductor in the boost circuit is acquired and used as the input current. The preset integration threshold is determined based on the input current, and the input current and the preset integration threshold are negatively correlated.

[0059] In one possible implementation, the device further includes a blockade release module for: If the integral value is less than the integral recovery threshold, the blocking of the drive signal of the switch arm unit is released.

[0060] In one possible implementation, the integration acquisition module 110 is used for: When the boost circuit meets the preset stability condition and the duty cycle of the drive signal of the switching bridge arm unit is not within the preset duty cycle range, the integral value of the voltage control loop of the flying capacitor is obtained.

[0061] Figure 4 This is a schematic diagram of the controller provided in an embodiment of the present invention. Figure 4 As shown, the controller 4 in this embodiment includes a processor 40, a memory 41, and a computer program 42 stored in the memory 41 and executable on the processor 40. When the processor 40 executes the computer program 42, it implements the steps in the various method embodiments for preventing damage to the boost circuit described above, for example... Figure 2 Steps S101 to S102 are shown. Alternatively, when the processor 40 executes the computer program 42, it implements the functions of each module / unit in the above-described device embodiments, for example... Figure 3 The functions of modules 110 to 120 are shown.

[0062] For example, the computer program 42 may be divided into one or more modules / units, which are stored in the memory 41 and executed by the processor 40 to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program 42 in the controller 4.

[0063] The controller 4 may include, but is not limited to, a processor 40 and a memory 41. Those skilled in the art will understand that... Figure 4 This is merely an example of controller 4 and does not constitute a limitation on controller 4. It may include more or fewer components than shown, or combine certain components, or different components. For example, the controller may also include input / output devices, network access devices, buses, etc.

[0064] The processor 40 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0065] The memory 41 can be an internal storage unit of the controller 4, such as a hard disk or memory of the controller 4. The memory 41 can also be an external storage device of the controller 4, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the controller 4. Furthermore, the memory 41 can include both internal storage units and external storage devices of the controller 4. The memory 41 is used to store the computer program and other programs and data required by the controller. The memory 41 can also be used to temporarily store data that has been output or will be output.

[0066] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0067] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0068] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0069] In the embodiments provided by this invention, it should be understood that the disclosed devices / controllers and methods can be implemented in other ways. For example, the device / controller embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0070] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0071] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0072] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments for preventing damage to the boost circuit described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0073] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A method for preventing damage to a boost circuit, characterized in that, The boost circuit includes: a switching bridge arm unit, a flying capacitor, and a clamping unit; The flying capacitor is connected in parallel between the midpoint of the bridge arm of the switching bridge arm unit and the node of the switching transistor. The clamping unit is used to clamp the midpoint of the bridge arm to the midpoint of the output voltage divider; The method includes: When the boost circuit meets the preset stability conditions, the integral value of the voltage control loop of the flying capacitor is obtained; If the integral value exceeds a preset integral threshold within a first preset time period, the drive signal of the switch arm unit is blocked.

2. The method for preventing damage to the boost circuit according to claim 1, characterized in that, The preset stability condition is that the boost circuit is within a second preset time period after power-on.

3. The method for preventing damage to the boost circuit according to claim 1, characterized in that, The boost circuit also includes a boost inductor; the boost inductor is connected in series between the input terminal of the boost circuit and the switching bridge arm unit; Before blocking the drive signal of the switch arm unit if the integral value exceeds a preset integral threshold within a first preset time period, the method further includes: Obtain the current flowing through the boost inductor in the boost circuit and use it as the input current; The first preset duration is determined based on the input current, and the input current and the first preset duration are negatively correlated.

4. The method for preventing damage to the boost circuit according to claim 1, characterized in that, The boost circuit also includes a boost inductor; the boost inductor is connected in series between the input terminal of the boost circuit and the switching bridge arm unit; Before blocking the drive signal of the switch arm unit if the integral value exceeds a preset integral threshold within a first preset time period, the method further includes: Obtain the current flowing through the boost inductor in the boost circuit and use it as the input current; The preset integration threshold is determined based on the input current, and the input current and the preset integration threshold are negatively correlated.

5. The method for preventing damage to the boost circuit according to claim 1, characterized in that, After the step of blocking the drive signal of the switch arm unit if the integral value exceeds a preset integral threshold within a first preset time period, the method further includes: If the integral value is less than the integral recovery threshold, the blocking of the drive signal of the switch arm unit is released.

6. The method for preventing damage to the boost circuit according to claim 1, characterized in that, When the boost circuit meets the preset stability condition, obtaining the integral value of the voltage control loop of the flying capacitor includes: When the boost circuit meets the preset stability conditions and the duty cycle of the drive signal of the switching bridge arm unit is not within the preset duty cycle range, the integral value of the voltage control loop of the flying capacitor is obtained.

7. A device for preventing damage to a boost circuit, characterized in that, The boost circuit includes: a switching bridge arm unit, a flying capacitor, and a clamping unit; The flying capacitor is connected in parallel between the midpoint of the bridge arm of the switching bridge unit and the node of the switching transistor. The clamping unit is used to clamp the midpoint of the bridge arm to the midpoint of the output voltage divider; The device includes: An integral acquisition module is used to acquire the integral value of the voltage control loop of the flying capacitor when the boost circuit meets the preset stability conditions. The drive blocking module is used to block the drive signal of the switch bridge arm unit if the integral value exceeds a preset integral threshold within a first preset time period.

8. A controller comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method for preventing damage to the boost circuit as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method for preventing damage to the boost circuit as described in any one of claims 1 to 6.

10. A photovoltaic system, characterized in that, include: The boost circuit and the controller as described in claim 8.

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