Impedance injection type oscillation suppressor based on crossbar array of memristors

Abstract

The present application relates to the technical field of power electronic system stability control, and provides an impedance injection type oscillation suppressor based on a cross array of memristors, which comprises: a cross array of memristors, having a plurality of memristor units arranged along a row direction and a column direction, the resistance value of each memristor unit being configured to continuously change in response to a programming pulse applied thereto; a parallel programming driving circuit electrically connected with row lines and column lines of the cross array of memristors, configured to receive an impedance reconstruction instruction and apply a programming pulse to selected memristor units; a wideband impedance sensing network coupled to a target bus; an injection interface having an input end and an output end, the input end being electrically connected with an output port of the cross array of memristors, and the output end being configured to be coupled to the target bus; and a programming control unit in communication connection with the wideband impedance sensing network and the parallel programming driving circuit. The present application solves the problems of online continuous synthesis of physical damping and non-impact injection of wideband oscillation in a converter group grid-connected system.

Description

Technical Field

[0001] This invention relates to the technical field of stability control of power electronic systems, and specifically to an impedance injection type oscillation suppressor based on a memristor cross array. Background Technology

[0002] In offshore wind power and other new energy power generation systems, a large number of power electronic converters are connected to the busbar via long-distance cables. Unfavorable interactions can occur at certain frequencies between the converter's control loop and the line's distributed parameters, as well as between the controllers of different converters. When these interactions meet specific amplitude and phase conditions, continuous oscillations will appear on the busbar. The oscillation frequency ranges from several kilohertz to tens of kilohertz, often exceeding the effective bandwidth of the converter control system.

[0003] Current engineering methods for suppressing this type of oscillation can be broadly divided into two categories. One is a purely software approach, which incorporates damping algorithms into the converter's control program, such as embedding virtual impedance or notch filters in the current or voltage loops. The advantage of this approach is that it does not increase hardware costs, but its effective operating frequency is typically limited to a few hundred hertz to a few thousand hertz due to the constraints of digital control sampling frequency and pulse width modulation delay. For oscillations at tens of thousands of hertz or even higher, software methods offer almost no suppression capability.

[0004] Another type is the purely hardware approach, which involves a passive damping network consisting of resistors, inductors, and capacitors fixedly connected to the bus. Hardware damping does not have a bandwidth limit and can also be effective for medium- and high-frequency oscillations. However, a fixed-parameter RLC network can only be optimized for a specific oscillation frequency. In actual operation, the wind turbine output, the number of grid-connected converters, and the background harmonics of the power grid will all change, and the frequency and intensity of the oscillations will also change accordingly. Once the operating conditions deviate from the design conditions, the effectiveness of the fixed damping network will be reduced, and sometimes it may even introduce new resonances at other frequency points.

[0005] Existing technologies also use switching matrices as a control method, but these matrices essentially select from a set of discrete impedance values, failing to achieve continuous adjustment. Furthermore, the switching action itself introduces transient shocks, creating new disturbances in the bus voltage. The key challenge for this technical approach is whether the damping impedance can be made physically continuously adjustable without generating secondary shocks during adjustment. Summary of the Invention

[0006] One of the objectives of this invention is to solve the problem of online continuous synthesis and shock-free injection of physical damping for broadband oscillations in grid-connected converter groups.

[0007] To address the aforementioned objectives, in one embodiment of the present invention, an impedance injection-type oscillation suppressor based on a memristor cross array is proposed, comprising: a memristor cross array having a plurality of memristor cells arranged along the row and column directions, wherein the resistance value of each memristor cell is configured to continuously change in response to a programming pulse applied thereto; a parallel programming drive circuit electrically connected to the row and column lines of the memristor cross array, configured to receive an impedance reconstruction command and apply the programming pulse to a selected memristor cell; and a wideband impedance sensing network configured to be coupled to a target bus to obtain the actual voltage and current of the target bus. A real-time wideband oscillation characteristic signal; an injection interface having an input terminal and an output terminal, the input terminal being electrically connected to the output port of the memristor cross array, and the output terminal being configured to be coupled to the target bus; a programming control unit communicatively connected to the wideband impedance sensing network and the parallel programming drive circuit, the programming control unit being configured to calculate the target impedance value based on the real-time wideband oscillation characteristic signal, and convert the target impedance value into the impedance reconstruction command and send it to the parallel programming drive circuit, so that the memristor cross array injects physical damping corresponding to the target impedance value into the target bus through the injection interface.

[0008] Here, the memristor cross array utilizes the physical characteristic that the resistance value of the memristor unit can be continuously changed by the programming pulse to synthesize any target impedance value under the drive of the parallel programming driving circuit. The broadband impedance sensing network acquires the real-time broadband oscillation characteristic signal of the target bus in real time and provides it to the programming control unit. The programming control unit calculates the target impedance value to be injected based on the real-time broadband oscillation characteristic signal and converts it into an impedance reconstruction command for issuance. The parallel programming driving circuit applies the programming pulse to the memristor cross array according to the impedance reconstruction command, dynamically adjusting the resistance value of the memristor unit, thereby injecting the physical damping corresponding to the target impedance value into the target bus through the injection interface. Therefore, this closed-loop system realizes the online continuous synthesis and injection of oscillation damping at the physical level, solving the problems of bandwidth limitation of traditional software active damping and inability of fixed passive damping to adapt to changes in operating conditions.

[0009] Optionally, in some embodiments, the parallel programming drive circuit includes: a plurality of distributed pulse generation units, corresponding to each local subarray of the memristor cross array, each distributed pulse generation unit being configured to independently generate the programming pulse acting on the memristor cells within its subarray; the distributed pulse generation unit includes: a digital-to-analog converter configured to receive programming amplitude data from the programming control unit and output a reference voltage; a programmable pulse width modulator configured to receive programming timing data from the programming control unit and output a pulse control signal, the programmable pulse width modulator including a coarse-tuning counter and a fine-tuning delay chain to provide nanosecond-level time resolution; and a controlled voltage driver electrically connected to the digital-to-analog converter and the programmable pulse width modulator, and configured to output the programming pulse with an amplitude controlled by the reference voltage to the memristor cells during the effective period of the pulse control signal; wherein, the programming control unit is configured to parse the impedance reconstruction instruction and distribute it to the corresponding distributed pulse generation unit.

[0010] In this embodiment, by dividing the memristor cross array into multiple local subarrays and setting an independent distributed pulse generation unit for each local subarray, parallel programming of the memristor cells is achieved. The programmable pulse width modulator, combined with the coarse-adjustment counter and the fine-adjustment delay chain, can generate a pulse control signal with nanosecond-level precision. This signal, in conjunction with the reference voltage output by the digital-to-analog converter, enables the controlled voltage driver to output a programmable pulse with precisely controllable amplitude and pulse width. Therefore, this distributed precise pulse generation architecture ensures that the resistance value of each memristor cell in the large-scale array can be written quickly and accurately, providing the execution basis for online synthesis of the target impedance value.

[0011] Optionally, in some embodiments, the injection interface includes: a linear transimpedance amplifier, the input of which is electrically connected to the output port of the memristor cross array; a high-frequency magnetic coupling transformer, including a Z-shaped magnetic core, wherein the middle column of the Z-shaped magnetic core has a through-type single-turn secondary winding structure and is configured to be injected in series into the target busbar, the left column is wound with a primary winding, and the right column is wound with a bias winding, a fine-tuning magnetic path is formed between the left column and the middle column, and a bias magnetic path is formed between the right column and the middle column, wherein the fine-tuning magnetic path and the bias magnetic path achieve magnetic flux superposition within the middle column; the primary winding... A group is connected to the output of the linear transimpedance amplifier; an adjustable DC bias current source is electrically connected to the bias winding and configured to inject DC current into the bias winding to adjust the static permeability of the H-shaped magnetic core; a feedforward compensation winding is wound on the left column of the H-shaped magnetic core, concentric with the primary winding but opposite in polarity; the programming control unit is electrically connected to the feedforward compensation winding and configured to inject compensation current into the feedforward compensation winding according to the rate of change of current in the bias winding to counteract the coupling interference of the bias flux change on the fine-tuning signal in the primary winding.

[0012] Here, the fine-tuning magnetic path formed by the left column and the middle column of the shaped magnetic core, and the bias magnetic path formed by the right column and the middle column, achieve magnetic flux superposition within the middle column, allowing the coarse-tuning bias and the fine-tuning signal to be physically separated and synthesized on the magnetic circuit. The feedforward compensation winding actively injects compensation current according to the rate of change of the current in the bias winding, canceling the coupling interference of the bias magnetic flux change on the fine-tuning signal in the primary winding. Therefore, this injection interface achieves efficient transmission of physical damping to the target bus while solving the crosstalk problem between the coarse and fine adjustments.

[0013] Optionally, in some embodiments, the H-shaped magnetic core is wound from a microcrystalline alloy strip, the sum of the cross-sectional areas of the left and right columns is equal to the cross-sectional area of ​​the middle column, the ratio of the reluctance of the fine-tuning magnetic path to the reluctance of the bias magnetic path is set by the ratio of the cross-sectional areas of the left and right columns, the cross-sectional area of ​​the left column is 0.6 to 0.8 times that of the right column, so that the fine-tuning magnetic path always operates in the linear region of the magnetization curve of the microcrystalline alloy strip within the rated operating current range of the adjustable DC bias current source, and the number of turns of the bias winding on the right column is 2 to 3 times that of the primary winding on the left column, so as to generate a bias flux adjustment range sufficient to cover the full-range admittance change of the memristor cross array under the same DC bias current.

[0014] In this embodiment, by limiting the cross-sectional area ratio of the left column and the right column, and the turns ratio of the bias winding to the primary winding, not only is it ensured that the fine-tuning magnetic path operates in the linear region, but the bias flux adjustment range can also cover the entire admittance variation range of the memristor cross array. This quantitative design of geometric and electromagnetic parameters ensures that the injection interface can provide a stable and sufficient bias flux under different operating conditions, laying a reliable magnetic circuit foundation for the accurate online synthesis of the physical damping.

[0015] Optionally, in some embodiments, the wideband impedance sensing network further includes: an active integrator circuit electrically connected to the output of a Rogowski coil sensor and configured to integrate a signal proportional to the rate of change of current output by the Rogowski coil sensor to reconstruct a signal proportional to the current; a high-pass filter circuit connected in series with the output of the active integrator circuit; and a low-pass filter circuit connected in series with the output of a RC voltage divider sensor, the cutoff frequency of which is complementary to the cutoff frequency of the high-pass filter circuit in the frequency domain, the cutoff frequency of the high-pass filter circuit being set based on the minimum oscillation frequency of the target bus, and the cutoff frequency of the low-pass filter circuit being set based on the highest measurement frequency of the wideband impedance sensing network.

[0016] Here, the active integrator circuit restores the differential signal output by the Rogowski coil sensor to the current signal. The high-pass filter circuit and the low-pass filter circuit filter the current signal and the voltage signal respectively, and their cutoff frequencies are complementary. Therefore, this signal conditioning link ensures seamless acquisition of the voltage and current signals across the entire wideband range from the lowest oscillation frequency to the highest measurement frequency, thereby providing the programmable control unit with a complete and accurate real-time wideband oscillation characteristic signal.

[0017] Optionally, in some embodiments, the memristor cross array further includes: at least one column of reference memristor cells, manufactured using the same process as the memristor cells and programmed to a preset reference resistance state, the preset reference resistance state including multiple different resistance values ​​to cover the operating resistance range of the memristor cells; the parallel programming drive circuit further includes multiple readout circuits, corresponding to each of the memristor cells, each readout circuit being configured to apply a readout pulse to the corresponding memristor cell and detect its response current; the readout circuit is also configured to differentially measure the response current of the memristor cell and the response current of the reference memristor cell to eliminate common-mode interference of temperature drift on the resistance state readout; the programming control unit is communicatively connected to the readout circuit and is configured to compare the response current with a expected current threshold to verify whether the memristor cells are correctly programmed.

[0018] In this scheme, a reference memristor cell, manufactured using the same process as the memristor cell, provides a reference for the temperature common-mode reading. The readout circuit eliminates the common-mode interference of temperature drift on the resistance readout by differentially measuring the response currents of the memristor cell and the reference memristor cell, thereby achieving high-precision programming verification. Simultaneously, the programming control unit compares the response current with the expected current threshold to determine whether the memristor cell has been correctly programmed, forming a closed-loop verification mechanism for programming and readout. Therefore, this differential readout scheme significantly improves the resistance control accuracy and long-term stability of the memristor cross array.

[0019] Optionally, in some embodiments, the at least one column of reference memristor cells is programmed to multiple different preset reference states, each preset reference state being distributed logarithmically at intervals within the operating resistance range of the memristor cells. The readout circuit is configured to, when performing differential measurements on the target memristor cell, select from the at least one column of reference memristor cells the reference memristor cell corresponding to the preset reference state that is closest to the expected resistance value of the target memristor cell, as the differential reference object for this measurement. The readout circuit includes a multiplexer electrically connected to each of the reference memristor cells, and the programming control unit controls the selection state of the multiplexer according to the target resistance value set for the target memristor cell in the impedance reconstruction instruction.

[0020] Here, the plurality of preset reference resistance states are distributed at logarithmic intervals, covering the entire operating resistance range of the memristor unit. During each differential measurement, the multiplexer dynamically selects the reference memristor unit closest to the expected resistance value of the target memristor unit as a reference, ensuring that the differential measurement is always performed under optimal matching conditions, further improving the accuracy of the resistance reading. Therefore, this dynamic reference selection mechanism enables the differential readout to maintain extremely high accuracy throughout the entire operating resistance range.

[0021] Optionally, in some embodiments, each memristor unit in the memristor cross array is connected in series with a bidirectional threshold switch to form a 1S1R unit. The bidirectional threshold switch has a threshold voltage. When the voltage applied across the 1S1R unit is lower than the threshold voltage, the bidirectional threshold switch is in a high-impedance off state to block the creeping current path flowing through the unselected memristor unit. When the voltage applied across the 1S1R unit is higher than the threshold voltage, the bidirectional threshold switch is turned on. The programming pulse is applied across the memristor unit to change its resistance value. The threshold voltage of the bidirectional threshold switch is between the readout pulse amplitude and the programming pulse amplitude output by the programming control unit.

[0022] The 1S1R cell is an abbreviation for "a cell consisting of a gate transistor and a memristor connected in series," and can be called a gated memristor cell. "1S" refers to a bidirectional threshold switch, i.e., a gate transistor; "1R" refers to a memristor. In a cross-connect array, each memory node consists of such a gate transistor and a memristor connected in series.

[0023] The function of the bidirectional threshold switch is to suppress creeping current in the array. When the voltage applied across the series cell is lower than the switch's threshold voltage, the switch is in a high-impedance off state, effectively cutting off the current path. Thus, when a read or write operation is performed on a target cell in the array, unselected cells will not form a parallel leakage path, preventing interference with the target cell's read or programming from the selected row line through the unselected memristor cell, the unselected column line, and then to ground. When the applied voltage is higher than the threshold voltage, the switch turns on within approximately one nanosecond, allowing the programming pulse to rewrite the memristor's resistance value through the turned-on memristor cell.

[0024] In this design, the threshold voltage of the bidirectional threshold switch is set between the read pulse amplitude and the programming pulse amplitude. When the read pulse amplitude is below the threshold, the switch remains off during a read operation, and the read current flows only through the selected cell. When the programming pulse amplitude is above the threshold, the switch reliably conducts during a write operation.

[0025] Optionally, in some embodiments, the programming control unit is configured to: construct a state-space smooth transition model using the current admittance state of the memristor cross array and the target impedance value before converting the target impedance value into the impedance reconstruction instruction; solve the optimal control problem in the finite time domain online based on the state-space smooth transition model to generate a smooth admittance trajectory from the current admittance state to the target admittance state corresponding to the target impedance value; and convert the smooth admittance trajectory into a series of time-continuous impedance reconstruction instructions and send them to the parallel programming drive circuit.

[0026] In this embodiment, the programming control unit constructs the state-space smooth transition model to solve the optimal control problem online, generating a smooth admittance trajectory from the current admittance state to the target admittance state. This trajectory is converted into a time-continuous impedance reconstruction instruction, driving the parallel programming drive circuit to gradually adjust the resistance state of the memristor unit, avoiding the transient impact of impedance abrupt changes on the target bus. Therefore, this smooth transition control strategy solves the problem of shock-free injection.

[0027] Optionally, in some embodiments, the programming control unit is configured to: decompose the total admittance requirement corresponding to the target impedance value into multiple sub-admittance components; allocate each of the sub-admittance components to different local subarrays; and coordinate each of the distributed pulse generation units to perform programming operations on each of the local subarrays in parallel to globally reconstruct the target impedance value within a predetermined time.

[0028] Optionally, in some embodiments, the programming control unit is configured to: periodically read the current resistance state of the reference memristor cell and compare it with the preset reference resistance state to obtain the resistance state drift; and update the programming amplitude data in the impedance reconstruction instruction sent to the parallel programming drive circuit according to the resistance state drift to compensate for the long-term resistance state drift of the memristor cell.

[0029] Optionally, in some embodiments, the programming control unit is configured to: monitor the health index of memristor cells in each region of the memristor cross array; when the health index of the memristor cells in a certain region is detected to be lower than a preset threshold, remap the impedance synthesis task of that region to other regions with normal health index; and recalculate the decomposition scheme of the target impedance value based on the available resources after remapping.

[0030] Optionally, in some embodiments, the programming control unit includes: a field-programmable gate array (FPGA) chip, communicatively connected to the wideband impedance sensing network and the parallel programming drive circuit; the FPGA chip is configured to perform a fast Fourier transform on the real-time wideband oscillation characteristic signal to extract the frequency, amplitude, and damping ratio of the dominant oscillation mode, and to look up a preset impedance mapping table based on the frequency, amplitude, and damping ratio of the dominant oscillation mode to obtain the target impedance value; before performing the fast Fourier transform on the real-time wideband oscillation characteristic signal, the real-time wideband oscillation characteristic signal is divided into multi-level sub-bands by a set of orthogonal mirror filters to separate the oscillation components of different frequency bands; and for each frequency band whose energy proportion exceeds a preset threshold, the fast Fourier transform is performed respectively to extract multiple dominant oscillation modes.

[0031] In this scheme, the field-programmable gate array (FPGA) chip performs multi-level sub-band division on the real-time broadband oscillation characteristic signal through the orthogonal mirror filter, separating the oscillation components of different frequency bands. Then, it performs the Fast Fourier Transform (FFT) only on the frequency bands whose energy proportion exceeds the threshold, thereby efficiently extracting multiple dominant oscillation modes. The target impedance value is obtained by querying the preset impedance mapping table. This method not only solves the problem that a single FFT is insufficient to capture composite oscillations, but also significantly improves the efficiency and accuracy of the spectrum analysis. Therefore, this multimodal parallel detection and intelligent decision-making scheme provides a fast and accurate impedance calculation basis for subsequent damping injection.

[0032] Optionally, in some embodiments, the programming control unit is configured to: perform a windowed interpolation fast Fourier transform on the real-time broadband oscillation characteristic signal to extract the frequency, amplitude, and damping ratio of the dominant oscillation mode; recursively update the impedance parameter vector by minimizing the weighted sum of squares of the impedance spectrum estimation error to identify the broadband impedance spectrum of the target bus online; and search for the resonance peak with the smallest phase margin in the broadband impedance spectrum, and calculate the target impedance value based on the frequency and amplitude of the resonance peak.

[0033] Here, the programmable control unit uses windowed interpolation FFT to accurately extract the oscillation mode parameters, and then identifies the broadband impedance spectrum of the target bus online through the recursive least squares method, thereby automatically searching for the most dangerous resonance peak in the broadband impedance spectrum. Therefore, this online identification and intelligent search algorithm can track the system impedance changes in real time and accurately calculate the most needed target impedance value.

[0034] Optionally, in some embodiments, the field-programmable gate array chip is further configured to: apply multiple sliding time windows of different lengths to the real-time wideband oscillation characteristic signal to obtain multiple spectra; and weight and fuse the multiple spectra to extract the dominant oscillation mode.

[0035] In this embodiment, by using spectral weighted fusion of multiple sliding time windows of different lengths, both frequency resolution and time response are considered, overcoming the limitations of a single window. This allows for accurate extraction of the dominant oscillation mode even in rapidly changing oscillation scenarios. Therefore, this multi-time-window fusion technique improves the dynamic performance of mode identification.

[0036] Optionally, in some embodiments, the programming control unit is configured to: perform correlation matching between the real-time broadband oscillation characteristic signal and a preset oscillation event template library to identify the oscillation type, wherein the preset oscillation event template library stores templates composed of the spectral characteristics of historical oscillation events of the target bus; and, based on the identified oscillation type, retrieve the impedance calculation strategy corresponding to the oscillation type from the strategy library to perform the operation of calculating the target impedance value.

[0037] Here, by matching the current oscillation characteristics with the historical template, the oscillation type is quickly identified, and the corresponding calculation strategy is retrieved, enabling the system to adopt the most suitable impedance calculation method for different oscillation characteristics. Therefore, this template matching and strategy switching mechanism enhances the system's adaptability to complex and variable oscillation scenarios.

[0038] Optionally, in some embodiments, the programming control unit further includes: an adaptive notch filter module connected between the broadband impedance sensing network and the subsequent processing module; the adaptive notch filter module is configured to adjust its notch frequency in real time according to the steady-state fundamental and harmonic frequencies of the target bus, so as to attenuate the steady-state fundamental and harmonic components from the real-time broadband oscillation characteristic signal, and then output it to the subsequent processing module.

[0039] Optionally, in some embodiments, the programming control unit further includes: a digital twin engine, which internally maintains a real-time digital twin model of the target bus and the memristor cross array; the programming control unit is configured to synchronize the real-time broadband oscillation characteristic signal to the real-time digital twin model, and to simulate and deduce the effects of different damping injection strategies in the real-time digital twin model to assist in calculating the target impedance value.

[0040] Here, after synchronizing the real-time broadband oscillation characteristic signal, the digital twin engine rapidly simulates and extrapolates the effects of different damping injection strategies in digital space, providing predictive assistance for selecting the optimal target impedance value. Therefore, this decision-making assistance method based on digital twins further improves the specificity and effectiveness of the damping injection strategy.

[0041] Optionally, in some embodiments, the field-programmable gate array (FPGA) chip is configured to, when performing multi-level subband division on the real-time wideband oscillation characteristic signal: employ a cascaded multi-level filter bank structure, each filter bank including a low-pass finite impulse response (FIR) filter and a high-pass finite impulse response (FIR) filter. The coefficients of the low-pass FIR filter and the high-pass FIR filter are obtained based on the same prototype low-pass filter through frequency transformation, and the two have complementary amplitude-frequency response characteristics in the frequency domain. After the input signal passes through each filter bank, it is divided into low-frequency subband signals and high-frequency subband signals. The low-frequency subband signals are sent to the next level filter bank for further division, and the high-frequency subband signals are output to the subband energy calculation module of that level. The subband energy of the high-frequency subband signals output from each level and the low-frequency subband signals output from the last level are calculated in parallel, and the fast Fourier transform is performed.

[0042] In this scheme, the complementary amplitude-frequency characteristics of the low-pass finite impulse response (FIR) filter and the high-pass FIR filter in the cascaded multi-stage filter bank structure ensure the distortion-free reconstruction capability of the sub-band division. The high-frequency sub-band signals of each stage and the low-frequency sub-band signals of the last stage are calculated in parallel and subjected to the Fast Fourier Transform (FFT), thereby efficiently realizing the multimodal parallel detection. Therefore, this implementation structure significantly improves the processing speed while ensuring the detection accuracy. Attached Figure Description

[0043] Figure 1 A schematic diagram of the overall structure of an impedance injection type oscillation suppressor based on a memristor cross array according to an embodiment of the present invention is shown. Figure 2 A three-dimensional schematic diagram of the injection interface and the assembly structure of the memristor array of an impedance injection type oscillation suppressor based on a memristor cross array according to an embodiment of the present invention is shown. Figure 3 A schematic diagram of the differential readout and gating structure of a memristor array based on an impedance injection type oscillation suppressor according to an embodiment of the present invention is shown. Figure 4 It shows Figure 3 A three-dimensional exploded view of the injection interface and memristor array of an impedance injection type oscillation suppressor based on a memristor cross array. Figure 5 A schematic diagram of the current and voltage front-end isolation conditioning circuit of the broadband impedance sensing network in an embodiment of the present invention is shown. Detailed Implementation

[0044] Example 1 like Figure 1As shown in the attached figures, the impedance injection type oscillation suppressor based on the memristor cross array operates directly in parallel with the target bus 200. The target bus 200 may be a section of DC distribution network bus or a local node of AC system; no distinction is made here. When some form of oscillation occurs on the target bus 200, the system must be able to sense it in real time, calculate a suitable damping impedance, and then actually inject this impedance into the target bus 200 to dissipate the oscillation energy.

[0045] Figure 1 In this process, the wideband impedance sensing network 30 is responsible for acquiring the voltage and current signals on the target bus 200 and extracting the wideband oscillation characteristics from them. The output of the wideband impedance sensing network 30 is fed into the programming control unit 50. After receiving these real-time wideband oscillation characteristic signals, the programming control unit 50 calculates the target impedance value to be injected. This calculation process can be based on a preset impedance mapping table or solved online in real time, ultimately yielding a set of specific admittance values.

[0046] Having obtained the target impedance value, the programming control unit 50 converts it into an impedance reconstruction command and sends it to the parallel programming drive circuit 20. The parallel programming drive circuit 20 is connected to all the row lines 12 and column lines 13 of the memristor cross array 10. The memristor cross array 10 itself is composed of a cluster of memristor cells 11 arranged in a row-column matrix, with one memristor cell 11 at each crossover point. The resistance values ​​of these memristor cells 11 are not fixed; after applying a programming pulse, their resistance values ​​can continuously change, increasing or decreasing, as long as the amplitude, width, and polarity of the pulse are controlled. Therefore, the total admittance exhibited by the entire memristor cross array 10 can be finely adjusted.

[0047] The output port of the memristor cross array 10 is connected to the input port of the injection interface 40. The output port of the injection interface 40 is coupled back to the target bus 200. In this way, the impedance exhibited by the memristor cross array 10, after passing through the injection interface 40, is equivalent to a physical damper connected in parallel to the target bus 200. When this damper is properly matched with the oscillation mode, the oscillation will be suppressed.

[0048] The injection interface 40 has two electrical functions: first, to faithfully transmit the output characteristics of the memristor cross array 10 to the target bus 200; and second, to perform electrical isolation or impedance matching when necessary. In this embodiment, the injection interface 40 can use a linear transimpedance amplifier to drive a high-frequency transformer, with the transformer secondary winding injected into the target bus 200 in series.

[0049] The programming control unit 50 has communication links with both the wideband impedance sensing network 30 and the parallel programming drive circuit 20. The data transmitted from the wideband impedance sensing network 30 is a continuous sampling stream. The logic inside the programming control unit 50, which may be an FPGA or a DSP, processes this data in real time to extract the dominant mode of oscillation. For example, it first calculates the energy distribution of the signal in each frequency band, identifies the frequency with the highest energy, and then calculates the amplitude and attenuation factor of this oscillation component. Based on these parameters, it looks up a table or iterates in real time to obtain the admittance value that should be injected.

[0050] There are several ways to implement the wideband impedance sensing network 30. A Rogowski coil sensor can be used to acquire the differential signal of the current, and then a resistive-capacitive voltage divider sensor can be used to acquire the voltage. The Rogowski coil outputs di / dt, which, when followed by an active integrator circuit, can reconstruct i(t). Both the voltage and current signals are filtered before being fed into an ADC for sampling. The cutoff frequencies of the filters need to be coordinated: the cutoff frequency of the high-pass filter is set near the lowest possible oscillation frequency of the target bus 200, while the cutoff frequency of the low-pass filter is set near the highest frequency that the system needs to sense. These two filters complement each other in the frequency domain, thus covering the entire oscillation band of interest.

[0051] The programming control unit 50 can calculate the target impedance value using a relatively direct method. For example, it can perform an FFT on a sampled voltage and current data set to find the non-power frequency component with the largest amplitude, and calculate the corresponding frequency and damping ratio. If the damping ratio is less than a certain threshold, it indicates that the system is underdamped at this frequency and requires additional damping. Then, based on the impedance mapping table, it can determine the appropriate resistance and reactance components to inject at this frequency, thus obtaining the target impedance value. The impedance reconstruction instruction converts the target impedance value into the admittance matrix that the memristor cross array 10 needs to present.

[0052] The operation of the parallel programming driver circuit 20 on the memristor cross array 10 is relatively low-level. Assuming the memristor cross array 10 is a 256x256 array, each memristor cell 11 needs to be programmed to a precise resistance value. The resolution of the resistance value depends on the control precision of the programming pulse. The amplitude, width, and falling edge slope of the programming pulse all affect the final resistance value. The parallel programming driver circuit 20 integrates the digital-to-analog converter and the programmable pulse width modulator, enabling the generation of pulses with nanosecond-level adjustable precision, and the voltage amplitude can also be adjusted in millivolt-level steps. Thus, each memristor cell 11 can be programmed to an effective resolution of at least 6 to 8 bits.

[0053] The material of each memristor cell 11 in the memristor cross array 10 may be a metal oxide, such as HfOx or TaOx. During programming, oxygen vacancy migration leads to the formation or breakage of the conductive filaments, thereby changing the resistance. The process is dependent on temperature and voltage stress, but in the context of this embodiment, we are primarily concerned with its electrical behavior: it is a two-terminal device where the resistance decreases when a positive pulse is applied, increases when a negative pulse is applied, and remains constant after the pulse ends. Utilizing these characteristics, the array can be used like an analog adjustable resistor network.

[0054] When the system operates continuously, the wideband impedance sensing network 30 continuously sends the latest oscillation characteristic data to the programming control unit 50. The programming control unit 50 then determines in each control cycle whether the injected damping needs adjustment. If the oscillation has subsided, the injected damping may need to be gradually withdrawn to avoid unnecessary losses to the normal power transmission of the system. If the oscillation becomes stronger, the damping needs to be increased, that is, the admittance of the memristor cross array 10 needs to be increased. This process is closed-loop.

[0055] Various power electronic converters, loads, and lines may be connected to the target bus 200. Their interactions cause negative damping at certain frequencies, leading to oscillations. The function of this suppressor is to provide positive resistive losses at these frequencies, dissipating excess oscillation energy. The actual power consumed by the memristor cross array 10 is not large because it primarily provides a damping path rather than directly carrying the main power flow. Most of the energy is dissipated as heat within the memristor cells 11; however, since the resistance of the memristor cells 11 can be made relatively large, the actual power consumption is small.

[0056] Example 2 The parallel programming driver circuit 20 is divided into multiple local subarrays, each corresponding to a distributed pulse generation unit. When many memristor units 11 need to be adjusted simultaneously, the programming task can be distributed to each distributed pulse generation unit, which independently generates programming pulses, instead of being scanned line by line by a centralized pulse generator. This is crucial for scenarios requiring rapid impedance reconstruction.

[0057] Figure 1 Only the block diagram of the parallel programming driver circuit 20 is shown, but... Figure 3Its internal structure is partially visible. The distributed pulse generation unit's internal circuitry includes a digital-to-analog converter (DAC), a programmable pulse width modulator (PWM), and a controlled voltage driver. The DAC receives programmed amplitude data from the programming control unit 50 and outputs an analog reference voltage. The PWM receives programmed timing data and generates pulse control signals. The key design feature of this PWM is its high time resolution. It internally uses a coarse-adjustment counter and a fine-adjustment delay chain. The coarse-adjustment counter sets the pulse width in units of the system clock cycle, while the fine-adjustment delay chain inserts several to tens of gate-level delays to adjust the pulse width to the nanosecond level. This allows for precise control of the pulse energy applied to the memristor unit 11.

[0058] The controlled voltage driver is a high-voltage operational amplifier or push-pull driver stage. When the pulse control signal is active, it outputs a programming pulse with an amplitude equal to the reference voltage to the two ends of memristor unit 11. When the pulse control signal is inactive, the output is in a high-impedance state or pulled back to zero. The polarity of the pulse is controlled by a separate polarity switching circuit, but here it can be simplified so that the output of the controlled voltage driver can be selectively applied in either the forward or reverse direction via row and column lines.

[0059] Figure 3 The readout circuit 25 and the reference memristor unit 111 are shown, which will be described in detail in subsequent embodiments.

[0060] When generating the impedance reconstruction instruction, the programming control unit 50 first parses the target admittance matrix. Assume the target admittance value corresponds to the admittance value of a specific memristor unit 11. The programming control unit 50 reads the current admittance value of the memristor unit 11. Calculate the admittance difference that needs to be changed. Then, based on the programming characteristic curve of the memristor unit 11, which is a known nonlinear function, the... Mapped to the desired programmed pulse amplitude and the pulse width This mapping relationship can be pre-measured and stored in the memory of the programming control unit 50 in the form of a lookup table.

[0061] The impedance reconstruction command is distributed to each of the distributed pulse generation units. Each distributed pulse generation unit parses the command within its jurisdiction and extracts the programming amplitude data and programming timing data corresponding to the memristor unit 11. The time for the digital-to-analog converter to establish the reference voltage is in the microsecond range, and the delay jitter of the pulse generated by the programmable pulse width modulator is in the nanosecond range. The total time for the entire distributed pulse generation unit to complete the application of one programming pulse is within a few microseconds. If multiple distributed pulse generation units operate simultaneously, the entire memristor cross array 10 can complete large-scale impedance state updates in a very short time.

[0062] Some memristor cells 11 may only require fine-tuning of the resistance value, in which case the amplitude of the programming pulse is small and the pulse is narrow. Others require large resistance value jumps, which may require applying a long pulse sequence to gradually approach the target value. When distributing the instructions, the programming control unit 50 generates a micro-instruction sequence for each memristor cell 11, with each micro-instruction corresponding to a programming pulse and its parameters. The distributed pulse generation unit executes these micro-instructions sequentially. In this way, the impedance reconstruction of the entire memristor cross array 10 is like playing a game of chess, with each step precisely controlled, ultimately presenting the desired admittance distribution globally.

[0063] In this embodiment, the fine-tuning delay chain of the programmable pulse width modulator is crucial. It utilizes the propagation delay of CMOS gates as the basic delay unit, and different delay amounts are obtained by selecting taps. The coarse-tuning counter is implemented using a synchronous counter; after the count value is latched, it is compared with the pulse end time to trigger the pulse's trailing edge. The combination of coarse and fine tuning can cover pulse widths ranging from tens of nanoseconds to hundreds of microseconds, with steps within 1 nanosecond.

[0064] This precise pulse control allows memristor cell 11 to be programmed to a very high resistance resolution. For example, if the operating resistance range of memristor cell 11 is 1kΩ to 100kΩ, then theoretically, using 8-bit amplitude control and 16-bit pulse width control, an effective resistance resolution of over 10 bits can be achieved. In practice, due to the nonlinearity, inter-cycle variations, and noise inherent in the memristor cell 11, the effective resolution will be somewhat lower, but this can be compensated for through verification and reprogramming.

[0065] Example 3 The injection interface 40 is responsible for transmitting the adjustable impedance characteristics generated by the memristor cross array 10 to the target bus 200. If the target bus 200 is on the high-voltage side, electrical isolation must be considered. Here, a high-frequency magnetic coupling transformer is used to achieve isolation and impedance transformation.

[0066] The input terminal of injection interface 40 is connected to the output port of memristor cross array 10, and passes through a linear transimpedance amplifier. This linear transimpedance amplifier converts the current signal at the output terminal of memristor cross array 10 into a voltage signal, and its transimpedance gain is fixed. Therefore, the admittance characteristic of the entire memristor cross array 10 is linearly converted into a voltage signal.

[0067] This voltage signal drives the primary winding 422 of the high-frequency magnetic coupling transformer. The high-frequency magnetic coupling transformer uses a Z-shaped magnetic core. The Z-shaped magnetic core has three columns: left column, middle column, and right column. The middle column adopts a through-type single-turn secondary winding structure, that is, one phase conductor of the target bus 200 is directly passed through the middle column, or a single-turn copper tube is wrapped around the middle column and connected in series in the circuit of the target bus 200. The primary winding is wound on the left column and connected to the output terminal of the linear transimpedance amplifier 41. The bias winding is wound on the right column.

[0068] The magnetic flux in the middle column is the result of the superposition of the fine-tuning flux in the left column and the bias flux in the right column. The secondary winding has only one turn, so the secondary voltage directly depends on the rate of change of the middle column flux. The current in the primary winding, driven by a linear transimpedance amplifier, generates a fine-tuning flux, which closes through the left column and the middle column. The bias winding, driven by an adjustable DC bias current source, generates a DC bias flux that closes through the right column and the middle column. These two fluxes converge in the middle column. Since the permeability of the core changes with the DC bias, adjusting the bias current changes the transformer's operating point, i.e., changes the static permeability. Changes in static permeability directly affect the equivalent coupling efficiency of the primary winding to the secondary winding, thus indirectly adjusting the equivalent impedance transformation ratio of the entire injection interface 40.

[0069] The cross-sectional areas of the left and right columns are carefully chosen. The cross-sectional area of ​​the left column is approximately 0.6 to 0.8 times that of the right column. This results in a relatively high reluctance for the fine-tuning magnetic path and a relatively low reluctance for the bias magnetic path. Within the rated operating range of the adjustable DC bias current source, the fine-tuning magnetic path always operates in the linear region of the magnetization curve, preventing deep saturation and ensuring linear transmission of the fine-tuning signal. If the cross-sectional area of ​​the left column is too large, a slightly larger bias current will push the entire core towards saturation, drastically increasing the distortion of the fine-tuning signal.

[0070] The number of turns in the bias winding is two to three times that of the primary winding. This allows a smaller DC bias current to generate a sufficient bias magnetomotive force (MOF) to cover the bias flux adjustment range required for the full-scale admittance variation of the memristor cross array. For example, if the primary winding has 20 turns, the bias winding could have 50 turns. An adjustable DC bias current source outputting 0 to 200 mA can generate a 10 amp-turn bias MOF, sufficient to operate the core in different sections of the magnetization curve.

[0071] The 421 H-shaped magnetic core is made of microcrystalline alloy strip wound together. Microcrystalline alloys have high initial permeability, low coercivity, and low magnetostriction, making them suitable for high-frequency operation. The core post of the strip-wound core can be made very thin, passing directly through a single-turn secondary conductor.

[0072] A feedforward compensation winding 425, concentric with but opposite in polarity to the primary winding, is also wound on the left column. This compensation winding suppresses the coupling interference of bias flux changes on the fine-tuning signal. When the adjustable DC bias current source adjusts the bias current, the bias flux on the right column changes. This change couples to the primary winding of the left column through the middle column, inducing a noise voltage across the primary winding. The feedforward compensation winding is driven by the programmable control unit 50 based on the rate of change of the bias current. The programmable control unit 50 monitors changes in the bias current command, calculates the rate of change, and then injects a compensation current proportionally into the compensation winding, generating a compensation flux opposite in direction to the interference flux, thereby canceling the interference at the primary winding terminals.

[0073] The connection method between the injection interface 40 and the target bus 200 determines its equivalent circuit. Looking in from the target bus 200 side, it's equivalent to having a controlled voltage source connected in series on the line. The amplitude and phase of this voltage source are jointly determined by the admittance of the memristor cross array 10, the gain of the transimpedance amplifier, and the transformer turns ratio. Since the admittance of the memristor cross array 10 is programmable, the injected equivalent impedance is also programmable.

[0074] Example 4 Regarding the core design, the H-shaped core utilizes the aforementioned microcrystalline alloy strip, with the grade being 1K107 or a similar specification. The strip thickness is between 18 μm and 25 μm, and it is wound into a rectangular H-shape. The sum of the cross-sectional areas of the left and right pillars is strictly equal to the cross-sectional area of ​​the middle pillar to ensure magnetic flux continuity and prevent local saturation caused by magnetic flux compression or diffusion at the middle pillar.

[0075] The ratio of the reluctance of the fine-tuning magnetic path to the reluctance of the bias magnetic path is set by the ratio of the cross-sectional areas of the left column and the right column. Since the reluctance is inversely proportional to the cross-sectional area, the cross-sectional area of ​​the left column is 0.6 to 0.8 times that of the right column, meaning that the reluctance of the fine-tuning magnetic path is 1.25 to 1.67 times that of the bias magnetic path. The intention of this design is that, during the process of the bias current increasing from zero to the rated maximum value, the bias flux first increases, pushing the operating point of the magnetic core from the lower end of the linear region to a higher position, but the total flux of the middle column does not enter the deep saturation. The fine-tuning flux is superimposed on the already biased flux, still operating in the linear region.

[0076] When the bias current is stable, the rate of change is zero, and there is no current in the feedforward compensation winding. When a rapid adjustment of the injection impedance is required to change the bias current, the compensation current is briefly injected to eliminate transient coupling interference. Thus, even during the rapid impedance switching process, the output of the injection interface 40 does not carry significant bias adjustment noise.

[0077] The rated operating current range of the adjustable DC bias current source can be 0 to 1 A. Within this range, the magnetic flux density in the left column remains below the knee of the magnetization curve of the microcrystalline alloy. For example, if the saturation magnetic flux density of the microcrystalline alloy is approximately 1.2 T, the design ensures that the peak magnetic flux density of the left column under the maximum bias plus the maximum fine-tuning signal does not exceed 0.9 T, thus providing sufficient margin.

[0078] The number of turns in the bias winding is 2 to 3 times that of the primary winding, with the specific value determined based on the required bias flux adjustment range. The full-scale admittance change of the memristor cross array 10, such as from a near-open-circuit state to a minimum resistance state, may require a dynamic range of tens of dB for the corresponding injection impedance change. By changing the permeability through the bias, and in conjunction with the gain adjustment of the transimpedance amplifier, this dynamic range can be completely covered.

[0079] The specific parameters of the feedforward compensation winding are as follows: its number of turns can be the same as or slightly less than that of the primary winding. Since it only needs to generate the compensation magnetomotive force proportional to the bias change rate and does not undertake the main power transmission, the wire diameter can be very fine. The programmable control unit 50 drives the compensation current through a low-power voltage-controlled current source. The accuracy of the compensation depends on the estimation of the bias current change rate. A sampling resistor can be connected in series at the output terminal of the adjustable DC bias current source to measure the current, and then the change rate can be obtained using the analog differentiator or the digital differentiating algorithm, and then the compensation current command can be generated accordingly.

[0080] The magnetic core design described in this embodiment allows for a wide operating frequency band of the injection interface 40. The microcrystalline alloy magnetic core exhibits low high-frequency loss and maintains good magnetic properties even at frequencies of several hundred kilohertz. Combined with the bias adjustment and feedforward compensation, the entire injection interface 40 can cover an injection bandwidth from tens of Hz to hundreds of kilohertz, sufficient to handle the subsynchronous oscillations and mid-to-high frequency oscillations commonly found in power systems.

[0081] Example 5 The wideband impedance sensing network 30 includes the Rogowski coil sensor and the RC voltage divider sensor. The Rogowski coil is wound around the target bus 200, and the output voltage signal is proportional to the rate of change di / dt of the current on the bus. This signal passes through the active integrator circuit, where the operational amplifier, feedback capacitor, and resistor convert the di / dt signal into a signal proportional to i(t). The time constant of the integrator is set according to the frequency range of the measured current, and the low-frequency cutoff frequency is set much lower than the lowest oscillation frequency, for example, below 0.1 Hz.

[0082] A high-pass filter circuit is connected in series after the active integrator circuit to further filter out the DC and extremely low-frequency drift. The cutoff frequency of the high-pass filter circuit is set based on the minimum oscillation frequency of the target bus 200. For example, if the lowest possible oscillation frequency of the system is known to be around 5 Hz, then the cutoff frequency of the high-pass filter can be set between 1 Hz and 3 Hz, thus retaining the oscillation information above 5 Hz while suppressing the drift below the power frequency.

[0083] The RC voltage divider sensor extracts the voltage signal between the conductor and ground of the target bus 200. The output of the RC voltage divider sensor is connected in series with a low-pass filter circuit, the cutoff frequency of which is set based on the highest measurement frequency of the wideband impedance sensing network 30. Assuming the highest oscillation frequency that the system needs to sense is 10 kHz, then the cutoff frequency of the low-pass filter is set to around 10 kHz, possibly slightly higher, such as 12 kHz, to ensure in-band flatness.

[0084] The cutoff frequencies of the high-pass filter circuit and the low-pass filter circuit are complementary and interconnected in the frequency domain, with no gaps or redundancy between their cutoff frequencies. If the cutoff frequency of the high-pass filter is 3 Hz and the cutoff frequency of the low-pass filter is 12 kHz, then the entire sensing bandwidth is from 3 Hz to 12 kHz. This bandwidth covers the typical frequency bands of subsynchronous oscillation (a few Hz to tens of Hz), supersynchronous oscillation (tens of Hz to hundreds of Hz), and mid-to-high frequency resonance (hundreds of Hz to thousands of Hz).

[0085] The filtered voltage and current signals are sampled synchronously. The sampling rate of the ADC is at least 5 to 10 times the highest measurement frequency; 200 ksps is sufficient here. The sampled digital signals are then fed into the programming control unit 50 for real-time processing.

[0086] The Rogowski coil sensor itself has poor low-frequency characteristics because its output is a differential signal, resulting in a low signal-to-noise ratio when directly measuring low-frequency current. The active integrator circuit is introduced to improve the signal-to-noise ratio in the low-frequency range. However, the integrator may introduce DC drift, so a high-pass filter circuit is used to filter out residual DC and extremely low-frequency drift. The RC voltage divider sensor has good low-frequency characteristics and is suitable for measuring low-frequency voltage, but it may be affected by stray capacitance at high frequencies. Therefore, a low-pass filter circuit is used to limit high-frequency noise. In this way, the two signals are conditioned separately and then spliced ​​together in the frequency domain to form a complete wideband voltage and current dataset.

[0087] Furthermore, in the aforementioned engineering implementation, Figure 5 The diagram illustrates the implementation of the front-end hardware conditioning circuit for acquiring analog quantities of the target bus voltage and current in the wideband impedance sensing network 30, which can be considered as a wideband impedance sensing unit within the wideband impedance sensing network 30. This circuit employs a high-linearity opto-isolation structure with transient overvoltage protection. On its input side, a precision resistor voltage divider and a bidirectional TVS diode resist operational surges and high-frequency transient interference generated in the target bus secondary circuit. After being buffered by the first-stage buffer, the signal is driven by the servo drive stage composed of the operational amplifier and the integrating capacitor, which drives the light-emitting diode inside the HCNR201 high-linearity optocoupler. The current from the feedback photodiode is introduced to construct a deep negative feedback loop to suppress the nonlinearity and temperature drift of the light-emitting diode. On the isolated output side, the secondary operational amplifier, in conjunction with the transimpedance resistor and the filter capacitor, converts the optocoupler-received current into a corresponding voltage signal and filters out high-frequency noise, ultimately providing the high-fidelity and electrically isolated wideband sampling signal to the analog-to-digital converter of the system-on-a-chip.

[0088] In the design of the active integrator circuit, the input bias current of the operational amplifier should be as small as possible, the feedback capacitor should be a polystyrene capacitor with low dielectric absorption or an NPO ceramic capacitor, and the feedback resistor should be a metal film resistor with a low temperature coefficient. These details in the analog circuit determine the accuracy and stability of the entire broadband impedance sensing network 30.

[0089] After acquiring the broadband signals of the voltage and current, the programming control unit 50 can calculate the broadband impedance spectrum of the target bus 200 in real time, or it can extract only the dominant oscillation mode. Regardless of the algorithm used, the quality of the raw data provided by the broadband impedance sensing network 30 is the foundation of the algorithm's performance.

[0090] Example 6 exist Figure 3 In the memristor cross array 10, in addition to the normal memristor cells 11, at least one column of reference memristor cells 111 is specially provided. These reference memristor cells 111 are manufactured on the same chip or substrate using the exact same process as the normal memristor cells 11, and their physical characteristics (e.g., temperature coefficient, aging characteristics) are highly consistent. The reference memristor cells 111 are programmed to preset reference resistance states at the factory or during system calibration, and these preset reference resistance states are multiple different resistance values, uniformly or logarithmically covering the entire operating resistance range.

[0091] The readout circuit 25 is configured to correspond to each normal memristor cell 11. Its function is to periodically or as needed detect the current resistance value of the memristor cell 11 to confirm whether it has been correctly programmed to the target value. If it is incorrect, it needs to be reprogrammed or compensated.

[0092] When the readout circuit 25 operates, it applies a readout pulse to the target memristor cell 11. This readout pulse has a very small amplitude, insufficient to change the resistance state of the memristor cell 11, but it generates a detectable response current. Simultaneously, the readout circuit 25 applies the same readout pulse to a selected reference memristor cell 111. Then, the readout circuit 25 obtains the difference between the response current of the target memristor cell 11 and the response current of the reference memristor cell 111 through differential measurement. Since both are operating at the same temperature, the resistance change caused by temperature drift is suppressed as a common-mode signal in the differential output, greatly improving the accuracy of the resistance state readout.

[0093] The programming control unit 50 is communicatively connected to all readout circuits 25. The readout circuits 25 convert the differential current value into a digital value and report it. The programming control unit 50 internally maintains a target resistance value mapping table for each memristor cell 11. After receiving the actual differential current value, it compares it with the expected current threshold. The expected current threshold is the ideal response current range calculated based on the target resistance value. If the actual differential current falls within the expected range, it means that the memristor cell 11 has been correctly programmed. If the deviation exceeds the allowable error band, the programming control unit 50 generates a corrected impedance reconstruction command, reapplying a programming pulse to the memristor cell 11 for adjustment until the resistance value falls within the target range.

[0094] This closed-loop write-read-verify mechanism enables the memristor cross array 10 to maintain high impedance accuracy during long-term operation. It's important to understand that the resistance state of the memristor cell 11 drifts over time, especially rapidly immediately after programming, before stabilizing. With real-time readout and compensation, the effects of this drift can be effectively eliminated.

[0095] Figure 3 The readout circuit 25 is connected to the multi-row memristor unit 11 via a multiplexer 251. Figure 3 The connections between the multiplexer 251, the reference memristor unit 111, and the normal memristor unit 11 are shown. The readout circuit 25 contains a differential transimpedance amplifier that converts the input current difference into a voltage, which is then sampled and output by the ADC.

[0096] The reference memristor unit 111 has several preset reference resistance states with different values. Which one is selected as the reference for the current differential measurement depends on the expected resistance value of the target memristor unit 11. Logically, the reference resistance state that is closest to the expected resistance value should be selected, so that the differential current is smaller, the dynamic range of the amplifier can be fully utilized, and the measurement accuracy is higher.

[0097] Example 7 The preset reference states of the reference memristor cell 111 are distributed logarithmically within the operating resistance range of the memristor cell 11. For example, if the operating resistance range is 1kΩ to 100kΩ, then the logarithmic interval means that a reference state is set near each of the following resistance values: 1kΩ, 2kΩ, 5kΩ, 10kΩ, 20kΩ, 50kΩ, and 100kΩ. In this way, for any normal memristor cell 11, a relatively close reference state can always be found, and the ratio between the two generally does not exceed 2 to 3 times.

[0098] The input terminals of multiplexer 251 are connected to each of the reference memristor units 111, and the output terminal is connected to the reference input terminal of readout circuit 25. The selection state of multiplexer 251 is controlled by programming control unit 50. When issuing impedance reconstruction command, programming control unit 50 already knows the target resistance value of each target memristor unit 11. Therefore, before starting the readout verification process, it first calculates the closest reference resistance state index based on this target resistance value, and then sends a selection signal to multiplexer 251 to connect the corresponding reference memristor unit 111 to the reference channel of readout circuit 25.

[0099] When the readout circuit 25 performs the differential measurement, it actually measures the minute deviation between the resistance value of the target memristor unit 11 and the resistance value of the selected reference memristor unit 111. Since the reference resistance is a pre-calibrated precise value, this deviation can be converted into the absolute resistance value of the target memristor unit 11. If the deviation exceeds a preset error tolerance, such as ±5% of the target value, the reprogramming is triggered.

[0100] The reference memristor cells 111 are also affected by temperature and aging, but once programmed to those standard resistive states, they are generally not frequently rewritten and are relatively stable. Furthermore, since they are manufactured using the same process and from the same batch as the normal memristor cells 11, the direction and magnitude of their drift are correlated, and the differential measurement can offset most of the common-mode drift.

[0101] When the entire system is online, the readout verification operation is performed intermittently and can be scheduled during the quiet period after impedance reconstruction. The amplitude of the readout pulse is very small and will not cause perceptible disturbance to the programmed resistive state. If some memristor cells 11 exhibit a continuous drift trend in multiple verifications, the programming control unit 50 can activate predictive compensation, that is, intentionally overshoot a little during programming to ensure that the drifted steady-state value falls within the target range.

[0102] Example 8 like Figure 3 As shown, each memristor unit 11 is connected in series with a bidirectional threshold switch 112, forming a 1S1R unit 113. The bidirectional threshold switch 112 can physically be a bidirectional threshold switch device based on a chalcogenide compound, exhibiting significant threshold voltage characteristics.

[0103] The threshold voltage of the bidirectional threshold switch 112 is designed to be between the read pulse amplitude and the programming pulse amplitude. The read pulse amplitude is typically in the range of 0.1V to 0.3V, which is lower than the threshold voltage of the bidirectional threshold switch 112, thus placing the bidirectional threshold switch 112 in a high-impedance off state. In the high-impedance off state, the current flowing through the 1S1R cell 113 is extremely small, almost equivalent to an open circuit. Thus, during read operations, even if an unselected memristor cell 11 forms a potential creeping current path electrically through the row and column lines, it will be blocked by the series-connected bidirectional threshold switch 112. Creeping current problems are common in resistive random access memory (RRAM) cross-connect arrays and can severely affect read accuracy. With the introduction of the bidirectional threshold switch 112, only the row and column lines of the selected 1S1R cell 113 will be subjected to a sufficiently high voltage to make the voltage difference across it exceed the threshold voltage, at which point the bidirectional threshold switch 112 will turn on, allowing the read or programming current to flow through the memristor cell 11.

[0104] The amplitude of the programming pulse is typically between 1V and 3V or even higher, which is obviously higher than the threshold voltage of the bidirectional threshold switch 112. When the programming control unit 50 selects a 1S1R unit 113 for programming, a programming pulse is applied between the corresponding row and column lines. The voltage across the unit quickly exceeds the threshold voltage, the bidirectional threshold switch 112 turns on, and the programming current flows through the memristor unit 11, changing its resistance state. After programming is completed, the pulse is removed, the voltage drops, and the bidirectional threshold switch 112 returns to the high-resistance off state.

[0105] The specific threshold voltage value of the bidirectional threshold switch 112 depends on the manufacturing process. For example, the threshold voltage can be set to 0.6V. The readout pulse amplitude is set to 0.2V, and the programmable pulse amplitude range is between 1.2V and 2.5V. This provides sufficient voltage margin to ensure reliable selection and shutdown.

[0106] The physical structure of each 1S1R unit 113 can be achieved by first fabricating the bidirectional threshold switch 112 on the substrate, and then stacking the memristor unit 11 on top of the bidirectional threshold switch 112, with the connection made through a via. This vertical stacking structure can save chip area and increase array density.

[0107] Due to the presence of the bidirectional threshold switch 112, the parasitic leakage path of the entire memristor cross array 10 is significantly reduced. The array's static power consumption is extremely low when no cell is selected. During parallel programming, multiple 1S1R cells 113 can be selected simultaneously without interfering with each other, as long as they do not share the same row or column line.

[0108] Another function of the bidirectional threshold switch 112 is to protect the memristor unit 11. Various surges and transient overvoltages may couple into the power system bus. Although isolated and attenuated by the injection interface 40, a high voltage may still be induced at the port of the memristor cross array 10. If this voltage is directly applied to the unprotected memristor unit 11, it may cause misprogramming or even permanent damage. The bidirectional threshold switch 112 is normally in a high-resistance state and only conducts when the programming control unit 50 actively applies a sufficiently high voltage, thus providing a certain degree of protection.

[0109] Example 9 Regarding the process of the programming control unit 50 constructing a state-space smooth transition model and generating a smooth admittance trajectory, one optional implementation is as follows: The target impedance value is read from the generation queue of the impedance reconstruction instruction, and the target impedance value is converted into a target admittance value, where the target admittance value is the reciprocal of the target impedance value. The current resistance value of each memristor cell 11 is read from the current state register of the memristor cross array 10, and the reciprocals of each current resistance value are arranged in the row and column arrangement of the memristor cross array 10 to form a current admittance matrix. The summation of all elements of the current admittance matrix yields the current admittance state. The current admittance state is used as the initial state variable, and the target admittance value is used as the terminal state variable. The total number of steps from the initial state variable to the terminal state variable is set as a preset smoothing step number, where the preset smoothing step number is a positive integer not less than 20. A first-order linear state-space model is constructed, where the state variables are admittance values ​​and the control input is the admittance rate of change. The upper limit of the magnitude of the admittance rate of change is set as the maximum conductance change of the memristor unit 11 under a single programming pulse divided by the programming period. Within each discrete time step, with the optimization objective of minimizing the sum of squares of the admittance rate of change and the upper limit of the magnitude of the admittance rate of change as a constraint, the optimal control sequence that minimizes the cumulative squared rate of change of the state variable from the admittance value of the current step to the terminal state variable is solved. The admittance values ​​of each time step in the optimal control sequence are arranged in chronological order to obtain the smooth admittance trajectory.

[0110] Assuming the target impedance is 500Ω, then the target admittance is... S. Let the memristor cross array 10 be... Given a simplified array, where the current resistance values ​​of each memristor unit 11 are 10kΩ, 20kΩ, 50kΩ, and 100kΩ, the current admittance matrix is: The summation of each element yields the current admittance state as follows: S. The initial state variable is set to... The terminal state variable is set to The preset smoothing step count is set to 20 steps. The maximum conductance change of the memristor unit 11 under a single programming pulse is... S, the programming period is 1.8ms divided by 20 equals 90μs, and the upper limit of the amplitude of the admittance change rate is... Divide by Approximately equal to S / s. In the first step of the solution, the admittance value of the current step is... Distance from the terminal state variable The difference is The upper limit of the magnitude of the admittance change rate As a constraint, the rate of change of the admittance of the optimal control sequence in step 1 is... The updated admittance value is And so on, each subsequent step is calculated in turn, until the admittance value is reached in step 17. In step 18, the terminal state variable is the limiting factor. The rate of change of admittance was adjusted to Divide by Approximately equal to The admittance value is updated to Then maintain each step. This remains unchanged until step 20. The final generated smooth admittance trajectory is from... Monotonically increasing to 20 discrete value sequences.

[0111] Another optional implementation of the process of progressively generating the smooth admittance trajectory is as follows: The current admittance state of the memristor cross array 10 is used as the initial state variable, and the target admittance state is used as the terminal state variable. A preset smoothing step number is set as the total number of steps from the initial state variable to the terminal state variable. This preset smoothing step number is a positive integer not less than 20. The current step number is initialized to 1, and the admittance value of the current step is initialized to the initial state variable. In each step, the remaining admittance difference from the current step's admittance value to the terminal state variable is calculated. This remaining admittance difference is equal to the terminal state variable minus the current step's admittance value. The remaining step number is calculated, which is equal to the preset smoothing step number minus the current step number plus 1. The remaining admittance difference is divided by the remaining step number to obtain the admittance increment for that step. The maximum conductance change of the memristor cell 11 during a single programming pulse is read from the parameter register of the memristor cross array 10. The maximum conductance change is divided by the programming period to obtain the upper limit of the admittance rate of change amplitude. The absolute value of the admittance increment is compared with the upper limit of the amplitude. If the absolute value of the admittance increment exceeds the upper limit of the amplitude, the admittance increment is truncated to the boundary value of the upper limit of the amplitude, and the sign of the truncated admittance increment is the same as before truncation. The truncated admittance increment is added to the admittance value of the current step to obtain the admittance value of the next step. The current step number is incremented by 1, and the admittance value of the next step is used as the new admittance value of the current step. The above calculation process is repeated until the current step number equals the preset number of smoothing steps. The admittance values ​​calculated in each step are arranged in chronological order to generate the smooth admittance trajectory.

[0112] Let the initial state variable be S, the terminal state variable is S, the preset smoothing step number is 20 steps, and the upper limit of the amplitude of the admittance change rate is... S / s. Step 1: Current step admittance value. Residual admittance difference Remaining steps: 20, admittance increment The absolute value of the admittance increment Less than the upper limit of amplitude No truncation is needed. Next, the admittance value... Step 2: Current step admittance value Residual admittance difference Remaining steps: 19; Admittance increment: Next admittance value Following this recursive process up to step 20, the admittance value reaches... S, the generated smooth admittance trajectory consists of 20 monotonically increasing discrete values.

[0113] The periodic reading of the current resistance state of the reference memristor unit 111 and acquisition of the resistance state drift by the programming control unit 50 can be implemented as follows: The current time is obtained from the system clock; the time interval between the current time and the last reference unit calibration time is calculated; when the time interval is greater than a preset calibration period of 60 minutes, the current calibration process is initiated. A reference unit readout command is sent to the readout circuit 25, the readout command containing the row address and column address of the reference memristor unit 111 to be read. The differential voltage signal returned by the readout circuit 25 is received; the differential voltage signal is divided by the constant current source current value of the readout circuit 25 to obtain the current resistance state measurement value of the reference memristor unit 111. The preset reference resistance state written by the reference memristor unit 111 during factory calibration is read from the non-volatile memory. The current resistance state measurement value is subtracted from the preset reference resistance state to obtain the difference. The absolute value of the difference is divided by the preset reference resistance state to obtain the resistance state drift amount, which is expressed as a percentage.

[0114] Assuming the current time recorded by the system clock is 3600s, the last reference unit calibration time is 0s, and the time interval 3600s equals the preset calibration period of 60min, the current calibration process is initiated. The differential voltage signal returned by the readout circuit 25 is 0.050V. The constant current source current value is 1μA, and the current resistance measurement value is... kΩ. The preset reference resistance state read from the non-volatile memory is 50kΩ. The difference is 50kΩ minus 50kΩ equals 0kΩ, and the resistance state drift is... Assuming that in another calibration, the differential voltage signal is 0.052V, and the current resistance measurement is... kΩ. The difference is... kΩ, the resistive state drift is .

[0115] To monitor the health indicators of memristor cells 11 in each region of the memristor cross array 10, the programming control unit 50 can be implemented as follows: Maintain a health counter for each local subarray of the memristor cross array 10, with an initial value of 1000. After each programming operation on a memristor cell 11 within the local subarray, read the programming verification result of that memristor cell 11. If the verification fails, set the single programming failure flag corresponding to that memristor cell 11 to 1; if the verification succeeds, set it to 0. At each preset health evaluation cycle, count the cumulative number of times the single programming failure flag of each memristor cell 11 within the local subarray is 1 during this evaluation cycle. Divide the cumulative number by the total number of programming attempts for that memristor cell 11 during this evaluation cycle to obtain the programming success rate of that memristor cell 11. The resistance hold time recorded in the previous resistance hold test of the memristor unit 11 is read. The resistance hold time is the time interval from the programming completion time to the time when the resistance drift exceeds the preset allowable range. The programming success rate and the resistance hold time are weighted and summed with a weighting coefficient of 0.5 to obtain the unit health of the memristor unit 11. The average value of the unit health of all memristor units 11 in the local subarray is used as the health index and stored in the current value register of the health counter.

[0116] The health counter of a local subarray A of the memristor cross array 10 is initially set to 1000. Within one evaluation cycle, this subarray has 100 memristor cells 11, and each cell has a total of 200 programming attempts within that cycle. Cell number 1 has a cumulative total of 3 programming failures with the single programming failure flag set to 1, resulting in a programming success rate of... The resistive hold-up time is 7200s. The cell health is... Unit number 2 has a cumulative failure count of 15, resulting in a programming success rate of 100%. The resistive state retention time is 5400s, and the cell health is... The health of all 100 units is calculated in this manner, summed, and divided by 100 to obtain the health index of 0.912, which is then stored in the current value register of the health counter.

[0117] When the field-programmable gate array chip 51 uses a cascaded multi-stage filter bank structure to perform the multi-stage subband division, the following process can be adopted: A discrete-time sequence with a length of 4096 sampling points is read from the current sampling buffer of the real-time wideband oscillation characteristic signal, with a sampling frequency of 100 MSa / s. The discrete-time sequence is sent to the first-stage filter bank, which includes a low-pass finite impulse response (FIR) filter and a high-pass finite impulse response (FIR) filter. The coefficients of the low-pass FIR filter and the high-pass FIR filter are obtained based on the same prototype low-pass filter through frequency transformation, and the two have complementary amplitude-frequency response characteristics in the frequency domain. The first-stage filter bank divides the discrete-time sequence into a first low-frequency subband signal and a first high-frequency subband signal. The first low-frequency subband signal is sent to the second-stage filter bank for further division, and the first high-frequency subband signal is output to the first-stage subband energy calculation module. The second-stage filter bank divides the first low-frequency sub-band signal into a second low-frequency sub-band signal and a second high-frequency sub-band signal. The second low-frequency sub-band signal is sent to the next-stage filter bank, and the second high-frequency sub-band signal is output to the second-stage sub-band energy calculation module. This division is performed stage by stage until the last-stage filter bank outputs a last low-frequency sub-band signal and a high-frequency sub-band signal. The last low-frequency sub-band signal is output to the last-stage sub-band energy calculation module. The sub-band energy is calculated in parallel for the high-frequency sub-band signal and the last low-frequency sub-band signal output from each stage. The sub-band energy is the sum of the squares of the sampled values ​​in the corresponding sub-band signal. Each sub-band energy is divided by the sum of all sub-band energies to obtain the energy proportion of each sub-band. The energy proportion of each sub-band is compared with a preset threshold, and the sub-bands with an energy proportion greater than the preset threshold are marked as target frequency bands. A fast Fourier transform is performed on the time-domain reconstructed signal corresponding to each target frequency band to obtain the spectral data of that target frequency band.

[0118] Suppose a 4-level decomposition is performed, resulting in 16 sub-bands, each with a bandwidth of 100MHz divided by 32, which equals 3.125MHz. The wavelet packet coefficient sequence for sub-band 1 (0 to 3.125MHz) is as follows: arrive The sum of squares of the 256 coefficients is 0.25. The sum of squares of the coefficients in sub-band 5 (12.5 to 15.625 MHz) is 8.50, and the sum of squares of the coefficients in sub-band 6 (15.625 to 18.75 MHz) is 3.20. The energy values ​​of the remaining sub-bands are all less than 0.5. The total energy is... The energy percentage of sub-band 1 is... If the value is below a preset threshold of 5%, it will not be marked. The energy percentage of sub-band 5 is... This is marked as the target frequency band. The energy percentage of sub-band 6 is... This is marked as the target frequency band. Single-subband reconstruction is performed on the coefficient sequence of sub-band 5 to obtain the time-domain reconstructed signal. After performing a Fast Fourier Transform, the peak value of 2.18V with the largest amplitude is found at 15.0MHz. Sub-band 6 has an amplitude of 1.05V found at 17.2MHz.

[0119] The implementation process of the programming control unit 50 in online identification of the broadband impedance spectrum of the target bus 200 is as follows: An impedance parameter vector of a preset order is maintained, where each component of the impedance parameter vector corresponds to the impedance amplitude and phase of the target bus 200 at different frequency points near the frequency of the dominant oscillation mode. The impedance parameter vector is initialized to factory preset values. After receiving new sampling data of the real-time broadband oscillation characteristic signal, the voltage and current sampling values ​​in the sampling data are respectively constructed into observation vectors. Using the current component in the current impedance parameter vector and the observation vector, the impedance spectrum estimate is calculated through complex multiplication. The impedance spectrum estimate is the voltage estimate at each frequency point. The voltage estimate is subtracted element-wise from the measured voltage value in the observation vector to obtain the prediction error vector. The sum of the squares of each element in the prediction error vector is divided by the dimension of the observation vector to obtain the current prediction error power. Dividing the current prediction error power by a preset reference noise power yields the reciprocal of the signal-to-noise ratio (SNR). Multiplying this SNR by a preset gain adjustment factor yields an adaptive gain factor, where the adaptive gain factor ranges from 0 to 1. Multiplying the prediction error vector by the adaptive gain factor, and then by the conjugate transpose of the current component in the observation vector, yields the update increment of the impedance parameter vector. Adding this update increment to the current impedance parameter vector yields the updated impedance parameter vector, thus completing the online identification process recursively.

[0120] Assume the preset order of the impedance parameter vector is 2, corresponding to frequencies of 15.0MHz and 15.1MHz, and the factory preset value is... In the newly sampled data, the measured voltage at 15.0 MHz was 2.35 V and the current was 0.0047 A. The measured voltage at 15.1 MHz was 2.18 V and the current was 0.0045 A. The current component in the observation vector is... A, the measured voltage component is V. Calculate the voltage estimate using the current impedance parameters at 15.0 MHz. Its amplitude is approximately 2.40V. At 15.1MHz We take its amplitude to be approximately 2.23V. The prediction error vector is... V. Prediction error power is The preset reference noise power is 0.01, and the reciprocal of the signal-to-noise ratio is... The preset gain adjustment factor is 0.8, and the adaptive gain factor is... Update the incremental components of each dimension as follows: The conjugate of is approximately equal to The first dimension of the updated impedance parameter vector is The online identification process is completed by recursion in this manner.

Claims

1. An impedance injection type oscillation suppressor based on a memristor cross array, including: A memristor cross array having multiple memristor cells arranged along the row and column directions, wherein the resistance value of each memristor cell is configured to change continuously in response to a programming pulse applied thereto. A parallel programming drive circuit, electrically connected to the row and column lines of the memristor cross array, is configured to receive impedance reconstruction instructions and apply the programming pulse to the selected memristor cells; A broadband impedance sensing network is configured to be coupled to a target bus to obtain real-time broadband oscillation characteristic signals of the voltage and current of the target bus; An injection interface has an input terminal and an output terminal, the input terminal being electrically connected to the output port of the memristor cross array, and the output terminal being configured to be coupled to the target bus. The programming control unit is communicatively connected to the wideband impedance sensing network and the parallel programming drive circuit. The programming control unit is configured to calculate the target impedance value based on the real-time wideband oscillation characteristic signal, and convert the target impedance value into the impedance reconstruction instruction and send it to the parallel programming drive circuit, so that the memristor cross array injects physical damping corresponding to the target impedance value into the target bus through the injection interface.

2. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 1, wherein, The parallel programming driver circuit includes: Multiple distributed pulse generation units are configured to correspond to each local subarray of the memristor cross array, and each distributed pulse generation unit is configured to independently generate the programming pulse that acts on the memristor unit within its subarray. The distributed pulse generation unit includes: A digital-to-analog converter is configured to receive programmed amplitude data from the programming control unit and output a reference voltage; A programmable pulse width modulator, configured to receive programming timing data from the programming control unit and output a pulse control signal, the programmable pulse width modulator including a coarse-tuning counter and a fine-tuning delay chain to provide nanosecond-level time resolution; and A controlled voltage driver, electrically connected to the digital-to-analog converter and the programmable pulse width modulator, is configured to output the programmable pulse, the amplitude of which is controlled by the reference voltage, to the memristor unit during the effective period of the pulse control signal; The programming control unit is configured to parse the impedance reconstruction instruction and distribute it to the corresponding distributed pulse generation unit.

3. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 1, wherein, The injection interface includes: A linear transimpedance amplifier, the input of which is electrically connected to the output port of the memristor cross array; A high-frequency magnetic coupling transformer includes a Z-shaped magnetic core. The middle column of the Z-shaped magnetic core has a through-type single-turn secondary winding structure and is configured to be injected in series into the target busbar. The left column is wound with a primary winding, and the right column is wound with a bias winding. A fine-tuning magnetic path is formed between the left column and the middle column, and a bias magnetic path is formed between the right column and the middle column. The fine-tuning magnetic path and the bias magnetic path achieve magnetic flux superposition within the middle column. The primary winding is connected to the output of the linear transimpedance amplifier; An adjustable DC bias current source is electrically connected to the bias winding and configured to inject DC current into the bias winding to adjust the static permeability of the H-shaped magnetic core. The feedforward compensation winding is wound on the left column of the H-shaped magnetic core and is concentric with the primary winding but opposite in polarity. The programming control unit is electrically connected to the feedforward compensation winding and is configured to inject compensation current into the feedforward compensation winding according to the rate of change of current in the bias winding, so as to counteract the coupling interference of the bias flux change on the fine-tuning signal in the primary winding.

4. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 3, wherein, The H-shaped magnetic core is made of ultra-microcrystalline alloy strip wound together. The sum of the cross-sectional areas of the left column and the right column is equal to the cross-sectional area of ​​the middle column. The ratio of the magnetic reluctance of the fine-tuning magnetic path to the magnetic reluctance of the bias magnetic path is set by the ratio of the cross-sectional areas of the left column and the right column. The cross-sectional area of ​​the left column is 0.6 to 0.8 times that of the right column, ensuring that the fine-tuning magnetic path always operates within the linear region of the magnetization curve of the microcrystalline alloy strip within the rated operating current range of the adjustable DC bias current source. The number of turns of the bias winding on the right column is 2 to 3 times the number of turns of the primary winding on the left column, so as to generate a bias flux adjustment range sufficient to cover the full range admittance variation of the memristor cross array under the same DC bias current.

5. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 1, wherein, The broadband impedance sensing network also includes: An active integrator circuit is electrically connected to the output of a Rogowski coil sensor and is configured to integrate the signal output by the Rogowski coil sensor in proportion to the rate of change of current in order to reconstruct a signal in proportion to the current. A high-pass filter circuit is connected in series with the output of the active integrator circuit; and A low-pass filter circuit is connected in series with the output terminal of the RC voltage divider sensor. Its cutoff frequency is complementary to the cutoff frequency of the high-pass filter circuit in the frequency domain. The cutoff frequency of the high-pass filter circuit is set based on the minimum oscillation frequency of the target bus, and the cutoff frequency of the low-pass filter circuit is set based on the highest measurement frequency of the broadband impedance sensing network.

6. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 1, wherein, The memristor cross array also includes: At least one column of reference memristor cells is manufactured using the same process as the memristor cell and programmed to a preset reference resistance state, the preset reference resistance state including multiple different resistance values ​​to cover the operating resistance range of the memristor cell; The parallel programming drive circuit also includes multiple readout circuits, which are configured to correspond to each memristor unit. Each readout circuit is configured to apply a readout pulse to the corresponding memristor unit and detect its response current. The readout circuit is also configured to differentially measure the response current of the memristor cell and the response current of the reference memristor cell to eliminate common-mode interference of temperature drift on resistive readout. The programming control unit is communicatively connected to the readout circuit and is configured to compare the response current with a expected current threshold to verify whether the memristor unit has been correctly programmed.

7. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 6, wherein, The at least one column of reference memristor cells is programmed to multiple different preset reference states. Each of the preset reference resistance states is distributed logarithmically within the operating resistance range of the memristor cell. The readout circuit is configured to, when performing differential measurements on the target memristor cell, select from the at least one column of reference memristor cells the reference memristor cell corresponding to the preset reference resistance state that is closest to the expected resistance value of the target memristor cell, as the differential reference object for this measurement. The readout circuit includes a multiplexer electrically connected to each of the reference memristor units, and the programmable control unit controls the selection state of the multiplexer according to the target resistance value set for the target memristor unit in the impedance reconstruction instruction.

8. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 1, wherein, Each memristor cell in the memristor cross array is connected in series with a bidirectional threshold switch to form a gating memristor cell. The bidirectional threshold switch has a threshold voltage. When the voltage applied across the selected memristor cell is lower than the threshold voltage, the bidirectional threshold switch is in a high-impedance off state to block the creeping current path flowing through the unselected memristor cell. When the voltage applied across the selected memristor unit is higher than the threshold voltage, the bidirectional threshold switch is turned on, and the programming pulse is applied across the memristor unit to change its resistance value. The threshold voltage of the bidirectional threshold switch is between the readout pulse amplitude and the programming pulse amplitude output by the programming control unit.

9. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 1, wherein, The programming control unit is configured to: Before converting the target impedance value into the impedance reconstruction instruction, a state-space smooth transition model is constructed using the current admittance state of the memristor cross array and the target impedance value. Based on the state-space smooth transition model, the optimal control problem in the finite time domain is solved online to generate a smooth admittance trajectory from the current admittance state to the target admittance state corresponding to the target impedance value. as well as The smooth admittance trajectory is converted into a series of timing-continuous impedance reconstruction instructions and sent to the parallel programming drive circuit.

10. The impedance injection type oscillation suppressor based on a memristor cross array according to claim 2, wherein, The programming control unit is configured to: The total admittance requirement corresponding to the target impedance value is decomposed into multiple sub-admittance components; Assigning each of the subadmittance components to different local subarrays; and The distributed pulse generation units are coordinated to perform programming operations on each of the local subarrays in parallel to globally reconstruct the target impedance value within a predetermined time.

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